| blob | 2091e5dbbcdd9f50d0d0dec422cd2e1c3aac2d4f |
1 /* Copyright 2008-2011 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
30 /********************************************************/
31 #define ETH_HLEN 14
32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
33 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
34 #define ETH_MIN_PACKET_SIZE 60
35 #define ETH_MAX_PACKET_SIZE 1500
36 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
37 #define MDIO_ACCESS_TIMEOUT 1000
38 #define BMAC_CONTROL_RX_ENABLE 2
39 #define WC_LANE_MAX 4
40 #define I2C_SWITCH_WIDTH 2
41 #define I2C_BSC0 0
42 #define I2C_BSC1 1
43 #define I2C_WA_RETRY_CNT 3
44 #define MCPR_IMC_COMMAND_READ_OP 1
45 #define MCPR_IMC_COMMAND_WRITE_OP 2
47 /* LED Blink rate that will achieve ~15.9Hz */
48 #define LED_BLINK_RATE_VAL_E3 354
49 #define LED_BLINK_RATE_VAL_E1X_E2 480
50 /***********************************************************/
51 /* Shortcut definitions */
52 /***********************************************************/
54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
56 #define NIG_STATUS_EMAC0_MI_INT \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
58 #define NIG_STATUS_XGXS0_LINK10G \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
60 #define NIG_STATUS_XGXS0_LINK_STATUS \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
64 #define NIG_STATUS_SERDES0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
66 #define NIG_MASK_MI_INT \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
68 #define NIG_MASK_XGXS0_LINK10G \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
70 #define NIG_MASK_XGXS0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
72 #define NIG_MASK_SERDES0_LINK_STATUS \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
75 #define MDIO_AN_CL73_OR_37_COMPLETE \
76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
79 #define XGXS_RESET_BITS \
80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
86 #define SERDES_RESET_BITS \
87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
92 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
93 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
94 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
95 #define AUTONEG_PARALLEL \
96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
97 #define AUTONEG_SGMII_FIBER_AUTODET \
98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
99 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
105 #define GP_STATUS_SPEED_MASK \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
107 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
108 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
109 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
110 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
111 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
112 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
113 #define GP_STATUS_10G_HIG \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
115 #define GP_STATUS_10G_CX4 \
116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
118 #define GP_STATUS_10G_KX4 \
119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
121 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
123 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
124 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
125 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
126 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
127 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
128 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
129 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
130 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
131 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
132 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
133 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
134 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
135 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
136 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
137 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
138 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
142 /* */
143 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
144 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
145 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
148 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
149 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
150 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
151 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
153 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
155 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
157 #define SFP_EEPROM_OPTIONS_ADDR 0x40
158 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
159 #define SFP_EEPROM_OPTIONS_SIZE 2
161 #define EDC_MODE_LINEAR 0x0022
162 #define EDC_MODE_LIMITING 0x0044
163 #define EDC_MODE_PASSIVE_DAC 0x0055
165 /* BRB default for class 0 E2 */
166 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
167 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
168 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
169 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
171 /* BRB thresholds for E2*/
172 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
173 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
175 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
176 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
178 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
179 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
181 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
182 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
184 /* BRB default for class 0 E3A0 */
185 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
186 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
187 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
188 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
190 /* BRB thresholds for E3A0 */
191 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
192 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
194 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
195 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
197 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
198 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
200 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
201 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
203 /* BRB default for E3B0 */
204 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
205 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
206 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
207 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
209 /* BRB thresholds for E3B0 2 port mode*/
210 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
211 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
213 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
214 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
216 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
217 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
219 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
220 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
222 /* only for E3B0*/
223 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
224 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
226 /* Lossy +Lossless GUARANTIED == GUART */
227 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
228 /* Lossless +Lossless*/
229 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
230 /* Lossy +Lossy*/
231 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
233 /* Lossy +Lossless*/
234 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
235 /* Lossless +Lossless*/
236 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
237 /* Lossy +Lossy*/
238 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
239 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
241 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
242 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
244 /* BRB thresholds for E3B0 4 port mode */
245 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
246 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
248 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
249 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
251 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
252 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
254 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
255 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
257 /* only for E3B0*/
258 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
259 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
260 #define PFC_E3B0_4P_LB_GUART 120
262 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
263 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
265 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
266 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
268 /* Pause defines*/
269 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
270 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
271 #define DEFAULT_E3B0_LB_GUART 40
273 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
274 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
276 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
277 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
279 /* ETS defines*/
280 #define DCBX_INVALID_COS (0xFF)
282 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
283 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
284 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
285 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
286 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
288 #define MAX_PACKET_SIZE (9700)
289 #define WC_UC_TIMEOUT 100
290 #define MAX_KR_LINK_RETRY 4
292 /**********************************************************/
293 /* INTERFACE */
294 /**********************************************************/
296 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
297 bnx2x_cl45_write(_bp, _phy, \
298 (_phy)->def_md_devad, \
299 (_bank + (_addr & 0xf)), \
300 _val)
302 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
303 bnx2x_cl45_read(_bp, _phy, \
304 (_phy)->def_md_devad, \
305 (_bank + (_addr & 0xf)), \
306 _val)
309 {
315 }
318 {
324 }
326 /******************************************************************/
327 /* EPIO/GPIO section */
328 /******************************************************************/
330 {
333 /* Sanity check */
337 }
340 /* Set this EPIO to output */
345 }
347 {
350 /* Sanity check */
354 }
357 /* Set this EPIO to output */
361 else
366 /* Set the value for this EPIO */
369 }
372 {
381 }
382 }
385 {
394 }
397 }
398 /******************************************************************/
399 /* ETS section */
400 /******************************************************************/
402 {
403 /* ETS disabled configuration*/
408 /*
409 * mapping between entry priority to client number (0,1,2 -debug and
410 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
411 * 3bits client num.
412 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
413 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
414 */
417 /*
418 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
419 * as strict. Bits 0,1,2 - debug and management entries, 3 -
420 * COS0 entry, 4 - COS1 entry.
421 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
422 * bit4 bit3 bit2 bit1 bit0
423 * MCP and debug are strict
424 */
427 /* defines which entries (clients) are subjected to WFQ arbitration */
429 /*
430 * For strict priority entries defines the number of consecutive
431 * slots for the highest priority.
432 */
434 /*
435 * mapping between the CREDIT_WEIGHT registers and actual client
436 * numbers
437 */
445 /* ETS mode disable */
447 /*
448 * If ETS mode is enabled (there is no strict priority) defines a WFQ
449 * weight for COS0/COS1.
450 */
453 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
456 /* Defines the number of consecutive slots for the strict priority */
458 }
459 /******************************************************************************
460 * Description:
461 * Getting min_w_val will be set according to line speed .
462 *.
463 ******************************************************************************/
465 {
467 /* Calculate min_w_val.*/
471 else
475 /**
476 * If the link isn't up (static configuration for example ) The
477 * link will be according to 20GBPS.
478 */
480 }
481 /******************************************************************************
482 * Description:
483 * Getting credit upper bound form min_w_val.
484 *.
485 ******************************************************************************/
487 {
489 MAX_PACKET_SIZE);
491 }
492 /******************************************************************************
493 * Description:
494 * Set credit upper bound for NIG.
495 *.
496 ******************************************************************************/
500 {
521 credit_upper_bound);
523 credit_upper_bound);
525 credit_upper_bound);
526 }
527 }
528 /******************************************************************************
529 * Description:
530 * Will return the NIG ETS registers to init values.Except
531 * credit_upper_bound.
532 * That isn't used in this configuration (No WFQ is enabled) and will be
533 * configured acording to spec
534 *.
535 ******************************************************************************/
538 {
542 /**
543 * mapping between entry priority to client number (0,1,2 -debug and
544 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
545 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
546 * reset value or init tool
547 */
554 }
555 /**
556 * For strict priority entries defines the number of consecutive
557 * slots for the highest priority.
558 */
559 /* TODO_ETS - Should be done by reset value or init tool */
562 /**
563 * mapping between the CREDIT_WEIGHT registers and actual client
564 * numbers
565 */
566 /* TODO_ETS - Should be done by reset value or init tool */
568 /*Port 1 has 6 COS*/
572 /*Port 0 has 9 COS*/
576 }
578 /**
579 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
580 * as strict. Bits 0,1,2 - debug and management entries, 3 -
581 * COS0 entry, 4 - COS1 entry.
582 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
583 * bit4 bit3 bit2 bit1 bit0
584 * MCP and debug are strict
585 */
588 else
590 /* defines which entries (clients) are subjected to WFQ arbitration */
594 /**
595 * Please notice the register address are note continuous and a
596 * for here is note appropriate.In 2 port mode port0 only COS0-5
597 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
598 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
599 * are never used for WFQ
600 */
617 }
620 }
621 /******************************************************************************
622 * Description:
623 * Set credit upper bound for PBF.
624 *.
625 ******************************************************************************/
629 {
637 /**
638 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
639 * port mode port1 has COS0-2 that can be used for WFQ.
640 */
647 }
651 }
653 /******************************************************************************
654 * Description:
655 * Will return the PBF ETS registers to init values.Except
656 * credit_upper_bound.
657 * That isn't used in this configuration (No WFQ is enabled) and will be
658 * configured acording to spec
659 *.
660 ******************************************************************************/
662 {
670 /**
671 * mapping between entry priority to client number 0 - COS0
672 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
673 * TODO_ETS - Should be done by reset value or init tool
674 */
676 /* 0x688 (|011|0 10|00 1|000) */
678 else
679 /* (10 1|100 |011|0 10|00 1|000) */
682 /* TODO_ETS - Should be done by reset value or init tool */
684 /* 0x688 (|011|0 10|00 1|000)*/
686 else
687 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
699 /**
700 * In 2 port mode port0 has COS0-5 that can be used for WFQ.
701 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
702 */
709 }
715 }
716 /******************************************************************************
717 * Description:
718 * E3B0 disable will return basicly the values to init values.
719 *.
720 ******************************************************************************/
723 {
730 }
737 }
739 /******************************************************************************
740 * Description:
741 * Disable will return basicly the values to init values.
742 *.
743 ******************************************************************************/
746 {
757 }
760 }
762 /******************************************************************************
763 * Description
764 * Set the COS mappimg to SP and BW until this point all the COS are not
765 * set as SP or BW.
766 ******************************************************************************/
771 {
786 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
787 nig_cli_subject2wfq_bitmap);
790 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
791 pbf_cli_subject2wfq_bitmap);
794 }
796 /******************************************************************************
797 * Description:
798 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
799 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
800 ******************************************************************************/
808 {
811 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
817 nig_reg_adress_crd_weight =
819 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
825 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
826 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
832 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
833 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
841 nig_reg_adress_crd_weight =
842 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
843 pbf_reg_adress_crd_weight =
844 PBF_REG_COS3_WEIGHT_P0;
849 nig_reg_adress_crd_weight =
850 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
856 nig_reg_adress_crd_weight =
857 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
860 }
867 }
868 /******************************************************************************
869 * Description:
870 * Calculate the total BW.A value of 0 isn't legal.
871 *.
872 ******************************************************************************/
877 {
884 /* Calculate total BW requested */
891 /*
892 * This is to prevent a state when ramrods
893 * can't be sent
894 */
897 }
900 }
901 }
903 /* Check total BW is valid */
909 }
912 /*
913 * We can handle a case whre the BW isn't 100 this can happen
914 * if the TC are joined.
915 */
916 }
918 }
920 /******************************************************************************
921 * Description:
922 * Invalidate all the sp_pri_to_cos.
923 *.
924 ******************************************************************************/
926 {
930 }
931 /******************************************************************************
932 * Description:
933 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
934 * according to sp_pri_to_cos.
935 *.
936 ******************************************************************************/
940 {
944 DCBX_E3B0_MAX_NUM_COS_PORT0;
948 "parameter There can't be two COS's with "
951 }
957 }
962 }
964 /******************************************************************************
965 * Description:
966 * Returns the correct value according to COS and priority in
967 * the sp_pri_cli register.
968 *.
969 ******************************************************************************/
974 {
980 }
981 /******************************************************************************
982 * Description:
983 * Returns the correct value according to COS and priority in the
984 * sp_pri_cli register for NIG.
985 *.
986 ******************************************************************************/
988 {
989 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
996 }
997 /******************************************************************************
998 * Description:
999 * Returns the correct value according to COS and priority in the
1000 * sp_pri_cli register for PBF.
1001 *.
1002 ******************************************************************************/
1004 {
1011 }
1013 /******************************************************************************
1014 * Description:
1015 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1016 * according to sp_pri_to_cos.(which COS has higher priority)
1017 *.
1018 ******************************************************************************/
1021 {
1025 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1031 DCBX_E3B0_MAX_NUM_COS_PORT0;
1035 /* Set all the strict priority first */
1040 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1043 }
1051 /* COS is used remove it from bitmap.*/
1054 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1055 "invalid There can't be two COS's with"
1058 }
1060 pri_set++;
1061 }
1062 }
1064 /* Set all the Non strict priority i= COS*/
1067 /* Check if COS was already used for SP */
1069 /* COS wasn't used for SP */
1075 /* COS is used remove it from bitmap.*/
1077 pri_set++;
1078 }
1079 }
1085 }
1088 /* Only 6 usable clients*/
1094 /* Only 9 usable clients*/
1099 pri_cli_nig_lsb);
1101 pri_cli_nig_msb);
1104 }
1106 }
1108 /******************************************************************************
1109 * Description:
1110 * Configure the COS to ETS according to BW and SP settings.
1111 ******************************************************************************/
1115 {
1126 DCBX_E3B0_MAX_NUM_COS_PORT0;
1133 }
1139 }
1141 /* Prepare sp strict priority parameters*/
1144 /* Prepare BW parameters*/
1151 }
1153 /*
1154 * Upper bound is set according to current link speed (min_w_val
1155 * should be the same for upper bound and COS credit val).
1156 */
1164 /*
1165 * The function also sets the BW in HW(not the mappin
1166 * yet)
1167 */
1170 total_bw,
1172 port);
1178 params,
1179 sp_pri_to_cos,
1181 cos_entry);
1187 }
1192 }
1193 }
1195 /* Set SP register (which COS has higher priority) */
1197 sp_pri_to_cos);
1203 }
1205 /* Set client mapping of BW and strict */
1207 cos_sp_bitmap,
1208 cos_bw_bitmap);
1213 }
1215 }
1217 {
1218 /* ETS disabled configuration */
1221 /*
1222 * defines which entries (clients) are subjected to WFQ arbitration
1223 * COS0 0x8
1224 * COS1 0x10
1225 */
1227 /*
1228 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1229 * client numbers (WEIGHT_0 does not actually have to represent
1230 * client 0)
1231 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1232 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1233 */
1237 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1239 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1241 /* ETS mode enabled*/
1244 /* Defines the number of consecutive slots for the strict priority */
1246 /*
1247 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1248 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1249 * entry, 4 - COS1 entry.
1250 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1251 * bit4 bit3 bit2 bit1 bit0
1252 * MCP and debug are strict
1253 */
1256 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1258 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1260 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1261 }
1265 {
1266 /* ETS disabled configuration*/
1279 }
1282 total_bw;
1284 total_bw;
1293 }
1296 {
1297 /* ETS disabled configuration*/
1302 /*
1303 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1304 * as strict. Bits 0,1,2 - debug and management entries,
1305 * 3 - COS0 entry, 4 - COS1 entry.
1306 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1307 * bit4 bit3 bit2 bit1 bit0
1308 * MCP and debug are strict
1309 */
1311 /*
1312 * For strict priority entries defines the number of consecutive slots
1313 * for the highest priority.
1314 */
1316 /* ETS mode disable */
1318 /* Defines the number of consecutive slots for the strict priority */
1321 /* Defines the number of consecutive slots for the strict priority */
1324 /*
1325 * mapping between entry priority to client number (0,1,2 -debug and
1326 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1327 * 3bits client num.
1328 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1329 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1330 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1331 */
1336 }
1337 /******************************************************************/
1338 /* PFC section */
1339 /******************************************************************/
1342 u8 is_lb)
1343 {
1345 u32 xmac_base;
1348 /* XMAC base adrr */
1351 /* Initialize pause and pfc registers */
1356 /* No PFC support */
1358 FEATURE_CONFIG_PFC_ENABLED)) {
1360 /*
1361 * RX flow control - Process pause frame in receive direction
1362 */
1366 /*
1367 * TX flow control - Send pause packet when buffer is full
1368 */
1373 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1374 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1375 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1376 }
1378 /* Write pause and PFC registers */
1384 /* Set MAC address for source TX Pause/PFC frames */
1395 }
1401 {
1402 /* Read pfc statistic */
1410 /* PFC received frames */
1412 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1419 /* PFC received sent */
1421 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1427 }
1429 /* Read pfc statistic*/
1433 {
1434 /* Read pfc statistic */
1445 pfc_frames_received);
1446 }
1447 }
1448 /******************************************************************/
1449 /* MAC/PBF section */
1450 /******************************************************************/
1452 {
1454 /**
1455 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1456 * (a value of 49==0x31) and make sure that the AUTO poll is off
1457 */
1461 else
1465 EMAC_MDIO_MODE_CLOCK_CNT);
1468 else
1475 }
1477 {
1478 u32 port4mode_ovwr_val;
1479 /* Check 4-port override enabled */
1482 /* Return 4-port mode override value */
1484 }
1485 /* Return 4-port mode from input pin */
1487 }
1491 {
1492 /* reset and unreset the emac core */
1496 u32 val;
1497 u16 timeout;
1505 /* init emac - use read-modify-write */
1506 /* self clear reset */
1517 }
1518 timeout--;
1521 /* Set mac address */
1531 }
1534 u16 tx_pause_en,
1535 u8 enable)
1536 {
1540 enable);
1542 enable);
1545 }
1548 {
1555 /* Disable RX and TX */
1557 }
1561 {
1562 u32 val;
1565 /* Reset UMAC */
1575 /**
1576 * This register determines on which events the MAC will assert
1577 * error on the i/f to the NIG along w/ EOP.
1578 */
1580 /**
1581 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1582 * params->port*0x14, 0xfffff.
1583 */
1584 /* This register opens the gate for the UMAC despite its name */
1588 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1589 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1590 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1608 }
1618 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1628 /* Enable RX and TX */
1631 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1635 /* Remove SW Reset */
1638 /* Check loopback mode */
1643 /*
1644 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1645 * length used by the MAC receive logic to check frames.
1646 */
1652 }
1654 /* Define the XMAC mode */
1656 {
1660 /*
1661 * In 4-port mode, need to set the mode only once, so if XMAC is
1662 * already out of reset, it means the mode has already been set,
1663 * and it must not* reset the XMAC again, since it controls both
1664 * ports of the path
1665 */
1669 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1673 }
1675 /* Hard reset */
1677 MISC_REGISTERS_RESET_REG_2_XMAC);
1681 MISC_REGISTERS_RESET_REG_2_XMAC);
1685 /* Set the number of ports on the system side to up to 2 */
1688 /* Set the number of ports on the Warp Core to 10G */
1691 /* Set the number of ports on the system side to 1 */
1696 /* Set the number of ports on the Warp Core to 10G */
1701 /* Set the number of ports on the Warp Core to 20G */
1703 }
1704 }
1705 /* Soft reset */
1707 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1711 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1713 }
1716 {
1722 MISC_REGISTERS_RESET_REG_2_XMAC) {
1723 /*
1724 * Send an indication to change the state in the NIG back to XON
1725 * Clearing this bit enables the next set of this bit to get
1726 * rising edge
1727 */
1735 }
1736 }
1740 {
1749 /*
1750 * This register determines on which events the MAC will assert
1751 * error on the i/f to the NIG along w/ EOP.
1752 */
1754 /*
1755 * This register tells the NIG whether to send traffic to UMAC
1756 * or XMAC
1757 */
1760 /* Set Max packet size */
1763 /* CRC append for Tx packets */
1766 /* update PFC */
1769 /* Enable TX and RX */
1772 /* Check loopback mode */
1782 }
1786 {
1790 u32 val;
1794 /* Disable BMAC */
1798 /* enable emac and not bmac */
1801 /* ASIC */
1804 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1805 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1808 /* select the master lanes (out of 0-3) */
1810 /* select XGXS */
1815 /* select SerDes */
1817 }
1820 EMAC_RX_MODE_RESET);
1822 EMAC_TX_MODE_RESET);
1825 /* config GMII mode */
1829 /* pause enable/disable */
1831 EMAC_RX_MODE_FLOW_EN);
1835 EMAC_TX_MODE_FLOW_EN));
1837 FEATURE_CONFIG_PFC_ENABLED)) {
1840 EMAC_REG_EMAC_RX_MODE,
1841 EMAC_RX_MODE_FLOW_EN);
1845 EMAC_REG_EMAC_TX_MODE,
1847 EMAC_TX_MODE_FLOW_EN));
1850 EMAC_TX_MODE_FLOW_EN);
1851 }
1853 /* KEEP_VLAN_TAG, promiscuous */
1857 /*
1858 * Setting this bit causes MAC control frames (except for pause
1859 * frames) to be passed on for processing. This setting has no
1860 * affect on the operation of the pause frames. This bit effects
1861 * all packets regardless of RX Parser packet sorting logic.
1862 * Turn the PFC off to make sure we are in Xon state before
1863 * enabling it.
1864 */
1868 /* Enable PFC again */
1870 EMAC_REG_RX_PFC_MODE_RX_EN |
1871 EMAC_REG_RX_PFC_MODE_TX_EN |
1872 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1876 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1878 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1880 }
1883 /* Set Loopback */
1887 else
1891 /* enable emac */
1894 /* enable emac for jumbo packets */
1899 /* strip CRC */
1902 /* disable the NIG in/out to the bmac */
1907 /* enable the NIG in/out to the emac */
1911 FEATURE_CONFIG_PFC_ENABLED) ||
1922 }
1926 {
1930 NIG_REG_INGRESS_BMAC0_MEM;
1934 FEATURE_CONFIG_PFC_ENABLED)) &&
1936 /* Enable BigMAC to react on received Pause packets */
1942 /* tx control */
1945 FEATURE_CONFIG_PFC_ENABLED) &&
1951 }
1955 u8 is_lb)
1956 {
1957 /*
1958 * Set rx control: Strip CRC and enable BigMAC to relay
1959 * control packets to the system as well
1960 */
1964 NIG_REG_INGRESS_BMAC0_MEM;
1968 FEATURE_CONFIG_PFC_ENABLED)) &&
1970 /* Enable BigMAC to react on received Pause packets */
1977 /* Tx control */
1980 FEATURE_CONFIG_PFC_ENABLED) &&
1989 /* Enable PFC RX & TX & STATS and set 8 COS */
1999 /* Clear the force Xon */
2003 /* disable PFC RX & TX & STATS and set 8 COS */
2006 }
2010 /*
2011 * Set Time (based unit is 512 bit time) between automatic
2012 * re-sending of PP packets amd enable automatic re-send of
2013 * Per-Priroity Packet as long as pp_gen is asserted and
2014 * pp_disable is low.
2015 */
2025 /* mac control */
2030 }
2031 /* When PFC enabled, Pass pause frames towards the NIG. */
2038 }
2040 /* PFC BRB internal port configuration params */
2042 u32 pause_xoff;
2043 u32 pause_xon;
2044 u32 full_xoff;
2045 u32 full_xon;
2046 };
2049 u32 per_class_guaranty_mode;
2050 u32 lb_guarantied_hyst;
2051 u32 full_lb_xoff_th;
2052 u32 full_lb_xon_threshold;
2053 u32 lb_guarantied;
2054 u32 mac_0_class_t_guarantied;
2055 u32 mac_0_class_t_guarantied_hyst;
2056 u32 mac_1_class_t_guarantied;
2057 u32 mac_1_class_t_guarantied_hyst;
2058 };
2066 };
2070 {
2080 /* class0 defaults */
2082 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2084 DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2086 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2088 DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2089 /* pause able*/
2091 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2093 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2095 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2097 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2098 /* non pause able*/
2100 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2102 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2104 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2106 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2108 /* class0 defaults */
2110 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2112 DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2114 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2116 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2117 /* pause able */
2119 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2121 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2123 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2125 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2126 /* non pause able*/
2128 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2130 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2132 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2134 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2136 /* class0 defaults */
2138 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2140 DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2142 DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2144 DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2147 FLAGS_4_PORT_MODE) {
2149 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2151 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2153 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2155 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2156 /* non pause able*/
2158 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2160 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2162 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2164 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2167 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2169 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2171 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2173 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2174 /* non pause able*/
2176 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2178 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2180 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2182 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2183 }
2188 }
2192 struct bnx2x_pfc_brb_e3b0_val
2196 {
2202 FLAGS_4_PORT_MODE) {
2204 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2206 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2208 PFC_E3B0_4P_LB_GUART;
2210 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2212 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2214 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2216 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2219 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2221 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2223 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2225 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2227 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2231 /* nonpauseable= Lossy + pauseable = Lossless*/
2233 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2235 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2237 /* Lossless +Lossless*/
2239 PFC_E3B0_2P_PAUSE_LB_GUART;
2241 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2243 /* Lossy +Lossy*/
2245 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2247 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2248 }
2249 }
2254 DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2256 DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2258 DEFAULT_E3B0_LB_GUART;
2260 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2262 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2264 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2266 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2267 }
2268 }
2271 struct bnx2x_nig_brb_pfc_port_params
2273 {
2280 FEATURE_CONFIG_PFC_ENABLED;
2285 /* default - pause configuration */
2292 /* First COS */
2295 else
2299 /*
2300 * The number of free blocks below which the pause signal to class 0
2301 * of MAC #n is asserted. n=0,1
2302 */
2304 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2306 /*
2307 * The number of free blocks above which the pause signal to class 0
2308 * of MAC #n is de-asserted. n=0,1
2309 */
2312 /*
2313 * The number of free blocks below which the full signal to class 0
2314 * of MAC #n is asserted. n=0,1
2315 */
2318 /*
2319 * The number of free blocks above which the full signal to class 0
2320 * of MAC #n is de-asserted. n=0,1
2321 */
2326 /* Second COS */
2329 else
2333 /*
2334 * The number of free blocks below which the pause signal to
2335 * class 1 of MAC #n is asserted. n=0,1
2336 */
2338 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2341 /*
2342 * The number of free blocks above which the pause signal to
2343 * class 1 of MAC #n is de-asserted. n=0,1
2344 */
2346 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2348 /*
2349 * The number of free blocks below which the full signal to
2350 * class 1 of MAC #n is asserted. n=0,1
2351 */
2353 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2355 /*
2356 * The number of free blocks above which the full signal to
2357 * class 1 of MAC #n is de-asserted. n=0,1
2358 */
2360 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2365 params,
2367 pfc_params,
2368 pfc_enabled);
2373 /*
2374 * The hysteresis on the guarantied buffer space for the Lb
2375 * port before signaling XON.
2376 */
2380 /*
2381 * The number of free blocks below which the full signal to the
2382 * LB port is asserted.
2383 */
2386 /*
2387 * The number of free blocks above which the full signal to the
2388 * LB port is de-asserted.
2389 */
2392 /*
2393 * The number of blocks guarantied for the MAC #n port. n=0,1
2394 */
2396 /* The number of blocks guarantied for the LB port.*/
2400 /*
2401 * The number of blocks guarantied for the MAC #n port.
2402 */
2407 /*
2408 * The number of blocks guarantied for class #t in MAC0. t=0,1
2409 */
2414 /*
2415 * The hysteresis on the guarantied buffer space for class in
2416 * MAC0. t=0,1
2417 */
2423 /*
2424 * The number of blocks guarantied for class #t in MAC1.t=0,1
2425 */
2430 /*
2431 * The hysteresis on the guarantied buffer space for class #t
2432 * in MAC1. t=0,1
2433 */
2438 }
2441 }
2443 /******************************************************************************
2444 * Description:
2445 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2446 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2447 ******************************************************************************/
2449 u8 cos_entry,
2451 {
2457 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2458 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2462 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2463 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2467 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2468 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2485 }
2490 }
2492 {
2498 }
2503 {
2511 FEATURE_CONFIG_PFC_ENABLED;
2514 /*
2515 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2516 * MAC control frames (that are not pause packets)
2517 * will be forwarded to the XCM.
2518 */
2520 NIG_REG_LLH0_XCM_MASK);
2521 /*
2522 * nig params will override non PFC params, since it's possible to
2523 * do transition from PFC to SAFC
2524 */
2531 else
2534 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2546 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2548 }
2569 /* output enable for RX_XCM # IF */
2573 /* HW PFC TX enable */
2586 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2590 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2592 }
2594 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2595 pkt_priority_to_cos);
2596 }
2601 {
2602 /*
2603 * The PFC and pause are orthogonal to one another, meaning when
2604 * PFC is enabled, the pause are disabled, and when PFC is
2605 * disabled, pause are set according to the pause result.
2606 */
2607 u32 val;
2614 else
2619 /* update NIG params */
2622 /* update BRB params */
2641 }
2644 else
2649 FEATURE_CONFIG_PFC_ENABLED) ||
2653 }
2655 }
2660 u8 is_lb)
2661 {
2665 NIG_REG_INGRESS_BMAC0_MEM;
2667 u32 val;
2671 /* XGXS control */
2677 /* tx MAC SA */
2686 /* mac control */
2691 }
2696 /* set rx mtu */
2703 /* set tx mtu */
2708 /* set cnt max size */
2713 /* configure safc */
2720 }
2724 u8 is_lb)
2725 {
2729 NIG_REG_INGRESS_BMAC0_MEM;
2739 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2747 /* tx MAC SA */
2759 /* Configure SAFC */
2766 /* set rx mtu */
2772 /* set tx mtu */
2777 /* set cnt max size */
2785 }
2789 u8 is_lb)
2790 {
2794 u32 val;
2795 /* reset and unreset the BigMac */
2803 /* enable access for bmac registers */
2806 /* Enable BMAC according to BMAC type*/
2809 else
2816 FEATURE_CONFIG_PFC_ENABLED) ||
2828 }
2831 {
2833 NIG_REG_INGRESS_BMAC0_MEM;
2837 /* Only if the bmac is out of reset */
2840 nig_bmac_enable) {
2843 /* Clear Rx Enable bit in BMAC_CONTROL register */
2845 BIGMAC2_REGISTER_BMAC_CONTROL,
2849 BIGMAC2_REGISTER_BMAC_CONTROL,
2852 /* Clear Rx Enable bit in BMAC_CONTROL register */
2854 BIGMAC_REGISTER_BMAC_CONTROL,
2858 BIGMAC_REGISTER_BMAC_CONTROL,
2860 }
2862 }
2863 }
2866 u32 line_speed)
2867 {
2873 /* disable port */
2876 /* wait for init credit */
2885 count--;
2886 }
2892 }
2900 /* update threshold */
2902 /* update init credit */
2909 /* update threshold */
2911 /* update init credit */
2918 line_speed);
2920 }
2921 }
2926 /* probe the credit changes */
2931 /* enable port */
2934 }
2936 /**
2937 * bnx2x_get_emac_base - retrive emac base address
2938 *
2939 * @bp: driver handle
2940 * @mdc_mdio_access: access type
2941 * @port: port id
2942 *
2943 * This function selects the MDC/MDIO access (through emac0 or
2944 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2945 * phy has a default access mode, which could also be overridden
2946 * by nvram configuration. This parameter, whether this is the
2947 * default phy configuration, or the nvram overrun
2948 * configuration, is passed here as mdc_mdio_access and selects
2949 * the emac_base for the CL45 read/writes operations
2950 */
2953 {
2961 else
2967 else
2978 }
2981 }
2983 /******************************************************************/
2984 /* CL22 access functions */
2985 /******************************************************************/
2989 {
2991 u8 i;
2993 /* Switch to CL22 */
2998 /* address */
3000 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3001 EMAC_MDIO_COMM_START_BUSY);
3011 }
3012 }
3016 }
3019 }
3024 {
3026 u16 i;
3029 /* Switch to CL22 */
3034 /* address */
3036 EMAC_MDIO_COMM_COMMAND_READ_22 |
3037 EMAC_MDIO_COMM_START_BUSY);
3048 }
3049 }
3055 }
3058 }
3060 /******************************************************************/
3061 /* CL45 access functions */
3062 /******************************************************************/
3065 {
3066 u32 val;
3067 u16 i;
3071 EMAC_MDIO_STATUS_10MB);
3072 /* address */
3074 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3075 EMAC_MDIO_COMM_START_BUSY);
3085 }
3086 }
3093 /* data */
3095 EMAC_MDIO_COMM_COMMAND_READ_45 |
3096 EMAC_MDIO_COMM_START_BUSY);
3103 EMAC_REG_EMAC_MDIO_COMM);
3107 }
3108 }
3114 }
3115 }
3116 /* Work around for E3 A0 */
3120 u16 temp_val;
3122 }
3123 }
3127 EMAC_MDIO_STATUS_10MB);
3129 }
3133 {
3134 u32 tmp;
3135 u8 i;
3139 EMAC_MDIO_STATUS_10MB);
3141 /* address */
3144 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3145 EMAC_MDIO_COMM_START_BUSY);
3155 }
3156 }
3162 /* data */
3164 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3165 EMAC_MDIO_COMM_START_BUSY);
3172 EMAC_REG_EMAC_MDIO_COMM);
3176 }
3177 }
3182 }
3183 }
3184 /* Work around for E3 A0 */
3188 u16 temp_val;
3190 }
3191 }
3194 EMAC_MDIO_STATUS_10MB);
3196 }
3197 /******************************************************************/
3198 /* BSC access functions from E3 */
3199 /******************************************************************/
3201 {
3207 /* Read I2C output PINs */
3213 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3215 /* Read I2C output value */
3224 }
3228 u8 sl_devid,
3229 u16 sl_addr,
3230 u8 lc_addr,
3231 u8 xfer_cnt,
3233 {
3241 }
3245 xfer_cnt);
3247 }
3252 /* enable the engine */
3257 /* program slave device ID */
3261 /* start xfer with 0 byte to update the address pointer ???*/
3264 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3268 /* poll for completion */
3276 i);
3279 }
3280 }
3284 /* start xfer with read op */
3287 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3292 /* poll for completion */
3302 }
3303 }
3309 #ifdef __BIG_ENDIAN
3314 #endif
3315 }
3317 }
3321 {
3322 u16 val;
3325 }
3329 {
3330 u8 phy_index;
3331 /*
3332 * Probe for the phy according to the given phy_addr, and execute
3333 * the read request on it
3334 */
3340 }
3341 }
3343 }
3347 {
3348 u8 phy_index;
3349 /*
3350 * Probe for the phy according to the given phy_addr, and execute
3351 * the write request on it
3352 */
3358 }
3359 }
3361 }
3364 {
3376 /*figure out path swap value */
3380 else
3386 /*figure out port swap value */
3390 else
3399 /*figure out path swap value */
3400 path_swap_ovr =
3405 path_swap =
3407 }
3412 }
3414 }
3418 {
3419 u32 ser_lane;
3423 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3424 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3431 /*
3432 * In Dual-lane mode, two lanes are joined together,
3433 * so in order to configure them, the AER broadcast method is
3434 * used here.
3435 * 0x200 is the broadcast address for lanes 0,1
3436 * 0x201 is the broadcast address for lanes 2,3
3437 */
3442 else
3448 }
3450 /******************************************************************/
3451 /* Internal phy section */
3452 /******************************************************************/
3455 {
3458 /* Set Clause 22 */
3464 /* Set Clause 45 */
3466 }
3469 {
3470 u32 val;
3476 /* reset and unreset the SerDes/XGXS */
3484 DEFAULT_PHY_DEV_ADDR);
3485 }
3488 {
3490 u8 port;
3491 u32 val;
3497 /* reset and unreset the SerDes/XGXS */
3505 }
3509 {
3512 /**
3513 * resolve pause mode and advertisement Please refer to Table
3514 * 28B-3 of the 802.3ab-1999 spec
3515 */
3521 else
3523 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3539 }
3541 }
3545 {
3549 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3551 phy_index++) {
3559 }
3573 SPEED_AUTO_NEG)
3581 }
3582 }
3587 {
3588 u16 val;
3590 /* read modify write pause advertizing */
3595 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3598 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3599 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3601 }
3603 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3604 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3606 }
3609 }
3631 }
3636 }
3641 {
3645 u16 pause_result;
3647 /* read twice */
3664 MDIO_AN_DEVAD,
3667 MDIO_AN_DEVAD,
3669 }
3675 pause_result);
3677 }
3679 }
3680 /******************************************************************/
3681 /* Warpcore section */
3682 /******************************************************************/
3683 /* The init_internal_warpcore should mirror the xgxs,
3684 * i.e. reset the lane (if needed), set aer for the
3685 * init configuration, and set/clear SGMII flag. Internal
3686 * phy init is done purely in phy_init stage.
3687 */
3695 /* Disable Autoneg: re-enable it after adv is done. */
3699 /* Check adding advertisement for 1G KX */
3703 u16 sd_digital;
3706 /* Enable CL37 1G Parallel Detect */
3710 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3714 }
3718 /* Check adding advertisement for 10G KR */
3720 /* Enable 10G Parallel Detect */
3725 }
3727 /* Set Transmit PMD settings */
3735 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3738 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3741 /* Advertised speeds */
3745 /* Advertised and set FEC (Forward Error Correction) */
3747 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3749 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3751 /* Enable CL37 BAM */
3755 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3761 }
3763 /* Advertise pause */
3766 /*
3767 * Set KR Autoneg Work-Around flag for Warpcore version older than D108
3768 */
3774 }
3782 /* Over 1G - AN local device user page 1 */
3786 /* Enable Autoneg */
3790 }
3795 {
3797 u16 val;
3799 /* Disable Autoneg */
3821 /* Disable CL36 PCS Tx */
3825 /* Double Wide Single Data Rate @ pll rate */
3829 /* Leave cl72 training enable, needed for KR */
3831 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3834 /* Leave CL72 enabled */
3836 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3839 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3842 /* Set speed via PMA/PMD register */
3849 /*Enable encoded forced speed */
3853 /* Turn TX scramble payload only the 64/66 scrambler */
3857 /* Turn RX scramble payload only the 64/66 scrambler */
3861 /* set and clear loopback to cause a reset to 64/66 decoder */
3867 }
3871 u8 is_xfi)
3872 {
3875 /* Hold rxSeqStart */
3881 /* Hold tx_fifo_reset */
3887 /* Disable CL73 AN */
3890 /* Disable 100FX Enable and Auto-Detect */
3896 /* Disable 100FX Idle detect */
3902 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3908 /* Turn off auto-detect & fiber mode */
3912 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3915 /* Set filter_force_link, disable_false_link and parallel_detect */
3919 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3922 /* Set XFI / SFI */
3933 tx_driver_val =
3943 tx_driver_val =
3947 }
3951 /* Set Transmit PMD settings */
3954 MDIO_WC_REG_TX_FIR_TAP,
3958 tx_driver_val);
3960 /* Enable fiber mode, enable and invert sig_det */
3966 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3972 /* 10G XFI Full Duplex */
3976 /* Release tx_fifo_reset */
3982 /* Release rxSeqStart */
3987 }
3991 {
3993 }
3997 u16 lane)
3998 {
3999 /* Rx0 anaRxControl1G */
4003 /* Rx2 anaRxControl1G */
4031 /* Serdes Digital Misc1 */
4035 /* Serdes Digital4 Misc3 */
4039 /* Set Transmit PMD settings */
4041 MDIO_WC_REG_TX_FIR_TAP,
4045 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4051 }
4055 u8 fiber_mode,
4056 u8 always_autoneg)
4057 {
4061 /* Clear XFI clock comp in non-10G single lane mode. */
4068 /* SGMII Autoneg */
4072 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4092 }
4105 }
4107 /* SGMII Slave mode and disable signal detect */
4112 else
4116 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4117 digctrl_kx1);
4119 /* Turn off parallel detect */
4123 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4126 /* Re-enable parallel detect */
4128 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4131 /* Enable autodet */
4133 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4135 }
4139 u8 reset)
4140 {
4141 u16 val;
4142 /* Take lane out of reset after configuration is finished */
4147 else
4153 }
4154 /* Clear SFI/XFI link settings registers */
4157 u16 lane)
4158 {
4160 u16 val16;
4162 /* Set XFI clock comp as default. */
4194 }
4197 u32 chip_id,
4200 {
4201 u32 cfg_pin;
4208 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4209 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4211 /*
4212 * Should not happen. This function called upon interrupt
4213 * triggered by GPIO ( since EPIO can only generate interrupts
4214 * to MCP).
4215 * So if this function was called and none of the GPIOs was set,
4216 * it means the shit hit the fan.
4217 */
4222 cfg_pin);
4224 }
4231 }
4234 }
4238 {
4241 u32 gpio_val;
4248 /* Call the handling function in case module is detected */
4251 else
4253 }
4256 {
4266 }
4271 {
4273 u32 serdes_net_if;
4282 /* return if there is no link partner */
4286 }
4292 PORT_HW_CFG_NET_SERDES_IF_MASK);
4296 /* Do we get link yet? */
4300 /*10G KR*/
4312 /*reset the lane to see if link comes up.*/
4316 /* restart Autoneg */
4323 }
4328 }
4332 }
4337 {
4339 u32 serdes_net_if;
4340 u8 fiber_mode;
4345 PORT_HW_CFG_NET_SERDES_IF_MASK);
4363 /* Enable KR Auto Neg */
4369 }
4384 }
4386 params,
4387 fiber_mode,
4389 }
4403 }
4404 /* Issue Module detection */
4413 }
4416 /* Issue Module detection */
4425 }
4433 serdes_net_if);
4435 }
4436 }
4438 /* Take lane out of reset after configuration is finished */
4441 }
4445 u8 tx_en)
4446 {
4448 u32 cfg_pin;
4454 PORT_HW_CFG_TX_LASER_MASK;
4455 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4457 /* For 20G, the expected pin to be used is 3 pins after the current */
4462 }
4466 {
4468 u16 val16;
4472 /* Global register */
4475 /* Clear loopback settings (if any) */
4476 /* 10G & 20G */
4488 /* Update those 1-copy registers */
4491 /* Enable 1G MDIO (1-copy) */
4493 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4496 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4502 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4505 }
4509 {
4511 u16 val16;
4512 u32 lane;
4517 /* 10/100/1000 */
4519 /* Update those 1-copy registers */
4522 /* Enable 1G MDIO (1-copy) */
4524 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4527 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4529 /* Set 1G loopback based on lane (1-copy) */
4534 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4537 /* Switch back to 4-copy registers */
4540 /* 10G & 20G */
4551 }
4552 }
4557 {
4559 u8 link_10g_plus;
4569 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4572 /* fall thru */
4579 /* fall thru */
4587 /* fall thru */
4594 /* fall thru */
4607 }
4624 }
4629 /* anything 10 and over uses the bmac */
4635 else
4640 else
4642 }
4652 /* indicate no mac active */
4656 }
4657 }
4661 {
4665 /* Update PHY configuration */
4674 /* Sync media type */
4682 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4685 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4688 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4691 /* Sync AEU offset */
4698 /* Sync PFC status */
4701 FEATURE_CONFIG_PFC_ENABLED;
4702 else
4710 }
4714 {
4718 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4719 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4721 /* set the master_ln for AN */
4723 MDIO_REG_BANK_XGXS_BLOCK2,
4724 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4728 MDIO_REG_BANK_XGXS_BLOCK2 ,
4729 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4731 }
4735 u8 set_serdes)
4736 {
4738 u16 mii_control;
4739 u16 i;
4741 MDIO_REG_BANK_COMBO_IEEE0,
4744 /* reset the unicore */
4746 MDIO_REG_BANK_COMBO_IEEE0,
4747 MDIO_COMBO_IEEE0_MII_CONTROL,
4749 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4753 /* wait for the reset to self clear */
4757 /* the reset erased the previous bank value */
4759 MDIO_REG_BANK_COMBO_IEEE0,
4760 MDIO_COMBO_IEEE0_MII_CONTROL,
4766 }
4767 }
4775 }
4779 {
4781 /*
4782 * Each two bits represents a lane number:
4783 * No swap is 0123 => 0x1b no need to enable the swap
4784 */
4788 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4789 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4791 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4792 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4796 MDIO_REG_BANK_XGXS_BLOCK2,
4797 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4799 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4800 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4803 MDIO_REG_BANK_XGXS_BLOCK2,
4805 }
4809 MDIO_REG_BANK_XGXS_BLOCK2,
4810 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4812 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4815 MDIO_REG_BANK_XGXS_BLOCK2,
4817 }
4818 }
4822 {
4824 u16 control2;
4826 MDIO_REG_BANK_SERDES_DIGITAL,
4827 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4831 else
4836 MDIO_REG_BANK_SERDES_DIGITAL,
4837 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4838 control2);
4842 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4846 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4847 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4848 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4851 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4852 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4856 control2 |=
4857 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4860 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4861 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4862 control2);
4864 /* Disable parallel detection of HiG */
4866 MDIO_REG_BANK_XGXS_BLOCK2,
4867 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4868 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4869 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4870 }
4871 }
4876 u8 enable_cl73)
4877 {
4879 u16 reg_val;
4881 /* CL37 Autoneg */
4883 MDIO_REG_BANK_COMBO_IEEE0,
4886 /* CL37 Autoneg Enabled */
4891 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4894 MDIO_REG_BANK_COMBO_IEEE0,
4897 /* Enable/Disable Autodetection */
4900 MDIO_REG_BANK_SERDES_DIGITAL,
4903 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4907 else
4911 MDIO_REG_BANK_SERDES_DIGITAL,
4914 /* Enable TetonII and BAM autoneg */
4916 MDIO_REG_BANK_BAM_NEXT_PAGE,
4917 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4920 /* Enable BAM aneg Mode and TetonII aneg Mode */
4922 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4924 /* TetonII and BAM Autoneg Disabled */
4926 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4927 }
4929 MDIO_REG_BANK_BAM_NEXT_PAGE,
4930 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4931 reg_val);
4934 /* Enable Cl73 FSM status bits */
4936 MDIO_REG_BANK_CL73_USERB0,
4937 MDIO_CL73_USERB0_CL73_UCTRL,
4940 /* Enable BAM Station Manager*/
4942 MDIO_REG_BANK_CL73_USERB0,
4943 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4944 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4945 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4946 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4948 /* Advertise CL73 link speeds */
4950 MDIO_REG_BANK_CL73_IEEEB1,
4951 MDIO_CL73_IEEEB1_AN_ADV2,
4954 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4957 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4961 MDIO_REG_BANK_CL73_IEEEB1,
4962 MDIO_CL73_IEEEB1_AN_ADV2,
4963 reg_val);
4965 /* CL73 Autoneg Enabled */
4972 MDIO_REG_BANK_CL73_IEEEB0,
4974 }
4976 /* program SerDes, forced speed */
4980 {
4982 u16 reg_val;
4984 /* program duplex, disable autoneg and sgmii*/
4986 MDIO_REG_BANK_COMBO_IEEE0,
4989 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4990 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4994 MDIO_REG_BANK_COMBO_IEEE0,
4997 /*
4998 * program speed
4999 * - needed only if the speed is greater than 1G (2.5G or 10G)
5000 */
5002 MDIO_REG_BANK_SERDES_DIGITAL,
5004 /* clearing the speed value before setting the right speed */
5008 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5015 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5017 reg_val |=
5018 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5019 }
5022 MDIO_REG_BANK_SERDES_DIGITAL,
5025 }
5029 {
5033 /* configure the 48 bits for BAM AN */
5035 /* set extended capabilities */
5041 MDIO_REG_BANK_OVER_1G,
5045 MDIO_REG_BANK_OVER_1G,
5047 }
5051 u16 ieee_fc)
5052 {
5054 u16 val;
5055 /* for AN, we are always publishing full duplex */
5058 MDIO_REG_BANK_COMBO_IEEE0,
5061 MDIO_REG_BANK_CL73_IEEEB1,
5066 MDIO_REG_BANK_CL73_IEEEB1,
5068 }
5072 u8 enable_cl73)
5073 {
5075 u16 mii_control;
5078 /* Enable and restart BAM/CL37 aneg */
5082 MDIO_REG_BANK_CL73_IEEEB0,
5083 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5087 MDIO_REG_BANK_CL73_IEEEB0,
5088 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5090 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5091 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5095 MDIO_REG_BANK_COMBO_IEEE0,
5096 MDIO_COMBO_IEEE0_MII_CONTROL,
5100 mii_control);
5102 MDIO_REG_BANK_COMBO_IEEE0,
5103 MDIO_COMBO_IEEE0_MII_CONTROL,
5105 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5106 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5107 }
5108 }
5113 {
5115 u16 control1;
5117 /* in SGMII mode, the unicore is always slave */
5120 MDIO_REG_BANK_SERDES_DIGITAL,
5121 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5124 /* set sgmii mode (and not fiber) */
5126 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5127 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5129 MDIO_REG_BANK_SERDES_DIGITAL,
5130 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5131 control1);
5133 /* if forced speed */
5135 /* set speed, disable autoneg */
5136 u16 mii_control;
5139 MDIO_REG_BANK_COMBO_IEEE0,
5140 MDIO_COMBO_IEEE0_MII_CONTROL,
5143 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5144 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5148 mii_control |=
5149 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5152 mii_control |=
5153 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5156 /* there is nothing to set for 10M */
5159 /* invalid speed for SGMII */
5163 }
5165 /* setting the full duplex */
5167 mii_control |=
5168 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5170 MDIO_REG_BANK_COMBO_IEEE0,
5171 MDIO_COMBO_IEEE0_MII_CONTROL,
5172 mii_control);
5175 /* enable and restart AN */
5177 }
5178 }
5181 /*
5182 * link management
5183 */
5187 {
5193 MDIO_REG_BANK_SERDES_DIGITAL,
5194 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5197 MDIO_REG_BANK_SERDES_DIGITAL,
5198 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5204 }
5207 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5208 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5215 }
5217 }
5222 u32 gp_status)
5223 {
5227 u16 pause_result;
5231 /* resolve from gp_status in case of AN complete and not sgmii */
5241 }
5244 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5246 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5249 MDIO_REG_BANK_CL73_IEEEB1,
5250 MDIO_CL73_IEEEB1_AN_ADV1,
5253 MDIO_REG_BANK_CL73_IEEEB1,
5254 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5257 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5260 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5263 pause_result);
5266 MDIO_REG_BANK_COMBO_IEEE0,
5267 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5270 MDIO_REG_BANK_COMBO_IEEE0,
5271 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5278 pause_result);
5279 }
5281 }
5283 }
5287 {
5291 /* Step 1: Make sure signal is detected */
5293 MDIO_REG_BANK_RX0,
5294 MDIO_RX0_RX_STATUS,
5301 MDIO_REG_BANK_CL73_IEEEB0,
5302 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5303 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5305 }
5306 /* Step 2: Check CL73 state machine */
5308 MDIO_REG_BANK_CL73_USERB0,
5309 MDIO_CL73_USERB0_CL73_USTAT1,
5313 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5315 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5319 }
5320 /*
5321 * Step 3: Check CL37 Message Pages received to indicate LP
5322 * supports only CL37
5323 */
5325 MDIO_REG_BANK_REMOTE_PHY,
5326 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5330 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5332 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5335 cl37_fsm_received);
5337 }
5338 /*
5339 * The combined cl37/cl73 fsm state information indicating that
5340 * we are connected to a device which does not support cl73, but
5341 * does support cl37 BAM. In this case we disable cl73 and
5342 * restart cl37 auto-neg
5343 */
5345 /* Disable CL73 */
5347 MDIO_REG_BANK_CL73_IEEEB0,
5348 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5350 /* Restart CL37 autoneg */
5353 }
5358 u32 gp_status)
5359 {
5362 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5366 LINK_STATUS_PARALLEL_DETECTION_USED;
5367 }
5371 u16 is_link_up,
5372 u16 speed_mask,
5373 u16 is_duplex)
5374 {
5389 else
5397 else
5406 else
5414 else
5422 speed_mask);
5441 speed_mask);
5443 }
5452 }
5456 }
5461 {
5467 /* Read gp_status */
5469 MDIO_REG_BANK_GP_STATUS,
5470 MDIO_GP_STATUS_TOP_AN_STATUS1,
5480 duplex);
5489 gp_status);
5490 }
5494 /* Check signal is detected */
5496 }
5497 }
5502 }
5507 {
5509 u8 lane;
5513 /* Read gp_status */
5515 u16 temp_link_up;
5529 /* Check for either KR or generic link up. */
5536 /* Check Autoneg complete */
5538 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5542 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5544 /* Check parallel detect used */
5546 MDIO_WC_REG_PAR_DET_10G_STATUS,
5550 LINK_STATUS_PARALLEL_DETECTION_USED;
5551 }
5553 }
5554 }
5562 }
5571 duplex);
5576 }
5578 {
5581 u16 lp_up2;
5582 u16 tx_driver;
5583 u16 bank;
5585 /* read precomp */
5587 MDIO_REG_BANK_OVER_1G,
5590 /* bits [10:7] at lp_up2, positioned at [15:12] */
5592 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5593 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5601 bank,
5604 /* replace tx_driver bits [15:12] */
5610 bank,
5612 }
5613 }
5614 }
5618 {
5625 EMAC_REG_EMAC_MODE,
5627 EMAC_MODE_PORT_MII_10M |
5628 EMAC_MODE_HALF_DUPLEX));
5647 /* 10G not valid for EMAC */
5651 }
5657 mode);
5661 }
5665 {
5673 bank,
5674 MDIO_RX0_RX_EQ_BOOST,
5676 }
5681 bank,
5682 MDIO_TX0_TX_DRIVER,
5684 }
5685 }
5690 {
5697 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5700 /* forced speed requested? */
5706 /* disable autoneg */
5709 /* program speed and duplex */
5715 /* AN enabled */
5718 /* program duplex & pause advertisement (for aneg) */
5722 /* enable autoneg */
5725 /* enable and restart AN */
5727 }
5733 }
5734 }
5739 {
5747 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5749 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5752 else
5761 /* reset the SerDes and wait for reset bit return low */
5766 /* setting the masterLn_def again after the reset */
5770 }
5773 }
5778 {
5780 /* Wait for soft reset to get cleared up to 1 sec */
5785 else
5787 MDIO_PMA_DEVAD,
5792 }
5800 }
5803 {
5805 u32 mask;
5808 /* Setting the status to report on link up for either XGXS or SerDes */
5815 NIG_MASK_XGXS0_LINK_STATUS);
5819 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5822 }
5829 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5832 }
5833 }
5836 mask);
5848 }
5851 u8 exp_mi_int)
5852 {
5855 /*
5856 * Disable the MI INT ( external phy int ) by writing 1 to the
5857 * status register. Link down indication is high-active-signal,
5858 * so in this case we need to write the status to clear the XOR
5859 */
5860 /* Read Latched signals */
5864 /* Handle only those with latched-signal=up.*/
5867 NIG_REG_STATUS_INTERRUPT_PORT0
5869 NIG_STATUS_EMAC0_MI_INT);
5870 else
5872 NIG_REG_STATUS_INTERRUPT_PORT0
5874 NIG_STATUS_EMAC0_MI_INT);
5878 /* For all latched-signal=up : Re-Arm Latch signals */
5881 }
5882 /* For all latched-signal=up,Write original_signal to status */
5883 }
5887 {
5890 u32 mask;
5891 /*
5892 * First reset all status we assume only one line will be
5893 * change at a time
5894 */
5897 NIG_STATUS_XGXS0_LINK_STATUS |
5898 NIG_STATUS_SERDES0_LINK_STATUS));
5906 /*
5907 * Disable the link interrupt by writing 1 to
5908 * the relevant lane in the status register
5909 */
5910 u32 ser_lane =
5912 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5913 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5915 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5918 }
5920 mask);
5923 mask);
5924 }
5925 }
5928 {
5932 u8 digit;
5935 /* Need more than 10chars for this format */
5939 }
5949 else
5952 str_ptr++;
5957 str_ptr++;
5960 }
5961 }
5963 }
5967 {
5971 }
5975 {
5985 /* Extract first external phy*/
5991 ver_p,
5994 }
6000 ver_p++;
6001 remain_len--;
6003 spirom_ver,
6004 ver_p,
6007 }
6008 }
6011 }
6015 {
6025 /* change the uni_phy_addr in the nig */
6031 }
6045 /* set aer mmd back */
6049 /* and md_devad */
6051 md_devad);
6052 }
6054 u16 mii_ctrl;
6063 mii_ctrl |
6064 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6065 }
6066 }
6070 {
6074 u8 phy_idx;
6075 u32 tmp;
6081 /* In case */
6086 }
6087 }
6094 SHARED_HW_CFG_LED_MAC1);
6098 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6103 }
6107 /*
6108 * For all other phys, OPER mode is same as ON, so in case
6109 * link is down, do nothing
6110 */
6115 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6117 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6119 /*
6120 * This is a work-around for E2+8727 Configurations
6121 */
6130 /*
6131 * return here without enabling traffic
6132 * LED blink and setting rate in ON mode.
6133 * In oper mode, enabling LED blink
6134 * and setting rate is needed.
6135 */
6138 }
6140 /*
6141 * This is a work-around for HW issue found when link
6142 * is up in CL73
6143 */
6153 else
6155 hw_led_mode);
6157 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6164 hw_led_mode);
6167 /* Set blinking rate to ~15.9Hz */
6170 LED_BLINK_RATE_VAL_E3);
6171 else
6173 LED_BLINK_RATE_VAL_E1X_E2);
6177 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6182 }
6189 /*
6190 * On Everest 1 Ax chip versions for speeds less than
6191 * 10G LED scheme is different
6192 */
6199 }
6205 mode);
6207 }
6210 }
6212 /*
6213 * This function comes to reflect the actual link state read DIRECTLY from the
6214 * HW
6215 */
6217 u8 is_serdes)
6218 {
6226 u16 link_up;
6229 /* Check 20G link */
6236 /* Check 10G link and below*/
6239 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6244 }
6249 MDIO_REG_BANK_GP_STATUS,
6250 MDIO_GP_STATUS_TOP_AN_STATUS1,
6252 /* link is up only if both local phy and external phy are up */
6255 }
6256 /* In XGXS loopback mode, do not check external PHY */
6262 /* No external PHY */
6271 phy_index++) {
6273 ETH_PHY_SFP_FIBER) ||
6275 ETH_PHY_XFP_FIBER) ||
6277 ETH_PHY_DA_TWINAX));
6282 ext_phy_link_up |=
6286 }
6287 }
6289 }
6293 }
6297 {
6301 /*
6302 * In case of external phy existence, the line speed would be the
6303 * line speed linked up by the external phy. In case it is direct
6304 * only, then the line_speed during initialization will be
6305 * equal to the req_line_speed
6306 */
6309 /*
6310 * Initialize the internal phy in case this is a direct board
6311 * (no external phys), or this board has external phy which requires
6312 * to first.
6313 */
6316 /* init ext phy and enable link state int */
6330 params,
6331 vars);
6332 }
6334 /* Init external phy*/
6337 SUPPORTED_FIBRE)
6341 phy_index++) {
6342 /*
6343 * No need to initialize second phy in case of first
6344 * phy only selection. In case of second phy, we do
6345 * need to initialize the first phy, since they are
6346 * connected.
6347 */
6349 SUPPORTED_FIBRE)
6354 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6358 }
6362 }
6363 }
6364 /* Reset the interrupt indication after phy was initialized */
6368 NIG_STATUS_XGXS0_LINK_STATUS |
6369 NIG_STATUS_SERDES0_LINK_STATUS |
6370 NIG_MASK_MI_INT));
6373 }
6377 {
6378 /* reset the SerDes/XGXS */
6381 }
6385 {
6387 u8 gpio_port;
6388 /* HW reset */
6391 else
6394 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6395 gpio_port);
6397 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6398 gpio_port);
6400 }
6404 {
6411 /* indicate no mac active */
6414 /* update shared memory */
6416 LINK_STATUS_LINK_UP |
6417 LINK_STATUS_PHYSICAL_LINK_FLAG |
6418 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6419 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6420 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6421 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6425 /* activate nig drain */
6428 /* disable emac */
6433 /* reset BigMac/Xmac */
6438 MISC_REGISTERS_RESET_REG_2_CLEAR,
6440 }
6444 }
6447 }
6451 u8 link_10g)
6452 {
6458 LINK_STATUS_PHYSICAL_LINK_FLAG);
6463 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6467 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6476 }
6481 }
6491 }
6499 /* AN complete? */
6501 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6505 }
6506 }
6508 /* PBF - link up */
6513 /* disable drain */
6516 /* update shared memory */
6520 }
6521 /*
6522 * The bnx2x_link_update function should be called upon link
6523 * interrupt.
6524 * Link is considered up as follows:
6525 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6526 * to be up
6527 * - SINGLE_MEDIA - The link between the 577xx and the external
6528 * phy (XGXS) need to up as well as the external link of the
6529 * phy (PHY_EXT1)
6530 * - DUAL_MEDIA - The link between the 577xx and the first
6531 * external phy needs to be up, and at least one of the 2
6532 * external phy link must be up.
6533 */
6535 {
6547 phy_index++) {
6555 }
6568 is_mi_int,
6575 /* disable emac */
6579 /*
6580 * Step 1:
6581 * Check external link change only for external phys, and apply
6582 * priority selection between them in case the link on both phys
6583 * is up. Note that instead of the common vars, a temporary
6584 * vars argument is used since each phy may have different link/
6585 * speed/duplex result
6586 */
6588 phy_index++) {
6592 /* Read link status and params of this ext phy */
6597 phy_index);
6600 phy_index);
6602 }
6611 /*
6612 * In this option, the first PHY makes sure to pass the
6613 * traffic through itself only.
6614 * Its not clear how to reset the link on the second phy
6615 */
6619 /*
6620 * In this option, the first PHY makes sure to pass the
6621 * traffic through the second PHY.
6622 */
6626 /*
6627 * Link indication on both PHYs with the following cases
6628 * is invalid:
6629 * - FIRST_PHY means that second phy wasn't initialized,
6630 * hence its link is expected to be down
6631 * - SECOND_PHY means that first phy should not be able
6632 * to link up by itself (using configuration)
6633 * - DEFAULT should be overriden during initialiazation
6634 */
6640 }
6641 }
6642 }
6644 /*
6645 * Step 2:
6646 * Read the status of the internal phy. In case of
6647 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6648 * otherwise this is the link between the 577xx and the first
6649 * external phy
6650 */
6655 /*
6656 * The INT_PHY flow control reside in the vars. This include the
6657 * case where the speed or flow control are not set to AUTO.
6658 * Otherwise, the active external phy flow control result is set
6659 * to the vars. The ext_phy_line_speed is needed to check if the
6660 * speed is different between the internal phy and external phy.
6661 * This case may be result of intermediate link speed change.
6662 */
6665 /*
6666 * Link speed is taken from the XGXS. AN and FC result from
6667 * the external phy.
6668 */
6671 /*
6672 * if active_external_phy is first PHY and link is up - disable
6673 * disable TX on second external PHY
6674 */
6682 }
6683 }
6688 SUPPORTED_FIBRE)
6690 else
6693 active_external_phy);
6694 }
6697 phy_index++) {
6699 FLAGS_REARM_LATCH_SIGNAL) {
6701 phy_index ==
6702 active_external_phy);
6704 }
6705 }
6709 /*
6710 * Upon link speed change set the NIG into drain mode. Comes to
6711 * deals with possible FIFO glitch due to clk change when speed
6712 * is decreased without link down indicator
6713 */
6719 " different than the external"
6721 ext_phy_line_speed);
6727 }
6728 }
6730 /* anything 10 and over uses the bmac */
6735 /*
6736 * In case external phy link is up, and internal link is down
6737 * (not initialized yet probably after link initialization, it
6738 * needs to be initialized.
6739 * Note that after link down-up as result of cable plug, the xgxs
6740 * link would probably become up again without the need
6741 * initialize it
6742 */
6748 FLAGS_INIT_XGXS_FIRST);
6750 FLAGS_INIT_XGXS_FIRST)
6755 else
6761 vars);
6762 }
6763 }
6764 /*
6765 * Link is up only if both local phy and external phy (in case of
6766 * non-direct board) are up and no fault detected on active PHY.
6767 */
6775 else
6779 }
6781 /*****************************************************************************/
6782 /* External Phy section */
6783 /*****************************************************************************/
6785 {
6791 }
6795 {
6801 }
6805 u8 port)
6806 {
6815 }
6820 {
6821 u16 val;
6823 MDIO_AN_DEVAD,
6826 MDIO_AN_DEVAD,
6832 }
6834 /******************************************************************/
6835 /* common BCM8073/BCM8727 PHY SECTION */
6836 /******************************************************************/
6840 {
6846 }
6850 u16 pause_result;
6854 MDIO_AN_DEVAD,
6858 MDIO_AN_DEVAD,
6867 pause_result);
6868 }
6869 }
6872 u8 port)
6873 {
6878 /* Boot port from external ROM */
6879 /* EDC grst */
6881 MDIO_PMA_DEVAD,
6882 MDIO_PMA_REG_GEN_CTRL,
6885 /* ucode reboot and rst */
6887 MDIO_PMA_DEVAD,
6888 MDIO_PMA_REG_GEN_CTRL,
6892 MDIO_PMA_DEVAD,
6895 /* Reset internal microprocessor */
6897 MDIO_PMA_DEVAD,
6898 MDIO_PMA_REG_GEN_CTRL,
6899 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6901 /* Release srst bit */
6903 MDIO_PMA_DEVAD,
6904 MDIO_PMA_REG_GEN_CTRL,
6905 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6907 /* Delay 100ms per the PHY specifications */
6910 /* 8073 sometimes taking longer to download */
6912 count++;
6915 "bnx2x_8073_8727_external_rom_boot port %x:"
6920 }
6923 MDIO_PMA_DEVAD,
6926 MDIO_PMA_DEVAD,
6932 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6934 /* Clear ser_boot_ctl bit */
6936 MDIO_PMA_DEVAD,
6941 "bnx2x_8073_8727_external_rom_boot port %x:"
6946 }
6948 /******************************************************************/
6949 /* BCM8073 PHY SECTION */
6950 /******************************************************************/
6952 {
6953 /* This is only required for 8073A1, version 102 only */
6954 u16 val;
6956 /* Read 8073 HW revision*/
6958 MDIO_PMA_DEVAD,
6962 /* No need to workaround in 8073 A1 */
6964 }
6967 MDIO_PMA_DEVAD,
6970 /* SNR should be applied only for version 0x102 */
6975 }
6978 {
6982 MDIO_PMA_DEVAD,
6986 /* No need to workaround in 8073 A1 */
6988 }
6989 /* XAUI workaround in 8073 A0: */
6991 /*
6992 * After loading the boot ROM and restarting Autoneg, poll
6993 * Dev1, Reg $C820:
6994 */
6998 MDIO_PMA_DEVAD,
6999 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7001 /*
7002 * If bit [14] = 0 or bit [13] = 0, continue on with
7003 * system initialization (XAUI work-around not required, as
7004 * these bits indicate 2.5G or 1G link up).
7005 */
7011 /*
7012 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7013 * MSB (bit15) goes to 1 (indicating that the XAUI
7014 * workaround has completed), then continue on with
7015 * system initialization.
7016 */
7019 MDIO_PMA_DEVAD,
7025 }
7027 }
7029 }
7031 }
7034 }
7037 {
7038 /* Force KR or KX */
7047 }
7052 {
7053 u16 cl37_val;
7059 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7062 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7063 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7065 }
7067 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7068 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7070 }
7072 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7073 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7075 }
7082 }
7087 {
7090 u8 gpio_port;
7095 else
7097 /* Restore normal power mode*/
7104 /* enable LASI */
7120 /* Swap polarity if required - Must be done only in non-1G mode */
7122 /* Configure the 8073 to swap _P and _N of the KR lines */
7124 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7126 MDIO_PMA_DEVAD,
7129 MDIO_PMA_DEVAD,
7130 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7132 }
7135 /* Enable CL37 BAM */
7139 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7142 MDIO_AN_DEVAD,
7145 MDIO_AN_DEVAD,
7148 }
7156 }
7162 /*
7163 * Note that 2.5G works only when used with 1G
7164 * advertisement
7165 */
7171 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7174 /* Note that 2.5G works only when used with 1G advertisement */
7177 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7180 }
7188 u16 phy_ver;
7189 /* Allow 2.5G for A1 and above */
7196 else
7201 }
7204 /* Add support for CL37 (passive mode) II */
7211 /* Add support for CL37 (passive mode) III */
7214 /*
7215 * The SNR will improve about 2db by changing BW and FEE main
7216 * tap. Rest commands are executed after link is up
7217 * Change FFE main cursor to 5 in EDC register
7218 */
7224 /* Enable FEC (Forware Error Correction) Request in the AN */
7231 /* Restart autoneg */
7237 }
7242 {
7254 /* clear the interrupt LASI status register */
7260 /* Clear MSG-OUT */
7264 /* Check the LASI */
7270 /* Check the link status */
7286 }
7292 /* Check the link status on 1.1.2 */
7302 /*
7303 * The SNR will improve about 2dbby changing the BW and FEE main
7304 * tap. The 1st write to change FFE main tap is set before
7305 * restart AN. Change PLL Bandwidth in EDC register
7306 */
7311 /* Change CDR Bandwidth in EDC register */
7315 }
7320 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7340 }
7343 /* Swap polarity if required */
7345 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7346 /* Configure the 8073 to swap P and N of the KR lines */
7348 MDIO_XS_DEVAD,
7350 /*
7351 * Set bit 3 to invert Rx in 1G mode and clear this bit
7352 * when it`s in 10G mode.
7353 */
7362 MDIO_XS_DEVAD,
7363 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7364 val1);
7365 }
7369 }
7371 }
7375 {
7377 u8 gpio_port;
7380 else
7383 gpio_port);
7385 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7386 gpio_port);
7387 }
7389 /******************************************************************/
7390 /* BCM8705 PHY SECTION */
7391 /******************************************************************/
7395 {
7398 /* Restore normal power mode*/
7401 /* HW reset */
7414 /* BCM8705 doesn't have microcode, hence the 0 */
7417 }
7422 {
7448 }
7450 }
7452 /******************************************************************/
7453 /* SFP+ module Section */
7454 /******************************************************************/
7457 u8 pmd_dis)
7458 {
7460 /*
7461 * Disable transmitter only for bootcodes which can enable it afterwards
7462 * (for D3 link)
7463 */
7466 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7471 }
7475 MDIO_PMA_DEVAD,
7477 }
7480 {
7481 u8 gpio_port;
7486 else
7491 }
7495 u8 tx_en)
7496 {
7497 u16 val;
7500 u32 tx_en_mode;
7502 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7506 PORT_HW_CFG_TX_LASER_MASK;
7513 MDIO_PMA_DEVAD,
7514 MDIO_PMA_REG_PHY_IDENTIFIER,
7519 else
7523 MDIO_PMA_DEVAD,
7524 MDIO_PMA_REG_PHY_IDENTIFIER,
7525 val);
7531 {
7532 u16 gpio_pin;
7536 else
7543 }
7547 }
7548 }
7552 u8 tx_en)
7553 {
7558 else
7560 }
7565 {
7568 u16 i;
7573 }
7574 /* Set the read command byte count */
7579 /* Set the read command address */
7582 addr);
7584 /* Activate read command */
7589 /* Wait up to 500us for command complete status */
7592 MDIO_PMA_DEVAD,
7595 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7598 }
7601 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7606 }
7608 /* Read the buffer */
7611 MDIO_PMA_DEVAD,
7614 }
7618 MDIO_PMA_DEVAD,
7621 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7624 }
7626 }
7632 {
7636 u16 addr32;
7638 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7639 " addr %d, cnt %d\n",
7640 addr, byte_cnt);*/
7645 }
7647 /* 4 byte aligned address */
7651 data_array);
7657 j++;
7658 }
7659 }
7662 }
7667 {
7675 }
7677 /* Need to read from 1.8000 to clear it */
7679 MDIO_PMA_DEVAD,
7680 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7683 /* Set the read command byte count */
7685 MDIO_PMA_DEVAD,
7686 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7689 /* Set the read command address */
7691 MDIO_PMA_DEVAD,
7692 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7693 addr);
7694 /* Set the destination address */
7696 MDIO_PMA_DEVAD,
7698 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7700 /* Activate read command */
7702 MDIO_PMA_DEVAD,
7703 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7705 /*
7706 * Wait appropriate time for two-wire command to finish before
7707 * polling the status register
7708 */
7711 /* Wait up to 500us for command complete status */
7714 MDIO_PMA_DEVAD,
7717 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7720 }
7723 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7728 }
7730 /* Read the buffer */
7733 MDIO_PMA_DEVAD,
7736 }
7740 MDIO_PMA_DEVAD,
7743 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7746 }
7749 }
7754 {
7770 }
7772 }
7777 {
7784 /* First check for copper cable */
7786 params,
7787 SFP_EEPROM_CON_TYPE_ADDR,
7792 }
7796 {
7797 u8 copper_module_type;
7799 /*
7800 * Check if its active cable (includes SFP+ module)
7801 * of passive cable
7802 */
7804 params,
7805 SFP_EEPROM_FC_TX_TECH_ADDR,
7809 "Failed to read copper-cable-type"
7812 }
7815 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7819 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7823 EDC_MODE_PASSIVE_DAC;
7827 copper_module_type);
7829 }
7831 }
7839 val);
7841 }
7846 /* Update media type for non-PMF sync */
7852 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7855 }
7856 }
7861 params,
7862 SFP_EEPROM_OPTIONS_ADDR,
7863 SFP_EEPROM_OPTIONS_SIZE,
7868 }
7871 else
7873 }
7876 }
7877 /*
7878 * This function read the relevant field from the module (SFP+), and verify it
7879 * is compliant with this board
7880 */
7883 {
7894 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7897 }
7900 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7901 /* Use specific phy request */
7904 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7905 /* Use first phy request only in case of non-dual media*/
7910 }
7913 /* No support in OPT MDL detection */
7917 }
7924 }
7926 /* format the warning message */
7928 params,
7929 SFP_EEPROM_VENDOR_NAME_ADDR,
7930 SFP_EEPROM_VENDOR_NAME_SIZE,
7933 else
7936 params,
7937 SFP_EEPROM_PART_NO_ADDR,
7938 SFP_EEPROM_PART_NO_SIZE,
7941 else
7949 }
7954 {
7955 u8 val;
7957 u16 timeout;
7958 /*
7959 * Initialization time after hot-plug may take up to 300ms for
7960 * some phys type ( e.g. JDSU )
7961 */
7970 }
7972 }
7974 }
7978 u8 is_power_up) {
7979 /* Make sure GPIOs are not using for LED mode */
7980 u16 val;
7981 /*
7982 * In the GPIO register, bit 4 is use to determine if the GPIOs are
7983 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7984 * output
7985 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7986 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7987 * where the 1st bit is the over-current(only input), and 2nd bit is
7988 * for power( only output )
7989 *
7990 * In case of NOC feature is disabled and power is up, set GPIO control
7991 * as input to enable listening of over-current indication
7992 */
7997 else
7998 /*
7999 * Set GPIO control to OUTPUT, and set the power bit
8000 * to according to the is_power_up
8001 */
8005 MDIO_PMA_DEVAD,
8006 MDIO_PMA_REG_8727_GPIO_CTRL,
8007 val);
8008 }
8012 u16 edc_mode)
8013 {
8014 u16 cur_limiting_mode;
8017 MDIO_PMA_DEVAD,
8018 MDIO_PMA_REG_ROM_VER2,
8021 cur_limiting_mode);
8026 MDIO_PMA_DEVAD,
8027 MDIO_PMA_REG_ROM_VER2,
8028 EDC_MODE_LIMITING);
8033 /*
8034 * Changing to LRM mode takes quite few seconds. So do it only
8035 * if current mode is limiting (default is LRM)
8036 */
8041 MDIO_PMA_DEVAD,
8042 MDIO_PMA_REG_LRM_MODE,
8045 MDIO_PMA_DEVAD,
8046 MDIO_PMA_REG_ROM_VER2,
8049 MDIO_PMA_DEVAD,
8050 MDIO_PMA_REG_MISC_CTRL0,
8053 MDIO_PMA_DEVAD,
8054 MDIO_PMA_REG_LRM_MODE,
8056 }
8058 }
8062 u16 edc_mode)
8063 {
8064 u16 phy_identifier;
8065 u16 rom_ver2_val;
8067 MDIO_PMA_DEVAD,
8068 MDIO_PMA_REG_PHY_IDENTIFIER,
8072 MDIO_PMA_DEVAD,
8073 MDIO_PMA_REG_PHY_IDENTIFIER,
8077 MDIO_PMA_DEVAD,
8078 MDIO_PMA_REG_ROM_VER2,
8080 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8082 MDIO_PMA_DEVAD,
8083 MDIO_PMA_REG_ROM_VER2,
8087 MDIO_PMA_DEVAD,
8088 MDIO_PMA_REG_PHY_IDENTIFIER,
8092 }
8096 u32 action)
8097 {
8110 action);
8112 }
8113 }
8116 u8 gpio_mode)
8117 {
8123 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8131 {
8134 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8139 }
8143 fault_led_gpio);
8144 }
8145 }
8148 u8 gpio_mode)
8149 {
8150 u32 pin_cfg;
8156 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8157 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8161 }
8164 u8 gpio_mode)
8165 {
8169 /*
8170 * Low ==> if SFP+ module is supported otherwise
8171 * High ==> if SFP+ module is not on the approved vendor list
8172 */
8176 }
8180 u8 power)
8181 {
8182 u32 pin_cfg;
8188 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8189 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8195 /*
8196 * Low ==> corresponding SFP+ module is powered
8197 * high ==> the SFP+ module is powered down
8198 */
8200 }
8204 {
8207 /* Put Warpcore in low power mode */
8210 /* Put LCPLL in low power mode */
8214 }
8218 u8 power)
8219 {
8233 }
8234 }
8237 u16 edc_mode)
8238 {
8244 /* This is a global register which controls all lanes */
8259 }
8264 /* A must read */
8268 /* Restart microcode to re-read the new mode */
8272 }
8276 u16 edc_mode)
8277 {
8289 }
8290 }
8294 {
8296 u16 edc_mode;
8305 /* Power up module */
8311 /* check SFP+ module compatibility */
8314 /* Turn on fault module-detected led */
8316 MISC_REGISTERS_GPIO_HIGH);
8318 /* Check if need to power down the SFP+ module */
8320 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8324 }
8326 /* Turn off fault module-detected led */
8328 }
8330 /*
8331 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8332 * is done automatically
8333 */
8336 /*
8337 * Enable transmit for this module if the module is approved, or
8338 * if unapproved modules should also enable the Tx laser
8339 */
8342 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8344 else
8348 }
8351 {
8354 u32 gpio_val;
8358 else
8366 }
8368 /* Set valid module led off */
8371 /* Get current gpio val reflecting module plugged in / out*/
8374 /* Call the handling function in case module is detected */
8378 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8379 gpio_port);
8382 else
8388 config));
8390 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8391 gpio_port);
8392 /*
8393 * Module was plugged out.
8394 * Disable transmit for this module
8395 */
8398 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8401 }
8402 }
8404 /******************************************************************/
8405 /* Used by 8706 and 8727 */
8406 /******************************************************************/
8409 u16 alarm_status_offset,
8410 u16 alarm_ctrl_offset)
8411 {
8419 /* Mask or enable the fault event. */
8423 else
8426 }
8427 /******************************************************************/
8428 /* common BCM8706/BCM8726 PHY SECTION */
8429 /******************************************************************/
8433 {
8438 /* Clear RX Alarm*/
8443 MDIO_PMA_LASI_TXCTRL);
8445 /* clear LASI indication*/
8463 /*
8464 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8465 * are set, or if the autoneg bit 1 is set
8466 */
8471 else
8475 }
8477 /* Capture 10G link fault. Read twice to clear stale value. */
8485 }
8488 }
8490 /******************************************************************/
8491 /* BCM8706 PHY SECTION */
8492 /******************************************************************/
8496 {
8497 u32 tx_en_mode;
8503 /* HW reset */
8508 /* Wait until fw is loaded */
8515 }
8518 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8519 u8 i;
8520 u16 reg;
8524 MDIO_XS_8706_REG_BANK_RX0);
8526 /* Clear first 3 bits of the control */
8528 /* Set control bits according to configuration */
8533 }
8534 }
8535 /* Force speed */
8540 MDIO_PMA_DEVAD,
8545 /* Arm LASI for link and Tx fault. */
8549 /* Force 1Gbps using autoneg with 1G advertisement */
8551 /* Allow CL37 through CL73 */
8556 /* Enable Full-Duplex advertisement on CL37 */
8559 /* Enable CL37 AN */
8562 /* 1G support */
8566 /* Enable clause 73 AN */
8575 }
8578 /*
8579 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8580 * power mode, if TX Laser is disabled
8581 */
8595 }
8598 }
8603 {
8605 }
8607 /******************************************************************/
8608 /* BCM8726 PHY SECTION */
8609 /******************************************************************/
8612 {
8616 }
8620 {
8622 /* Need to wait 100ms after reset */
8625 /* Micro controller re-boot */
8629 /* Set soft reset */
8631 MDIO_PMA_DEVAD,
8632 MDIO_PMA_REG_GEN_CTRL,
8633 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8636 MDIO_PMA_DEVAD,
8640 MDIO_PMA_DEVAD,
8641 MDIO_PMA_REG_GEN_CTRL,
8642 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8644 /* wait for 150ms for microcode load */
8647 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8649 MDIO_PMA_DEVAD,
8654 }
8659 {
8661 u16 val1;
8671 }
8672 }
8674 }
8680 {
8689 /*
8690 * Need to call module detected on initialization since the module
8691 * detection triggered by actual module insertion might occur before
8692 * driver is loaded, and when driver is loaded, it reset all
8693 * registers, including the transmitter
8694 */
8710 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8712 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8713 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8715 /* Set Flow control */
8727 /*
8728 * Enable RX-ALARM control to receive interrupt for 1G speed
8729 * change
8730 */
8740 }
8742 /* Set TX PreEmphasis if needed */
8744 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8750 MDIO_PMA_DEVAD,
8751 MDIO_PMA_REG_8726_TX_CTRL1,
8755 MDIO_PMA_DEVAD,
8756 MDIO_PMA_REG_8726_TX_CTRL2,
8758 }
8762 }
8766 {
8769 /* Set serial boot control for external load */
8771 MDIO_PMA_DEVAD,
8773 }
8775 /******************************************************************/
8776 /* BCM8727 PHY SECTION */
8777 /******************************************************************/
8781 {
8785 u16 val;
8786 /* Only NOC flavor requires to set the LED specifically */
8803 }
8805 MDIO_PMA_DEVAD,
8806 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8811 MDIO_PMA_DEVAD,
8812 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8813 val);
8815 MDIO_PMA_DEVAD,
8816 MDIO_PMA_REG_8727_GPIO_CTRL,
8821 MDIO_PMA_DEVAD,
8822 MDIO_PMA_REG_8727_GPIO_CTRL,
8823 val);
8824 }
8828 u8 port;
8829 /*
8830 * The PHY reset is controlled by GPIO 1. Fake the port number
8831 * to cancel the swap done in set_gpio()
8832 */
8839 }
8844 {
8845 u32 tx_en_mode;
8847 u16 rx_alarm_ctrl_val;
8848 u16 lasi_ctrl_val;
8850 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8854 /* Should be 0x6 to enable XS on Tx side. */
8858 /* enable LASI */
8861 rx_alarm_ctrl_val);
8868 /*
8869 * Initially configure MOD_ABS to interrupt when module is
8870 * presence( bit 8)
8871 */
8874 /*
8875 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8876 * When the EDC is off it locks onto a reference clock and avoids
8877 * becoming 'lost'
8878 */
8886 /* Enable/Disable PHY transmitter output */
8889 /* Make MOD_ABS give interrupt on change */
8896 /*
8897 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8898 * status which reflect SFP+ module over-current
8899 */
8913 /* Set option 1G speed */
8923 /*
8924 * Power down the XAUI until link is up in case of dual-media
8925 * and 1G
8926 */
8929 MDIO_PMA_DEVAD,
8933 MDIO_PMA_DEVAD,
8935 }
8938 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8940 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8941 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8949 /*
8950 * Since the 8727 has only single reset pin, need to set the 10G
8951 * registers although it is default
8952 */
8963 }
8965 /*
8966 * Set 2-wire transfer rate of SFP+ module EEPROM
8967 * to 100Khz since some DACs(direct attached cables) do
8968 * not work at 400Khz.
8969 */
8974 /* Set TX PreEmphasis if needed */
8976 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8987 }
8989 /*
8990 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8991 * power mode, if TX Laser is disabled
8992 */
9007 }
9010 }
9014 {
9020 config));
9022 MDIO_PMA_DEVAD,
9026 /* Module is absent */
9030 /*
9031 * 1. Set mod_abs to detect next module
9032 * presence event
9033 * 2. Set EDC off by setting OPTXLOS signal input to low
9034 * (bit 9).
9035 * When the EDC is off it locks onto a reference clock and
9036 * avoids becoming 'lost'.
9037 */
9042 MDIO_PMA_DEVAD,
9045 /*
9046 * Clear RX alarm since it stays up as long as
9047 * the mod_abs wasn't changed
9048 */
9050 MDIO_PMA_DEVAD,
9054 /* Module is present */
9057 /*
9058 * First disable transmitter, and if the module is ok, the
9059 * module_detection will enable it
9060 * 1. Set mod_abs to detect next module absent event ( bit 8)
9061 * 2. Restore the default polarity of the OPRXLOS signal and
9062 * this signal will then correctly indicate the presence or
9063 * absence of the Rx signal. (bit 9)
9064 */
9069 MDIO_PMA_DEVAD,
9072 /*
9073 * Clear RX alarm since it stays up as long as the mod_abs
9074 * wasn't changed. This is need to be done before calling the
9075 * module detection, otherwise it will clear* the link update
9076 * alarm
9077 */
9079 MDIO_PMA_DEVAD,
9084 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9089 else
9091 }
9094 rx_alarm_status);
9095 /* No need to check link status in case of module plugged in/out */
9096 }
9102 {
9108 /* If PHY is not initialized, do not check link status */
9115 /* Check the LASI on Rx */
9123 MDIO_PMA_LASI_TXCTRL);
9130 /* Clear MSG-OUT */
9134 /*
9135 * If a module is present and there is need to check
9136 * for over current
9137 */
9139 /* Check over-current using 8727 GPIO0 input*/
9149 oc_port);
9151 "been detected and the power to "
9152 "that SFP+ module has been removed "
9153 "to prevent failure of the card. "
9154 "Please remove the SFP+ module and "
9155 "restart the system to clear this "
9157 oc_port);
9158 /* Disable all RX_ALARMs except for mod_abs */
9160 MDIO_PMA_DEVAD,
9164 MDIO_PMA_DEVAD,
9166 /* Wait for module_absent_event */
9169 MDIO_PMA_DEVAD,
9171 /* Clear RX alarm */
9173 MDIO_PMA_DEVAD,
9176 }
9179 /* When module absent bit is set, check module */
9182 /* Enable all mod_abs and link detection bits */
9186 }
9189 /* If transmitter is disabled, ignore false link up indication */
9195 }
9198 MDIO_PMA_DEVAD,
9201 /*
9202 * Bits 0..2 --> speed detected,
9203 * Bits 13..15--> link is down
9204 */
9219 }
9221 /* Capture 10G link fault. */
9231 }
9232 }
9238 }
9243 MDIO_PMA_DEVAD,
9245 /*
9246 * In case of dual-media board and 1G, power up the XAUI side,
9247 * otherwise power it down. For 10G it is done automatically
9248 */
9251 else
9254 MDIO_PMA_DEVAD,
9256 }
9258 }
9262 {
9265 /* Enable/Disable PHY transmitter output */
9268 /* Disable Transmitter */
9270 /* Clear LASI */
9273 }
9275 /******************************************************************/
9276 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9277 /******************************************************************/
9280 u8 port)
9281 {
9290 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9291 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9303 }
9310 }
9313 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9322 }
9329 }
9331 /* lower 16 bits of the register SPI_FW_STATUS */
9333 /* upper 16 bits of register SPI_FW_STATUS */
9338 }
9340 }
9343 {
9346 /* PHYC_CTL_LED_CTL */
9348 MDIO_PMA_DEVAD,
9354 MDIO_PMA_DEVAD,
9358 MDIO_PMA_DEVAD,
9359 MDIO_PMA_REG_8481_LED1_MASK,
9363 MDIO_PMA_DEVAD,
9364 MDIO_PMA_REG_8481_LED2_MASK,
9367 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9369 MDIO_PMA_DEVAD,
9370 MDIO_PMA_REG_8481_LED3_MASK,
9373 /* Select the closest activity blink rate to that in 10/100/1000 */
9375 MDIO_PMA_DEVAD,
9376 MDIO_PMA_REG_8481_LED3_BLINK,
9379 /* Configure the blink rate to ~15.9 Hz */
9381 MDIO_PMA_DEVAD,
9382 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9383 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9387 else
9396 /* 'Interrupt Mask' */
9398 MDIO_AN_DEVAD,
9400 }
9405 {
9408 u16 tmp_req_line_speed;
9415 /* Save spirom version */
9417 }
9418 /*
9419 * This phy uses the NIG latch mechanism since link indication
9420 * arrives through its LED4 and not via its LASI signal, so we
9421 * get steady signal instead of clear on read
9422 */
9431 /* set 1000 speed advertisement */
9438 MDIO_AN_DEVAD,
9439 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9444 /* Disable forced speed */
9450 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9462 an_1000_val);
9464 /* set 100 speed advertisement */
9468 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9470 /* Enable autoneg and restart autoneg for legacy speeds */
9476 }
9477 /* set 10 speed advertisement */
9481 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9484 SUPPORTED_10baseT_Full)))) {
9490 }
9492 /* Only 10/100 are allowed to work in FORCE mode */
9496 SUPPORTED_100baseT_Full))) {
9498 /* Enabled AUTO-MDIX when autoneg is disabled */
9502 /* The PHY needs this set even for forced link. */
9505 }
9509 SUPPORTED_10baseT_Full))) {
9510 /* Enabled AUTO-MDIX when autoneg is disabled */
9515 }
9519 an_10_100_val);
9524 /*
9525 * Always write this if this is not 84833.
9526 * For 84833, write it only when it's a forced speed.
9527 */
9531 MDIO_AN_DEVAD,
9536 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9539 /* Restart autoneg for 10G*/
9542 MDIO_AN_DEVAD,
9543 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9546 MDIO_AN_DEVAD,
9547 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9554 MDIO_AN_DEVAD,
9555 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9561 }
9566 {
9568 /* Restore normal power mode*/
9572 /* HW reset */
9578 }
9580 #define PHY84833_CMDHDLR_WAIT 300
9581 #define PHY84833_CMDHDLR_MAX_ARGS 5
9584 u16 fw_cmd,
9585 u16 cmd_args[])
9586 {
9587 u32 idx;
9588 u16 val;
9590 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9592 MDIO_84833_CMD_HDLR_STATUS,
9593 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9600 }
9604 }
9606 /* Prepare argument(s) and issue command */
9611 }
9621 }
9626 }
9627 /* Gather returning data */
9632 }
9634 MDIO_84833_CMD_HDLR_STATUS,
9635 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9637 }
9643 {
9644 u32 pair_swap;
9649 /* Check for configuration. */
9653 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9658 /* Only the second argument is used for this command */
9667 }
9670 u32 shmem_base_path[],
9671 u32 chip_id)
9672 {
9674 u32 idx;
9675 u8 reset_gpios;
9677 /* Assume that these will be GPIOs, not EPIOs. */
9679 /* Map config param to register bit. */
9684 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9685 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9688 }
9691 /* E2, look from diff place of shmem. */
9700 }
9702 }
9705 }
9709 {
9711 u8 reset_gpios;
9714 other_shmem_base_addr));
9726 reset_gpios);
9729 }
9731 #define PHY84833_CONSTANT_LATENCY 1193
9735 {
9738 u16 val;
9747 else
9752 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9753 port);
9755 /* MDIO reset */
9757 MDIO_PMA_DEVAD,
9759 }
9763 /* Wait for GPHY to come out of reset */
9766 /*
9767 * BCM84823 requires that XGXS links up first @ 10G for normal
9768 * behavior.
9769 */
9770 u16 temp;
9776 }
9781 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9782 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9783 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9784 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9788 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9791 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9792 }
9798 /* Do nothing. Essentially this is like the priority copper */
9807 /* Do nothing here. The first PHY won't be initialized at all */
9813 }
9825 /* Keep AutogrEEEn disabled. */
9834 }
9837 else
9839 /* 84833 PHY has a better feature and doesn't need to support this. */
9844 PORT_HW_CFG_ENABLE_CMS_MASK;
9850 else
9854 }
9857 /* Bring PHY out of super isolate mode as the final step. */
9859 MDIO_CTL_DEVAD,
9863 MDIO_CTL_DEVAD,
9865 }
9867 }
9872 {
9878 /* Check 10G-BaseT link status */
9879 /* Check PMD signal ok */
9887 /* Check link 10G */
9896 /* Enable expansion register 0x42 (Operation mode status) */
9898 MDIO_AN_DEVAD,
9901 /* Get legacy speed operation status */
9903 MDIO_AN_DEVAD,
9904 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9908 legacy_status);
9923 else
9930 /* Check legacy speed AN resolution */
9932 MDIO_AN_DEVAD,
9933 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9937 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9939 MDIO_AN_DEVAD,
9940 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9944 LINK_STATUS_PARALLEL_DETECTION_USED;
9945 }
9946 }
9951 }
9954 }
9958 {
9960 u32 spirom_ver;
9964 }
9968 {
9973 }
9977 {
9982 }
9986 {
9988 u8 port;
9989 u16 val16;
9993 else
9998 MISC_REGISTERS_GPIO_OUTPUT_LOW,
9999 port);
10002 MDIO_CTL_DEVAD,
10006 MDIO_CTL_DEVAD,
10008 }
10009 }
10013 {
10015 u16 val;
10016 u8 port;
10020 else
10029 SHARED_HW_CFG_LED_EXTPHY1) {
10031 /* Set LED masks */
10033 MDIO_PMA_DEVAD,
10034 MDIO_PMA_REG_8481_LED1_MASK,
10038 MDIO_PMA_DEVAD,
10039 MDIO_PMA_REG_8481_LED2_MASK,
10043 MDIO_PMA_DEVAD,
10044 MDIO_PMA_REG_8481_LED3_MASK,
10048 MDIO_PMA_DEVAD,
10049 MDIO_PMA_REG_8481_LED5_MASK,
10054 MDIO_PMA_DEVAD,
10055 MDIO_PMA_REG_8481_LED1_MASK,
10057 }
10062 port);
10065 SHARED_HW_CFG_LED_EXTPHY1) {
10067 /* Set LED masks */
10069 MDIO_PMA_DEVAD,
10070 MDIO_PMA_REG_8481_LED1_MASK,
10074 MDIO_PMA_DEVAD,
10075 MDIO_PMA_REG_8481_LED2_MASK,
10079 MDIO_PMA_DEVAD,
10080 MDIO_PMA_REG_8481_LED3_MASK,
10084 MDIO_PMA_DEVAD,
10085 MDIO_PMA_REG_8481_LED5_MASK,
10090 MDIO_PMA_DEVAD,
10091 MDIO_PMA_REG_8481_LED1_MASK,
10093 }
10100 SHARED_HW_CFG_LED_EXTPHY1) {
10101 /* Set control reg */
10103 MDIO_PMA_DEVAD,
10104 MDIO_PMA_REG_8481_LINK_SIGNAL,
10110 MDIO_PMA_DEVAD,
10111 MDIO_PMA_REG_8481_LINK_SIGNAL,
10112 val);
10114 /* Set LED masks */
10116 MDIO_PMA_DEVAD,
10117 MDIO_PMA_REG_8481_LED1_MASK,
10121 MDIO_PMA_DEVAD,
10122 MDIO_PMA_REG_8481_LED2_MASK,
10126 MDIO_PMA_DEVAD,
10127 MDIO_PMA_REG_8481_LED3_MASK,
10131 MDIO_PMA_DEVAD,
10132 MDIO_PMA_REG_8481_LED5_MASK,
10136 MDIO_PMA_DEVAD,
10137 MDIO_PMA_REG_8481_LED1_MASK,
10139 }
10147 SHARED_HW_CFG_LED_EXTPHY1) {
10149 /* Set control reg */
10151 MDIO_PMA_DEVAD,
10152 MDIO_PMA_REG_8481_LINK_SIGNAL,
10156 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10160 MDIO_PMA_DEVAD,
10161 MDIO_PMA_REG_8481_LINK_SIGNAL,
10163 }
10165 /* Set LED masks */
10167 MDIO_PMA_DEVAD,
10168 MDIO_PMA_REG_8481_LED1_MASK,
10172 MDIO_PMA_DEVAD,
10173 MDIO_PMA_REG_8481_LED2_MASK,
10177 MDIO_PMA_DEVAD,
10178 MDIO_PMA_REG_8481_LED3_MASK,
10182 MDIO_PMA_DEVAD,
10183 MDIO_PMA_REG_8481_LED5_MASK,
10188 MDIO_PMA_DEVAD,
10189 MDIO_PMA_REG_8481_LED1_MASK,
10192 /* Tell LED3 to blink on source */
10194 MDIO_PMA_DEVAD,
10195 MDIO_PMA_REG_8481_LINK_SIGNAL,
10200 MDIO_PMA_DEVAD,
10201 MDIO_PMA_REG_8481_LINK_SIGNAL,
10202 val);
10203 }
10205 }
10207 /*
10208 * This is a workaround for E3+84833 until autoneg
10209 * restart is fixed in f/w
10210 */
10214 }
10215 }
10217 /******************************************************************/
10218 /* 54618SE PHY SECTION */
10219 /******************************************************************/
10223 {
10225 u8 port;
10227 u32 cfg_pin;
10232 /*
10233 * This works with E3 only, no need to check the chip
10234 * before determining the port.
10235 */
10241 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10242 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10244 /* Drive pin high to bring the GPHY out of reset. */
10247 /* wait for GPHY to reset */
10250 /* reset phy */
10255 /*wait for GPHY to reset */
10258 /* Configure LED4: set to INTR (0x6). */
10259 /* Accessing shadow register 0xe. */
10261 MDIO_REG_GPHY_SHADOW,
10262 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10264 MDIO_REG_GPHY_SHADOW,
10269 MDIO_REG_GPHY_SHADOW,
10271 /* Configure INTR based on link status change. */
10273 MDIO_REG_INTR_MASK,
10276 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10278 MDIO_REG_GPHY_SHADOW,
10279 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10281 MDIO_REG_GPHY_SHADOW,
10285 MDIO_REG_GPHY_SHADOW,
10288 /* Set up fc */
10289 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10293 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10297 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10300 /* read all advertisement */
10310 MDIO_PMA_REG_CTRL,
10313 /* Disable forced speed */
10320 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10332 an_1000_val);
10337 /* set 100 speed advertisement */
10341 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10343 /* Enable autoneg and restart autoneg for legacy speeds */
10349 }
10351 /* set 10 speed advertisement */
10355 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10361 }
10363 /* Only 10/100 are allowed to work in FORCE mode */
10366 /* Enabled AUTO-MDIX when autoneg is disabled */
10371 }
10373 /* Enabled AUTO-MDIX when autoneg is disabled */
10378 }
10380 /* Check if we should turn on Auto-GrEEEn */
10384 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10390 }
10394 MDIO_REG_GPHY_CL45_DATA_REG,
10395 MDIO_REG_GPHY_EEE_ADV);
10397 MDIO_REG_GPHY_CL45_ADDR_REG,
10400 MDIO_REG_GPHY_CL45_DATA_REG,
10401 temp);
10402 }
10415 }
10420 {
10422 u16 temp;
10425 MDIO_REG_GPHY_SHADOW,
10426 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10428 MDIO_REG_GPHY_SHADOW,
10446 }
10448 MDIO_REG_GPHY_SHADOW,
10451 }
10456 {
10458 u32 cfg_pin;
10459 u8 port;
10461 /*
10462 * In case of no EPIO routed to reset the GPHY, put it
10463 * in low power mode.
10464 */
10466 /*
10467 * This works with E3 only, no need to check the chip
10468 * before determining the port.
10469 */
10474 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10475 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10477 /* Drive pin low to put GPHY in reset. */
10479 }
10484 {
10486 u16 val;
10490 /* Get speed operation status */
10496 /* Read status to clear the PHY interrupt. */
10498 MDIO_REG_INTR_STATUS,
10514 }
10515 /* Omitting 100Base-T4 for now */
10533 /* Check legacy speed AN resolution */
10539 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10545 LINK_STATUS_PARALLEL_DETECTION_USED;
10550 /* Report whether EEE is resolved. */
10554 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10558 MDIO_REG_GPHY_CL45_ADDR_REG,
10559 MDIO_AN_DEVAD);
10561 MDIO_REG_GPHY_CL45_DATA_REG,
10562 MDIO_REG_GPHY_EEE_RESOLVED);
10564 MDIO_REG_GPHY_CL45_ADDR_REG,
10567 MDIO_REG_GPHY_CL45_DATA_REG,
10569 }
10571 }
10574 }
10576 }
10580 {
10582 u16 val;
10587 /* Enable master/slave manual mmode and set to master */
10588 /* mii write 9 [bits set 11 12] */
10591 /* forced 1G and disable autoneg */
10592 /* set val [mii read 0] */
10593 /* set val [expr $val & [bits clear 6 12 13]] */
10594 /* set val [expr $val | [bits set 6 8]] */
10595 /* mii write 0 $val */
10601 /* Set external loopback and Tx using 6dB coding */
10602 /* mii write 0x18 7 */
10603 /* set val [mii read 0x18] */
10604 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10609 /* This register opens the gate for the UMAC despite its name */
10612 /*
10613 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10614 * length used by the MAC receive logic to check frames.
10615 */
10617 }
10619 /******************************************************************/
10620 /* SFX7101 PHY SECTION */
10621 /******************************************************************/
10624 {
10626 /* SFX7101_XGXS_TEST1 */
10629 }
10634 {
10639 /* Restore normal power mode*/
10642 /* HW reset */
10653 /* Restart autoneg */
10660 /* Save spirom version */
10669 }
10674 {
10676 u8 link_up;
10691 /* if link is up print the AN outcome of the SFX7101 PHY */
10702 }
10704 }
10707 {
10717 }
10720 {
10724 MDIO_PMA_DEVAD,
10729 /* Writes a self-clearing reset */
10731 MDIO_PMA_DEVAD,
10732 MDIO_PMA_REG_7101_RESET,
10734 /* Wait for clear */
10736 MDIO_PMA_DEVAD,
10741 }
10742 }
10746 /* Low power mode is controlled by GPIO 2 */
10749 /* The PHY reset is controlled by GPIO 1 */
10752 }
10756 {
10770 }
10772 MDIO_PMA_DEVAD,
10773 MDIO_PMA_REG_7107_LINK_LED_CNTL,
10774 val);
10775 }
10777 /******************************************************************/
10778 /* STATIC PHY DECLARATION */
10779 /******************************************************************/
10805 };
10816 SUPPORTED_10baseT_Full |
10817 SUPPORTED_100baseT_Half |
10818 SUPPORTED_100baseT_Full |
10819 SUPPORTED_1000baseT_Full |
10820 SUPPORTED_2500baseX_Full |
10821 SUPPORTED_TP |
10822 SUPPORTED_Autoneg |
10823 SUPPORTED_Pause |
10824 SUPPORTED_Asym_Pause),
10840 };
10851 SUPPORTED_10baseT_Full |
10852 SUPPORTED_100baseT_Half |
10853 SUPPORTED_100baseT_Full |
10854 SUPPORTED_1000baseT_Full |
10855 SUPPORTED_2500baseX_Full |
10856 SUPPORTED_10000baseT_Full |
10857 SUPPORTED_FIBRE |
10858 SUPPORTED_Autoneg |
10859 SUPPORTED_Pause |
10860 SUPPORTED_Asym_Pause),
10876 };
10886 SUPPORTED_10baseT_Full |
10887 SUPPORTED_100baseT_Half |
10888 SUPPORTED_100baseT_Full |
10889 SUPPORTED_1000baseT_Full |
10890 SUPPORTED_10000baseT_Full |
10891 SUPPORTED_20000baseKR2_Full |
10892 SUPPORTED_20000baseMLD2_Full |
10893 SUPPORTED_FIBRE |
10894 SUPPORTED_Autoneg |
10895 SUPPORTED_Pause |
10896 SUPPORTED_Asym_Pause),
10912 };
10924 SUPPORTED_TP |
10925 SUPPORTED_Autoneg |
10926 SUPPORTED_Pause |
10927 SUPPORTED_Asym_Pause),
10943 };
10953 SUPPORTED_2500baseX_Full |
10954 SUPPORTED_1000baseT_Full |
10955 SUPPORTED_FIBRE |
10956 SUPPORTED_Autoneg |
10957 SUPPORTED_Pause |
10958 SUPPORTED_Asym_Pause),
10974 };
10984 SUPPORTED_FIBRE |
10985 SUPPORTED_Pause |
10986 SUPPORTED_Asym_Pause),
11002 };
11012 SUPPORTED_1000baseT_Full |
11013 SUPPORTED_FIBRE |
11014 SUPPORTED_Pause |
11015 SUPPORTED_Asym_Pause),
11031 };
11038 FLAGS_INIT_XGXS_FIRST),
11043 SUPPORTED_1000baseT_Full |
11044 SUPPORTED_Autoneg |
11045 SUPPORTED_FIBRE |
11046 SUPPORTED_Pause |
11047 SUPPORTED_Asym_Pause),
11063 };
11074 SUPPORTED_1000baseT_Full |
11075 SUPPORTED_FIBRE |
11076 SUPPORTED_Pause |
11077 SUPPORTED_Asym_Pause),
11093 };
11099 FLAGS_REARM_LATCH_SIGNAL,
11104 SUPPORTED_10baseT_Full |
11105 SUPPORTED_100baseT_Half |
11106 SUPPORTED_100baseT_Full |
11107 SUPPORTED_1000baseT_Full |
11108 SUPPORTED_10000baseT_Full |
11109 SUPPORTED_TP |
11110 SUPPORTED_Autoneg |
11111 SUPPORTED_Pause |
11112 SUPPORTED_Asym_Pause),
11128 };
11135 FLAGS_REARM_LATCH_SIGNAL,
11140 SUPPORTED_10baseT_Full |
11141 SUPPORTED_100baseT_Half |
11142 SUPPORTED_100baseT_Full |
11143 SUPPORTED_1000baseT_Full |
11144 SUPPORTED_10000baseT_Full |
11145 SUPPORTED_TP |
11146 SUPPORTED_Autoneg |
11147 SUPPORTED_Pause |
11148 SUPPORTED_Asym_Pause),
11164 };
11171 FLAGS_REARM_LATCH_SIGNAL,
11176 SUPPORTED_100baseT_Full |
11177 SUPPORTED_1000baseT_Full |
11178 SUPPORTED_10000baseT_Full |
11179 SUPPORTED_TP |
11180 SUPPORTED_Autoneg |
11181 SUPPORTED_Pause |
11182 SUPPORTED_Asym_Pause),
11198 };
11209 SUPPORTED_10baseT_Full |
11210 SUPPORTED_100baseT_Half |
11211 SUPPORTED_100baseT_Full |
11212 SUPPORTED_1000baseT_Full |
11213 SUPPORTED_TP |
11214 SUPPORTED_Autoneg |
11215 SUPPORTED_Pause |
11216 SUPPORTED_Asym_Pause),
11232 };
11233 /*****************************************************************/
11234 /* */
11235 /* Populate the phy according. Main function: bnx2x_populate_phy */
11236 /* */
11237 /*****************************************************************/
11241 u8 phy_index)
11242 {
11243 /* Get the 4 lanes xgxs config rx and tx */
11246 /*
11247 * INT_PHY and EXT_PHY1 share the same value location in the
11248 * shmem. When num_phys is greater than 1, than this value
11249 * applies only to EXT_PHY1
11250 */
11267 }
11274 }
11275 }
11279 {
11295 }
11298 }
11301 {
11302 u32 phy_addr;
11303 u32 chip_id;
11307 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11313 u32 serdes_net_if;
11315 MISC_REG_WC0_CTRL_PHY_ADDR);
11319 else
11321 /* Check Dual mode */
11325 PORT_HW_CFG_NET_SERDES_IF_MASK);
11326 /*
11327 * Set the appropriate supported and flags indications per
11328 * interface type of the chip
11329 */
11333 SUPPORTED_10baseT_Full |
11334 SUPPORTED_100baseT_Half |
11335 SUPPORTED_100baseT_Full |
11336 SUPPORTED_1000baseT_Full |
11337 SUPPORTED_FIBRE |
11338 SUPPORTED_Autoneg |
11339 SUPPORTED_Pause |
11340 SUPPORTED_Asym_Pause);
11348 SUPPORTED_10000baseT_Full |
11349 SUPPORTED_FIBRE |
11350 SUPPORTED_Pause |
11351 SUPPORTED_Asym_Pause);
11357 SUPPORTED_10000baseT_Full |
11358 SUPPORTED_FIBRE |
11359 SUPPORTED_Autoneg |
11360 SUPPORTED_Pause |
11361 SUPPORTED_Asym_Pause);
11367 SUPPORTED_FIBRE |
11368 SUPPORTED_Pause |
11369 SUPPORTED_Asym_Pause);
11375 SUPPORTED_FIBRE |
11376 SUPPORTED_Pause |
11377 SUPPORTED_Asym_Pause);
11381 serdes_net_if);
11383 }
11385 /*
11386 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11387 * was not set as expected. For B0, ECO will be enabled so there
11388 * won't be an issue there
11389 */
11392 else
11398 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11404 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11411 }
11412 }
11415 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11416 port);
11419 else
11427 }
11430 u8 phy_index,
11431 u32 shmem_base,
11432 u32 shmem2_base,
11433 u8 port,
11435 {
11441 /* Select the phy type */
11458 /* BCM8727_NOC => BCM8727 no over current */
11489 /* In case external PHY wasn't found */
11494 }
11499 /*
11500 * The shmem address of the phy version is located on different
11501 * structures. In case this structure is too old, do not set
11502 * the address
11503 */
11510 /* Check specific mdc mdio settings */
11513 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11522 }
11523 /* Check specific mdc mdio settings */
11526 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11528 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11529 }
11534 /*
11535 * Remove 100Mb link supported for BCM84833 when phy fw
11536 * version lower than or equal to 1.39
11537 */
11542 SUPPORTED_100baseT_Full);
11543 }
11545 /*
11546 * In case mdc/mdio_access of the external phy is different than the
11547 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11548 * to prevent one port interfere with another port's CL45 operations.
11549 */
11557 }
11561 {
11569 }
11573 u8 phy_index)
11574 {
11576 u32 link_config;
11577 /* Populate the default phy configuration for MF mode */
11584 dev_info.
11592 dev_info.
11594 }
11623 }
11641 }
11642 }
11645 {
11650 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11653 PORT_HW_CFG_PHY_SELECTION_MASK;
11669 }
11674 }
11678 {
11686 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11689 phy_index++) {
11696 }
11706 phy_index);
11709 phy_index++)
11712 }
11721 /*
11722 * Update media type for non-PMF sync only for the first time
11723 * In case the media type changes afterwards, it will be updated
11724 * using the update_status function
11725 */
11730 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11732 actual_phy_idx));
11733 }
11738 }
11742 }
11746 {
11758 /* set bmac loopback */
11762 }
11766 {
11777 /* set bmac loopback */
11781 }
11785 {
11790 else
11796 /*
11797 * Set WC to loopback mode since link is required to provide clock
11798 * to the XMAC in 20G mode
11799 */
11804 params);
11808 }
11812 {
11823 }
11827 {
11834 else
11847 }
11851 else
11853 }
11856 /* set 10G XGXS loopback */
11859 params);
11862 /* set external phy loopback */
11863 u8 phy_index;
11869 params);
11870 }
11871 }
11875 }
11878 {
11894 /* disable attentions */
11897 NIG_MASK_XGXS0_LINK10G |
11898 NIG_MASK_SERDES0_LINK_STATUS |
11899 NIG_MASK_MI_INT));
11906 }
11931 else
11933 }
11938 }
11940 }
11943 u8 reset_ext_phy)
11944 {
11948 /* disable attentions */
11953 NIG_MASK_XGXS0_LINK10G |
11954 NIG_MASK_SERDES0_LINK_STATUS |
11955 NIG_MASK_MI_INT));
11957 /* activate nig drain */
11960 /* disable nig egress interface */
11964 }
11966 /* Stop BigMac rx */
11972 }
11973 /* disable emac */
11978 /* The PHY reset is controlled by GPIO 1
11979 * Hold it as vars low
11980 */
11981 /* clear link led */
11987 phy_index++) {
11993 params);
11994 }
11996 FLAGS_REARM_LATCH_SIGNAL)
11998 }
11999 }
12002 /* Clear latching indication */
12006 }
12011 /* disable nig ingress interface */
12013 /* reset BigMac */
12022 MISC_REGISTERS_RESET_REG_2_XMAC)
12024 XMAC_CTRL_REG_SOFT_RESET);
12025 }
12029 }
12031 /****************************************************************************/
12032 /* Common function */
12033 /****************************************************************************/
12035 u32 shmem_base_path[],
12037 u32 chip_id)
12038 {
12041 u16 val;
12049 /* PART1 - Reset both phys */
12052 /* In E2, same phy is using for port0 of the two paths */
12061 }
12063 /* Extract the ext phy address for the port */
12069 }
12070 /* disable attentions */
12074 NIG_MASK_XGXS0_LINK10G |
12075 NIG_MASK_SERDES0_LINK_STATUS |
12076 NIG_MASK_MI_INT));
12078 /* Need to take the phy out of low power mode in order
12079 to write to access its registers */
12081 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12082 port);
12084 /* Reset the phy */
12086 MDIO_PMA_DEVAD,
12087 MDIO_PMA_REG_CTRL,
12089 }
12091 /* Add delay of 150ms after reset */
12100 }
12102 /* PART2 - Download firmware to both phys */
12106 else
12112 port_of_path))
12115 /* Only set bit 10 = 1 (Tx power down) */
12117 MDIO_PMA_DEVAD,
12120 /* Phase1 of TX_POWER_DOWN reset */
12122 MDIO_PMA_DEVAD,
12123 MDIO_PMA_REG_TX_POWER_DOWN,
12125 }
12127 /*
12128 * Toggle Transmitter: Power down and then up with 600ms delay
12129 * between
12130 */
12133 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12135 /* Phase2 of POWER_DOWN_RESET */
12136 /* Release bit 10 (Release Tx power down) */
12138 MDIO_PMA_DEVAD,
12142 MDIO_PMA_DEVAD,
12146 /* Read modify write the SPI-ROM version select register */
12148 MDIO_PMA_DEVAD,
12151 MDIO_PMA_DEVAD,
12154 /* set GPIO2 back to LOW */
12157 }
12159 }
12161 u32 shmem_base_path[],
12163 u32 chip_id)
12164 {
12165 u32 val;
12166 s8 port;
12168 /* Use port1 because of the static port-swap */
12169 /* Enable the module detection interrupt */
12180 /* In E2, same phy is using for port0 of the two paths */
12187 }
12188 /* Extract the ext phy address for the port */
12194 }
12196 /* Reset phy*/
12201 /* Set fault module detected LED on */
12203 MISC_REGISTERS_GPIO_HIGH,
12204 port);
12205 }
12208 }
12211 {
12250 /* Don't override the io_gpio and io_port */
12252 }
12253 }
12256 u32 shmem_base_path[],
12258 u32 chip_id)
12259 {
12264 s8 port_of_path;
12271 /*
12272 * Retrieve the reset gpio/port which control the reset.
12273 * Default is GPIO1, PORT1
12274 */
12278 /* Calculate the port based on port swap */
12281 /* Initiate PHY reset*/
12283 port);
12286 port);
12290 /* PART1 - Reset both phys */
12294 /* In E2, same phy is using for port0 of the two paths */
12303 }
12305 /* Extract the ext phy address for the port */
12311 }
12312 /* disable attentions */
12316 NIG_MASK_XGXS0_LINK10G |
12317 NIG_MASK_SERDES0_LINK_STATUS |
12318 NIG_MASK_MI_INT));
12321 /* Reset the phy */
12324 }
12326 /* Add delay of 150ms after reset */
12334 }
12335 /* PART2 - Download firmware to both phys */
12339 else
12344 port_of_path))
12346 /* Disable PHY transmitter output */
12348 MDIO_PMA_DEVAD,
12351 }
12353 }
12356 u32 shmem_base_path[],
12357 u32 shmem2_base_path[],
12358 u8 phy_index,
12359 u32 chip_id)
12360 {
12361 u8 reset_gpios;
12367 reset_gpios);
12369 }
12373 {
12375 /* Wait for FW completing its initialization. */
12378 MDIO_PMA_DEVAD,
12383 }
12387 }
12389 /* Put the port in super isolate mode. */
12391 MDIO_CTL_DEVAD,
12395 MDIO_CTL_DEVAD,
12398 /* Save spirom version */
12401 }
12404 u32 shmem_base,
12405 u32 shmem2_base,
12406 u32 chip_id)
12407 {
12415 }
12422 }
12424 }
12429 {
12435 shmem2_base_path,
12442 shmem2_base_path,
12447 /*
12448 * GPIO1 affects both ports, so there's need to pull
12449 * it for single port alone
12450 */
12452 shmem2_base_path,
12456 /*
12457 * GPIO3's are linked, and so both need to be toggled
12458 * to obtain required 2us pulse.
12459 */
12461 shmem2_base_path,
12470 ext_phy_type);
12472 }
12479 }
12483 {
12492 /* Enable EPIO */
12495 }
12496 /* Check if common init was already done */
12502 phy_ver);
12504 }
12506 /* Read the ext_phy_type for arbitrary port(0) */
12508 phy_index++) {
12514 shmem2_base_path,
12516 chip_id);
12517 }
12519 }
12523 {
12525 u32 cfg_pin;
12527 u32 pin_val;
12532 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12533 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12535 /* Ignore check if no external input PIN available */
12542 " been detected and the power to "
12543 "that SFP+ module has been removed"
12544 " to prevent failure of the card."
12545 " Please remove the SFP+ module and"
12546 " restart the system to clear this"
12550 }
12553 }
12557 {
12559 /* Compare new value with previous value */
12560 u8 led_mode;
12566 /* If values differ */
12570 /*
12571 * a. Update shmem->link_status accordingly
12572 * b. Update link_vars->link_up
12573 */
12579 /*
12580 * Set LED mode to off since the PHY doesn't know about these
12581 * errors
12582 */
12590 }
12591 /* Update the LED according to the link state */
12594 /* Update link status in the shared memory */
12597 /* C. Trigger General Attention */
12600 }
12602 /******************************************************************************
12603 * Description:
12604 * This function checks for half opened connection change indication.
12605 * When such change occurs, it calls the bnx2x_analyze_link_error
12606 * to check if Remote Fault is set or cleared. Reception of remote fault
12607 * status message in the MAC indicates that the peer's MAC has detected
12608 * a fault, for example, due to break in the TX side of fiber.
12609 *
12610 ******************************************************************************/
12613 {
12616 u32 mac_base;
12617 /* In case link status is physically up @ 10G do */
12624 /* Check E3 XMAC */
12625 /*
12626 * Note that link speed cannot be queried here, since it may be
12627 * zero while link is down. In case UMAC is active, LSS will
12628 * simply not be set
12629 */
12632 /* Clear stick bits (Requires rising edge) */
12635 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12636 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12643 /* Check E1X / E2 BMAC */
12644 u32 lss_status_reg;
12647 NIG_REG_INGRESS_BMAC0_MEM;
12648 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12651 else
12658 }
12659 }
12662 {
12664 u16 phy_idx;
12670 }
12671 }
12678 }
12680 }
12683 {
12684 u8 phy_index;
12687 phy_index++) {
12692 }
12696 }
12698 }
12701 u32 shmem_base,
12702 u32 shmem2_base,
12703 u8 port)
12704 {
12708 phy_index++) {
12714 }
12716 FLAGS_FAN_FAILURE_DET_REQ);
12717 }
12719 }
12722 {
12723 u8 phy_index;
12728 NIG_MASK_XGXS0_LINK10G |
12729 NIG_MASK_SERDES0_LINK_STATUS |
12730 NIG_MASK_MI_INT));
12733 phy_index++) {
12737 params);
12739 }
12740 }
12741 }
12745 u8 port)
12746 {
12748 u32 val;
12752 shmem_base,
12753 port,
12760 phy_index++) {
12766 }
12771 }
12772 }
12773 }
12778 /* Set GPIO3 to trigger SFP+ module insertion/removal */
12798 else
12801 /* Open appropriate AEU for interrupts */
12806 /* Enable the GPIO to trigger interrupt */
12810 }