Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_link.h
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1 /* Copyright 2008-2011 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
13 * Written by Yaniv Rosner
17 #ifndef BNX2X_LINK_H
18 #define BNX2X_LINK_H
22 /***********************************************************/
23 /* Defines */
24 /***********************************************************/
25 #define DEFAULT_PHY_DEV_ADDR 3
26 #define E2_DEFAULT_PHY_DEV_ADDR 5
30 #define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
31 #define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
32 #define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
33 #define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
34 #define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
36 #define NET_SERDES_IF_XFI 1
37 #define NET_SERDES_IF_SFI 2
38 #define NET_SERDES_IF_KR 3
39 #define NET_SERDES_IF_DXGXS 4
41 #define SPEED_AUTO_NEG 0
42 #define SPEED_20000 20000
44 #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
45 #define SFP_EEPROM_VENDOR_NAME_SIZE 16
46 #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
47 #define SFP_EEPROM_VENDOR_OUI_SIZE 3
48 #define SFP_EEPROM_PART_NO_ADDR 0x28
49 #define SFP_EEPROM_PART_NO_SIZE 16
50 #define SFP_EEPROM_REVISION_ADDR 0x38
51 #define SFP_EEPROM_REVISION_SIZE 4
52 #define SFP_EEPROM_SERIAL_ADDR 0x44
53 #define SFP_EEPROM_SERIAL_SIZE 16
54 #define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
55 #define SFP_EEPROM_DATE_SIZE 6
56 #define PWR_FLT_ERR_MSG_LEN 250
58 #define XGXS_EXT_PHY_TYPE(ext_phy_config) \
59 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
60 #define XGXS_EXT_PHY_ADDR(ext_phy_config) \
61 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
62 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
63 #define SERDES_EXT_PHY_TYPE(ext_phy_config) \
64 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
66 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
67 #define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
68 /* Single Media board contains single external phy */
69 #define SINGLE_MEDIA(params) (params->num_phys == 2)
70 /* Dual Media board contains two external phy with different media */
71 #define DUAL_MEDIA(params) (params->num_phys == 3)
73 #define FW_PARAM_PHY_ADDR_MASK 0x000000FF
74 #define FW_PARAM_PHY_TYPE_MASK 0x0000FF00
75 #define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
76 #define FW_PARAM_MDIO_CTRL_OFFSET 16
77 #define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
78 FW_PARAM_PHY_ADDR_MASK)
79 #define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
80 FW_PARAM_PHY_TYPE_MASK)
81 #define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
82 FW_PARAM_MDIO_CTRL_MASK) >> \
83 FW_PARAM_MDIO_CTRL_OFFSET)
84 #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
85 (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
88 #define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
89 #define PFC_BRB_FULL_LB_XON_THRESHOLD 250
91 #define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
92 /***********************************************************/
93 /* Structs */
94 /***********************************************************/
95 #define INT_PHY 0
96 #define EXT_PHY1 1
97 #define EXT_PHY2 2
98 #define MAX_PHYS 3
100 /* Same configuration is shared between the XGXS and the first external phy */
101 #define LINK_CONFIG_SIZE (MAX_PHYS - 1)
102 #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
103 0 : (_phy_idx - 1))
104 /***********************************************************/
105 /* bnx2x_phy struct */
106 /* Defines the required arguments and function per phy */
107 /***********************************************************/
108 struct link_vars;
109 struct link_params;
110 struct bnx2x_phy;
112 typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
113 struct link_vars *vars);
114 typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
115 struct link_vars *vars);
116 typedef void (*link_reset_t)(struct bnx2x_phy *phy,
117 struct link_params *params);
118 typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
119 struct link_params *params);
120 typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
121 typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
122 typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
123 struct link_params *params, u8 mode);
124 typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
125 struct link_params *params, u32 action);
127 struct bnx2x_phy {
128 u32 type;
130 /* Loaded during init */
131 u8 addr;
132 u8 def_md_devad;
133 u16 flags;
134 /* Require HW lock */
135 #define FLAGS_HW_LOCK_REQUIRED (1<<0)
136 /* No Over-Current detection */
137 #define FLAGS_NOC (1<<1)
138 /* Fan failure detection required */
139 #define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
140 /* Initialize first the XGXS and only then the phy itself */
141 #define FLAGS_INIT_XGXS_FIRST (1<<3)
142 #define FLAGS_WC_DUAL_MODE (1<<4)
143 #define FLAGS_4_PORT_MODE (1<<5)
144 #define FLAGS_REARM_LATCH_SIGNAL (1<<6)
145 #define FLAGS_SFP_NOT_APPROVED (1<<7)
146 #define FLAGS_MDC_MDIO_WA (1<<8)
147 #define FLAGS_DUMMY_READ (1<<9)
148 #define FLAGS_MDC_MDIO_WA_B0 (1<<10)
149 #define FLAGS_TX_ERROR_CHECK (1<<12)
151 /* preemphasis values for the rx side */
152 u16 rx_preemphasis[4];
154 /* preemphasis values for the tx side */
155 u16 tx_preemphasis[4];
157 /* EMAC address for access MDIO */
158 u32 mdio_ctrl;
160 u32 supported;
162 u32 media_type;
163 #define ETH_PHY_UNSPECIFIED 0x0
164 #define ETH_PHY_SFP_FIBER 0x1
165 #define ETH_PHY_XFP_FIBER 0x2
166 #define ETH_PHY_DA_TWINAX 0x3
167 #define ETH_PHY_BASE_T 0x4
168 #define ETH_PHY_KR 0xf0
169 #define ETH_PHY_CX4 0xf1
170 #define ETH_PHY_NOT_PRESENT 0xff
172 /* The address in which version is located*/
173 u32 ver_addr;
175 u16 req_flow_ctrl;
177 u16 req_line_speed;
179 u32 speed_cap_mask;
181 u16 req_duplex;
182 u16 rsrv;
183 /* Called per phy/port init, and it configures LASI, speed, autoneg,
184 duplex, flow control negotiation, etc. */
185 config_init_t config_init;
187 /* Called due to interrupt. It determines the link, speed */
188 read_status_t read_status;
190 /* Called when driver is unloading. Should reset the phy */
191 link_reset_t link_reset;
193 /* Set the loopback configuration for the phy */
194 config_loopback_t config_loopback;
196 /* Format the given raw number into str up to len */
197 format_fw_ver_t format_fw_ver;
199 /* Reset the phy (both ports) */
200 hw_reset_t hw_reset;
202 /* Set link led mode (on/off/oper)*/
203 set_link_led_t set_link_led;
205 /* PHY Specific tasks */
206 phy_specific_func_t phy_specific_func;
207 #define DISABLE_TX 1
208 #define ENABLE_TX 2
211 /* Inputs parameters to the CLC */
212 struct link_params {
214 u8 port;
216 /* Default / User Configuration */
217 u8 loopback_mode;
218 #define LOOPBACK_NONE 0
219 #define LOOPBACK_EMAC 1
220 #define LOOPBACK_BMAC 2
221 #define LOOPBACK_XGXS 3
222 #define LOOPBACK_EXT_PHY 4
223 #define LOOPBACK_EXT 5
224 #define LOOPBACK_UMAC 6
225 #define LOOPBACK_XMAC 7
227 /* Device parameters */
228 u8 mac_addr[6];
230 u16 req_duplex[LINK_CONFIG_SIZE];
231 u16 req_flow_ctrl[LINK_CONFIG_SIZE];
233 u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
235 /* shmem parameters */
236 u32 shmem_base;
237 u32 shmem2_base;
238 u32 speed_cap_mask[LINK_CONFIG_SIZE];
239 u32 switch_cfg;
240 #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
241 #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
242 #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
244 u32 lane_config;
246 /* Phy register parameter */
247 u32 chip_id;
249 /* features */
250 u32 feature_config_flags;
251 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
252 #define FEATURE_CONFIG_PFC_ENABLED (1<<1)
253 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
254 #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
255 #define FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
256 #define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
257 /* Will be populated during common init */
258 struct bnx2x_phy phy[MAX_PHYS];
260 /* Will be populated during common init */
261 u8 num_phys;
263 u8 rsrv;
264 u16 hw_led_mode; /* part of the hw_config read from the shmem */
265 u32 multi_phy_config;
267 /* Device pointer passed to all callback functions */
268 struct bnx2x *bp;
269 u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
270 req_flow_ctrl is set to AUTO */
273 /* Output parameters */
274 struct link_vars {
275 u8 phy_flags;
276 #define PHY_XGXS_FLAG (1<<0)
277 #define PHY_SGMII_FLAG (1<<1)
278 #define PHY_PHYSICAL_LINK_FLAG (1<<2)
279 #define PHY_HALF_OPEN_CONN_FLAG (1<<3)
280 #define PHY_OVER_CURRENT_FLAG (1<<4)
282 u8 mac_type;
283 #define MAC_TYPE_NONE 0
284 #define MAC_TYPE_EMAC 1
285 #define MAC_TYPE_BMAC 2
286 #define MAC_TYPE_UMAC 3
287 #define MAC_TYPE_XMAC 4
289 u8 phy_link_up; /* internal phy link indication */
290 u8 link_up;
292 u16 line_speed;
293 u16 duplex;
295 u16 flow_ctrl;
296 u16 ieee_fc;
298 /* The same definitions as the shmem parameter */
299 u32 link_status;
300 u8 fault_detected;
301 u8 rsrv1;
302 u16 periodic_flags;
303 #define PERIODIC_FLAGS_LINK_EVENT 0x0001
305 u32 aeu_int_mask;
306 u8 rx_tx_asic_rst;
307 u8 turn_to_run_wc_rt;
308 u16 rsrv2;
311 /***********************************************************/
312 /* Functions */
313 /***********************************************************/
314 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);
316 /* Reset the link. Should be called when driver or interface goes down
317 Before calling phy firmware upgrade, the reset_ext_phy should be set
318 to 0 */
319 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
320 u8 reset_ext_phy);
322 /* bnx2x_link_update should be called upon link interrupt */
323 int bnx2x_link_update(struct link_params *params, struct link_vars *vars);
325 /* use the following phy functions to read/write from external_phy
326 In order to use it to read/write internal phy registers, use
327 DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
328 the register */
329 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
330 u8 devad, u16 reg, u16 *ret_val);
332 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
333 u8 devad, u16 reg, u16 val);
335 /* Reads the link_status from the shmem,
336 and update the link vars accordingly */
337 void bnx2x_link_status_update(struct link_params *input,
338 struct link_vars *output);
339 /* returns string representing the fw_version of the external phy */
340 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
341 u8 *version, u16 len);
343 /* Set/Unset the led
344 Basically, the CLC takes care of the led for the link, but in case one needs
345 to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
346 blink the led, and LED_MODE_OFF to set the led off.*/
347 int bnx2x_set_led(struct link_params *params,
348 struct link_vars *vars, u8 mode, u32 speed);
349 #define LED_MODE_OFF 0
350 #define LED_MODE_ON 1
351 #define LED_MODE_OPER 2
352 #define LED_MODE_FRONT_PANEL_OFF 3
354 /* bnx2x_handle_module_detect_int should be called upon module detection
355 interrupt */
356 void bnx2x_handle_module_detect_int(struct link_params *params);
358 /* Get the actual link status. In case it returns 0, link is up,
359 otherwise link is down*/
360 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
361 u8 is_serdes);
363 /* One-time initialization for external phy after power up */
364 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
365 u32 shmem2_base_path[], u32 chip_id);
367 /* Reset the external PHY using GPIO */
368 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
370 /* Reset the external of SFX7101 */
371 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
373 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
374 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
375 struct link_params *params, u16 addr,
376 u8 byte_cnt, u8 *o_buf);
378 void bnx2x_hw_reset_phy(struct link_params *params);
380 /* Checks if HW lock is required for this phy/board type */
381 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
382 u32 shmem2_base);
384 /* Check swap bit and adjust PHY order */
385 u32 bnx2x_phy_selection(struct link_params *params);
387 /* Probe the phys on board, and populate them in "params" */
388 int bnx2x_phy_probe(struct link_params *params);
390 /* Checks if fan failure detection is required on one of the phys on board */
391 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
392 u32 shmem2_base, u8 port);
396 /* DCBX structs */
398 /* Number of maximum COS per chip */
399 #define DCBX_E2E3_MAX_NUM_COS (2)
400 #define DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
401 #define DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
402 #define DCBX_E3B0_MAX_NUM_COS ( \
403 MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
404 DCBX_E3B0_MAX_NUM_COS_PORT1))
406 #define DCBX_MAX_NUM_COS ( \
407 MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
408 DCBX_E2E3_MAX_NUM_COS))
410 /* PFC port configuration params */
411 struct bnx2x_nig_brb_pfc_port_params {
412 /* NIG */
413 u32 pause_enable;
414 u32 llfc_out_en;
415 u32 llfc_enable;
416 u32 pkt_priority_to_cos;
417 u8 num_of_rx_cos_priority_mask;
418 u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
419 u32 llfc_high_priority_classes;
420 u32 llfc_low_priority_classes;
421 /* BRB */
422 u32 cos0_pauseable;
423 u32 cos1_pauseable;
427 /* ETS port configuration params */
428 struct bnx2x_ets_bw_params {
429 u8 bw;
432 struct bnx2x_ets_sp_params {
434 * valid values are 0 - 5. 0 is highest strict priority.
435 * There can't be two COS's with the same pri.
437 u8 pri;
440 enum bnx2x_cos_state {
441 bnx2x_cos_state_strict = 0,
442 bnx2x_cos_state_bw = 1,
445 struct bnx2x_ets_cos_params {
446 enum bnx2x_cos_state state ;
447 union {
448 struct bnx2x_ets_bw_params bw_params;
449 struct bnx2x_ets_sp_params sp_params;
450 } params;
453 struct bnx2x_ets_params {
454 u8 num_of_cos; /* Number of valid COS entries*/
455 struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
459 * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
460 * when link is already up
462 int bnx2x_update_pfc(struct link_params *params,
463 struct link_vars *vars,
464 struct bnx2x_nig_brb_pfc_port_params *pfc_params);
467 /* Used to configure the ETS to disable */
468 int bnx2x_ets_disabled(struct link_params *params,
469 struct link_vars *vars);
471 /* Used to configure the ETS to BW limited */
472 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
473 const u32 cos1_bw);
475 /* Used to configure the ETS to strict */
476 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
479 /* Configure the COS to ETS according to BW and SP settings.*/
480 int bnx2x_ets_e3b0_config(const struct link_params *params,
481 const struct link_vars *vars,
482 struct bnx2x_ets_params *ets_params);
483 /* Read pfc statistic*/
484 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
485 u32 pfc_frames_sent[2],
486 u32 pfc_frames_received[2]);
487 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
488 u32 chip_id, u32 shmem_base, u32 shmem2_base,
489 u8 port);
491 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
492 struct link_params *params);
494 void bnx2x_period_func(struct link_params *params, struct link_vars *vars);
496 #endif /* BNX2X_LINK_H */