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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
blob0fcb45624796c29942a30125439d6eeb5ab1d407
1 /*
2 * Copyright (C) 2005 - 2011 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 #include "be.h"
19 #include "be_cmds.h"
20
21 /* Must be a power of 2 or else MODULO will BUG_ON */
22 static int be_get_temp_freq = 64;
23
24 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
25 {
26 return wrb->payload.embedded_payload;
27 }
28
29 static void be_mcc_notify(struct be_adapter *adapter)
30 {
31 struct be_queue_info *mccq = &adapter->mcc_obj.q;
32 u32 val = 0;
33
34 if (be_error(adapter))
35 return;
36
37 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
38 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
39
40 wmb();
41 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
42 }
43
44 /* To check if valid bit is set, check the entire word as we don't know
45 * the endianness of the data (old entry is host endian while a new entry is
46 * little endian) */
47 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
48 {
49 if (compl->flags != 0) {
50 compl->flags = le32_to_cpu(compl->flags);
51 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
52 return true;
53 } else {
54 return false;
55 }
56 }
57
58 /* Need to reset the entire word that houses the valid bit */
59 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
60 {
61 compl->flags = 0;
62 }
63
64 static int be_mcc_compl_process(struct be_adapter *adapter,
65 struct be_mcc_compl *compl)
66 {
67 u16 compl_status, extd_status;
68
69 /* Just swap the status to host endian; mcc tag is opaquely copied
70 * from mcc_wrb */
71 be_dws_le_to_cpu(compl, 4);
72
73 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
74 CQE_STATUS_COMPL_MASK;
75
76 if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
77 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
78 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
79 adapter->flash_status = compl_status;
80 complete(&adapter->flash_compl);
81 }
82
83 if (compl_status == MCC_STATUS_SUCCESS) {
84 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
85 (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
86 (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
87 be_parse_stats(adapter);
88 adapter->stats_cmd_sent = false;
89 }
90 if (compl->tag0 ==
91 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) {
92 struct be_mcc_wrb *mcc_wrb =
93 queue_index_node(&adapter->mcc_obj.q,
94 compl->tag1);
95 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
96 embedded_payload(mcc_wrb);
97 adapter->drv_stats.be_on_die_temperature =
98 resp->on_die_temperature;
99 }
100 } else {
101 if (compl->tag0 == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
102 be_get_temp_freq = 0;
103
104 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
105 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
106 goto done;
107
108 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
109 dev_warn(&adapter->pdev->dev, "This domain(VM) is not "
110 "permitted to execute this cmd (opcode %d)\n",
111 compl->tag0);
112 } else {
113 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
114 CQE_STATUS_EXTD_MASK;
115 dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:"
116 "status %d, extd-status %d\n",
117 compl->tag0, compl_status, extd_status);
118 }
119 }
120 done:
121 return compl_status;
122 }
123
124 /* Link state evt is a string of bytes; no need for endian swapping */
125 static void be_async_link_state_process(struct be_adapter *adapter,
126 struct be_async_event_link_state *evt)
127 {
128 /* When link status changes, link speed must be re-queried from FW */
129 adapter->link_speed = -1;
130
131 /* For the initial link status do not rely on the ASYNC event as
132 * it may not be received in some cases.
133 */
134 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
135 be_link_status_update(adapter, evt->port_link_status);
136 }
137
138 /* Grp5 CoS Priority evt */
139 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
140 struct be_async_event_grp5_cos_priority *evt)
141 {
142 if (evt->valid) {
143 adapter->vlan_prio_bmap = evt->available_priority_bmap;
144 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
145 adapter->recommended_prio =
146 evt->reco_default_priority << VLAN_PRIO_SHIFT;
147 }
148 }
149
150 /* Grp5 QOS Speed evt */
151 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
152 struct be_async_event_grp5_qos_link_speed *evt)
153 {
154 if (evt->physical_port == adapter->port_num) {
155 /* qos_link_speed is in units of 10 Mbps */
156 adapter->link_speed = evt->qos_link_speed * 10;
157 }
158 }
159
160 /*Grp5 PVID evt*/
161 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
162 struct be_async_event_grp5_pvid_state *evt)
163 {
164 if (evt->enabled)
165 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
166 else
167 adapter->pvid = 0;
168 }
169
170 static void be_async_grp5_evt_process(struct be_adapter *adapter,
171 u32 trailer, struct be_mcc_compl *evt)
172 {
173 u8 event_type = 0;
174
175 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
176 ASYNC_TRAILER_EVENT_TYPE_MASK;
177
178 switch (event_type) {
179 case ASYNC_EVENT_COS_PRIORITY:
180 be_async_grp5_cos_priority_process(adapter,
181 (struct be_async_event_grp5_cos_priority *)evt);
182 break;
183 case ASYNC_EVENT_QOS_SPEED:
184 be_async_grp5_qos_speed_process(adapter,
185 (struct be_async_event_grp5_qos_link_speed *)evt);
186 break;
187 case ASYNC_EVENT_PVID_STATE:
188 be_async_grp5_pvid_state_process(adapter,
189 (struct be_async_event_grp5_pvid_state *)evt);
190 break;
191 default:
192 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
193 break;
194 }
195 }
196
197 static inline bool is_link_state_evt(u32 trailer)
198 {
199 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
200 ASYNC_TRAILER_EVENT_CODE_MASK) ==
201 ASYNC_EVENT_CODE_LINK_STATE;
202 }
203
204 static inline bool is_grp5_evt(u32 trailer)
205 {
206 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
207 ASYNC_TRAILER_EVENT_CODE_MASK) ==
208 ASYNC_EVENT_CODE_GRP_5);
209 }
210
211 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
212 {
213 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
214 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
215
216 if (be_mcc_compl_is_new(compl)) {
217 queue_tail_inc(mcc_cq);
218 return compl;
219 }
220 return NULL;
221 }
222
223 void be_async_mcc_enable(struct be_adapter *adapter)
224 {
225 spin_lock_bh(&adapter->mcc_cq_lock);
226
227 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
228 adapter->mcc_obj.rearm_cq = true;
229
230 spin_unlock_bh(&adapter->mcc_cq_lock);
231 }
232
233 void be_async_mcc_disable(struct be_adapter *adapter)
234 {
235 adapter->mcc_obj.rearm_cq = false;
236 }
237
238 int be_process_mcc(struct be_adapter *adapter, int *status)
239 {
240 struct be_mcc_compl *compl;
241 int num = 0;
242 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
243
244 spin_lock_bh(&adapter->mcc_cq_lock);
245 while ((compl = be_mcc_compl_get(adapter))) {
246 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
247 /* Interpret flags as an async trailer */
248 if (is_link_state_evt(compl->flags))
249 be_async_link_state_process(adapter,
250 (struct be_async_event_link_state *) compl);
251 else if (is_grp5_evt(compl->flags))
252 be_async_grp5_evt_process(adapter,
253 compl->flags, compl);
254 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
255 *status = be_mcc_compl_process(adapter, compl);
256 atomic_dec(&mcc_obj->q.used);
257 }
258 be_mcc_compl_use(compl);
259 num++;
260 }
261
262 spin_unlock_bh(&adapter->mcc_cq_lock);
263 return num;
264 }
265
266 /* Wait till no more pending mcc requests are present */
267 static int be_mcc_wait_compl(struct be_adapter *adapter)
268 {
269 #define mcc_timeout 120000 /* 12s timeout */
270 int i, num, status = 0;
271 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
272
273 for (i = 0; i < mcc_timeout; i++) {
274 if (be_error(adapter))
275 return -EIO;
276
277 num = be_process_mcc(adapter, &status);
278 if (num)
279 be_cq_notify(adapter, mcc_obj->cq.id,
280 mcc_obj->rearm_cq, num);
281
282 if (atomic_read(&mcc_obj->q.used) == 0)
283 break;
284 udelay(100);
285 }
286 if (i == mcc_timeout) {
287 dev_err(&adapter->pdev->dev, "FW not responding\n");
288 adapter->fw_timeout = true;
289 return -1;
290 }
291 return status;
292 }
293
294 /* Notify MCC requests and wait for completion */
295 static int be_mcc_notify_wait(struct be_adapter *adapter)
296 {
297 be_mcc_notify(adapter);
298 return be_mcc_wait_compl(adapter);
299 }
300
301 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
302 {
303 int msecs = 0;
304 u32 ready;
305
306 do {
307 if (be_error(adapter))
308 return -EIO;
309
310 ready = ioread32(db);
311 if (ready == 0xffffffff)
312 return -1;
313
314 ready &= MPU_MAILBOX_DB_RDY_MASK;
315 if (ready)
316 break;
317
318 if (msecs > 4000) {
319 dev_err(&adapter->pdev->dev, "FW not responding\n");
320 adapter->fw_timeout = true;
321 be_detect_dump_ue(adapter);
322 return -1;
323 }
324
325 msleep(1);
326 msecs++;
327 } while (true);
328
329 return 0;
330 }
331
332 /*
333 * Insert the mailbox address into the doorbell in two steps
334 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
335 */
336 static int be_mbox_notify_wait(struct be_adapter *adapter)
337 {
338 int status;
339 u32 val = 0;
340 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
341 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
342 struct be_mcc_mailbox *mbox = mbox_mem->va;
343 struct be_mcc_compl *compl = &mbox->compl;
344
345 /* wait for ready to be set */
346 status = be_mbox_db_ready_wait(adapter, db);
347 if (status != 0)
348 return status;
349
350 val |= MPU_MAILBOX_DB_HI_MASK;
351 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
352 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
353 iowrite32(val, db);
354
355 /* wait for ready to be set */
356 status = be_mbox_db_ready_wait(adapter, db);
357 if (status != 0)
358 return status;
359
360 val = 0;
361 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
362 val |= (u32)(mbox_mem->dma >> 4) << 2;
363 iowrite32(val, db);
364
365 status = be_mbox_db_ready_wait(adapter, db);
366 if (status != 0)
367 return status;
368
369 /* A cq entry has been made now */
370 if (be_mcc_compl_is_new(compl)) {
371 status = be_mcc_compl_process(adapter, &mbox->compl);
372 be_mcc_compl_use(compl);
373 if (status)
374 return status;
375 } else {
376 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
377 return -1;
378 }
379 return 0;
380 }
381
382 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
383 {
384 u32 sem;
385
386 if (lancer_chip(adapter))
387 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
388 else
389 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
390
391 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
392 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
393 return -1;
394 else
395 return 0;
396 }
397
398 int be_cmd_POST(struct be_adapter *adapter)
399 {
400 u16 stage;
401 int status, timeout = 0;
402 struct device *dev = &adapter->pdev->dev;
403
404 do {
405 status = be_POST_stage_get(adapter, &stage);
406 if (status) {
407 dev_err(dev, "POST error; stage=0x%x\n", stage);
408 return -1;
409 } else if (stage != POST_STAGE_ARMFW_RDY) {
410 if (msleep_interruptible(2000)) {
411 dev_err(dev, "Waiting for POST aborted\n");
412 return -EINTR;
413 }
414 timeout += 2;
415 } else {
416 return 0;
417 }
418 } while (timeout < 60);
419
420 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
421 return -1;
422 }
423
424
425 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
426 {
427 return &wrb->payload.sgl[0];
428 }
429
430
431 /* Don't touch the hdr after it's prepared */
432 /* mem will be NULL for embedded commands */
433 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
434 u8 subsystem, u8 opcode, int cmd_len,
435 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
436 {
437 struct be_sge *sge;
438
439 req_hdr->opcode = opcode;
440 req_hdr->subsystem = subsystem;
441 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
442 req_hdr->version = 0;
443
444 wrb->tag0 = opcode;
445 wrb->tag1 = subsystem;
446 wrb->payload_length = cmd_len;
447 if (mem) {
448 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
449 MCC_WRB_SGE_CNT_SHIFT;
450 sge = nonembedded_sgl(wrb);
451 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
452 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
453 sge->len = cpu_to_le32(mem->size);
454 } else
455 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
456 be_dws_cpu_to_le(wrb, 8);
457 }
458
459 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
460 struct be_dma_mem *mem)
461 {
462 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
463 u64 dma = (u64)mem->dma;
464
465 for (i = 0; i < buf_pages; i++) {
466 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
467 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
468 dma += PAGE_SIZE_4K;
469 }
470 }
471
472 /* Converts interrupt delay in microseconds to multiplier value */
473 static u32 eq_delay_to_mult(u32 usec_delay)
474 {
475 #define MAX_INTR_RATE 651042
476 const u32 round = 10;
477 u32 multiplier;
478
479 if (usec_delay == 0)
480 multiplier = 0;
481 else {
482 u32 interrupt_rate = 1000000 / usec_delay;
483 /* Max delay, corresponding to the lowest interrupt rate */
484 if (interrupt_rate == 0)
485 multiplier = 1023;
486 else {
487 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
488 multiplier /= interrupt_rate;
489 /* Round the multiplier to the closest value.*/
490 multiplier = (multiplier + round/2) / round;
491 multiplier = min(multiplier, (u32)1023);
492 }
493 }
494 return multiplier;
495 }
496
497 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
498 {
499 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
500 struct be_mcc_wrb *wrb
501 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
502 memset(wrb, 0, sizeof(*wrb));
503 return wrb;
504 }
505
506 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
507 {
508 struct be_queue_info *mccq = &adapter->mcc_obj.q;
509 struct be_mcc_wrb *wrb;
510
511 if (atomic_read(&mccq->used) >= mccq->len) {
512 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
513 return NULL;
514 }
515
516 wrb = queue_head_node(mccq);
517 queue_head_inc(mccq);
518 atomic_inc(&mccq->used);
519 memset(wrb, 0, sizeof(*wrb));
520 return wrb;
521 }
522
523 /* Tell fw we're about to start firing cmds by writing a
524 * special pattern across the wrb hdr; uses mbox
525 */
526 int be_cmd_fw_init(struct be_adapter *adapter)
527 {
528 u8 *wrb;
529 int status;
530
531 if (mutex_lock_interruptible(&adapter->mbox_lock))
532 return -1;
533
534 wrb = (u8 *)wrb_from_mbox(adapter);
535 *wrb++ = 0xFF;
536 *wrb++ = 0x12;
537 *wrb++ = 0x34;
538 *wrb++ = 0xFF;
539 *wrb++ = 0xFF;
540 *wrb++ = 0x56;
541 *wrb++ = 0x78;
542 *wrb = 0xFF;
543
544 status = be_mbox_notify_wait(adapter);
545
546 mutex_unlock(&adapter->mbox_lock);
547 return status;
548 }
549
550 /* Tell fw we're done with firing cmds by writing a
551 * special pattern across the wrb hdr; uses mbox
552 */
553 int be_cmd_fw_clean(struct be_adapter *adapter)
554 {
555 u8 *wrb;
556 int status;
557
558 if (mutex_lock_interruptible(&adapter->mbox_lock))
559 return -1;
560
561 wrb = (u8 *)wrb_from_mbox(adapter);
562 *wrb++ = 0xFF;
563 *wrb++ = 0xAA;
564 *wrb++ = 0xBB;
565 *wrb++ = 0xFF;
566 *wrb++ = 0xFF;
567 *wrb++ = 0xCC;
568 *wrb++ = 0xDD;
569 *wrb = 0xFF;
570
571 status = be_mbox_notify_wait(adapter);
572
573 mutex_unlock(&adapter->mbox_lock);
574 return status;
575 }
576 int be_cmd_eq_create(struct be_adapter *adapter,
577 struct be_queue_info *eq, int eq_delay)
578 {
579 struct be_mcc_wrb *wrb;
580 struct be_cmd_req_eq_create *req;
581 struct be_dma_mem *q_mem = &eq->dma_mem;
582 int status;
583
584 if (mutex_lock_interruptible(&adapter->mbox_lock))
585 return -1;
586
587 wrb = wrb_from_mbox(adapter);
588 req = embedded_payload(wrb);
589
590 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
591 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
592
593 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
594
595 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
596 /* 4byte eqe*/
597 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
598 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
599 __ilog2_u32(eq->len/256));
600 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
601 eq_delay_to_mult(eq_delay));
602 be_dws_cpu_to_le(req->context, sizeof(req->context));
603
604 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
605
606 status = be_mbox_notify_wait(adapter);
607 if (!status) {
608 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
609 eq->id = le16_to_cpu(resp->eq_id);
610 eq->created = true;
611 }
612
613 mutex_unlock(&adapter->mbox_lock);
614 return status;
615 }
616
617 /* Use MCC */
618 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
619 u8 type, bool permanent, u32 if_handle, u32 pmac_id)
620 {
621 struct be_mcc_wrb *wrb;
622 struct be_cmd_req_mac_query *req;
623 int status;
624
625 spin_lock_bh(&adapter->mcc_lock);
626
627 wrb = wrb_from_mccq(adapter);
628 if (!wrb) {
629 status = -EBUSY;
630 goto err;
631 }
632 req = embedded_payload(wrb);
633
634 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
635 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
636 req->type = type;
637 if (permanent) {
638 req->permanent = 1;
639 } else {
640 req->if_id = cpu_to_le16((u16) if_handle);
641 req->pmac_id = cpu_to_le32(pmac_id);
642 req->permanent = 0;
643 }
644
645 status = be_mcc_notify_wait(adapter);
646 if (!status) {
647 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
648 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
649 }
650
651 err:
652 spin_unlock_bh(&adapter->mcc_lock);
653 return status;
654 }
655
656 /* Uses synchronous MCCQ */
657 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
658 u32 if_id, u32 *pmac_id, u32 domain)
659 {
660 struct be_mcc_wrb *wrb;
661 struct be_cmd_req_pmac_add *req;
662 int status;
663
664 spin_lock_bh(&adapter->mcc_lock);
665
666 wrb = wrb_from_mccq(adapter);
667 if (!wrb) {
668 status = -EBUSY;
669 goto err;
670 }
671 req = embedded_payload(wrb);
672
673 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
674 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
675
676 req->hdr.domain = domain;
677 req->if_id = cpu_to_le32(if_id);
678 memcpy(req->mac_address, mac_addr, ETH_ALEN);
679
680 status = be_mcc_notify_wait(adapter);
681 if (!status) {
682 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
683 *pmac_id = le32_to_cpu(resp->pmac_id);
684 }
685
686 err:
687 spin_unlock_bh(&adapter->mcc_lock);
688
689 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
690 status = -EPERM;
691
692 return status;
693 }
694
695 /* Uses synchronous MCCQ */
696 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
697 {
698 struct be_mcc_wrb *wrb;
699 struct be_cmd_req_pmac_del *req;
700 int status;
701
702 if (pmac_id == -1)
703 return 0;
704
705 spin_lock_bh(&adapter->mcc_lock);
706
707 wrb = wrb_from_mccq(adapter);
708 if (!wrb) {
709 status = -EBUSY;
710 goto err;
711 }
712 req = embedded_payload(wrb);
713
714 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
715 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
716
717 req->hdr.domain = dom;
718 req->if_id = cpu_to_le32(if_id);
719 req->pmac_id = cpu_to_le32(pmac_id);
720
721 status = be_mcc_notify_wait(adapter);
722
723 err:
724 spin_unlock_bh(&adapter->mcc_lock);
725 return status;
726 }
727
728 /* Uses Mbox */
729 int be_cmd_cq_create(struct be_adapter *adapter,
730 struct be_queue_info *cq, struct be_queue_info *eq,
731 bool sol_evts, bool no_delay, int coalesce_wm)
732 {
733 struct be_mcc_wrb *wrb;
734 struct be_cmd_req_cq_create *req;
735 struct be_dma_mem *q_mem = &cq->dma_mem;
736 void *ctxt;
737 int status;
738
739 if (mutex_lock_interruptible(&adapter->mbox_lock))
740 return -1;
741
742 wrb = wrb_from_mbox(adapter);
743 req = embedded_payload(wrb);
744 ctxt = &req->context;
745
746 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
747 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
748
749 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
750 if (lancer_chip(adapter)) {
751 req->hdr.version = 2;
752 req->page_size = 1; /* 1 for 4K */
753 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
754 no_delay);
755 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
756 __ilog2_u32(cq->len/256));
757 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
758 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
759 ctxt, 1);
760 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
761 ctxt, eq->id);
762 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
763 } else {
764 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
765 coalesce_wm);
766 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
767 ctxt, no_delay);
768 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
769 __ilog2_u32(cq->len/256));
770 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
771 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
772 ctxt, sol_evts);
773 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
774 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
775 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
776 }
777
778 be_dws_cpu_to_le(ctxt, sizeof(req->context));
779
780 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
781
782 status = be_mbox_notify_wait(adapter);
783 if (!status) {
784 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
785 cq->id = le16_to_cpu(resp->cq_id);
786 cq->created = true;
787 }
788
789 mutex_unlock(&adapter->mbox_lock);
790
791 return status;
792 }
793
794 static u32 be_encoded_q_len(int q_len)
795 {
796 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
797 if (len_encoded == 16)
798 len_encoded = 0;
799 return len_encoded;
800 }
801
802 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
803 struct be_queue_info *mccq,
804 struct be_queue_info *cq)
805 {
806 struct be_mcc_wrb *wrb;
807 struct be_cmd_req_mcc_ext_create *req;
808 struct be_dma_mem *q_mem = &mccq->dma_mem;
809 void *ctxt;
810 int status;
811
812 if (mutex_lock_interruptible(&adapter->mbox_lock))
813 return -1;
814
815 wrb = wrb_from_mbox(adapter);
816 req = embedded_payload(wrb);
817 ctxt = &req->context;
818
819 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
820 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
821
822 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
823 if (lancer_chip(adapter)) {
824 req->hdr.version = 1;
825 req->cq_id = cpu_to_le16(cq->id);
826
827 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
828 be_encoded_q_len(mccq->len));
829 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
830 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
831 ctxt, cq->id);
832 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
833 ctxt, 1);
834
835 } else {
836 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
837 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
838 be_encoded_q_len(mccq->len));
839 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
840 }
841
842 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
843 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
844 be_dws_cpu_to_le(ctxt, sizeof(req->context));
845
846 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
847
848 status = be_mbox_notify_wait(adapter);
849 if (!status) {
850 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
851 mccq->id = le16_to_cpu(resp->id);
852 mccq->created = true;
853 }
854 mutex_unlock(&adapter->mbox_lock);
855
856 return status;
857 }
858
859 int be_cmd_mccq_org_create(struct be_adapter *adapter,
860 struct be_queue_info *mccq,
861 struct be_queue_info *cq)
862 {
863 struct be_mcc_wrb *wrb;
864 struct be_cmd_req_mcc_create *req;
865 struct be_dma_mem *q_mem = &mccq->dma_mem;
866 void *ctxt;
867 int status;
868
869 if (mutex_lock_interruptible(&adapter->mbox_lock))
870 return -1;
871
872 wrb = wrb_from_mbox(adapter);
873 req = embedded_payload(wrb);
874 ctxt = &req->context;
875
876 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
877 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
878
879 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
880
881 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
882 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
883 be_encoded_q_len(mccq->len));
884 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
885
886 be_dws_cpu_to_le(ctxt, sizeof(req->context));
887
888 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
889
890 status = be_mbox_notify_wait(adapter);
891 if (!status) {
892 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
893 mccq->id = le16_to_cpu(resp->id);
894 mccq->created = true;
895 }
896
897 mutex_unlock(&adapter->mbox_lock);
898 return status;
899 }
900
901 int be_cmd_mccq_create(struct be_adapter *adapter,
902 struct be_queue_info *mccq,
903 struct be_queue_info *cq)
904 {
905 int status;
906
907 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
908 if (status && !lancer_chip(adapter)) {
909 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
910 "or newer to avoid conflicting priorities between NIC "
911 "and FCoE traffic");
912 status = be_cmd_mccq_org_create(adapter, mccq, cq);
913 }
914 return status;
915 }
916
917 int be_cmd_txq_create(struct be_adapter *adapter,
918 struct be_queue_info *txq,
919 struct be_queue_info *cq)
920 {
921 struct be_mcc_wrb *wrb;
922 struct be_cmd_req_eth_tx_create *req;
923 struct be_dma_mem *q_mem = &txq->dma_mem;
924 void *ctxt;
925 int status;
926
927 spin_lock_bh(&adapter->mcc_lock);
928
929 wrb = wrb_from_mccq(adapter);
930 if (!wrb) {
931 status = -EBUSY;
932 goto err;
933 }
934
935 req = embedded_payload(wrb);
936 ctxt = &req->context;
937
938 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
939 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
940
941 if (lancer_chip(adapter)) {
942 req->hdr.version = 1;
943 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
944 adapter->if_handle);
945 }
946
947 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
948 req->ulp_num = BE_ULP1_NUM;
949 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
950
951 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
952 be_encoded_q_len(txq->len));
953 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
954 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
955
956 be_dws_cpu_to_le(ctxt, sizeof(req->context));
957
958 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
959
960 status = be_mcc_notify_wait(adapter);
961 if (!status) {
962 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
963 txq->id = le16_to_cpu(resp->cid);
964 txq->created = true;
965 }
966
967 err:
968 spin_unlock_bh(&adapter->mcc_lock);
969
970 return status;
971 }
972
973 /* Uses MCC */
974 int be_cmd_rxq_create(struct be_adapter *adapter,
975 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
976 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
977 {
978 struct be_mcc_wrb *wrb;
979 struct be_cmd_req_eth_rx_create *req;
980 struct be_dma_mem *q_mem = &rxq->dma_mem;
981 int status;
982
983 spin_lock_bh(&adapter->mcc_lock);
984
985 wrb = wrb_from_mccq(adapter);
986 if (!wrb) {
987 status = -EBUSY;
988 goto err;
989 }
990 req = embedded_payload(wrb);
991
992 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
993 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
994
995 req->cq_id = cpu_to_le16(cq_id);
996 req->frag_size = fls(frag_size) - 1;
997 req->num_pages = 2;
998 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
999 req->interface_id = cpu_to_le32(if_id);
1000 req->max_frame_size = cpu_to_le16(max_frame_size);
1001 req->rss_queue = cpu_to_le32(rss);
1002
1003 status = be_mcc_notify_wait(adapter);
1004 if (!status) {
1005 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1006 rxq->id = le16_to_cpu(resp->id);
1007 rxq->created = true;
1008 *rss_id = resp->rss_id;
1009 }
1010
1011 err:
1012 spin_unlock_bh(&adapter->mcc_lock);
1013 return status;
1014 }
1015
1016 /* Generic destroyer function for all types of queues
1017 * Uses Mbox
1018 */
1019 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1020 int queue_type)
1021 {
1022 struct be_mcc_wrb *wrb;
1023 struct be_cmd_req_q_destroy *req;
1024 u8 subsys = 0, opcode = 0;
1025 int status;
1026
1027 if (mutex_lock_interruptible(&adapter->mbox_lock))
1028 return -1;
1029
1030 wrb = wrb_from_mbox(adapter);
1031 req = embedded_payload(wrb);
1032
1033 switch (queue_type) {
1034 case QTYPE_EQ:
1035 subsys = CMD_SUBSYSTEM_COMMON;
1036 opcode = OPCODE_COMMON_EQ_DESTROY;
1037 break;
1038 case QTYPE_CQ:
1039 subsys = CMD_SUBSYSTEM_COMMON;
1040 opcode = OPCODE_COMMON_CQ_DESTROY;
1041 break;
1042 case QTYPE_TXQ:
1043 subsys = CMD_SUBSYSTEM_ETH;
1044 opcode = OPCODE_ETH_TX_DESTROY;
1045 break;
1046 case QTYPE_RXQ:
1047 subsys = CMD_SUBSYSTEM_ETH;
1048 opcode = OPCODE_ETH_RX_DESTROY;
1049 break;
1050 case QTYPE_MCCQ:
1051 subsys = CMD_SUBSYSTEM_COMMON;
1052 opcode = OPCODE_COMMON_MCC_DESTROY;
1053 break;
1054 default:
1055 BUG();
1056 }
1057
1058 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1059 NULL);
1060 req->id = cpu_to_le16(q->id);
1061
1062 status = be_mbox_notify_wait(adapter);
1063 if (!status)
1064 q->created = false;
1065
1066 mutex_unlock(&adapter->mbox_lock);
1067 return status;
1068 }
1069
1070 /* Uses MCC */
1071 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1072 {
1073 struct be_mcc_wrb *wrb;
1074 struct be_cmd_req_q_destroy *req;
1075 int status;
1076
1077 spin_lock_bh(&adapter->mcc_lock);
1078
1079 wrb = wrb_from_mccq(adapter);
1080 if (!wrb) {
1081 status = -EBUSY;
1082 goto err;
1083 }
1084 req = embedded_payload(wrb);
1085
1086 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1087 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1088 req->id = cpu_to_le16(q->id);
1089
1090 status = be_mcc_notify_wait(adapter);
1091 if (!status)
1092 q->created = false;
1093
1094 err:
1095 spin_unlock_bh(&adapter->mcc_lock);
1096 return status;
1097 }
1098
1099 /* Create an rx filtering policy configuration on an i/f
1100 * Uses MCCQ
1101 */
1102 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1103 u8 *mac, u32 *if_handle, u32 *pmac_id, u32 domain)
1104 {
1105 struct be_mcc_wrb *wrb;
1106 struct be_cmd_req_if_create *req;
1107 int status;
1108
1109 spin_lock_bh(&adapter->mcc_lock);
1110
1111 wrb = wrb_from_mccq(adapter);
1112 if (!wrb) {
1113 status = -EBUSY;
1114 goto err;
1115 }
1116 req = embedded_payload(wrb);
1117
1118 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1119 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1120 req->hdr.domain = domain;
1121 req->capability_flags = cpu_to_le32(cap_flags);
1122 req->enable_flags = cpu_to_le32(en_flags);
1123 if (mac)
1124 memcpy(req->mac_addr, mac, ETH_ALEN);
1125 else
1126 req->pmac_invalid = true;
1127
1128 status = be_mcc_notify_wait(adapter);
1129 if (!status) {
1130 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1131 *if_handle = le32_to_cpu(resp->interface_id);
1132 if (mac)
1133 *pmac_id = le32_to_cpu(resp->pmac_id);
1134 }
1135
1136 err:
1137 spin_unlock_bh(&adapter->mcc_lock);
1138 return status;
1139 }
1140
1141 /* Uses MCCQ */
1142 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1143 {
1144 struct be_mcc_wrb *wrb;
1145 struct be_cmd_req_if_destroy *req;
1146 int status;
1147
1148 if (interface_id == -1)
1149 return 0;
1150
1151 spin_lock_bh(&adapter->mcc_lock);
1152
1153 wrb = wrb_from_mccq(adapter);
1154 if (!wrb) {
1155 status = -EBUSY;
1156 goto err;
1157 }
1158 req = embedded_payload(wrb);
1159
1160 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1161 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1162 req->hdr.domain = domain;
1163 req->interface_id = cpu_to_le32(interface_id);
1164
1165 status = be_mcc_notify_wait(adapter);
1166 err:
1167 spin_unlock_bh(&adapter->mcc_lock);
1168 return status;
1169 }
1170
1171 /* Get stats is a non embedded command: the request is not embedded inside
1172 * WRB but is a separate dma memory block
1173 * Uses asynchronous MCC
1174 */
1175 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1176 {
1177 struct be_mcc_wrb *wrb;
1178 struct be_cmd_req_hdr *hdr;
1179 int status = 0;
1180
1181 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1182 be_cmd_get_die_temperature(adapter);
1183
1184 spin_lock_bh(&adapter->mcc_lock);
1185
1186 wrb = wrb_from_mccq(adapter);
1187 if (!wrb) {
1188 status = -EBUSY;
1189 goto err;
1190 }
1191 hdr = nonemb_cmd->va;
1192
1193 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1194 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1195
1196 if (adapter->generation == BE_GEN3)
1197 hdr->version = 1;
1198
1199 be_mcc_notify(adapter);
1200 adapter->stats_cmd_sent = true;
1201
1202 err:
1203 spin_unlock_bh(&adapter->mcc_lock);
1204 return status;
1205 }
1206
1207 /* Lancer Stats */
1208 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1209 struct be_dma_mem *nonemb_cmd)
1210 {
1211
1212 struct be_mcc_wrb *wrb;
1213 struct lancer_cmd_req_pport_stats *req;
1214 int status = 0;
1215
1216 spin_lock_bh(&adapter->mcc_lock);
1217
1218 wrb = wrb_from_mccq(adapter);
1219 if (!wrb) {
1220 status = -EBUSY;
1221 goto err;
1222 }
1223 req = nonemb_cmd->va;
1224
1225 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1226 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1227 nonemb_cmd);
1228
1229 req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1230 req->cmd_params.params.reset_stats = 0;
1231
1232 be_mcc_notify(adapter);
1233 adapter->stats_cmd_sent = true;
1234
1235 err:
1236 spin_unlock_bh(&adapter->mcc_lock);
1237 return status;
1238 }
1239
1240 /* Uses synchronous mcc */
1241 int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1242 u16 *link_speed, u8 *link_status, u32 dom)
1243 {
1244 struct be_mcc_wrb *wrb;
1245 struct be_cmd_req_link_status *req;
1246 int status;
1247
1248 spin_lock_bh(&adapter->mcc_lock);
1249
1250 if (link_status)
1251 *link_status = LINK_DOWN;
1252
1253 wrb = wrb_from_mccq(adapter);
1254 if (!wrb) {
1255 status = -EBUSY;
1256 goto err;
1257 }
1258 req = embedded_payload(wrb);
1259
1260 if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
1261 req->hdr.version = 1;
1262
1263 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1264 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1265
1266 status = be_mcc_notify_wait(adapter);
1267 if (!status) {
1268 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1269 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1270 if (link_speed)
1271 *link_speed = le16_to_cpu(resp->link_speed);
1272 if (mac_speed)
1273 *mac_speed = resp->mac_speed;
1274 }
1275 if (link_status)
1276 *link_status = resp->logical_link_status;
1277 }
1278
1279 err:
1280 spin_unlock_bh(&adapter->mcc_lock);
1281 return status;
1282 }
1283
1284 /* Uses synchronous mcc */
1285 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1286 {
1287 struct be_mcc_wrb *wrb;
1288 struct be_cmd_req_get_cntl_addnl_attribs *req;
1289 u16 mccq_index;
1290 int status;
1291
1292 spin_lock_bh(&adapter->mcc_lock);
1293
1294 mccq_index = adapter->mcc_obj.q.head;
1295
1296 wrb = wrb_from_mccq(adapter);
1297 if (!wrb) {
1298 status = -EBUSY;
1299 goto err;
1300 }
1301 req = embedded_payload(wrb);
1302
1303 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1304 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1305 wrb, NULL);
1306
1307 wrb->tag1 = mccq_index;
1308
1309 be_mcc_notify(adapter);
1310
1311 err:
1312 spin_unlock_bh(&adapter->mcc_lock);
1313 return status;
1314 }
1315
1316 /* Uses synchronous mcc */
1317 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1318 {
1319 struct be_mcc_wrb *wrb;
1320 struct be_cmd_req_get_fat *req;
1321 int status;
1322
1323 spin_lock_bh(&adapter->mcc_lock);
1324
1325 wrb = wrb_from_mccq(adapter);
1326 if (!wrb) {
1327 status = -EBUSY;
1328 goto err;
1329 }
1330 req = embedded_payload(wrb);
1331
1332 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1333 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1334 req->fat_operation = cpu_to_le32(QUERY_FAT);
1335 status = be_mcc_notify_wait(adapter);
1336 if (!status) {
1337 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1338 if (log_size && resp->log_size)
1339 *log_size = le32_to_cpu(resp->log_size) -
1340 sizeof(u32);
1341 }
1342 err:
1343 spin_unlock_bh(&adapter->mcc_lock);
1344 return status;
1345 }
1346
1347 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1348 {
1349 struct be_dma_mem get_fat_cmd;
1350 struct be_mcc_wrb *wrb;
1351 struct be_cmd_req_get_fat *req;
1352 u32 offset = 0, total_size, buf_size,
1353 log_offset = sizeof(u32), payload_len;
1354 int status;
1355
1356 if (buf_len == 0)
1357 return;
1358
1359 total_size = buf_len;
1360
1361 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1362 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1363 get_fat_cmd.size,
1364 &get_fat_cmd.dma);
1365 if (!get_fat_cmd.va) {
1366 status = -ENOMEM;
1367 dev_err(&adapter->pdev->dev,
1368 "Memory allocation failure while retrieving FAT data\n");
1369 return;
1370 }
1371
1372 spin_lock_bh(&adapter->mcc_lock);
1373
1374 while (total_size) {
1375 buf_size = min(total_size, (u32)60*1024);
1376 total_size -= buf_size;
1377
1378 wrb = wrb_from_mccq(adapter);
1379 if (!wrb) {
1380 status = -EBUSY;
1381 goto err;
1382 }
1383 req = get_fat_cmd.va;
1384
1385 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1386 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1387 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1388 &get_fat_cmd);
1389
1390 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1391 req->read_log_offset = cpu_to_le32(log_offset);
1392 req->read_log_length = cpu_to_le32(buf_size);
1393 req->data_buffer_size = cpu_to_le32(buf_size);
1394
1395 status = be_mcc_notify_wait(adapter);
1396 if (!status) {
1397 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1398 memcpy(buf + offset,
1399 resp->data_buffer,
1400 le32_to_cpu(resp->read_log_length));
1401 } else {
1402 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1403 goto err;
1404 }
1405 offset += buf_size;
1406 log_offset += buf_size;
1407 }
1408 err:
1409 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1410 get_fat_cmd.va,
1411 get_fat_cmd.dma);
1412 spin_unlock_bh(&adapter->mcc_lock);
1413 }
1414
1415 /* Uses synchronous mcc */
1416 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1417 char *fw_on_flash)
1418 {
1419 struct be_mcc_wrb *wrb;
1420 struct be_cmd_req_get_fw_version *req;
1421 int status;
1422
1423 spin_lock_bh(&adapter->mcc_lock);
1424
1425 wrb = wrb_from_mccq(adapter);
1426 if (!wrb) {
1427 status = -EBUSY;
1428 goto err;
1429 }
1430
1431 req = embedded_payload(wrb);
1432
1433 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1434 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1435 status = be_mcc_notify_wait(adapter);
1436 if (!status) {
1437 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1438 strcpy(fw_ver, resp->firmware_version_string);
1439 if (fw_on_flash)
1440 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1441 }
1442 err:
1443 spin_unlock_bh(&adapter->mcc_lock);
1444 return status;
1445 }
1446
1447 /* set the EQ delay interval of an EQ to specified value
1448 * Uses async mcc
1449 */
1450 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1451 {
1452 struct be_mcc_wrb *wrb;
1453 struct be_cmd_req_modify_eq_delay *req;
1454 int status = 0;
1455
1456 spin_lock_bh(&adapter->mcc_lock);
1457
1458 wrb = wrb_from_mccq(adapter);
1459 if (!wrb) {
1460 status = -EBUSY;
1461 goto err;
1462 }
1463 req = embedded_payload(wrb);
1464
1465 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1466 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1467
1468 req->num_eq = cpu_to_le32(1);
1469 req->delay[0].eq_id = cpu_to_le32(eq_id);
1470 req->delay[0].phase = 0;
1471 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1472
1473 be_mcc_notify(adapter);
1474
1475 err:
1476 spin_unlock_bh(&adapter->mcc_lock);
1477 return status;
1478 }
1479
1480 /* Uses sycnhronous mcc */
1481 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1482 u32 num, bool untagged, bool promiscuous)
1483 {
1484 struct be_mcc_wrb *wrb;
1485 struct be_cmd_req_vlan_config *req;
1486 int status;
1487
1488 spin_lock_bh(&adapter->mcc_lock);
1489
1490 wrb = wrb_from_mccq(adapter);
1491 if (!wrb) {
1492 status = -EBUSY;
1493 goto err;
1494 }
1495 req = embedded_payload(wrb);
1496
1497 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1498 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1499
1500 req->interface_id = if_id;
1501 req->promiscuous = promiscuous;
1502 req->untagged = untagged;
1503 req->num_vlan = num;
1504 if (!promiscuous) {
1505 memcpy(req->normal_vlan, vtag_array,
1506 req->num_vlan * sizeof(vtag_array[0]));
1507 }
1508
1509 status = be_mcc_notify_wait(adapter);
1510
1511 err:
1512 spin_unlock_bh(&adapter->mcc_lock);
1513 return status;
1514 }
1515
1516 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1517 {
1518 struct be_mcc_wrb *wrb;
1519 struct be_dma_mem *mem = &adapter->rx_filter;
1520 struct be_cmd_req_rx_filter *req = mem->va;
1521 int status;
1522
1523 spin_lock_bh(&adapter->mcc_lock);
1524
1525 wrb = wrb_from_mccq(adapter);
1526 if (!wrb) {
1527 status = -EBUSY;
1528 goto err;
1529 }
1530 memset(req, 0, sizeof(*req));
1531 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1532 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1533 wrb, mem);
1534
1535 req->if_id = cpu_to_le32(adapter->if_handle);
1536 if (flags & IFF_PROMISC) {
1537 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1538 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1539 if (value == ON)
1540 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1541 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1542 } else if (flags & IFF_ALLMULTI) {
1543 req->if_flags_mask = req->if_flags =
1544 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1545 } else {
1546 struct netdev_hw_addr *ha;
1547 int i = 0;
1548
1549 req->if_flags_mask = req->if_flags =
1550 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1551
1552 /* Reset mcast promisc mode if already set by setting mask
1553 * and not setting flags field
1554 */
1555 req->if_flags_mask |=
1556 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1557
1558 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1559 netdev_for_each_mc_addr(ha, adapter->netdev)
1560 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1561 }
1562
1563 status = be_mcc_notify_wait(adapter);
1564 err:
1565 spin_unlock_bh(&adapter->mcc_lock);
1566 return status;
1567 }
1568
1569 /* Uses synchrounous mcc */
1570 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1571 {
1572 struct be_mcc_wrb *wrb;
1573 struct be_cmd_req_set_flow_control *req;
1574 int status;
1575
1576 spin_lock_bh(&adapter->mcc_lock);
1577
1578 wrb = wrb_from_mccq(adapter);
1579 if (!wrb) {
1580 status = -EBUSY;
1581 goto err;
1582 }
1583 req = embedded_payload(wrb);
1584
1585 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1586 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1587
1588 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1589 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1590
1591 status = be_mcc_notify_wait(adapter);
1592
1593 err:
1594 spin_unlock_bh(&adapter->mcc_lock);
1595 return status;
1596 }
1597
1598 /* Uses sycn mcc */
1599 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1600 {
1601 struct be_mcc_wrb *wrb;
1602 struct be_cmd_req_get_flow_control *req;
1603 int status;
1604
1605 spin_lock_bh(&adapter->mcc_lock);
1606
1607 wrb = wrb_from_mccq(adapter);
1608 if (!wrb) {
1609 status = -EBUSY;
1610 goto err;
1611 }
1612 req = embedded_payload(wrb);
1613
1614 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1615 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1616
1617 status = be_mcc_notify_wait(adapter);
1618 if (!status) {
1619 struct be_cmd_resp_get_flow_control *resp =
1620 embedded_payload(wrb);
1621 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1622 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1623 }
1624
1625 err:
1626 spin_unlock_bh(&adapter->mcc_lock);
1627 return status;
1628 }
1629
1630 /* Uses mbox */
1631 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1632 u32 *mode, u32 *caps)
1633 {
1634 struct be_mcc_wrb *wrb;
1635 struct be_cmd_req_query_fw_cfg *req;
1636 int status;
1637
1638 if (mutex_lock_interruptible(&adapter->mbox_lock))
1639 return -1;
1640
1641 wrb = wrb_from_mbox(adapter);
1642 req = embedded_payload(wrb);
1643
1644 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1645 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1646
1647 status = be_mbox_notify_wait(adapter);
1648 if (!status) {
1649 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1650 *port_num = le32_to_cpu(resp->phys_port);
1651 *mode = le32_to_cpu(resp->function_mode);
1652 *caps = le32_to_cpu(resp->function_caps);
1653 }
1654
1655 mutex_unlock(&adapter->mbox_lock);
1656 return status;
1657 }
1658
1659 /* Uses mbox */
1660 int be_cmd_reset_function(struct be_adapter *adapter)
1661 {
1662 struct be_mcc_wrb *wrb;
1663 struct be_cmd_req_hdr *req;
1664 int status;
1665
1666 if (mutex_lock_interruptible(&adapter->mbox_lock))
1667 return -1;
1668
1669 wrb = wrb_from_mbox(adapter);
1670 req = embedded_payload(wrb);
1671
1672 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1673 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1674
1675 status = be_mbox_notify_wait(adapter);
1676
1677 mutex_unlock(&adapter->mbox_lock);
1678 return status;
1679 }
1680
1681 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1682 {
1683 struct be_mcc_wrb *wrb;
1684 struct be_cmd_req_rss_config *req;
1685 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1686 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1687 0x3ea83c02, 0x4a110304};
1688 int status;
1689
1690 if (mutex_lock_interruptible(&adapter->mbox_lock))
1691 return -1;
1692
1693 wrb = wrb_from_mbox(adapter);
1694 req = embedded_payload(wrb);
1695
1696 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1697 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1698
1699 req->if_id = cpu_to_le32(adapter->if_handle);
1700 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1701 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1702 memcpy(req->cpu_table, rsstable, table_size);
1703 memcpy(req->hash, myhash, sizeof(myhash));
1704 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1705
1706 status = be_mbox_notify_wait(adapter);
1707
1708 mutex_unlock(&adapter->mbox_lock);
1709 return status;
1710 }
1711
1712 /* Uses sync mcc */
1713 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1714 u8 bcn, u8 sts, u8 state)
1715 {
1716 struct be_mcc_wrb *wrb;
1717 struct be_cmd_req_enable_disable_beacon *req;
1718 int status;
1719
1720 spin_lock_bh(&adapter->mcc_lock);
1721
1722 wrb = wrb_from_mccq(adapter);
1723 if (!wrb) {
1724 status = -EBUSY;
1725 goto err;
1726 }
1727 req = embedded_payload(wrb);
1728
1729 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1730 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1731
1732 req->port_num = port_num;
1733 req->beacon_state = state;
1734 req->beacon_duration = bcn;
1735 req->status_duration = sts;
1736
1737 status = be_mcc_notify_wait(adapter);
1738
1739 err:
1740 spin_unlock_bh(&adapter->mcc_lock);
1741 return status;
1742 }
1743
1744 /* Uses sync mcc */
1745 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1746 {
1747 struct be_mcc_wrb *wrb;
1748 struct be_cmd_req_get_beacon_state *req;
1749 int status;
1750
1751 spin_lock_bh(&adapter->mcc_lock);
1752
1753 wrb = wrb_from_mccq(adapter);
1754 if (!wrb) {
1755 status = -EBUSY;
1756 goto err;
1757 }
1758 req = embedded_payload(wrb);
1759
1760 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1761 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1762
1763 req->port_num = port_num;
1764
1765 status = be_mcc_notify_wait(adapter);
1766 if (!status) {
1767 struct be_cmd_resp_get_beacon_state *resp =
1768 embedded_payload(wrb);
1769 *state = resp->beacon_state;
1770 }
1771
1772 err:
1773 spin_unlock_bh(&adapter->mcc_lock);
1774 return status;
1775 }
1776
1777 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1778 u32 data_size, u32 data_offset, const char *obj_name,
1779 u32 *data_written, u8 *addn_status)
1780 {
1781 struct be_mcc_wrb *wrb;
1782 struct lancer_cmd_req_write_object *req;
1783 struct lancer_cmd_resp_write_object *resp;
1784 void *ctxt = NULL;
1785 int status;
1786
1787 spin_lock_bh(&adapter->mcc_lock);
1788 adapter->flash_status = 0;
1789
1790 wrb = wrb_from_mccq(adapter);
1791 if (!wrb) {
1792 status = -EBUSY;
1793 goto err_unlock;
1794 }
1795
1796 req = embedded_payload(wrb);
1797
1798 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1799 OPCODE_COMMON_WRITE_OBJECT,
1800 sizeof(struct lancer_cmd_req_write_object), wrb,
1801 NULL);
1802
1803 ctxt = &req->context;
1804 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1805 write_length, ctxt, data_size);
1806
1807 if (data_size == 0)
1808 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1809 eof, ctxt, 1);
1810 else
1811 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1812 eof, ctxt, 0);
1813
1814 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1815 req->write_offset = cpu_to_le32(data_offset);
1816 strcpy(req->object_name, obj_name);
1817 req->descriptor_count = cpu_to_le32(1);
1818 req->buf_len = cpu_to_le32(data_size);
1819 req->addr_low = cpu_to_le32((cmd->dma +
1820 sizeof(struct lancer_cmd_req_write_object))
1821 & 0xFFFFFFFF);
1822 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1823 sizeof(struct lancer_cmd_req_write_object)));
1824
1825 be_mcc_notify(adapter);
1826 spin_unlock_bh(&adapter->mcc_lock);
1827
1828 if (!wait_for_completion_timeout(&adapter->flash_compl,
1829 msecs_to_jiffies(12000)))
1830 status = -1;
1831 else
1832 status = adapter->flash_status;
1833
1834 resp = embedded_payload(wrb);
1835 if (!status) {
1836 *data_written = le32_to_cpu(resp->actual_write_len);
1837 } else {
1838 *addn_status = resp->additional_status;
1839 status = resp->status;
1840 }
1841
1842 return status;
1843
1844 err_unlock:
1845 spin_unlock_bh(&adapter->mcc_lock);
1846 return status;
1847 }
1848
1849 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1850 u32 data_size, u32 data_offset, const char *obj_name,
1851 u32 *data_read, u32 *eof, u8 *addn_status)
1852 {
1853 struct be_mcc_wrb *wrb;
1854 struct lancer_cmd_req_read_object *req;
1855 struct lancer_cmd_resp_read_object *resp;
1856 int status;
1857
1858 spin_lock_bh(&adapter->mcc_lock);
1859
1860 wrb = wrb_from_mccq(adapter);
1861 if (!wrb) {
1862 status = -EBUSY;
1863 goto err_unlock;
1864 }
1865
1866 req = embedded_payload(wrb);
1867
1868 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1869 OPCODE_COMMON_READ_OBJECT,
1870 sizeof(struct lancer_cmd_req_read_object), wrb,
1871 NULL);
1872
1873 req->desired_read_len = cpu_to_le32(data_size);
1874 req->read_offset = cpu_to_le32(data_offset);
1875 strcpy(req->object_name, obj_name);
1876 req->descriptor_count = cpu_to_le32(1);
1877 req->buf_len = cpu_to_le32(data_size);
1878 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
1879 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
1880
1881 status = be_mcc_notify_wait(adapter);
1882
1883 resp = embedded_payload(wrb);
1884 if (!status) {
1885 *data_read = le32_to_cpu(resp->actual_read_len);
1886 *eof = le32_to_cpu(resp->eof);
1887 } else {
1888 *addn_status = resp->additional_status;
1889 }
1890
1891 err_unlock:
1892 spin_unlock_bh(&adapter->mcc_lock);
1893 return status;
1894 }
1895
1896 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1897 u32 flash_type, u32 flash_opcode, u32 buf_size)
1898 {
1899 struct be_mcc_wrb *wrb;
1900 struct be_cmd_write_flashrom *req;
1901 int status;
1902
1903 spin_lock_bh(&adapter->mcc_lock);
1904 adapter->flash_status = 0;
1905
1906 wrb = wrb_from_mccq(adapter);
1907 if (!wrb) {
1908 status = -EBUSY;
1909 goto err_unlock;
1910 }
1911 req = cmd->va;
1912
1913 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1914 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
1915
1916 req->params.op_type = cpu_to_le32(flash_type);
1917 req->params.op_code = cpu_to_le32(flash_opcode);
1918 req->params.data_buf_size = cpu_to_le32(buf_size);
1919
1920 be_mcc_notify(adapter);
1921 spin_unlock_bh(&adapter->mcc_lock);
1922
1923 if (!wait_for_completion_timeout(&adapter->flash_compl,
1924 msecs_to_jiffies(40000)))
1925 status = -1;
1926 else
1927 status = adapter->flash_status;
1928
1929 return status;
1930
1931 err_unlock:
1932 spin_unlock_bh(&adapter->mcc_lock);
1933 return status;
1934 }
1935
1936 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1937 int offset)
1938 {
1939 struct be_mcc_wrb *wrb;
1940 struct be_cmd_write_flashrom *req;
1941 int status;
1942
1943 spin_lock_bh(&adapter->mcc_lock);
1944
1945 wrb = wrb_from_mccq(adapter);
1946 if (!wrb) {
1947 status = -EBUSY;
1948 goto err;
1949 }
1950 req = embedded_payload(wrb);
1951
1952 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1953 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
1954
1955 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1956 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1957 req->params.offset = cpu_to_le32(offset);
1958 req->params.data_buf_size = cpu_to_le32(0x4);
1959
1960 status = be_mcc_notify_wait(adapter);
1961 if (!status)
1962 memcpy(flashed_crc, req->params.data_buf, 4);
1963
1964 err:
1965 spin_unlock_bh(&adapter->mcc_lock);
1966 return status;
1967 }
1968
1969 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1970 struct be_dma_mem *nonemb_cmd)
1971 {
1972 struct be_mcc_wrb *wrb;
1973 struct be_cmd_req_acpi_wol_magic_config *req;
1974 int status;
1975
1976 spin_lock_bh(&adapter->mcc_lock);
1977
1978 wrb = wrb_from_mccq(adapter);
1979 if (!wrb) {
1980 status = -EBUSY;
1981 goto err;
1982 }
1983 req = nonemb_cmd->va;
1984
1985 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1986 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
1987 nonemb_cmd);
1988 memcpy(req->magic_mac, mac, ETH_ALEN);
1989
1990 status = be_mcc_notify_wait(adapter);
1991
1992 err:
1993 spin_unlock_bh(&adapter->mcc_lock);
1994 return status;
1995 }
1996
1997 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1998 u8 loopback_type, u8 enable)
1999 {
2000 struct be_mcc_wrb *wrb;
2001 struct be_cmd_req_set_lmode *req;
2002 int status;
2003
2004 spin_lock_bh(&adapter->mcc_lock);
2005
2006 wrb = wrb_from_mccq(adapter);
2007 if (!wrb) {
2008 status = -EBUSY;
2009 goto err;
2010 }
2011
2012 req = embedded_payload(wrb);
2013
2014 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2015 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2016 NULL);
2017
2018 req->src_port = port_num;
2019 req->dest_port = port_num;
2020 req->loopback_type = loopback_type;
2021 req->loopback_state = enable;
2022
2023 status = be_mcc_notify_wait(adapter);
2024 err:
2025 spin_unlock_bh(&adapter->mcc_lock);
2026 return status;
2027 }
2028
2029 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2030 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2031 {
2032 struct be_mcc_wrb *wrb;
2033 struct be_cmd_req_loopback_test *req;
2034 int status;
2035
2036 spin_lock_bh(&adapter->mcc_lock);
2037
2038 wrb = wrb_from_mccq(adapter);
2039 if (!wrb) {
2040 status = -EBUSY;
2041 goto err;
2042 }
2043
2044 req = embedded_payload(wrb);
2045
2046 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2047 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2048 req->hdr.timeout = cpu_to_le32(4);
2049
2050 req->pattern = cpu_to_le64(pattern);
2051 req->src_port = cpu_to_le32(port_num);
2052 req->dest_port = cpu_to_le32(port_num);
2053 req->pkt_size = cpu_to_le32(pkt_size);
2054 req->num_pkts = cpu_to_le32(num_pkts);
2055 req->loopback_type = cpu_to_le32(loopback_type);
2056
2057 status = be_mcc_notify_wait(adapter);
2058 if (!status) {
2059 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2060 status = le32_to_cpu(resp->status);
2061 }
2062
2063 err:
2064 spin_unlock_bh(&adapter->mcc_lock);
2065 return status;
2066 }
2067
2068 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2069 u32 byte_cnt, struct be_dma_mem *cmd)
2070 {
2071 struct be_mcc_wrb *wrb;
2072 struct be_cmd_req_ddrdma_test *req;
2073 int status;
2074 int i, j = 0;
2075
2076 spin_lock_bh(&adapter->mcc_lock);
2077
2078 wrb = wrb_from_mccq(adapter);
2079 if (!wrb) {
2080 status = -EBUSY;
2081 goto err;
2082 }
2083 req = cmd->va;
2084 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2085 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2086
2087 req->pattern = cpu_to_le64(pattern);
2088 req->byte_count = cpu_to_le32(byte_cnt);
2089 for (i = 0; i < byte_cnt; i++) {
2090 req->snd_buff[i] = (u8)(pattern >> (j*8));
2091 j++;
2092 if (j > 7)
2093 j = 0;
2094 }
2095
2096 status = be_mcc_notify_wait(adapter);
2097
2098 if (!status) {
2099 struct be_cmd_resp_ddrdma_test *resp;
2100 resp = cmd->va;
2101 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2102 resp->snd_err) {
2103 status = -1;
2104 }
2105 }
2106
2107 err:
2108 spin_unlock_bh(&adapter->mcc_lock);
2109 return status;
2110 }
2111
2112 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2113 struct be_dma_mem *nonemb_cmd)
2114 {
2115 struct be_mcc_wrb *wrb;
2116 struct be_cmd_req_seeprom_read *req;
2117 struct be_sge *sge;
2118 int status;
2119
2120 spin_lock_bh(&adapter->mcc_lock);
2121
2122 wrb = wrb_from_mccq(adapter);
2123 if (!wrb) {
2124 status = -EBUSY;
2125 goto err;
2126 }
2127 req = nonemb_cmd->va;
2128 sge = nonembedded_sgl(wrb);
2129
2130 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2131 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2132 nonemb_cmd);
2133
2134 status = be_mcc_notify_wait(adapter);
2135
2136 err:
2137 spin_unlock_bh(&adapter->mcc_lock);
2138 return status;
2139 }
2140
2141 int be_cmd_get_phy_info(struct be_adapter *adapter,
2142 struct be_phy_info *phy_info)
2143 {
2144 struct be_mcc_wrb *wrb;
2145 struct be_cmd_req_get_phy_info *req;
2146 struct be_dma_mem cmd;
2147 int status;
2148
2149 spin_lock_bh(&adapter->mcc_lock);
2150
2151 wrb = wrb_from_mccq(adapter);
2152 if (!wrb) {
2153 status = -EBUSY;
2154 goto err;
2155 }
2156 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2157 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2158 &cmd.dma);
2159 if (!cmd.va) {
2160 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2161 status = -ENOMEM;
2162 goto err;
2163 }
2164
2165 req = cmd.va;
2166
2167 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2168 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2169 wrb, &cmd);
2170
2171 status = be_mcc_notify_wait(adapter);
2172 if (!status) {
2173 struct be_phy_info *resp_phy_info =
2174 cmd.va + sizeof(struct be_cmd_req_hdr);
2175 phy_info->phy_type = le16_to_cpu(resp_phy_info->phy_type);
2176 phy_info->interface_type =
2177 le16_to_cpu(resp_phy_info->interface_type);
2178 }
2179 pci_free_consistent(adapter->pdev, cmd.size,
2180 cmd.va, cmd.dma);
2181 err:
2182 spin_unlock_bh(&adapter->mcc_lock);
2183 return status;
2184 }
2185
2186 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2187 {
2188 struct be_mcc_wrb *wrb;
2189 struct be_cmd_req_set_qos *req;
2190 int status;
2191
2192 spin_lock_bh(&adapter->mcc_lock);
2193
2194 wrb = wrb_from_mccq(adapter);
2195 if (!wrb) {
2196 status = -EBUSY;
2197 goto err;
2198 }
2199
2200 req = embedded_payload(wrb);
2201
2202 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2203 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2204
2205 req->hdr.domain = domain;
2206 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2207 req->max_bps_nic = cpu_to_le32(bps);
2208
2209 status = be_mcc_notify_wait(adapter);
2210
2211 err:
2212 spin_unlock_bh(&adapter->mcc_lock);
2213 return status;
2214 }
2215
2216 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2217 {
2218 struct be_mcc_wrb *wrb;
2219 struct be_cmd_req_cntl_attribs *req;
2220 struct be_cmd_resp_cntl_attribs *resp;
2221 int status;
2222 int payload_len = max(sizeof(*req), sizeof(*resp));
2223 struct mgmt_controller_attrib *attribs;
2224 struct be_dma_mem attribs_cmd;
2225
2226 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2227 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2228 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2229 &attribs_cmd.dma);
2230 if (!attribs_cmd.va) {
2231 dev_err(&adapter->pdev->dev,
2232 "Memory allocation failure\n");
2233 return -ENOMEM;
2234 }
2235
2236 if (mutex_lock_interruptible(&adapter->mbox_lock))
2237 return -1;
2238
2239 wrb = wrb_from_mbox(adapter);
2240 if (!wrb) {
2241 status = -EBUSY;
2242 goto err;
2243 }
2244 req = attribs_cmd.va;
2245
2246 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2247 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2248 &attribs_cmd);
2249
2250 status = be_mbox_notify_wait(adapter);
2251 if (!status) {
2252 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2253 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2254 }
2255
2256 err:
2257 mutex_unlock(&adapter->mbox_lock);
2258 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2259 attribs_cmd.dma);
2260 return status;
2261 }
2262
2263 /* Uses mbox */
2264 int be_cmd_req_native_mode(struct be_adapter *adapter)
2265 {
2266 struct be_mcc_wrb *wrb;
2267 struct be_cmd_req_set_func_cap *req;
2268 int status;
2269
2270 if (mutex_lock_interruptible(&adapter->mbox_lock))
2271 return -1;
2272
2273 wrb = wrb_from_mbox(adapter);
2274 if (!wrb) {
2275 status = -EBUSY;
2276 goto err;
2277 }
2278
2279 req = embedded_payload(wrb);
2280
2281 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2282 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2283
2284 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2285 CAPABILITY_BE3_NATIVE_ERX_API);
2286 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2287
2288 status = be_mbox_notify_wait(adapter);
2289 if (!status) {
2290 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2291 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2292 CAPABILITY_BE3_NATIVE_ERX_API;
2293 }
2294 err:
2295 mutex_unlock(&adapter->mbox_lock);
2296 return status;
2297 }
2298
2299 /* Uses synchronous MCCQ */
2300 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain,
2301 u32 *pmac_id)
2302 {
2303 struct be_mcc_wrb *wrb;
2304 struct be_cmd_req_get_mac_list *req;
2305 int status;
2306 int mac_count;
2307
2308 spin_lock_bh(&adapter->mcc_lock);
2309
2310 wrb = wrb_from_mccq(adapter);
2311 if (!wrb) {
2312 status = -EBUSY;
2313 goto err;
2314 }
2315 req = embedded_payload(wrb);
2316
2317 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2318 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2319 wrb, NULL);
2320
2321 req->hdr.domain = domain;
2322
2323 status = be_mcc_notify_wait(adapter);
2324 if (!status) {
2325 struct be_cmd_resp_get_mac_list *resp =
2326 embedded_payload(wrb);
2327 int i;
2328 u8 *ctxt = &resp->context[0][0];
2329 status = -EIO;
2330 mac_count = resp->mac_count;
2331 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
2332 for (i = 0; i < mac_count; i++) {
2333 if (!AMAP_GET_BITS(struct amap_get_mac_list_context,
2334 act, ctxt)) {
2335 *pmac_id = AMAP_GET_BITS
2336 (struct amap_get_mac_list_context,
2337 macid, ctxt);
2338 status = 0;
2339 break;
2340 }
2341 ctxt += sizeof(struct amap_get_mac_list_context) / 8;
2342 }
2343 }
2344
2345 err:
2346 spin_unlock_bh(&adapter->mcc_lock);
2347 return status;
2348 }
2349
2350 /* Uses synchronous MCCQ */
2351 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2352 u8 mac_count, u32 domain)
2353 {
2354 struct be_mcc_wrb *wrb;
2355 struct be_cmd_req_set_mac_list *req;
2356 int status;
2357 struct be_dma_mem cmd;
2358
2359 memset(&cmd, 0, sizeof(struct be_dma_mem));
2360 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2361 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2362 &cmd.dma, GFP_KERNEL);
2363 if (!cmd.va) {
2364 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2365 return -ENOMEM;
2366 }
2367
2368 spin_lock_bh(&adapter->mcc_lock);
2369
2370 wrb = wrb_from_mccq(adapter);
2371 if (!wrb) {
2372 status = -EBUSY;
2373 goto err;
2374 }
2375
2376 req = cmd.va;
2377 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2378 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2379 wrb, &cmd);
2380
2381 req->hdr.domain = domain;
2382 req->mac_count = mac_count;
2383 if (mac_count)
2384 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2385
2386 status = be_mcc_notify_wait(adapter);
2387
2388 err:
2389 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2390 cmd.va, cmd.dma);
2391 spin_unlock_bh(&adapter->mcc_lock);
2392 return status;
2393 }