drivers/net/ethernet/ibm/ehea/ehea.h

   1 /*
   2  *  linux/drivers/net/ehea/ehea.h
   3  *
   4  *  eHEA ethernet device driver for IBM eServer System p
   5  *
   6  *  (C) Copyright IBM Corp. 2006
   7  *
   8  *  Authors:
   9  *       Christoph Raisch <raisch@de.ibm.com>
  10  *       Jan-Bernd Themann <themann@de.ibm.com>
  11  *       Thomas Klein <tklein@de.ibm.com>
  12  *
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2, or (at your option)
  17  * any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28
  29 #ifndef __EHEA_H__
  30 #define __EHEA_H__
  31
  32 #include <linux/module.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <asm/ibmebus.h>
  38 #include <asm/abs_addr.h>
  39 #include <asm/io.h>
  40
  41 #define DRV_NAME        "ehea"
  42 #define DRV_VERSION     "EHEA_0107"
  43
  44 /* eHEA capability flags */
  45 #define DLPAR_PORT_ADD_REM 1
  46 #define DLPAR_MEM_ADD      2
  47 #define DLPAR_MEM_REM      4
  48 #define EHEA_CAPABILITIES  (DLPAR_PORT_ADD_REM | DLPAR_MEM_ADD | DLPAR_MEM_REM)
  49
  50 #define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \
  51         | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
  52
  53 #define EHEA_MAX_ENTRIES_RQ1 32767
  54 #define EHEA_MAX_ENTRIES_RQ2 16383
  55 #define EHEA_MAX_ENTRIES_RQ3 16383
  56 #define EHEA_MAX_ENTRIES_SQ  32767
  57 #define EHEA_MIN_ENTRIES_QP  127
  58
  59 #define EHEA_SMALL_QUEUES
  60
  61 #ifdef EHEA_SMALL_QUEUES
  62 #define EHEA_MAX_CQE_COUNT      1023
  63 #define EHEA_DEF_ENTRIES_SQ     1023
  64 #define EHEA_DEF_ENTRIES_RQ1    1023
  65 #define EHEA_DEF_ENTRIES_RQ2    1023
  66 #define EHEA_DEF_ENTRIES_RQ3    511
  67 #else
  68 #define EHEA_MAX_CQE_COUNT      4080
  69 #define EHEA_DEF_ENTRIES_SQ     4080
  70 #define EHEA_DEF_ENTRIES_RQ1    8160
  71 #define EHEA_DEF_ENTRIES_RQ2    2040
  72 #define EHEA_DEF_ENTRIES_RQ3    2040
  73 #endif
  74
  75 #define EHEA_MAX_ENTRIES_EQ 20
  76
  77 #define EHEA_SG_SQ  2
  78 #define EHEA_SG_RQ1 1
  79 #define EHEA_SG_RQ2 0
  80 #define EHEA_SG_RQ3 0
  81
  82 #define EHEA_MAX_PACKET_SIZE    9022    /* for jumbo frames */
  83 #define EHEA_RQ2_PKT_SIZE       2048
  84 #define EHEA_L_PKT_SIZE         256     /* low latency */
  85
  86 /* Send completion signaling */
  87
  88 /* Protection Domain Identifier */
  89 #define EHEA_PD_ID        0xaabcdeff
  90
  91 #define EHEA_RQ2_THRESHOLD         1
  92 #define EHEA_RQ3_THRESHOLD         4    /* use RQ3 threshold of 2048 bytes */
  93
  94 #define EHEA_SPEED_10G         10000
  95 #define EHEA_SPEED_1G           1000
  96 #define EHEA_SPEED_100M          100
  97 #define EHEA_SPEED_10M            10
  98 #define EHEA_SPEED_AUTONEG         0
  99
 100 /* Broadcast/Multicast registration types */
 101 #define EHEA_BCMC_SCOPE_ALL     0x08
 102 #define EHEA_BCMC_SCOPE_SINGLE  0x00
 103 #define EHEA_BCMC_MULTICAST     0x04
 104 #define EHEA_BCMC_BROADCAST     0x00
 105 #define EHEA_BCMC_UNTAGGED      0x02
 106 #define EHEA_BCMC_TAGGED        0x00
 107 #define EHEA_BCMC_VLANID_ALL    0x01
 108 #define EHEA_BCMC_VLANID_SINGLE 0x00
 109
 110 #define EHEA_CACHE_LINE          128
 111
 112 /* Memory Regions */
 113 #define EHEA_MR_ACC_CTRL       0x00800000
 114
 115 #define EHEA_BUSMAP_START      0x8000000000000000ULL
 116 #define EHEA_INVAL_ADDR        0xFFFFFFFFFFFFFFFFULL
 117 #define EHEA_DIR_INDEX_SHIFT 13                   /* 8k Entries in 64k block */
 118 #define EHEA_TOP_INDEX_SHIFT (EHEA_DIR_INDEX_SHIFT * 2)
 119 #define EHEA_MAP_ENTRIES (1 << EHEA_DIR_INDEX_SHIFT)
 120 #define EHEA_MAP_SIZE (0x10000)                   /* currently fixed map size */
 121 #define EHEA_INDEX_MASK (EHEA_MAP_ENTRIES - 1)
 122
 123
 124 #define EHEA_WATCH_DOG_TIMEOUT 10*HZ
 125
 126 /* utility functions */
 127
 128 void ehea_dump(void *adr, int len, char *msg);
 129
 130 #define EHEA_BMASK(pos, length) (((pos) << 16) + (length))
 131
 132 #define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1))
 133
 134 #define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)
 135
 136 #define EHEA_BMASK_MASK(mask) \
 137         (0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff))
 138
 139 #define EHEA_BMASK_SET(mask, value) \
 140         ((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask))
 141
 142 #define EHEA_BMASK_GET(mask, value) \
 143         (EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask)))
 144
 145 /*
 146  * Generic ehea page
 147  */
 148 struct ehea_page {
 149         u8 entries[PAGE_SIZE];
 150 };
 151
 152 /*
 153  * Generic queue in linux kernel virtual memory
 154  */
 155 struct hw_queue {
 156         u64 current_q_offset;           /* current queue entry */
 157         struct ehea_page **queue_pages; /* array of pages belonging to queue */
 158         u32 qe_size;                    /* queue entry size */
 159         u32 queue_length;               /* queue length allocated in bytes */
 160         u32 pagesize;
 161         u32 toggle_state;               /* toggle flag - per page */
 162         u32 reserved;                   /* 64 bit alignment */
 163 };
 164
 165 /*
 166  * For pSeries this is a 64bit memory address where
 167  * I/O memory is mapped into CPU address space
 168  */
 169 struct h_epa {
 170         void __iomem *addr;
 171 };
 172
 173 struct h_epa_user {
 174         u64 addr;
 175 };
 176
 177 struct h_epas {
 178         struct h_epa kernel;    /* kernel space accessible resource,
 179                                    set to 0 if unused */
 180         struct h_epa_user user; /* user space accessible resource
 181                                    set to 0 if unused */
 182 };
 183
 184 /*
 185  * Memory map data structures
 186  */
 187 struct ehea_dir_bmap
 188 {
 189         u64 ent[EHEA_MAP_ENTRIES];
 190 };
 191 struct ehea_top_bmap
 192 {
 193         struct ehea_dir_bmap *dir[EHEA_MAP_ENTRIES];
 194 };
 195 struct ehea_bmap
 196 {
 197         struct ehea_top_bmap *top[EHEA_MAP_ENTRIES];
 198 };
 199
 200 struct ehea_qp;
 201 struct ehea_cq;
 202 struct ehea_eq;
 203 struct ehea_port;
 204 struct ehea_av;
 205
 206 /*
 207  * Queue attributes passed to ehea_create_qp()
 208  */
 209 struct ehea_qp_init_attr {
 210         /* input parameter */
 211         u32 qp_token;           /* queue token */
 212         u8 low_lat_rq1;
 213         u8 signalingtype;       /* cqe generation flag */
 214         u8 rq_count;            /* num of receive queues */
 215         u8 eqe_gen;             /* eqe generation flag */
 216         u16 max_nr_send_wqes;   /* max number of send wqes */
 217         u16 max_nr_rwqes_rq1;   /* max number of receive wqes */
 218         u16 max_nr_rwqes_rq2;
 219         u16 max_nr_rwqes_rq3;
 220         u8 wqe_size_enc_sq;
 221         u8 wqe_size_enc_rq1;
 222         u8 wqe_size_enc_rq2;
 223         u8 wqe_size_enc_rq3;
 224         u8 swqe_imm_data_len;   /* immediate data length for swqes */
 225         u16 port_nr;
 226         u16 rq2_threshold;
 227         u16 rq3_threshold;
 228         u64 send_cq_handle;
 229         u64 recv_cq_handle;
 230         u64 aff_eq_handle;
 231
 232         /* output parameter */
 233         u32 qp_nr;
 234         u16 act_nr_send_wqes;
 235         u16 act_nr_rwqes_rq1;
 236         u16 act_nr_rwqes_rq2;
 237         u16 act_nr_rwqes_rq3;
 238         u8 act_wqe_size_enc_sq;
 239         u8 act_wqe_size_enc_rq1;
 240         u8 act_wqe_size_enc_rq2;
 241         u8 act_wqe_size_enc_rq3;
 242         u32 nr_sq_pages;
 243         u32 nr_rq1_pages;
 244         u32 nr_rq2_pages;
 245         u32 nr_rq3_pages;
 246         u32 liobn_sq;
 247         u32 liobn_rq1;
 248         u32 liobn_rq2;
 249         u32 liobn_rq3;
 250 };
 251
 252 /*
 253  * Event Queue attributes, passed as parameter
 254  */
 255 struct ehea_eq_attr {
 256         u32 type;
 257         u32 max_nr_of_eqes;
 258         u8 eqe_gen;        /* generate eqe flag */
 259         u64 eq_handle;
 260         u32 act_nr_of_eqes;
 261         u32 nr_pages;
 262         u32 ist1;          /* Interrupt service token */
 263         u32 ist2;
 264         u32 ist3;
 265         u32 ist4;
 266 };
 267
 268
 269 /*
 270  * Event Queue
 271  */
 272 struct ehea_eq {
 273         struct ehea_adapter *adapter;
 274         struct hw_queue hw_queue;
 275         u64 fw_handle;
 276         struct h_epas epas;
 277         spinlock_t spinlock;
 278         struct ehea_eq_attr attr;
 279 };
 280
 281 /*
 282  * HEA Queues
 283  */
 284 struct ehea_qp {
 285         struct ehea_adapter *adapter;
 286         u64 fw_handle;                  /* QP handle for firmware calls */
 287         struct hw_queue hw_squeue;
 288         struct hw_queue hw_rqueue1;
 289         struct hw_queue hw_rqueue2;
 290         struct hw_queue hw_rqueue3;
 291         struct h_epas epas;
 292         struct ehea_qp_init_attr init_attr;
 293 };
 294
 295 /*
 296  * Completion Queue attributes
 297  */
 298 struct ehea_cq_attr {
 299         /* input parameter */
 300         u32 max_nr_of_cqes;
 301         u32 cq_token;
 302         u64 eq_handle;
 303
 304         /* output parameter */
 305         u32 act_nr_of_cqes;
 306         u32 nr_pages;
 307 };
 308
 309 /*
 310  * Completion Queue
 311  */
 312 struct ehea_cq {
 313         struct ehea_adapter *adapter;
 314         u64 fw_handle;
 315         struct hw_queue hw_queue;
 316         struct h_epas epas;
 317         struct ehea_cq_attr attr;
 318 };
 319
 320 /*
 321  * Memory Region
 322  */
 323 struct ehea_mr {
 324         struct ehea_adapter *adapter;
 325         u64 handle;
 326         u64 vaddr;
 327         u32 lkey;
 328 };
 329
 330 /*
 331  * Port state information
 332  */
 333 struct port_stats {
 334         int poll_receive_errors;
 335         int queue_stopped;
 336         int err_tcp_cksum;
 337         int err_ip_cksum;
 338         int err_frame_crc;
 339 };
 340
 341 #define EHEA_IRQ_NAME_SIZE 20
 342
 343 /*
 344  * Queue SKB Array
 345  */
 346 struct ehea_q_skb_arr {
 347         struct sk_buff **arr;           /* skb array for queue */
 348         int len;                        /* array length */
 349         int index;                      /* array index */
 350         int os_skbs;                    /* rq2/rq3 only: outstanding skbs */
 351 };
 352
 353 /*
 354  * Port resources
 355  */
 356 struct ehea_port_res {
 357         struct napi_struct napi;
 358         struct port_stats p_stats;
 359         struct ehea_mr send_mr;         /* send memory region */
 360         struct ehea_mr recv_mr;         /* receive memory region */
 361         struct ehea_port *port;
 362         char int_recv_name[EHEA_IRQ_NAME_SIZE];
 363         char int_send_name[EHEA_IRQ_NAME_SIZE];
 364         struct ehea_qp *qp;
 365         struct ehea_cq *send_cq;
 366         struct ehea_cq *recv_cq;
 367         struct ehea_eq *eq;
 368         struct ehea_q_skb_arr rq1_skba;
 369         struct ehea_q_skb_arr rq2_skba;
 370         struct ehea_q_skb_arr rq3_skba;
 371         struct ehea_q_skb_arr sq_skba;
 372         int sq_skba_size;
 373         int swqe_refill_th;
 374         atomic_t swqe_avail;
 375         int swqe_ll_count;
 376         u32 swqe_id_counter;
 377         u64 tx_packets;
 378         u64 tx_bytes;
 379         u64 rx_packets;
 380         u64 rx_bytes;
 381         int sq_restart_flag;
 382 };
 383
 384
 385 #define EHEA_MAX_PORTS 16
 386
 387 #define EHEA_NUM_PORTRES_FW_HANDLES    6  /* QP handle, SendCQ handle,
 388                                              RecvCQ handle, EQ handle,
 389                                              SendMR handle, RecvMR handle */
 390 #define EHEA_NUM_PORT_FW_HANDLES       1  /* EQ handle */
 391 #define EHEA_NUM_ADAPTER_FW_HANDLES    2  /* MR handle, NEQ handle */
 392
 393 struct ehea_adapter {
 394         u64 handle;
 395         struct platform_device *ofdev;
 396         struct ehea_port *port[EHEA_MAX_PORTS];
 397         struct ehea_eq *neq;       /* notification event queue */
 398         struct tasklet_struct neq_tasklet;
 399         struct ehea_mr mr;
 400         u32 pd;                    /* protection domain */
 401         u64 max_mc_mac;            /* max number of multicast mac addresses */
 402         int active_ports;
 403         struct list_head list;
 404 };
 405
 406
 407 struct ehea_mc_list {
 408         struct list_head list;
 409         u64 macaddr;
 410 };
 411
 412 /* kdump support */
 413 struct ehea_fw_handle_entry {
 414         u64 adh;               /* Adapter Handle */
 415         u64 fwh;               /* Firmware Handle */
 416 };
 417
 418 struct ehea_fw_handle_array {
 419         struct ehea_fw_handle_entry *arr;
 420         int num_entries;
 421         struct mutex lock;
 422 };
 423
 424 struct ehea_bcmc_reg_entry {
 425         u64 adh;               /* Adapter Handle */
 426         u32 port_id;           /* Logical Port Id */
 427         u8 reg_type;           /* Registration Type */
 428         u64 macaddr;
 429 };
 430
 431 struct ehea_bcmc_reg_array {
 432         struct ehea_bcmc_reg_entry *arr;
 433         int num_entries;
 434         spinlock_t lock;
 435 };
 436
 437 #define EHEA_PORT_UP 1
 438 #define EHEA_PORT_DOWN 0
 439 #define EHEA_PHY_LINK_UP 1
 440 #define EHEA_PHY_LINK_DOWN 0
 441 #define EHEA_MAX_PORT_RES 16
 442 struct ehea_port {
 443         struct ehea_adapter *adapter;    /* adapter that owns this port */
 444         struct net_device *netdev;
 445         struct rtnl_link_stats64 stats;
 446         struct ehea_port_res port_res[EHEA_MAX_PORT_RES];
 447         struct platform_device  ofdev; /* Open Firmware Device */
 448         struct ehea_mc_list *mc_list;    /* Multicast MAC addresses */
 449         struct ehea_eq *qp_eq;
 450         struct work_struct reset_task;
 451         struct delayed_work stats_work;
 452         struct mutex port_lock;
 453         char int_aff_name[EHEA_IRQ_NAME_SIZE];
 454         int allmulti;                    /* Indicates IFF_ALLMULTI state */
 455         int promisc;                     /* Indicates IFF_PROMISC state */
 456         int num_mcs;
 457         int resets;
 458         unsigned long flags;
 459         u64 mac_addr;
 460         u32 logical_port_id;
 461         u32 port_speed;
 462         u32 msg_enable;
 463         u32 sig_comp_iv;
 464         u32 state;
 465         u8 phy_link;
 466         u8 full_duplex;
 467         u8 autoneg;
 468         u8 num_def_qps;
 469         wait_queue_head_t swqe_avail_wq;
 470         wait_queue_head_t restart_wq;
 471 };
 472
 473 struct port_res_cfg {
 474         int max_entries_rcq;
 475         int max_entries_scq;
 476         int max_entries_sq;
 477         int max_entries_rq1;
 478         int max_entries_rq2;
 479         int max_entries_rq3;
 480 };
 481
 482 enum ehea_flag_bits {
 483         __EHEA_STOP_XFER,
 484         __EHEA_DISABLE_PORT_RESET
 485 };
 486
 487 void ehea_set_ethtool_ops(struct net_device *netdev);
 488 int ehea_sense_port_attr(struct ehea_port *port);
 489 int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);
 490
 491 #endif  /* __EHEA_H__ */