| blob | 3911401ed65d59ceafe9b28080a6630f4adf6371 |
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/interrupt.h>
40 #include <linux/tcp.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/mii.h>
46 #include <linux/ethtool.h>
47 #include <linux/if_vlan.h>
48 #include <linux/cpu.h>
49 #include <linux/smp.h>
50 #include <linux/pm_qos.h>
51 #include <linux/pm_runtime.h>
52 #include <linux/aer.h>
53 #include <linux/prefetch.h>
77 };
80 u32 ofs;
82 };
98 /* General Registers */
103 /* Interrupt Registers */
106 /* Rx Registers */
122 /* Tx Registers */
139 /* List Terminator */
140 {}
141 };
143 /*
144 * e1000_regdump - register printout routine
145 */
147 {
169 }
173 }
175 /*
176 * e1000e_dump - Print registers, Tx-ring and Rx-ring
177 */
179 {
186 u64 a;
187 u64 b;
194 u64 a;
195 u64 b;
196 u64 c;
197 u64 d;
199 u32 staterr;
205 /* Print netdevice Info */
212 }
214 /* Print Registers */
220 }
222 /* Print Tx Ring Summary */
236 /* Print Tx Ring */
242 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
243 *
244 * Legacy Transmit Descriptor
245 * +--------------------------------------------------------------+
246 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
247 * +--------------------------------------------------------------+
248 * 8 | Special | CSS | Status | CMD | CSO | Length |
249 * +--------------------------------------------------------------+
250 * 63 48 47 36 35 32 31 24 23 16 15 0
251 *
252 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
253 * 63 48 47 40 39 32 31 16 15 8 7 0
254 * +----------------------------------------------------------------+
255 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
256 * +----------------------------------------------------------------+
257 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
258 * +----------------------------------------------------------------+
259 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
260 *
261 * Extended Data Descriptor (DTYP=0x1)
262 * +----------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] |
264 * +----------------------------------------------------------------+
265 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
266 * +----------------------------------------------------------------+
267 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
268 */
269 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
270 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
271 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
283 else
288 i,
300 }
302 /* Print Rx Ring Summary */
303 rx_ring_summary:
309 /* Print Rx Ring */
318 /* [Extended] Packet Split Receive Descriptor Format
319 *
320 * +-----------------------------------------------------+
321 * 0 | Buffer Address 0 [63:0] |
322 * +-----------------------------------------------------+
323 * 8 | Buffer Address 1 [63:0] |
324 * +-----------------------------------------------------+
325 * 16 | Buffer Address 2 [63:0] |
326 * +-----------------------------------------------------+
327 * 24 | Buffer Address 3 [63:0] |
328 * +-----------------------------------------------------+
329 */
330 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
331 /* [Extended] Receive Descriptor (Write-Back) Format
332 *
333 * 63 48 47 32 31 13 12 8 7 4 3 0
334 * +------------------------------------------------------+
335 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
336 * | Checksum | Ident | | Queue | | Type |
337 * +------------------------------------------------------+
338 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
339 * +------------------------------------------------------+
340 * 63 48 47 32 31 20 19 0
341 */
342 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
348 staterr =
355 else
359 /* Descriptor Done */
382 }
383 }
387 /* Extended Receive Descriptor (Read) Format
388 *
389 * +-----------------------------------------------------+
390 * 0 | Buffer Address [63:0] |
391 * +-----------------------------------------------------+
392 * 8 | Reserved |
393 * +-----------------------------------------------------+
394 */
395 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
396 /* Extended Receive Descriptor (Write-Back) Format
397 *
398 * 63 48 47 32 31 24 23 4 3 0
399 * +------------------------------------------------------+
400 * | RSS Hash | | | |
401 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
402 * | Packet | IP | | | Type |
403 * | Checksum | Ident | | | |
404 * +------------------------------------------------------+
405 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
406 * +------------------------------------------------------+
407 * 63 48 47 32 31 20 19 0
408 */
423 else
427 /* Descriptor Done */
445 phys_to_virt
449 }
450 }
451 }
453 exit:
455 }
457 /**
458 * e1000_desc_unused - calculate if we have unused descriptors
459 **/
461 {
466 }
468 /**
469 * e1000_receive_skb - helper function to handle Rx indications
470 * @adapter: board private structure
471 * @status: descriptor status field as written by hardware
472 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
473 * @skb: pointer to sk_buff to be indicated to stack
474 **/
478 {
486 }
488 /**
489 * e1000_rx_checksum - Receive Checksum Offload
490 * @adapter: board private structure
491 * @status_err: receive descriptor status and error fields
492 * @csum: receive descriptor csum field
493 * @sk_buff: socket buffer with received data
494 **/
497 {
503 /* Ignore Checksum bit is set */
506 /* TCP/UDP checksum error bit is set */
508 /* let the stack verify checksum errors */
511 }
513 /* TCP/UDP Checksum has not been calculated */
517 /* It must be a TCP or UDP packet with a valid checksum */
519 /* TCP checksum is good */
522 /*
523 * IP fragment with UDP payload
524 * Hardware complements the payload checksum, so we undo it
525 * and then put the value in host order for further stack use.
526 */
530 }
532 }
534 /**
535 * e1000e_update_tail_wa - helper function for e1000e_update_[rt]dt_wa()
536 * @hw: pointer to the HW structure
537 * @tail: address of tail descriptor register
538 * @i: value to write to tail descriptor register
539 *
540 * When updating the tail register, the ME could be accessing Host CSR
541 * registers at the same time. Normally, this is handled in h/w by an
542 * arbiter but on some parts there is a bug that acknowledges Host accesses
543 * later than it should which could result in the descriptor register to
544 * have an incorrect value. Workaround this by checking the FWSM register
545 * which has bit 24 set while ME is accessing Host CSR registers, wait
546 * if it is set and try again a number of times.
547 **/
550 {
563 }
566 {
575 }
576 }
579 {
588 }
589 }
591 /**
592 * e1000_alloc_rx_buffers - Replace used receive buffers
593 * @adapter: address of board private structure
594 **/
597 {
615 }
619 /* Better luck next round */
622 }
625 map_skb:
628 DMA_FROM_DEVICE);
633 }
639 /*
640 * Force memory writes to complete before letting h/w
641 * know there are new descriptors to fetch. (Only
642 * applicable for weak-ordered memory model archs,
643 * such as IA-64).
644 */
648 else
650 }
651 i++;
655 }
658 }
660 /**
661 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
662 * @adapter: address of board private structure
663 **/
666 {
685 /* all unused desc entries get hw null ptr */
689 }
695 }
699 DMA_FROM_DEVICE);
706 }
707 }
708 /*
709 * Refresh the desc even if buffer_addrs
710 * didn't change because each write-back
711 * erases this info.
712 */
715 }
719 gfp);
724 }
729 DMA_FROM_DEVICE);
733 /* cleanup skb */
737 }
742 /*
743 * Force memory writes to complete before letting h/w
744 * know there are new descriptors to fetch. (Only
745 * applicable for weak-ordered memory model archs,
746 * such as IA-64).
747 */
751 else
754 }
756 i++;
760 }
762 no_buffers:
764 }
766 /**
767 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
768 * @adapter: address of board private structure
769 * @cleaned_count: number of buffers to allocate this pass
770 **/
774 {
792 }
796 /* Better luck next round */
799 }
802 check_page:
803 /* allocate a new page if necessary */
809 }
810 }
815 PAGE_SIZE,
816 DMA_FROM_DEVICE);
824 }
831 /* Force memory writes to complete before letting h/w
832 * know there are new descriptors to fetch. (Only
833 * applicable for weak-ordered memory model archs,
834 * such as IA-64). */
838 else
840 }
841 }
843 /**
844 * e1000_clean_rx_irq - Send received data up the network stack; legacy
845 * @adapter: board private structure
846 *
847 * the return value indicates whether actual cleaning was done, there
848 * is no guarantee that everything was cleaned
849 **/
852 {
883 i++;
892 cleaned_count++;
896 DMA_FROM_DEVICE);
901 /*
902 * !EOP means multiple descriptors were used to store a single
903 * packet, if that's the case we need to toss it. In fact, we
904 * need to toss every packet with the EOP bit clear and the
905 * next frame that _does_ have the EOP bit set, as it is by
906 * definition only a frame fragment
907 */
912 /* All receives must fit into a single buffer */
914 /* recycle */
919 }
922 /* recycle */
925 }
927 /* adjust length to remove Ethernet CRC */
932 total_rx_packets++;
934 /*
935 * code added for copybreak, this should improve
936 * performance for small packets with large amounts
937 * of reassembly being done in the stack
938 */
946 NET_IP_ALIGN),
948 NET_IP_ALIGN));
949 /* save the skb in buffer_info as good */
952 }
953 /* else just continue with the old one */
954 }
955 /* end copybreak code */
958 /* Receive Checksum Offload */
966 next_desc:
969 /* return some buffers to hardware, one at a time is too slow */
972 GFP_ATOMIC);
974 }
976 /* use prefetched values */
981 }
991 }
995 {
1000 else
1004 }
1008 }
1010 }
1013 {
1016 print_hang_task);
1024 u16 pci_status;
1031 /* May be block on write-back, flush and detect again
1032 * flush pending descriptor writebacks to memory
1033 */
1035 /* execute the writes immediately */
1039 }
1040 /* Real hang detected */
1050 /* detected Hardware unit hang */
1071 eop,
1072 jiffies,
1075 phy_status,
1076 phy_1000t_status,
1077 phy_ext_status,
1078 pci_status);
1079 }
1081 /**
1082 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1083 * @adapter: board private structure
1084 *
1085 * the return value indicates whether actual cleaning was done, there
1086 * is no guarantee that everything was cleaned
1087 **/
1089 {
1118 pkts_compl++;
1119 }
1120 }
1125 i++;
1128 }
1134 }
1140 #define TX_WAKE_THRESHOLD 32
1143 /* Make sure that anybody stopping the queue after this
1144 * sees the new next_to_clean.
1145 */
1152 }
1153 }
1156 /*
1157 * Detect a transmit hang in hardware, this serializes the
1158 * check with the clearing of time_stamp and movement of i
1159 */
1166 else
1168 }
1172 }
1174 /**
1175 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1176 * @adapter: board private structure
1177 *
1178 * the return value indicates whether actual cleaning was done, there
1179 * is no guarantee that everything was cleaned
1180 **/
1183 {
1210 /* in the packet split case this is header only */
1213 i++;
1222 cleaned_count++;
1227 /* see !EOP comment in other Rx routine */
1237 }
1242 }
1250 }
1252 /* Good Receive */
1255 {
1256 /*
1257 * this looks ugly, but it seems compiler issues make it
1258 * more efficient than reusing j
1259 */
1262 /*
1263 * page alloc/put takes too long and effects small packet
1264 * throughput, so unsplit small packets and save the alloc/put
1265 * only valid in softirq (napi) context to call kmap_*
1266 */
1273 /*
1274 * there is no documentation about how to call
1275 * kmap_atomic, so we can't hold the mapping
1276 * very long
1277 */
1286 /* remove the CRC */
1293 }
1302 DMA_FROM_DEVICE);
1309 }
1311 /* strip the ethernet crc, problem is we're using pages now so
1312 * this whole operation can get a little cpu intensive
1313 */
1317 copydone:
1319 total_rx_packets++;
1331 next_desc:
1335 /* return some buffers to hardware, one at a time is too slow */
1338 GFP_ATOMIC);
1340 }
1342 /* use prefetched values */
1347 }
1357 }
1359 /**
1360 * e1000_consume_page - helper function
1361 **/
1363 u16 length)
1364 {
1369 }
1371 /**
1372 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1373 * @adapter: board private structure
1374 *
1375 * the return value indicates whether actual cleaning was done, there
1376 * is no guarantee that everything was cleaned
1377 **/
1381 {
1418 cleaned_count++;
1420 DMA_FROM_DEVICE);
1425 /* errors is only valid for DD + EOP descriptors */
1428 /* recycle both page and skb */
1430 /* an error means any chain goes out the window too */
1435 }
1437 #define rxtop (rx_ring->rx_skb_top)
1439 /* this descriptor is only the beginning (or middle) */
1441 /* this is the beginning of a chain */
1446 /* this is the middle of a chain */
1450 /* re-use the skb, only consumed the page */
1452 }
1457 /* end of the chain */
1461 /* re-use the current skb, we only consumed the
1462 * page */
1468 /* no chain, got EOP, this buf is the packet
1469 * copybreak to save the put_page/alloc_page */
1474 KM_SKB_DATA_SOFTIRQ);
1476 length);
1478 KM_SKB_DATA_SOFTIRQ);
1479 /* re-use the page, so don't erase
1480 * buffer_info->page */
1485 length);
1487 length);
1488 }
1489 }
1490 }
1492 /* Receive Checksum Offload XXX recompute due to CRC strip? */
1497 /* probably a little skewed due to removing CRC */
1499 total_rx_packets++;
1501 /* eth type trans needs skb->data to point to something */
1506 }
1511 next_desc:
1514 /* return some buffers to hardware, one at a time is too slow */
1517 GFP_ATOMIC);
1519 }
1521 /* use prefetched values */
1526 }
1536 }
1538 /**
1539 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1540 * @adapter: board private structure
1541 **/
1543 {
1550 /* Free all the Rx ring sk_buffs */
1557 DMA_FROM_DEVICE);
1560 PAGE_SIZE,
1561 DMA_FROM_DEVICE);
1565 DMA_FROM_DEVICE);
1567 }
1572 }
1577 }
1584 DMA_FROM_DEVICE);
1588 }
1589 }
1591 /* there also may be some cached data from a chained receive */
1595 }
1597 /* Zero out the descriptor ring */
1606 }
1609 {
1617 }
1619 /**
1620 * e1000_intr_msi - Interrupt Handler
1621 * @irq: interrupt number
1622 * @data: pointer to a network interface device structure
1623 **/
1625 {
1631 /*
1632 * read ICR disables interrupts using IAM
1633 */
1637 /*
1638 * ICH8 workaround-- Call gig speed drop workaround on cable
1639 * disconnect (LSC) before accessing any PHY registers
1640 */
1645 /*
1646 * 80003ES2LAN workaround-- For packet buffer work-around on
1647 * link down event; disable receives here in the ISR and reset
1648 * adapter in watchdog
1649 */
1652 /* disable receives */
1656 }
1657 /* guard against interrupt when we're going down */
1660 }
1668 }
1671 }
1673 /**
1674 * e1000_intr - Interrupt Handler
1675 * @irq: interrupt number
1676 * @data: pointer to a network interface device structure
1677 **/
1679 {
1688 /*
1689 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1690 * not set, then the adapter didn't send an interrupt
1691 */
1695 /*
1696 * Interrupt Auto-Mask...upon reading ICR,
1697 * interrupts are masked. No need for the
1698 * IMC write
1699 */
1703 /*
1704 * ICH8 workaround-- Call gig speed drop workaround on cable
1705 * disconnect (LSC) before accessing any PHY registers
1706 */
1711 /*
1712 * 80003ES2LAN workaround--
1713 * For packet buffer work-around on link down event;
1714 * disable receives here in the ISR and
1715 * reset adapter in watchdog
1716 */
1719 /* disable receives */
1723 }
1724 /* guard against interrupt when we're going down */
1727 }
1735 }
1738 }
1741 {
1751 }
1760 /* guard against interrupt when we're going down */
1763 }
1765 no_link_interrupt:
1770 }
1774 {
1785 /* Ring was not completely cleaned, so fire another interrupt */
1789 }
1792 {
1796 /* Write the ITR value calculated at the end of the
1797 * previous interrupt.
1798 */
1803 }
1809 }
1811 }
1813 /**
1814 * e1000_configure_msix - Configure MSI-X hardware
1815 *
1816 * e1000_configure_msix sets up the hardware to properly
1817 * generate MSI-X interrupts.
1818 **/
1820 {
1829 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1834 }
1836 #define E1000_IVAR_INT_ALLOC_VALID 0x8
1837 /* Configure Rx vector */
1843 else
1847 /* Configure Tx vector */
1849 vector++;
1853 else
1858 /* set vector for Other Causes, e.g. link changes */
1859 vector++;
1864 else
1867 /* Cause Tx interrupts on every write back */
1872 /* enable MSI-X PBA support */
1876 /* Auto-Mask Other interrupts upon ICR read */
1877 #define E1000_EIAC_MASK_82574 0x01F00000
1882 }
1885 {
1893 }
1894 }
1896 /**
1897 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1898 *
1899 * Attempt to configure interrupts using the best available
1900 * capabilities of the hardware and kernel.
1901 **/
1903 {
1913 GFP_KERNEL);
1923 }
1924 /* MSI-X failed, so fall through and try MSI */
1927 }
1929 /* Fall through */
1936 }
1937 /* Fall through */
1939 /* Don't do anything; this is the system default */
1941 }
1943 /* store the number of vectors being used */
1945 }
1947 /**
1948 * e1000_request_msix - Initialize MSI-X interrupts
1949 *
1950 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1951 * kernel.
1952 **/
1954 {
1962 else
1966 netdev);
1971 vector++;
1977 else
1981 netdev);
1986 vector++;
1995 out:
1997 }
1999 /**
2000 * e1000_request_irq - initialize interrupts
2001 *
2002 * Attempts to configure interrupts using the best available
2003 * capabilities of the hardware and kernel.
2004 **/
2006 {
2014 /* fall back to MSI */
2018 }
2025 /* fall back to legacy interrupt */
2028 }
2036 }
2039 {
2046 vector++;
2049 vector++;
2051 /* Other Causes interrupt vector */
2054 }
2057 }
2059 /**
2060 * e1000_irq_disable - Mask off interrupt generation on the NIC
2061 **/
2063 {
2077 }
2078 }
2080 /**
2081 * e1000_irq_enable - Enable default interrupt generation settings
2082 **/
2084 {
2092 }
2094 }
2096 /**
2097 * e1000e_get_hw_control - get control of the h/w from f/w
2098 * @adapter: address of board private structure
2099 *
2100 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2101 * For ASF and Pass Through versions of f/w this means that
2102 * the driver is loaded. For AMT version (only with 82573)
2103 * of the f/w this means that the network i/f is open.
2104 **/
2106 {
2108 u32 ctrl_ext;
2109 u32 swsm;
2111 /* Let firmware know the driver has taken over */
2118 }
2119 }
2121 /**
2122 * e1000e_release_hw_control - release control of the h/w to f/w
2123 * @adapter: address of board private structure
2124 *
2125 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2126 * For ASF and Pass Through versions of f/w this means that the
2127 * driver is no longer loaded. For AMT version (only with 82573) i
2128 * of the f/w this means that the network i/f is closed.
2129 *
2130 **/
2132 {
2134 u32 ctrl_ext;
2135 u32 swsm;
2137 /* Let firmware taken over control of h/w */
2144 }
2145 }
2147 /**
2148 * @e1000_alloc_ring - allocate memory for a ring structure
2149 **/
2152 {
2156 GFP_KERNEL);
2161 }
2163 /**
2164 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2165 * @adapter: board private structure
2166 *
2167 * Return 0 on success, negative on failure
2168 **/
2170 {
2179 /* round up to nearest 4K */
2191 err:
2195 }
2197 /**
2198 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2199 * @adapter: board private structure
2200 *
2201 * Returns 0 on success, negative on failure
2202 **/
2204 {
2218 GFP_KERNEL);
2221 }
2225 /* Round up to nearest 4K */
2239 err_pages:
2243 }
2244 err:
2248 }
2250 /**
2251 * e1000_clean_tx_ring - Free Tx Buffers
2252 * @adapter: board private structure
2253 **/
2255 {
2264 }
2277 }
2279 /**
2280 * e1000e_free_tx_resources - Free Tx Resources per Queue
2281 * @adapter: board private structure
2282 *
2283 * Free all transmit software resources
2284 **/
2286 {
2298 }
2300 /**
2301 * e1000e_free_rx_resources - Free Rx Resources
2302 * @adapter: board private structure
2303 *
2304 * Free all receive software resources
2305 **/
2308 {
2324 }
2326 /**
2327 * e1000_update_itr - update the dynamic ITR value based on statistics
2328 * @adapter: pointer to adapter
2329 * @itr_setting: current adapter->itr
2330 * @packets: the number of packets during this measurement interval
2331 * @bytes: the number of bytes during this measurement interval
2332 *
2333 * Stores a new ITR value based on packets and byte
2334 * counts during the last interrupt. The advantage of per interrupt
2335 * computation is faster updates and more accurate ITR for the current
2336 * traffic pattern. Constants in this function were computed
2337 * based on theoretical maximum wire speed and thresholds were set based
2338 * on testing data as well as attempting to minimize response time
2339 * while increasing bulk throughput. This functionality is controlled
2340 * by the InterruptThrottleRate module parameter.
2341 **/
2345 {
2353 /* handle TSO and jumbo frames */
2361 /* this if handles the TSO accounting */
2372 }
2380 }
2382 }
2384 update_itr_done:
2386 }
2389 {
2391 u16 current_itr;
2394 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2399 }
2404 }
2410 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2418 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2425 /* counts and packets in update_itr are dependent on these numbers */
2437 }
2439 set_itr_now:
2441 /*
2442 * this attempts to bias the interrupt rate towards Bulk
2443 * by adding intermediate steps when interrupt rate is
2444 * increasing
2445 */
2448 new_itr;
2453 else
2456 else
2458 }
2459 }
2461 /**
2462 * e1000_alloc_queues - Allocate memory for all rings
2463 * @adapter: board private structure to initialize
2464 **/
2466 {
2476 err:
2481 }
2483 /**
2484 * e1000_clean - NAPI Rx polling callback
2485 * @napi: struct associated with this polling callback
2486 * @budget: amount of packets driver is allowed to process this poll
2487 **/
2489 {
2503 clean_rx:
2509 /* If budget not fully consumed, exit the polling mode */
2517 else
2519 }
2520 }
2523 }
2526 {
2531 /* don't update vlan cookie if already programmed */
2533 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2537 /* add VID to filter table */
2543 }
2548 }
2551 {
2557 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2559 /* release control to f/w */
2562 }
2564 /* remove VID from filter table */
2570 }
2575 }
2577 /**
2578 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2579 * @adapter: board private structure to initialize
2580 **/
2582 {
2585 u32 rctl;
2588 /* disable VLAN receive filtering */
2596 }
2597 }
2598 }
2600 /**
2601 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2602 * @adapter: board private structure to initialize
2603 **/
2605 {
2607 u32 rctl;
2610 /* enable VLAN receive filtering */
2615 }
2616 }
2618 /**
2619 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2620 * @adapter: board private structure to initialize
2621 **/
2623 {
2625 u32 ctrl;
2627 /* disable VLAN tag insert/strip */
2631 }
2633 /**
2634 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2635 * @adapter: board private structure to initialize
2636 **/
2638 {
2640 u32 ctrl;
2642 /* enable VLAN tag insert/strip */
2646 }
2649 {
2655 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2658 }
2662 }
2665 {
2666 u16 vid;
2672 }
2675 {
2684 /*
2685 * enable receiving management packets to the host. this will probably
2686 * generate destination unreachable messages from the host OS, but
2687 * the packets will be handled on SMBUS
2688 */
2698 /*
2699 * Check if IPMI pass-through decision filter already exists;
2700 * if so, enable it.
2701 */
2705 /* Ignore filters with anything other than IPMI ports */
2709 /* Enable this decision filter in MANC2H */
2714 }
2719 /* Create new decision filter in an empty filter */
2723 E1000_MDEF_PORT_664));
2725 j++;
2727 }
2732 }
2736 }
2738 /**
2739 * e1000_configure_tx - Configure Transmit Unit after Reset
2740 * @adapter: board private structure
2741 *
2742 * Configure the Tx unit of the MAC after a reset.
2743 **/
2745 {
2748 u64 tdba;
2752 /* Setup the HW Tx Head and Tail descriptor pointers */
2763 /* Set the default values for the Tx Inter Packet Gap timer */
2775 /* Set the Tx Interrupt Delay register */
2777 /* Tx irq moderation */
2783 E1000_TXDCTL_WTHRESH);
2784 /*
2785 * set up some performance related parameters to encourage the
2786 * hardware to use the bus more efficiently in bursts, depends
2787 * on the tx_int_delay to be enabled,
2788 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2789 * hthresh = 1 ==> prefetch when one or more available
2790 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2791 * BEWARE: this seems to work but should be considered first if
2792 * there are Tx hangs or other Tx related bugs
2793 */
2796 /* erratum work around: set txdctl the same for both queues */
2798 }
2800 /* Program the Transmit Control Register */
2808 /*
2809 * set the speed mode bit, we'll clear it if we're not at
2810 * gigabit link later
2811 */
2812 #define SPEED_MODE_BIT (1 << 21)
2815 }
2817 /* errata: program both queues to unweighted RR */
2825 }
2827 /* Setup Transmit Descriptor Settings for eop descriptor */
2830 /* only set IDE if we are delaying interrupts using the timers */
2834 /* enable Report Status bit */
2840 }
2842 /**
2843 * e1000_setup_rctl - configure the receive control registers
2844 * @adapter: Board private structure
2845 **/
2846 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2847 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2849 {
2854 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2856 s32 ret_val;
2860 else
2865 }
2867 /* Program MC offset vector base */
2874 /* Do not Store bad packets */
2877 /* Enable Long Packet receive */
2880 else
2883 /* Some systems expect that the CRC is included in SMBUS traffic. The
2884 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2885 * host memory when this is enabled
2886 */
2890 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2892 u16 phy_data;
2905 }
2907 /* Setup buffer sizes */
2925 }
2927 /* Enable Extended Status in all Receive Descriptors */
2931 /*
2932 * 82571 and greater support packet-split where the protocol
2933 * header is placed in skb->data and the packet data is
2934 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2935 * In the case of a non-split, skb->data is linearly filled,
2936 * followed by the page buffers. Therefore, skb->data is
2937 * sized to hold the largest protocol header.
2938 *
2939 * allocations using alloc_page take too long for regular MTU
2940 * so only enable packet split for jumbo frames
2941 *
2942 * Using pages when the page size is greater than 16k wastes
2943 * a lot of memory, since we allocate 3 pages at all times
2944 * per packet.
2945 */
2950 else
2956 /*
2957 * disable packet split support for IPv6 extension headers,
2958 * because some malformed IPv6 headers can hang the Rx
2959 */
2961 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2963 /* Enable Packet split descriptors */
2967 E1000_PSRCTL_BSIZE0_SHIFT;
2972 E1000_PSRCTL_BSIZE3_SHIFT;
2975 E1000_PSRCTL_BSIZE2_SHIFT;
2978 E1000_PSRCTL_BSIZE1_SHIFT;
2980 }
2983 }
2987 /* just started the receive unit, no need to restart */
2989 }
2991 /**
2992 * e1000_configure_rx - Configure Receive Unit after Reset
2993 * @adapter: board private structure
2994 *
2995 * Configure the Rx unit of the MAC after a reset.
2996 **/
2998 {
3001 u64 rdba;
3005 /* this is a 32 byte descriptor */
3018 }
3020 /* disable receives while setting up the descriptors */
3028 /*
3029 * set the writeback threshold (only takes effect if the RDTR
3030 * is set). set GRAN=1 and write back up to 0x4 worth, and
3031 * enable prefetching of 0x20 Rx descriptors
3032 * granularity = 01
3033 * wthresh = 04,
3034 * hthresh = 04,
3035 * pthresh = 0x20
3036 */
3040 /*
3041 * override the delay timers for enabling bursting, only if
3042 * the value was not set by the user via module options
3043 */
3048 }
3050 /* set the Receive Delay Timer Register */
3053 /* irq moderation */
3059 /* Auto-Mask interrupts upon ICR access */
3065 /*
3066 * Setup the HW Rx Head and Tail Descriptor Pointers and
3067 * the Base and Length of the Rx Descriptor Ring
3068 */
3078 /* Enable Receive Checksum Offload for TCP and UDP */
3083 /*
3084 * IPv4 payload checksum for UDP fragments must be
3085 * used in conjunction with packet-split.
3086 */
3091 /* no need to clear IPPCSE as it defaults to 0 */
3092 }
3095 /*
3096 * Enable early receives on supported devices, only takes effect when
3097 * packet size is equal or larger than the specified value (in 8 byte
3098 * units), e.g. using jumbo frames when setting to E1000_ERT_2048
3099 */
3107 /*
3108 * With jumbo frames and early-receive enabled,
3109 * excessive C-state transition latencies result in
3110 * dropped transactions.
3111 */
3115 PM_QOS_DEFAULT_VALUE);
3116 }
3117 }
3119 /* Enable Receives */
3121 }
3123 /**
3124 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3125 * @netdev: network interface device structure
3126 *
3127 * Writes multicast address list to the MTA hash table.
3128 * Returns: -ENOMEM on failure
3129 * 0 on no addresses written
3130 * X on writing X addresses to MTA
3131 */
3133 {
3141 /* nothing to program, so clear mc list */
3144 }
3150 /* update_mc_addr_list expects a packed array of only addresses. */
3159 }
3161 /**
3162 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3163 * @netdev: network interface device structure
3164 *
3165 * Writes unicast address list to the RAR table.
3166 * Returns: -ENOMEM on failure/insufficient address space
3167 * 0 on no addresses written
3168 * X on writing X addresses to the RAR table
3169 **/
3171 {
3177 /* save a rar entry for our hardware address */
3178 rar_entries--;
3180 /* save a rar entry for the LAA workaround */
3182 rar_entries--;
3184 /* return ENOMEM indicating insufficient memory for addresses */
3191 /*
3192 * write the addresses in reverse order to avoid write
3193 * combining
3194 */
3199 count++;
3200 }
3201 }
3203 /* zero out the remaining RAR entries not used above */
3207 }
3211 }
3213 /**
3214 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3215 * @netdev: network interface device structure
3216 *
3217 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3218 * address list or the network interface flags are updated. This routine is
3219 * responsible for configuring the hardware for proper unicast, multicast,
3220 * promiscuous mode, and all-multi behavior.
3221 **/
3223 {
3226 u32 rctl;
3228 /* Check for Promiscuous and All Multicast modes */
3231 /* clear the affected bits */
3236 /* Do not hardware filter VLANs in promisc mode */
3243 /*
3244 * Write addresses to the MTA, if the attempt fails
3245 * then we should just turn on promiscuous mode so
3246 * that we can at least receive multicast traffic
3247 */
3251 }
3253 /*
3254 * Write addresses to available RAR registers, if there is not
3255 * sufficient space to store all the addresses then enable
3256 * unicast promiscuous mode
3257 */
3261 }
3267 else
3269 }
3271 /**
3272 * e1000_configure - configure the hardware for Rx and Tx
3273 * @adapter: private board structure
3274 **/
3276 {
3286 GFP_KERNEL);
3287 }
3289 /**
3290 * e1000e_power_up_phy - restore link in case the phy was powered down
3291 * @adapter: address of board private structure
3292 *
3293 * The phy may be powered down to save power and turn off link when the
3294 * driver is unloaded and wake on lan is not enabled (among others)
3295 * *** this routine MUST be followed by a call to e1000e_reset ***
3296 **/
3298 {
3303 }
3305 /**
3306 * e1000_power_down_phy - Power down the PHY
3307 *
3308 * Power down the PHY so no link is implied when interface is down.
3309 * The PHY cannot be powered down if management or WoL is active.
3310 */
3312 {
3313 /* WoL is enabled */
3319 }
3321 /**
3322 * e1000e_reset - bring the hardware into a known good state
3323 *
3324 * This function boots the hardware and enables some settings that
3325 * require a configuration cycle of the hardware - those cannot be
3326 * set/changed during runtime. After reset the device needs to be
3327 * properly configured for Rx, Tx etc.
3328 */
3330 {
3336 u16 hwm;
3338 /* reset Packet Buffer Allocation to default */
3342 /*
3343 * To maintain wire speed transmits, the Tx FIFO should be
3344 * large enough to accommodate two full transmit packets,
3345 * rounded up to the next 1KB and expressed in KB. Likewise,
3346 * the Rx FIFO should be large enough to accommodate at least
3347 * one full receive packet and is similarly rounded up and
3348 * expressed in KB.
3349 */
3351 /* upper 16 bits has Tx packet buffer allocation size in KB */
3353 /* lower 16 bits has Rx packet buffer allocation size in KB */
3355 /*
3356 * the Tx fifo also stores 16 bytes of information about the Tx
3357 * but don't include ethernet FCS because hardware appends it
3358 */
3364 /* software strips receive CRC, so leave room for it */
3369 /*
3370 * If current Tx allocation is less than the min Tx FIFO size,
3371 * and the min Tx FIFO size is less than the current Rx FIFO
3372 * allocation, take space away from current Rx allocation
3373 */
3378 /*
3379 * if short on Rx space, Rx wins and must trump Tx
3380 * adjustment or use Early Receive if available
3381 */
3384 /* ERT enabled in e1000_configure_rx */
3386 }
3389 }
3391 /*
3392 * flow control settings
3393 *
3394 * The high water mark must be low enough to fit one full frame
3395 * (or the size used for early receive) above it in the Rx FIFO.
3396 * Set it to the lower of:
3397 * - 90% of the Rx FIFO size, and
3398 * - the full Rx FIFO size minus the early receive size (for parts
3399 * with ERT support assuming ERT set to E1000_ERT_2048), or
3400 * - the full Rx FIFO size minus one full frame
3401 */
3404 else
3415 else
3423 /*
3424 * Workaround PCH LOM adapter hangs with certain network
3425 * loads. If hangs persist, try disabling Tx flow control.
3426 */
3433 }
3444 }
3446 }
3448 /*
3449 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
3450 * fit in receive buffer and early-receive not supported.
3451 */
3460 }
3467 }
3468 }
3470 /* Allow time for pending master requests to run */
3473 /*
3474 * For parts with AMT enabled, let the firmware know
3475 * that the network interface is in control
3476 */
3487 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3496 }
3503 /*
3504 * speed up time to link by disabling smart power down, ignore
3505 * the return value of this function because there is nothing
3506 * different we would do if it failed
3507 */
3511 }
3512 }
3515 {
3518 /* hardware has been reset, we need to reload some things */
3529 /* fire a link change interrupt to start the watchdog */
3532 else
3536 }
3539 {
3545 /* flush pending descriptor writebacks to memory */
3549 /* execute the writes immediately */
3551 }
3556 {
3561 /*
3562 * signal that we're down so the interrupt handler does not
3563 * reschedule our watchdog timer
3564 */
3567 /* disable receives in the hardware */
3571 /* flush and sleep below */
3575 /* disable transmits in the hardware */
3580 /* flush both disables and wait for them to finish */
3605 /*
3606 * TODO: for power management, we could drop the link and
3607 * pci_disable_device here.
3608 */
3609 }
3612 {
3619 }
3621 /**
3622 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3623 * @adapter: board private structure to initialize
3624 *
3625 * e1000_sw_init initializes the Adapter private data structure.
3626 * Fields are initialized based on PCI device information and
3627 * OS network device settings (MTU size).
3628 **/
3630 {
3645 /* Explicitly disable IRQ since the NIC can be in any state. */
3650 }
3652 /**
3653 * e1000_intr_msi_test - Interrupt Handler
3654 * @irq: interrupt number
3655 * @data: pointer to a network interface device structure
3656 **/
3658 {
3668 }
3671 }
3673 /**
3674 * e1000_test_msi_interrupt - Returns 0 for successful test
3675 * @adapter: board private struct
3676 *
3677 * code flow taken from tg3.c
3678 **/
3680 {
3685 /* poll_enable hasn't been called yet, so don't need disable */
3686 /* clear any pending events */
3689 /* free the real vector and request a test handler */
3693 /* Assume that the test fails, if it succeeds then the test
3694 * MSI irq handler will unset this flag */
3706 }
3712 /* fire an unusual interrupt on the test handler */
3730 msi_test_failed:
3733 }
3735 /**
3736 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3737 * @adapter: board private struct
3738 *
3739 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3740 **/
3742 {
3744 u16 pci_cmd;
3749 /* disable SERR in case the MSI write causes a master abort */
3757 /* re-enable SERR */
3762 }
3765 }
3767 /**
3768 * e1000_open - Called when a network interface is made active
3769 * @netdev: network interface device structure
3770 *
3771 * Returns 0 on success, negative value on failure
3772 *
3773 * The open entry point is called when a network interface is made
3774 * active by the system (IFF_UP). At this point all resources needed
3775 * for transmit and receive operations are allocated, the interrupt
3776 * handler is registered with the OS, the watchdog timer is started,
3777 * and the stack is notified that the interface is ready.
3778 **/
3780 {
3786 /* disallow open during test */
3794 /* allocate transmit descriptors */
3799 /* allocate receive descriptors */
3804 /*
3805 * If AMT is enabled, let the firmware know that the network
3806 * interface is now open and reset the part to a known state.
3807 */
3811 }
3817 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3820 /* DMA latency requirement to workaround early-receive/jumbo issue */
3824 PM_QOS_CPU_DMA_LATENCY,
3825 PM_QOS_DEFAULT_VALUE);
3827 /*
3828 * before we allocate an interrupt, we must be ready to handle it.
3829 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3830 * as soon as we call pci_request_irq, so we have to setup our
3831 * clean_rx handler before we do so.
3832 */
3839 /*
3840 * Work around PCIe errata with MSI interrupts causing some chipsets to
3841 * ignore e1000e MSI messages, which means we need to test our MSI
3842 * interrupt now
3843 */
3849 }
3850 }
3852 /* From here on the code is the same as e1000e_up() */
3865 /* fire a link status change interrupt to start the watchdog */
3868 else
3873 err_req_irq:
3877 err_setup_rx:
3879 err_setup_tx:
3884 }
3886 /**
3887 * e1000_close - Disables a network interface
3888 * @netdev: network interface device structure
3889 *
3890 * Returns 0, this is not allowed to fail
3891 *
3892 * The close entry point is called when an interface is de-activated
3893 * by the OS. The hardware is still under the drivers control, but
3894 * needs to be disabled. A global MAC reset is issued to stop the
3895 * hardware, and all transmit and receive resources are freed.
3896 **/
3898 {
3911 }
3917 /*
3918 * kill manageability vlan ID if supported, but not if a vlan with
3919 * the same ID is registered on the host OS (let 8021q kill it)
3920 */
3922 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
3925 /*
3926 * If AMT is enabled, let the firmware know that the network
3927 * interface is now closed
3928 */
3940 }
3941 /**
3942 * e1000_set_mac - Change the Ethernet Address of the NIC
3943 * @netdev: network interface device structure
3944 * @p: pointer to an address structure
3945 *
3946 * Returns 0 on success, negative on failure
3947 **/
3949 {
3962 /* activate the work around */
3965 /*
3966 * Hold a copy of the LAA in RAR[14] This is done so that
3967 * between the time RAR[0] gets clobbered and the time it
3968 * gets fixed (in e1000_watchdog), the actual LAA is in one
3969 * of the RARs and no incoming packets directed to this port
3970 * are dropped. Eventually the LAA will be in RAR[0] and
3971 * RAR[14]
3972 */
3976 }
3979 }
3981 /**
3982 * e1000e_update_phy_task - work thread to update phy
3983 * @work: pointer to our work struct
3984 *
3985 * this worker thread exists because we must acquire a
3986 * semaphore to read the phy, which we could msleep while
3987 * waiting for it, and we can't msleep in a timer.
3988 **/
3990 {
3998 }
4000 /*
4001 * Need to wait a few seconds after link up to get diagnostic information from
4002 * the phy
4003 */
4005 {
4012 }
4014 /**
4015 * e1000e_update_phy_stats - Update the PHY statistics counters
4016 * @adapter: board private structure
4017 *
4018 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4019 **/
4021 {
4023 s32 ret_val;
4024 u16 phy_data;
4030 /*
4031 * A page set is expensive so check if already on desired page.
4032 * If not, set to the page with the PHY status registers.
4033 */
4044 }
4046 /* Single Collision Count */
4052 /* Excessive Collision Count */
4058 /* Multiple Collision Count */
4064 /* Late Collision Count */
4070 /* Collision Count - also used for adaptive IFS */
4076 /* Defer Count */
4082 /* Transmit with no CRS */
4088 release:
4090 }
4092 /**
4093 * e1000e_update_stats - Update the board statistics counters
4094 * @adapter: board private structure
4095 **/
4097 {
4102 /*
4103 * Prevent stats update while adapter is being reset, or if the pci
4104 * connection is down.
4105 */
4121 /* Half-duplex statistics */
4137 }
4139 }
4154 /* used for adaptive IFS */
4165 /* Fill out the OS statistics structure */
4169 /* Rx Errors */
4171 /*
4172 * RLEC on some newer hardware can be incorrect so build
4173 * our own version based on RUC and ROC
4174 */
4185 /* Tx Errors */
4192 /* Tx Dropped needs to be maintained elsewhere */
4194 /* Management Stats */
4198 }
4200 /**
4201 * e1000_phy_read_status - Update the PHY register status snapshot
4202 * @adapter: board private structure
4203 **/
4205 {
4224 /*
4225 * Do not read PHY registers if link is not up
4226 * Set values to typical power-on defaults
4227 */
4231 BMSR_ERCAP);
4239 }
4240 }
4243 {
4247 /* Link status message must follow this format for user tools */
4255 }
4258 {
4263 /*
4264 * get_link_status is set on LSC (link status) interrupt or
4265 * Rx sequence error interrupt. get_link_status will stay
4266 * false until the check_for_link establishes link
4267 * for copper adapters ONLY
4268 */
4276 }
4289 }
4293 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
4295 }
4298 }
4301 {
4302 /* make sure the receive unit is started */
4309 }
4310 }
4313 {
4316 /*
4317 * With 82574 controllers, PHY needs to be checked periodically
4318 * for hung state and reset, if two calls return true
4319 */
4322 else
4328 }
4329 }
4331 /**
4332 * e1000_watchdog - Timer Call-back
4333 * @data: pointer to adapter cast into an unsigned long
4334 **/
4336 {
4339 /* Do the rest outside of interrupt context */
4342 /* TODO: make this use queue_delayed_work() */
4343 }
4346 {
4361 /* Cancel scheduled suspend requests. */
4366 }
4376 /* Cancel scheduled suspend requests. */
4379 /* update snapshot of PHY registers on LSC */
4385 /*
4386 * On supported PHYs, check for duplex mismatch only
4387 * if link has autonegotiated at 10/100 half
4388 */
4395 u16 autoneg_exp;
4400 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
4401 }
4403 /* adjust timeout factor according to speed/duplex */
4414 }
4416 /*
4417 * workaround: re-program speed mode bit after
4418 * link-up event
4419 */
4422 u32 tarc0;
4426 }
4428 /*
4429 * disable TSO for pcie and 10/100 speeds, to avoid
4430 * some hardware issues
4431 */
4445 /* oops */
4447 }
4448 }
4450 /*
4451 * enable transmits in the hardware, need to do this
4452 * after setting TARC(0)
4453 */
4458 /*
4459 * Perform any post-link-up configuration before
4460 * reporting link up.
4461 */
4470 }
4475 /* Link status message must follow this format */
4485 else
4487 LINK_TIMEOUT);
4488 }
4489 }
4491 link_up:
4510 /*
4511 * We've lost link, so the controller stops DMA,
4512 * but we've got queued Tx work that's never going
4513 * to get done, so reset controller to flush Tx.
4514 * (Do the reset outside of interrupt context).
4515 */
4517 /* return immediately since reset is imminent */
4519 }
4521 /* Simple mode for Interrupt Throttle Rate (ITR) */
4523 /*
4524 * Symmetric Tx/Rx gets a reduced ITR=2000;
4525 * Total asymmetrical Tx or Rx gets ITR=8000;
4526 * everyone else is between 2000-8000.
4527 */
4535 }
4537 /* Cause software interrupt to ensure Rx ring is cleaned */
4540 else
4543 /* flush pending descriptors to memory before detecting Tx hang */
4546 /* Force detection of hung controller every watchdog period */
4549 /*
4550 * With 82571 controllers, LAA may be overwritten due to controller
4551 * reset from the other port. Set the appropriate LAA in RAR[0]
4552 */
4559 /* Reset the timer */
4563 }
4565 #define E1000_TX_FLAGS_CSUM 0x00000001
4566 #define E1000_TX_FLAGS_VLAN 0x00000002
4567 #define E1000_TX_FLAGS_TSO 0x00000004
4568 #define E1000_TX_FLAGS_IPV4 0x00000008
4569 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4570 #define E1000_TX_FLAGS_VLAN_SHIFT 16
4574 {
4591 }
4609 }
4636 i++;
4642 }
4645 {
4650 u8 css;
4652 __be16 protocol;
4659 else
4668 /* XXX not handling all IPV6 headers */
4677 }
4696 i++;
4702 }
4704 #define E1000_MAX_PER_TXD 8192
4705 #define E1000_MAX_TXD_PWR 12
4711 {
4737 count++;
4740 i++;
4743 }
4744 }
4754 i++;
4772 count++;
4773 }
4774 }
4777 /* multiply data chunks by size of headers */
4787 dma_error:
4791 count--;
4796 i--;
4799 }
4802 }
4806 {
4815 E1000_TXD_CMD_TSE;
4820 }
4825 }
4830 }
4842 i++;
4849 /*
4850 * Force memory writes to complete before letting h/w
4851 * know there are new descriptors to fetch. (Only
4852 * applicable for weak-ordered memory model archs,
4853 * such as IA-64).
4854 */
4861 else
4864 /*
4865 * we need this if more than one processor can write to our tail
4866 * at a time, it synchronizes IO on IA64/Altix systems
4867 */
4869 }
4871 #define MINIMUM_DHCP_PACKET_SIZE 282
4874 {
4881 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4883 }
4891 {
4905 }
4908 }
4911 {
4915 /*
4916 * Herbert's original patch had:
4917 * smp_mb__after_netif_stop_queue();
4918 * but since that doesn't exist yet, just open code it.
4919 */
4922 /*
4923 * We need to check again in a case another CPU has just
4924 * made room available.
4925 */
4929 /* A reprieve! */
4933 }
4936 {
4942 }
4944 #define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
4947 {
4964 }
4969 }
4972 /*
4973 * The controller does a simple calculation to
4974 * make sure there is enough room in the FIFO before
4975 * initiating the DMA for each buffer. The calc is:
4976 * 4 = ceil(buffer len/mss). To make sure we don't
4977 * overrun the FIFO, adjust the max buffer len if mss
4978 * drops.
4979 */
4981 u8 hdr_len;
4985 /*
4986 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
4987 * points to just header, pull a few bytes of payload from
4988 * frags into skb->data
4989 */
4991 /*
4992 * we do this workaround for ES2LAN, but it is un-necessary,
4993 * avoiding it could save a lot of cycles
4994 */
5003 }
5005 }
5006 }
5008 /* reserve a descriptor for the offload context */
5010 count++;
5011 count++;
5018 max_txd_pwr);
5023 /*
5024 * need: count + 2 desc gap to keep tail from touching
5025 * head, otherwise try next time
5026 */
5033 }
5041 }
5048 /*
5049 * Old method was to assume IPv4 packet by default if TSO was enabled.
5050 * 82571 hardware supports TSO capabilities for IPv6 as well...
5051 * no longer assume, we must.
5052 */
5056 /* if count is 0 then mapping error has occurred */
5061 /* Make sure there is space in the ring for the next send. */
5068 }
5071 }
5073 /**
5074 * e1000_tx_timeout - Respond to a Tx Hang
5075 * @netdev: network interface device structure
5076 **/
5078 {
5081 /* Do the reset outside of interrupt context */
5084 }
5087 {
5091 /* don't run the task if already down */
5099 }
5101 }
5103 /**
5104 * e1000_get_stats64 - Get System Network Statistics
5105 * @netdev: network interface device structure
5106 * @stats: rtnl_link_stats64 pointer
5107 *
5108 * Returns the address of the device statistics structure.
5109 **/
5112 {
5118 /* Fill out the OS statistics structure */
5126 /* Rx Errors */
5128 /*
5129 * RLEC on some newer hardware can be incorrect so build
5130 * our own version based on RUC and ROC
5131 */
5142 /* Tx Errors */
5149 /* Tx Dropped needs to be maintained elsewhere */
5153 }
5155 /**
5156 * e1000_change_mtu - Change the Maximum Transfer Unit
5157 * @netdev: network interface device structure
5158 * @new_mtu: new value for maximum frame size
5159 *
5160 * Returns 0 on success, negative on failure
5161 **/
5163 {
5167 /* Jumbo frame support */
5172 }
5174 /* Supported frame sizes */
5179 }
5181 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5187 }
5189 /* 82573 Errata 17 */
5195 }
5199 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
5206 /*
5207 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5208 * means we reserve 2 more, this pushes us to allocate from the next
5209 * larger slab size.
5210 * i.e. RXBUFFER_2048 --> size-4096 slab
5211 * However with the new *_jumbo_rx* routines, jumbo receives will use
5212 * fragmented skbs
5213 */
5217 else
5220 /* adjust allocation if LPE protects us, and we aren't using SBP */
5228 else
5234 }
5238 {
5285 }
5290 }
5292 }
5295 {
5303 }
5304 }
5307 {
5313 /* copy MAC RARs to PHY RARs */
5320 }
5322 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5327 /* copy MAC MTA to PHY MTA - only needed for pchlan */
5334 }
5336 /* configure PHY Rx Control register */
5356 /* enable PHY wakeup in MAC register */
5360 /* configure and enable PHY wakeup in PHY registers */
5364 /* activate PHY wakeup */
5369 out:
5373 }
5377 {
5382 /* Runtime suspend should only enable wakeup for link changes */
5392 }
5407 /* turn on all-multi mode if wake on multicast is enabled */
5412 }
5415 /* advertise wake from D3Cold */
5416 #define E1000_CTRL_ADVD3WUC 0x00100000
5417 /* phy power management enable */
5418 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5426 e1000_media_type_internal_serdes) {
5427 /* keep the laser running in D3 */
5431 }
5436 /* Allow time for pending master requests to run */
5440 /* enable wakeup by the PHY */
5445 /* enable wakeup by the MAC */
5448 }
5452 }
5456 /* make sure adapter isn't asleep if manageability is enabled */
5464 /*
5465 * Release control of h/w to f/w. If f/w is AMT enabled, this
5466 * would have already happened in close and is redundant.
5467 */
5473 }
5476 {
5480 }
5484 }
5488 {
5492 /*
5493 * The pci-e switch on some quad port adapters will report a
5494 * correctable error when the MAC transitions from D0 to D3. To
5495 * prevent this we need to mask off the correctable errors on the
5496 * downstream port of the pci-e switch.
5497 */
5501 u16 devctl;
5512 }
5513 }
5515 #ifdef CONFIG_PCIEASPM
5517 {
5519 }
5520 #else
5522 {
5524 u16 reg16;
5526 /*
5527 * Both device and parent should have the same ASPM setting.
5528 * Disable ASPM in downstream component first and then upstream.
5529 */
5542 }
5543 #endif
5545 {
5551 }
5553 #ifdef CONFIG_PM
5555 {
5557 }
5560 {
5565 u32 err;
5583 }
5590 /* report the system wakeup cause from S3/S4 */
5592 u16 phy_data;
5603 }
5615 }
5617 }
5628 /*
5629 * If the controller has AMT, do not set DRV_LOAD until the interface
5630 * is up. For all other cases, let the f/w know that the h/w is now
5631 * under the control of the driver.
5632 */
5637 }
5639 #ifdef CONFIG_PM_SLEEP
5641 {
5651 }
5654 {
5663 }
5666 #ifdef CONFIG_PM_RUNTIME
5668 {
5677 }
5680 }
5683 {
5695 }
5698 }
5701 {
5711 }
5716 {
5723 }
5725 #ifdef CONFIG_NET_POLL_CONTROLLER
5728 {
5741 vector++;
5747 vector++;
5752 }
5755 }
5757 /*
5758 * Polling 'interrupt' - used by things like netconsole to send skbs
5759 * without having to re-enable interrupts. It's not called while
5760 * the interrupt routine is executing.
5761 */
5763 {
5780 }
5781 }
5782 #endif
5784 /**
5785 * e1000_io_error_detected - called when PCI error is detected
5786 * @pdev: Pointer to PCI device
5787 * @state: The current pci connection state
5788 *
5789 * This function is called after a PCI bus error affecting
5790 * this device has been detected.
5791 */
5793 pci_channel_state_t state)
5794 {
5807 /* Request a slot slot reset. */
5809 }
5811 /**
5812 * e1000_io_slot_reset - called after the pci bus has been reset.
5813 * @pdev: Pointer to PCI device
5814 *
5815 * Restart the card from scratch, as if from a cold-boot. Implementation
5816 * resembles the first-half of the e1000_resume routine.
5817 */
5819 {
5825 pci_ers_result_t result;
5850 }
5855 }
5857 /**
5858 * e1000_io_resume - called when traffic can start flowing again.
5859 * @pdev: Pointer to PCI device
5860 *
5861 * This callback is called when the error recovery driver tells us that
5862 * its OK to resume normal operation. Implementation resembles the
5863 * second-half of the e1000_resume routine.
5864 */
5866 {
5877 }
5878 }
5882 /*
5883 * If the controller has AMT, do not set DRV_LOAD until the interface
5884 * is up. For all other cases, let the f/w know that the h/w is now
5885 * under the control of the driver.
5886 */
5890 }
5893 {
5896 u32 ret_val;
5899 /* print bus type/speed/width info */
5901 /* bus width */
5904 /* MAC address */
5909 E1000_PBANUM_LENGTH);
5914 }
5917 {
5927 /* Deep Smart Power Down (DSPD) */
5930 }
5931 }
5934 netdev_features_t features)
5935 {
5943 NETIF_F_RXCSUM)))
5948 else
5952 }
5968 #ifdef CONFIG_NET_POLL_CONTROLLER
5970 #endif
5972 };
5974 /**
5975 * e1000_probe - Device Initialization Routine
5976 * @pdev: PCI device information struct
5977 * @ent: entry in e1000_pci_tbl
5978 *
5979 * Returns 0 on success, negative on failure
5980 *
5981 * e1000_probe initializes an adapter identified by a pci_dev structure.
5982 * The OS initialization, configuring of the adapter private structure,
5983 * and a hardware reset occur.
5984 **/
5987 {
6026 }
6027 }
6028 }
6032 e1000e_driver_name);
6036 /* AER (Advanced Error Reporting) hooks */
6040 /* PCI config space info */
6083 }
6085 /* construct the net_device struct */
6099 /* setup adapter struct */
6120 /* Copper options */
6125 }
6130 /* Set initial default active device features */
6132 NETIF_F_HW_VLAN_RX |
6133 NETIF_F_HW_VLAN_TX |
6134 NETIF_F_TSO |
6135 NETIF_F_TSO6 |
6136 NETIF_F_RXCSUM |
6137 NETIF_F_HW_CSUM);
6139 /* Set user-changeable features (subset of all device features) */
6146 NETIF_F_TSO |
6147 NETIF_F_TSO6 |
6148 NETIF_F_HW_CSUM);
6155 }
6160 /*
6161 * before reading the NVM, reset the controller to
6162 * put the device in a known good starting state
6163 */
6166 /*
6167 * systems with ASPM and others may see the checksum fail on the first
6168 * attempt. Let's give it a few tries
6169 */
6177 }
6178 }
6182 /* copy the MAC address */
6193 }
6209 /* Initialize link parameters. User can change them with ethtool */
6216 /* ring size defaults */
6220 /*
6221 * Initial Wake on LAN setting - If APM wake is enabled in
6222 * the EEPROM, enable the ACPI Magic Packet filter
6223 */
6225 /* APME bit in EEPROM is mapped to WUC.APME */
6236 else
6239 }
6241 /* fetch WoL from EEPROM */
6245 /*
6246 * now that we have the eeprom settings, apply the special cases
6247 * where the eeprom may be wrong or the board simply won't support
6248 * wake on lan on a particular port
6249 */
6253 /* initialize the wol settings based on the eeprom settings */
6257 /* save off EEPROM version number */
6260 /* reset the hardware with the new settings */
6263 /*
6264 * If the controller has AMT, do not set DRV_LOAD until the interface
6265 * is up. For all other cases, let the f/w know that the h/w is now
6266 * under the control of the driver.
6267 */
6276 /* carrier off reporting is important to ethtool even BEFORE open */
6286 err_register:
6289 err_eeprom:
6292 err_hw_init:
6295 err_sw_init:
6299 err_flashmap:
6301 err_ioremap:
6303 err_alloc_etherdev:
6306 err_pci_reg:
6307 err_dma:
6310 }
6312 /**
6313 * e1000_remove - Device Removal Routine
6314 * @pdev: PCI device information struct
6315 *
6316 * e1000_remove is called by the PCI subsystem to alert the driver
6317 * that it should release a PCI device. The could be caused by a
6318 * Hot-Plug event, or because the driver is going to be removed from
6319 * memory.
6320 **/
6322 {
6327 /*
6328 * The timers may be rescheduled, so explicitly disable them
6329 * from being rescheduled.
6330 */
6345 /* Don't lie to e1000_close() down the road. */
6353 /*
6354 * Release control of h/w to f/w. If f/w is AMT enabled, this
6355 * would have already happened in close and is redundant.
6356 */
6371 /* AER disable */
6375 }
6377 /* PCI Error Recovery (ERS) */
6382 };
6409 board_80003es2lan },
6411 board_80003es2lan },
6413 board_80003es2lan },
6415 board_80003es2lan },
6453 };
6456 #ifdef CONFIG_PM
6461 };
6462 #endif
6464 /* PCI Device API Driver */
6470 #ifdef CONFIG_PM
6472 #endif
6475 };
6477 /**
6478 * e1000_init_module - Driver Registration Routine
6479 *
6480 * e1000_init_module is the first routine called when the driver is
6481 * loaded. All it does is register with the PCI subsystem.
6482 **/
6484 {
6487 e1000e_driver_version);
6492 }
6495 /**
6496 * e1000_exit_module - Driver Exit Cleanup Routine
6497 *
6498 * e1000_exit_module is called just before the driver is removed
6499 * from memory.
6500 **/
6502 {
6504 }
6513 /* e1000_main.c */