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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_82599.c
blob4e59083a3de2404766b1357c7dcb6890d79988dd
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
42
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg,
49 bool autoneg_wait_to_complete);
50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
52 bool autoneg,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
58 bool autoneg,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
62 bool autoneg,
63 bool autoneg_wait_to_complete);
64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
66
67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
68 {
69 struct ixgbe_mac_info *mac = &hw->mac;
70
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
73 mac->ops.disable_tx_laser =
74 &ixgbe_disable_tx_laser_multispeed_fiber;
75 mac->ops.enable_tx_laser =
76 &ixgbe_enable_tx_laser_multispeed_fiber;
77 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
78 } else {
79 mac->ops.disable_tx_laser = NULL;
80 mac->ops.enable_tx_laser = NULL;
81 mac->ops.flap_tx_laser = NULL;
82 }
83
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
87 } else {
88 if ((mac->ops.get_media_type(hw) ==
89 ixgbe_media_type_backplane) &&
90 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
91 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw))
93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
94 else
95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
96 }
97 }
98
99 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
100 {
101 s32 ret_val = 0;
102 u32 reg_anlp1 = 0;
103 u32 i = 0;
104 u16 list_offset, data_offset, data_value;
105
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
107 ixgbe_init_mac_link_ops_82599(hw);
108
109 hw->phy.ops.reset = NULL;
110
111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
112 &data_offset);
113 if (ret_val != 0)
114 goto setup_sfp_out;
115
116 /* PHY config will finish before releasing the semaphore */
117 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
118 IXGBE_GSSR_MAC_CSR_SM);
119 if (ret_val != 0) {
120 ret_val = IXGBE_ERR_SWFW_SYNC;
121 goto setup_sfp_out;
122 }
123
124 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
125 while (data_value != 0xffff) {
126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
127 IXGBE_WRITE_FLUSH(hw);
128 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
129 }
130
131 /* Release the semaphore */
132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
133 /*
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
136 */
137 usleep_range(hw->eeprom.semaphore_delay * 1000,
138 hw->eeprom.semaphore_delay * 2000);
139
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
142 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
143 IXGBE_AUTOC_AN_RESTART));
144
145 /* Wait for AN to leave state 0 */
146 for (i = 0; i < 10; i++) {
147 usleep_range(4000, 8000);
148 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
149 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
150 break;
151 }
152 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
153 hw_dbg(hw, "sfp module setup not complete\n");
154 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
155 goto setup_sfp_out;
156 }
157
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
160 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
161 IXGBE_AUTOC_AN_RESTART));
162 }
163
164 setup_sfp_out:
165 return ret_val;
166 }
167
168 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
169 {
170 struct ixgbe_mac_info *mac = &hw->mac;
171
172 ixgbe_init_mac_link_ops_82599(hw);
173
174 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
175 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
176 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
177 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
178 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
180
181 return 0;
182 }
183
184 /**
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
187 *
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
191 *
192 **/
193 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
194 {
195 struct ixgbe_mac_info *mac = &hw->mac;
196 struct ixgbe_phy_info *phy = &hw->phy;
197 s32 ret_val = 0;
198
199 /* Identify the PHY or SFP module */
200 ret_val = phy->ops.identify(hw);
201
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw);
204
205 /* If copper media, overwrite with copper function pointers */
206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
207 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
208 mac->ops.get_link_capabilities =
209 &ixgbe_get_copper_link_capabilities_generic;
210 }
211
212 /* Set necessary function pointers based on phy type */
213 switch (hw->phy.type) {
214 case ixgbe_phy_tn:
215 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
216 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
217 phy->ops.get_firmware_version =
218 &ixgbe_get_phy_firmware_version_tnx;
219 break;
220 default:
221 break;
222 }
223
224 return ret_val;
225 }
226
227 /**
228 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
229 * @hw: pointer to hardware structure
230 * @speed: pointer to link speed
231 * @negotiation: true when autoneg or autotry is enabled
232 *
233 * Determines the link capabilities by reading the AUTOC register.
234 **/
235 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
236 ixgbe_link_speed *speed,
237 bool *negotiation)
238 {
239 s32 status = 0;
240 u32 autoc = 0;
241
242 /* Determine 1G link capabilities off of SFP+ type */
243 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
244 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
245 *speed = IXGBE_LINK_SPEED_1GB_FULL;
246 *negotiation = true;
247 goto out;
248 }
249
250 /*
251 * Determine link capabilities based on the stored value of AUTOC,
252 * which represents EEPROM defaults. If AUTOC value has not been
253 * stored, use the current register value.
254 */
255 if (hw->mac.orig_link_settings_stored)
256 autoc = hw->mac.orig_autoc;
257 else
258 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
259
260 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
261 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
262 *speed = IXGBE_LINK_SPEED_1GB_FULL;
263 *negotiation = false;
264 break;
265
266 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
267 *speed = IXGBE_LINK_SPEED_10GB_FULL;
268 *negotiation = false;
269 break;
270
271 case IXGBE_AUTOC_LMS_1G_AN:
272 *speed = IXGBE_LINK_SPEED_1GB_FULL;
273 *negotiation = true;
274 break;
275
276 case IXGBE_AUTOC_LMS_10G_SERIAL:
277 *speed = IXGBE_LINK_SPEED_10GB_FULL;
278 *negotiation = false;
279 break;
280
281 case IXGBE_AUTOC_LMS_KX4_KX_KR:
282 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
283 *speed = IXGBE_LINK_SPEED_UNKNOWN;
284 if (autoc & IXGBE_AUTOC_KR_SUPP)
285 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
286 if (autoc & IXGBE_AUTOC_KX4_SUPP)
287 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
288 if (autoc & IXGBE_AUTOC_KX_SUPP)
289 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
290 *negotiation = true;
291 break;
292
293 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
294 *speed = IXGBE_LINK_SPEED_100_FULL;
295 if (autoc & IXGBE_AUTOC_KR_SUPP)
296 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
297 if (autoc & IXGBE_AUTOC_KX4_SUPP)
298 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
299 if (autoc & IXGBE_AUTOC_KX_SUPP)
300 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
301 *negotiation = true;
302 break;
303
304 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
305 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
306 *negotiation = false;
307 break;
308
309 default:
310 status = IXGBE_ERR_LINK_SETUP;
311 goto out;
312 break;
313 }
314
315 if (hw->phy.multispeed_fiber) {
316 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
317 IXGBE_LINK_SPEED_1GB_FULL;
318 *negotiation = true;
319 }
320
321 out:
322 return status;
323 }
324
325 /**
326 * ixgbe_get_media_type_82599 - Get media type
327 * @hw: pointer to hardware structure
328 *
329 * Returns the media type (fiber, copper, backplane)
330 **/
331 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
332 {
333 enum ixgbe_media_type media_type;
334
335 /* Detect if there is a copper PHY attached. */
336 switch (hw->phy.type) {
337 case ixgbe_phy_cu_unknown:
338 case ixgbe_phy_tn:
339 media_type = ixgbe_media_type_copper;
340 goto out;
341 default:
342 break;
343 }
344
345 switch (hw->device_id) {
346 case IXGBE_DEV_ID_82599_KX4:
347 case IXGBE_DEV_ID_82599_KX4_MEZZ:
348 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
349 case IXGBE_DEV_ID_82599_KR:
350 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
351 case IXGBE_DEV_ID_82599_XAUI_LOM:
352 /* Default device ID is mezzanine card KX/KX4 */
353 media_type = ixgbe_media_type_backplane;
354 break;
355 case IXGBE_DEV_ID_82599_SFP:
356 case IXGBE_DEV_ID_82599_SFP_FCOE:
357 case IXGBE_DEV_ID_82599_SFP_EM:
358 case IXGBE_DEV_ID_82599_SFP_SF2:
359 case IXGBE_DEV_ID_82599_SFP_SF_QP:
360 case IXGBE_DEV_ID_82599EN_SFP:
361 media_type = ixgbe_media_type_fiber;
362 break;
363 case IXGBE_DEV_ID_82599_CX4:
364 media_type = ixgbe_media_type_cx4;
365 break;
366 case IXGBE_DEV_ID_82599_T3_LOM:
367 media_type = ixgbe_media_type_copper;
368 break;
369 case IXGBE_DEV_ID_82599_LS:
370 media_type = ixgbe_media_type_fiber_lco;
371 break;
372 default:
373 media_type = ixgbe_media_type_unknown;
374 break;
375 }
376 out:
377 return media_type;
378 }
379
380 /**
381 * ixgbe_start_mac_link_82599 - Setup MAC link settings
382 * @hw: pointer to hardware structure
383 * @autoneg_wait_to_complete: true when waiting for completion is needed
384 *
385 * Configures link settings based on values in the ixgbe_hw struct.
386 * Restarts the link. Performs autonegotiation if needed.
387 **/
388 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
389 bool autoneg_wait_to_complete)
390 {
391 u32 autoc_reg;
392 u32 links_reg;
393 u32 i;
394 s32 status = 0;
395
396 /* Restart link */
397 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
398 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
399 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
400
401 /* Only poll for autoneg to complete if specified to do so */
402 if (autoneg_wait_to_complete) {
403 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
404 IXGBE_AUTOC_LMS_KX4_KX_KR ||
405 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
406 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
407 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
408 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
409 links_reg = 0; /* Just in case Autoneg time = 0 */
410 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
411 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
412 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
413 break;
414 msleep(100);
415 }
416 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
417 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
418 hw_dbg(hw, "Autoneg did not complete.\n");
419 }
420 }
421 }
422
423 /* Add delay to filter out noises during initial link setup */
424 msleep(50);
425
426 return status;
427 }
428
429 /**
430 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
431 * @hw: pointer to hardware structure
432 *
433 * The base drivers may require better control over SFP+ module
434 * PHY states. This includes selectively shutting down the Tx
435 * laser on the PHY, effectively halting physical link.
436 **/
437 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
438 {
439 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
440
441 /* Disable tx laser; allow 100us to go dark per spec */
442 esdp_reg |= IXGBE_ESDP_SDP3;
443 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
444 IXGBE_WRITE_FLUSH(hw);
445 udelay(100);
446 }
447
448 /**
449 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
450 * @hw: pointer to hardware structure
451 *
452 * The base drivers may require better control over SFP+ module
453 * PHY states. This includes selectively turning on the Tx
454 * laser on the PHY, effectively starting physical link.
455 **/
456 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
457 {
458 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
459
460 /* Enable tx laser; allow 100ms to light up */
461 esdp_reg &= ~IXGBE_ESDP_SDP3;
462 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
463 IXGBE_WRITE_FLUSH(hw);
464 msleep(100);
465 }
466
467 /**
468 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
469 * @hw: pointer to hardware structure
470 *
471 * When the driver changes the link speeds that it can support,
472 * it sets autotry_restart to true to indicate that we need to
473 * initiate a new autotry session with the link partner. To do
474 * so, we set the speed then disable and re-enable the tx laser, to
475 * alert the link partner that it also needs to restart autotry on its
476 * end. This is consistent with true clause 37 autoneg, which also
477 * involves a loss of signal.
478 **/
479 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
480 {
481 if (hw->mac.autotry_restart) {
482 ixgbe_disable_tx_laser_multispeed_fiber(hw);
483 ixgbe_enable_tx_laser_multispeed_fiber(hw);
484 hw->mac.autotry_restart = false;
485 }
486 }
487
488 /**
489 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
490 * @hw: pointer to hardware structure
491 * @speed: new link speed
492 * @autoneg: true if autonegotiation enabled
493 * @autoneg_wait_to_complete: true when waiting for completion is needed
494 *
495 * Set the link speed in the AUTOC register and restarts link.
496 **/
497 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
498 ixgbe_link_speed speed,
499 bool autoneg,
500 bool autoneg_wait_to_complete)
501 {
502 s32 status = 0;
503 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
504 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
505 u32 speedcnt = 0;
506 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
507 u32 i = 0;
508 bool link_up = false;
509 bool negotiation;
510
511 /* Mask off requested but non-supported speeds */
512 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
513 &negotiation);
514 if (status != 0)
515 return status;
516
517 speed &= link_speed;
518
519 /*
520 * Try each speed one by one, highest priority first. We do this in
521 * software because 10gb fiber doesn't support speed autonegotiation.
522 */
523 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
524 speedcnt++;
525 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
526
527 /* If we already have link at this speed, just jump out */
528 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
529 false);
530 if (status != 0)
531 return status;
532
533 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
534 goto out;
535
536 /* Set the module link speed */
537 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
538 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
539 IXGBE_WRITE_FLUSH(hw);
540
541 /* Allow module to change analog characteristics (1G->10G) */
542 msleep(40);
543
544 status = ixgbe_setup_mac_link_82599(hw,
545 IXGBE_LINK_SPEED_10GB_FULL,
546 autoneg,
547 autoneg_wait_to_complete);
548 if (status != 0)
549 return status;
550
551 /* Flap the tx laser if it has not already been done */
552 hw->mac.ops.flap_tx_laser(hw);
553
554 /*
555 * Wait for the controller to acquire link. Per IEEE 802.3ap,
556 * Section 73.10.2, we may have to wait up to 500ms if KR is
557 * attempted. 82599 uses the same timing for 10g SFI.
558 */
559 for (i = 0; i < 5; i++) {
560 /* Wait for the link partner to also set speed */
561 msleep(100);
562
563 /* If we have link, just jump out */
564 status = hw->mac.ops.check_link(hw, &link_speed,
565 &link_up, false);
566 if (status != 0)
567 return status;
568
569 if (link_up)
570 goto out;
571 }
572 }
573
574 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
575 speedcnt++;
576 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
577 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
578
579 /* If we already have link at this speed, just jump out */
580 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
581 false);
582 if (status != 0)
583 return status;
584
585 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
586 goto out;
587
588 /* Set the module link speed */
589 esdp_reg &= ~IXGBE_ESDP_SDP5;
590 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
591 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
592 IXGBE_WRITE_FLUSH(hw);
593
594 /* Allow module to change analog characteristics (10G->1G) */
595 msleep(40);
596
597 status = ixgbe_setup_mac_link_82599(hw,
598 IXGBE_LINK_SPEED_1GB_FULL,
599 autoneg,
600 autoneg_wait_to_complete);
601 if (status != 0)
602 return status;
603
604 /* Flap the tx laser if it has not already been done */
605 hw->mac.ops.flap_tx_laser(hw);
606
607 /* Wait for the link partner to also set speed */
608 msleep(100);
609
610 /* If we have link, just jump out */
611 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
612 false);
613 if (status != 0)
614 return status;
615
616 if (link_up)
617 goto out;
618 }
619
620 /*
621 * We didn't get link. Configure back to the highest speed we tried,
622 * (if there was more than one). We call ourselves back with just the
623 * single highest speed that the user requested.
624 */
625 if (speedcnt > 1)
626 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
627 highest_link_speed,
628 autoneg,
629 autoneg_wait_to_complete);
630
631 out:
632 /* Set autoneg_advertised value based on input link speed */
633 hw->phy.autoneg_advertised = 0;
634
635 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
636 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
637
638 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
639 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
640
641 return status;
642 }
643
644 /**
645 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
646 * @hw: pointer to hardware structure
647 * @speed: new link speed
648 * @autoneg: true if autonegotiation enabled
649 * @autoneg_wait_to_complete: true when waiting for completion is needed
650 *
651 * Implements the Intel SmartSpeed algorithm.
652 **/
653 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
654 ixgbe_link_speed speed, bool autoneg,
655 bool autoneg_wait_to_complete)
656 {
657 s32 status = 0;
658 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
659 s32 i, j;
660 bool link_up = false;
661 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
662
663 /* Set autoneg_advertised value based on input link speed */
664 hw->phy.autoneg_advertised = 0;
665
666 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
667 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
668
669 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
670 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
671
672 if (speed & IXGBE_LINK_SPEED_100_FULL)
673 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
674
675 /*
676 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
677 * autoneg advertisement if link is unable to be established at the
678 * highest negotiated rate. This can sometimes happen due to integrity
679 * issues with the physical media connection.
680 */
681
682 /* First, try to get link with full advertisement */
683 hw->phy.smart_speed_active = false;
684 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
685 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
686 autoneg_wait_to_complete);
687 if (status != 0)
688 goto out;
689
690 /*
691 * Wait for the controller to acquire link. Per IEEE 802.3ap,
692 * Section 73.10.2, we may have to wait up to 500ms if KR is
693 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
694 * Table 9 in the AN MAS.
695 */
696 for (i = 0; i < 5; i++) {
697 mdelay(100);
698
699 /* If we have link, just jump out */
700 status = hw->mac.ops.check_link(hw, &link_speed,
701 &link_up, false);
702 if (status != 0)
703 goto out;
704
705 if (link_up)
706 goto out;
707 }
708 }
709
710 /*
711 * We didn't get link. If we advertised KR plus one of KX4/KX
712 * (or BX4/BX), then disable KR and try again.
713 */
714 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
715 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
716 goto out;
717
718 /* Turn SmartSpeed on to disable KR support */
719 hw->phy.smart_speed_active = true;
720 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
721 autoneg_wait_to_complete);
722 if (status != 0)
723 goto out;
724
725 /*
726 * Wait for the controller to acquire link. 600ms will allow for
727 * the AN link_fail_inhibit_timer as well for multiple cycles of
728 * parallel detect, both 10g and 1g. This allows for the maximum
729 * connect attempts as defined in the AN MAS table 73-7.
730 */
731 for (i = 0; i < 6; i++) {
732 mdelay(100);
733
734 /* If we have link, just jump out */
735 status = hw->mac.ops.check_link(hw, &link_speed,
736 &link_up, false);
737 if (status != 0)
738 goto out;
739
740 if (link_up)
741 goto out;
742 }
743
744 /* We didn't get link. Turn SmartSpeed back off. */
745 hw->phy.smart_speed_active = false;
746 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
747 autoneg_wait_to_complete);
748
749 out:
750 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
751 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
752 "the maximum advertised\n");
753 return status;
754 }
755
756 /**
757 * ixgbe_setup_mac_link_82599 - Set MAC link speed
758 * @hw: pointer to hardware structure
759 * @speed: new link speed
760 * @autoneg: true if autonegotiation enabled
761 * @autoneg_wait_to_complete: true when waiting for completion is needed
762 *
763 * Set the link speed in the AUTOC register and restarts link.
764 **/
765 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
766 ixgbe_link_speed speed, bool autoneg,
767 bool autoneg_wait_to_complete)
768 {
769 s32 status = 0;
770 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
771 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
772 u32 start_autoc = autoc;
773 u32 orig_autoc = 0;
774 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
775 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
776 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
777 u32 links_reg;
778 u32 i;
779 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
780
781 /* Check to see if speed passed in is supported. */
782 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
783 if (status != 0)
784 goto out;
785
786 speed &= link_capabilities;
787
788 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
789 status = IXGBE_ERR_LINK_SETUP;
790 goto out;
791 }
792
793 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
794 if (hw->mac.orig_link_settings_stored)
795 orig_autoc = hw->mac.orig_autoc;
796 else
797 orig_autoc = autoc;
798
799 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
800 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
801 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
802 /* Set KX4/KX/KR support according to speed requested */
803 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
804 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
805 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
806 autoc |= IXGBE_AUTOC_KX4_SUPP;
807 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
808 (hw->phy.smart_speed_active == false))
809 autoc |= IXGBE_AUTOC_KR_SUPP;
810 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
811 autoc |= IXGBE_AUTOC_KX_SUPP;
812 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
813 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
814 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
815 /* Switch from 1G SFI to 10G SFI if requested */
816 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
817 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
818 autoc &= ~IXGBE_AUTOC_LMS_MASK;
819 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
820 }
821 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
822 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
823 /* Switch from 10G SFI to 1G SFI if requested */
824 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
825 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
826 autoc &= ~IXGBE_AUTOC_LMS_MASK;
827 if (autoneg)
828 autoc |= IXGBE_AUTOC_LMS_1G_AN;
829 else
830 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
831 }
832 }
833
834 if (autoc != start_autoc) {
835 /* Restart link */
836 autoc |= IXGBE_AUTOC_AN_RESTART;
837 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
838
839 /* Only poll for autoneg to complete if specified to do so */
840 if (autoneg_wait_to_complete) {
841 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
842 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
843 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
844 links_reg = 0; /*Just in case Autoneg time=0*/
845 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
846 links_reg =
847 IXGBE_READ_REG(hw, IXGBE_LINKS);
848 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
849 break;
850 msleep(100);
851 }
852 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
853 status =
854 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
855 hw_dbg(hw, "Autoneg did not "
856 "complete.\n");
857 }
858 }
859 }
860
861 /* Add delay to filter out noises during initial link setup */
862 msleep(50);
863 }
864
865 out:
866 return status;
867 }
868
869 /**
870 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
871 * @hw: pointer to hardware structure
872 * @speed: new link speed
873 * @autoneg: true if autonegotiation enabled
874 * @autoneg_wait_to_complete: true if waiting is needed to complete
875 *
876 * Restarts link on PHY and MAC based on settings passed in.
877 **/
878 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
879 ixgbe_link_speed speed,
880 bool autoneg,
881 bool autoneg_wait_to_complete)
882 {
883 s32 status;
884
885 /* Setup the PHY according to input speed */
886 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
887 autoneg_wait_to_complete);
888 /* Set up MAC */
889 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
890
891 return status;
892 }
893
894 /**
895 * ixgbe_reset_hw_82599 - Perform hardware reset
896 * @hw: pointer to hardware structure
897 *
898 * Resets the hardware by resetting the transmit and receive units, masks
899 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
900 * reset.
901 **/
902 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
903 {
904 ixgbe_link_speed link_speed;
905 s32 status;
906 u32 ctrl, i, autoc, autoc2;
907 bool link_up = false;
908
909 /* Call adapter stop to disable tx/rx and clear interrupts */
910 status = hw->mac.ops.stop_adapter(hw);
911 if (status != 0)
912 goto reset_hw_out;
913
914 /* flush pending Tx transactions */
915 ixgbe_clear_tx_pending(hw);
916
917 /* PHY ops must be identified and initialized prior to reset */
918
919 /* Identify PHY and related function pointers */
920 status = hw->phy.ops.init(hw);
921
922 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
923 goto reset_hw_out;
924
925 /* Setup SFP module if there is one present. */
926 if (hw->phy.sfp_setup_needed) {
927 status = hw->mac.ops.setup_sfp(hw);
928 hw->phy.sfp_setup_needed = false;
929 }
930
931 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
932 goto reset_hw_out;
933
934 /* Reset PHY */
935 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
936 hw->phy.ops.reset(hw);
937
938 mac_reset_top:
939 /*
940 * Issue global reset to the MAC. Needs to be SW reset if link is up.
941 * If link reset is used when link is up, it might reset the PHY when
942 * mng is using it. If link is down or the flag to force full link
943 * reset is set, then perform link reset.
944 */
945 ctrl = IXGBE_CTRL_LNK_RST;
946 if (!hw->force_full_reset) {
947 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
948 if (link_up)
949 ctrl = IXGBE_CTRL_RST;
950 }
951
952 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
953 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
954 IXGBE_WRITE_FLUSH(hw);
955
956 /* Poll for reset bit to self-clear indicating reset is complete */
957 for (i = 0; i < 10; i++) {
958 udelay(1);
959 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
960 if (!(ctrl & IXGBE_CTRL_RST_MASK))
961 break;
962 }
963
964 if (ctrl & IXGBE_CTRL_RST_MASK) {
965 status = IXGBE_ERR_RESET_FAILED;
966 hw_dbg(hw, "Reset polling failed to complete.\n");
967 }
968
969 msleep(50);
970
971 /*
972 * Double resets are required for recovery from certain error
973 * conditions. Between resets, it is necessary to stall to allow time
974 * for any pending HW events to complete.
975 */
976 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
977 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
978 goto mac_reset_top;
979 }
980
981 /*
982 * Store the original AUTOC/AUTOC2 values if they have not been
983 * stored off yet. Otherwise restore the stored original
984 * values since the reset operation sets back to defaults.
985 */
986 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
987 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
988 if (hw->mac.orig_link_settings_stored == false) {
989 hw->mac.orig_autoc = autoc;
990 hw->mac.orig_autoc2 = autoc2;
991 hw->mac.orig_link_settings_stored = true;
992 } else {
993 if (autoc != hw->mac.orig_autoc)
994 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
995 IXGBE_AUTOC_AN_RESTART));
996
997 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
998 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
999 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1000 autoc2 |= (hw->mac.orig_autoc2 &
1001 IXGBE_AUTOC2_UPPER_MASK);
1002 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1003 }
1004 }
1005
1006 /* Store the permanent mac address */
1007 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1008
1009 /*
1010 * Store MAC address from RAR0, clear receive address registers, and
1011 * clear the multicast table. Also reset num_rar_entries to 128,
1012 * since we modify this value when programming the SAN MAC address.
1013 */
1014 hw->mac.num_rar_entries = 128;
1015 hw->mac.ops.init_rx_addrs(hw);
1016
1017 /* Store the permanent SAN mac address */
1018 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1019
1020 /* Add the SAN MAC address to the RAR only if it's a valid address */
1021 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1022 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1023 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1024
1025 /* Reserve the last RAR for the SAN MAC address */
1026 hw->mac.num_rar_entries--;
1027 }
1028
1029 /* Store the alternative WWNN/WWPN prefix */
1030 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1031 &hw->mac.wwpn_prefix);
1032
1033 reset_hw_out:
1034 return status;
1035 }
1036
1037 /**
1038 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1039 * @hw: pointer to hardware structure
1040 **/
1041 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1042 {
1043 int i;
1044 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1045 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1046
1047 /*
1048 * Before starting reinitialization process,
1049 * FDIRCMD.CMD must be zero.
1050 */
1051 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1052 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1053 IXGBE_FDIRCMD_CMD_MASK))
1054 break;
1055 udelay(10);
1056 }
1057 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1058 hw_dbg(hw, "Flow Director previous command isn't complete, "
1059 "aborting table re-initialization.\n");
1060 return IXGBE_ERR_FDIR_REINIT_FAILED;
1061 }
1062
1063 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1064 IXGBE_WRITE_FLUSH(hw);
1065 /*
1066 * 82599 adapters flow director init flow cannot be restarted,
1067 * Workaround 82599 silicon errata by performing the following steps
1068 * before re-writing the FDIRCTRL control register with the same value.
1069 * - write 1 to bit 8 of FDIRCMD register &
1070 * - write 0 to bit 8 of FDIRCMD register
1071 */
1072 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1073 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1074 IXGBE_FDIRCMD_CLEARHT));
1075 IXGBE_WRITE_FLUSH(hw);
1076 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1077 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1078 ~IXGBE_FDIRCMD_CLEARHT));
1079 IXGBE_WRITE_FLUSH(hw);
1080 /*
1081 * Clear FDIR Hash register to clear any leftover hashes
1082 * waiting to be programmed.
1083 */
1084 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1085 IXGBE_WRITE_FLUSH(hw);
1086
1087 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1088 IXGBE_WRITE_FLUSH(hw);
1089
1090 /* Poll init-done after we write FDIRCTRL register */
1091 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1092 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1093 IXGBE_FDIRCTRL_INIT_DONE)
1094 break;
1095 udelay(10);
1096 }
1097 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1098 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1099 return IXGBE_ERR_FDIR_REINIT_FAILED;
1100 }
1101
1102 /* Clear FDIR statistics registers (read to clear) */
1103 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1104 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1105 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1106 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1107 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1108
1109 return 0;
1110 }
1111
1112 /**
1113 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1114 * @hw: pointer to hardware structure
1115 * @fdirctrl: value to write to flow director control register
1116 **/
1117 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1118 {
1119 int i;
1120
1121 /* Prime the keys for hashing */
1122 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1123 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1124
1125 /*
1126 * Poll init-done after we write the register. Estimated times:
1127 * 10G: PBALLOC = 11b, timing is 60us
1128 * 1G: PBALLOC = 11b, timing is 600us
1129 * 100M: PBALLOC = 11b, timing is 6ms
1130 *
1131 * Multiple these timings by 4 if under full Rx load
1132 *
1133 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1134 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1135 * this might not finish in our poll time, but we can live with that
1136 * for now.
1137 */
1138 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1139 IXGBE_WRITE_FLUSH(hw);
1140 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1141 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1142 IXGBE_FDIRCTRL_INIT_DONE)
1143 break;
1144 usleep_range(1000, 2000);
1145 }
1146
1147 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1148 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1149 }
1150
1151 /**
1152 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1153 * @hw: pointer to hardware structure
1154 * @fdirctrl: value to write to flow director control register, initially
1155 * contains just the value of the Rx packet buffer allocation
1156 **/
1157 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1158 {
1159 /*
1160 * Continue setup of fdirctrl register bits:
1161 * Move the flexible bytes to use the ethertype - shift 6 words
1162 * Set the maximum length per hash bucket to 0xA filters
1163 * Send interrupt when 64 filters are left
1164 */
1165 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1166 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1167 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1168
1169 /* write hashes and fdirctrl register, poll for completion */
1170 ixgbe_fdir_enable_82599(hw, fdirctrl);
1171
1172 return 0;
1173 }
1174
1175 /**
1176 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1177 * @hw: pointer to hardware structure
1178 * @fdirctrl: value to write to flow director control register, initially
1179 * contains just the value of the Rx packet buffer allocation
1180 **/
1181 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1182 {
1183 /*
1184 * Continue setup of fdirctrl register bits:
1185 * Turn perfect match filtering on
1186 * Report hash in RSS field of Rx wb descriptor
1187 * Initialize the drop queue
1188 * Move the flexible bytes to use the ethertype - shift 6 words
1189 * Set the maximum length per hash bucket to 0xA filters
1190 * Send interrupt when 64 (0x4 * 16) filters are left
1191 */
1192 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1193 IXGBE_FDIRCTRL_REPORT_STATUS |
1194 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1195 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1196 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1197 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1198
1199 /* write hashes and fdirctrl register, poll for completion */
1200 ixgbe_fdir_enable_82599(hw, fdirctrl);
1201
1202 return 0;
1203 }
1204
1205 /*
1206 * These defines allow us to quickly generate all of the necessary instructions
1207 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1208 * for values 0 through 15
1209 */
1210 #define IXGBE_ATR_COMMON_HASH_KEY \
1211 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1212 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1213 do { \
1214 u32 n = (_n); \
1215 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1216 common_hash ^= lo_hash_dword >> n; \
1217 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1218 bucket_hash ^= lo_hash_dword >> n; \
1219 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1220 sig_hash ^= lo_hash_dword << (16 - n); \
1221 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1222 common_hash ^= hi_hash_dword >> n; \
1223 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1224 bucket_hash ^= hi_hash_dword >> n; \
1225 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1226 sig_hash ^= hi_hash_dword << (16 - n); \
1227 } while (0);
1228
1229 /**
1230 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1231 * @stream: input bitstream to compute the hash on
1232 *
1233 * This function is almost identical to the function above but contains
1234 * several optomizations such as unwinding all of the loops, letting the
1235 * compiler work out all of the conditional ifs since the keys are static
1236 * defines, and computing two keys at once since the hashed dword stream
1237 * will be the same for both keys.
1238 **/
1239 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1240 union ixgbe_atr_hash_dword common)
1241 {
1242 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1243 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1244
1245 /* record the flow_vm_vlan bits as they are a key part to the hash */
1246 flow_vm_vlan = ntohl(input.dword);
1247
1248 /* generate common hash dword */
1249 hi_hash_dword = ntohl(common.dword);
1250
1251 /* low dword is word swapped version of common */
1252 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1253
1254 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1255 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1256
1257 /* Process bits 0 and 16 */
1258 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1259
1260 /*
1261 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1262 * delay this because bit 0 of the stream should not be processed
1263 * so we do not add the vlan until after bit 0 was processed
1264 */
1265 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1266
1267 /* Process remaining 30 bit of the key */
1268 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1269 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1270 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1271 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1272 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1273 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1274 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1275 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1276 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1277 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1278 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1279 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1280 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1281 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1282 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1283
1284 /* combine common_hash result with signature and bucket hashes */
1285 bucket_hash ^= common_hash;
1286 bucket_hash &= IXGBE_ATR_HASH_MASK;
1287
1288 sig_hash ^= common_hash << 16;
1289 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1290
1291 /* return completed signature hash */
1292 return sig_hash ^ bucket_hash;
1293 }
1294
1295 /**
1296 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1297 * @hw: pointer to hardware structure
1298 * @input: unique input dword
1299 * @common: compressed common input dword
1300 * @queue: queue index to direct traffic to
1301 **/
1302 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1303 union ixgbe_atr_hash_dword input,
1304 union ixgbe_atr_hash_dword common,
1305 u8 queue)
1306 {
1307 u64 fdirhashcmd;
1308 u32 fdircmd;
1309
1310 /*
1311 * Get the flow_type in order to program FDIRCMD properly
1312 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1313 */
1314 switch (input.formatted.flow_type) {
1315 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1316 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1317 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1318 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1319 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1320 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1321 break;
1322 default:
1323 hw_dbg(hw, " Error on flow type input\n");
1324 return IXGBE_ERR_CONFIG;
1325 }
1326
1327 /* configure FDIRCMD register */
1328 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1329 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1330 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1331 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1332
1333 /*
1334 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1335 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1336 */
1337 fdirhashcmd = (u64)fdircmd << 32;
1338 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1339 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1340
1341 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1342
1343 return 0;
1344 }
1345
1346 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1347 do { \
1348 u32 n = (_n); \
1349 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1350 bucket_hash ^= lo_hash_dword >> n; \
1351 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1352 bucket_hash ^= hi_hash_dword >> n; \
1353 } while (0);
1354
1355 /**
1356 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1357 * @atr_input: input bitstream to compute the hash on
1358 * @input_mask: mask for the input bitstream
1359 *
1360 * This function serves two main purposes. First it applys the input_mask
1361 * to the atr_input resulting in a cleaned up atr_input data stream.
1362 * Secondly it computes the hash and stores it in the bkt_hash field at
1363 * the end of the input byte stream. This way it will be available for
1364 * future use without needing to recompute the hash.
1365 **/
1366 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1367 union ixgbe_atr_input *input_mask)
1368 {
1369
1370 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1371 u32 bucket_hash = 0;
1372
1373 /* Apply masks to input data */
1374 input->dword_stream[0] &= input_mask->dword_stream[0];
1375 input->dword_stream[1] &= input_mask->dword_stream[1];
1376 input->dword_stream[2] &= input_mask->dword_stream[2];
1377 input->dword_stream[3] &= input_mask->dword_stream[3];
1378 input->dword_stream[4] &= input_mask->dword_stream[4];
1379 input->dword_stream[5] &= input_mask->dword_stream[5];
1380 input->dword_stream[6] &= input_mask->dword_stream[6];
1381 input->dword_stream[7] &= input_mask->dword_stream[7];
1382 input->dword_stream[8] &= input_mask->dword_stream[8];
1383 input->dword_stream[9] &= input_mask->dword_stream[9];
1384 input->dword_stream[10] &= input_mask->dword_stream[10];
1385
1386 /* record the flow_vm_vlan bits as they are a key part to the hash */
1387 flow_vm_vlan = ntohl(input->dword_stream[0]);
1388
1389 /* generate common hash dword */
1390 hi_hash_dword = ntohl(input->dword_stream[1] ^
1391 input->dword_stream[2] ^
1392 input->dword_stream[3] ^
1393 input->dword_stream[4] ^
1394 input->dword_stream[5] ^
1395 input->dword_stream[6] ^
1396 input->dword_stream[7] ^
1397 input->dword_stream[8] ^
1398 input->dword_stream[9] ^
1399 input->dword_stream[10]);
1400
1401 /* low dword is word swapped version of common */
1402 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1403
1404 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1405 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1406
1407 /* Process bits 0 and 16 */
1408 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1409
1410 /*
1411 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1412 * delay this because bit 0 of the stream should not be processed
1413 * so we do not add the vlan until after bit 0 was processed
1414 */
1415 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1416
1417 /* Process remaining 30 bit of the key */
1418 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1419 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1420 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1421 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1422 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1423 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1424 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1425 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1426 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1427 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1428 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1429 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1430 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1431 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1432 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1433
1434 /*
1435 * Limit hash to 13 bits since max bucket count is 8K.
1436 * Store result at the end of the input stream.
1437 */
1438 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1439 }
1440
1441 /**
1442 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1443 * @input_mask: mask to be bit swapped
1444 *
1445 * The source and destination port masks for flow director are bit swapped
1446 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1447 * generate a correctly swapped value we need to bit swap the mask and that
1448 * is what is accomplished by this function.
1449 **/
1450 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1451 {
1452 u32 mask = ntohs(input_mask->formatted.dst_port);
1453 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1454 mask |= ntohs(input_mask->formatted.src_port);
1455 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1456 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1457 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1458 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1459 }
1460
1461 /*
1462 * These two macros are meant to address the fact that we have registers
1463 * that are either all or in part big-endian. As a result on big-endian
1464 * systems we will end up byte swapping the value to little-endian before
1465 * it is byte swapped again and written to the hardware in the original
1466 * big-endian format.
1467 */
1468 #define IXGBE_STORE_AS_BE32(_value) \
1469 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1470 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1471
1472 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1473 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1474
1475 #define IXGBE_STORE_AS_BE16(_value) \
1476 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1477
1478 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1479 union ixgbe_atr_input *input_mask)
1480 {
1481 /* mask IPv6 since it is currently not supported */
1482 u32 fdirm = IXGBE_FDIRM_DIPv6;
1483 u32 fdirtcpm;
1484
1485 /*
1486 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1487 * are zero, then assume a full mask for that field. Also assume that
1488 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1489 * cannot be masked out in this implementation.
1490 *
1491 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1492 * point in time.
1493 */
1494
1495 /* verify bucket hash is cleared on hash generation */
1496 if (input_mask->formatted.bkt_hash)
1497 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1498
1499 /* Program FDIRM and verify partial masks */
1500 switch (input_mask->formatted.vm_pool & 0x7F) {
1501 case 0x0:
1502 fdirm |= IXGBE_FDIRM_POOL;
1503 case 0x7F:
1504 break;
1505 default:
1506 hw_dbg(hw, " Error on vm pool mask\n");
1507 return IXGBE_ERR_CONFIG;
1508 }
1509
1510 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1511 case 0x0:
1512 fdirm |= IXGBE_FDIRM_L4P;
1513 if (input_mask->formatted.dst_port ||
1514 input_mask->formatted.src_port) {
1515 hw_dbg(hw, " Error on src/dst port mask\n");
1516 return IXGBE_ERR_CONFIG;
1517 }
1518 case IXGBE_ATR_L4TYPE_MASK:
1519 break;
1520 default:
1521 hw_dbg(hw, " Error on flow type mask\n");
1522 return IXGBE_ERR_CONFIG;
1523 }
1524
1525 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1526 case 0x0000:
1527 /* mask VLAN ID, fall through to mask VLAN priority */
1528 fdirm |= IXGBE_FDIRM_VLANID;
1529 case 0x0FFF:
1530 /* mask VLAN priority */
1531 fdirm |= IXGBE_FDIRM_VLANP;
1532 break;
1533 case 0xE000:
1534 /* mask VLAN ID only, fall through */
1535 fdirm |= IXGBE_FDIRM_VLANID;
1536 case 0xEFFF:
1537 /* no VLAN fields masked */
1538 break;
1539 default:
1540 hw_dbg(hw, " Error on VLAN mask\n");
1541 return IXGBE_ERR_CONFIG;
1542 }
1543
1544 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1545 case 0x0000:
1546 /* Mask Flex Bytes, fall through */
1547 fdirm |= IXGBE_FDIRM_FLEX;
1548 case 0xFFFF:
1549 break;
1550 default:
1551 hw_dbg(hw, " Error on flexible byte mask\n");
1552 return IXGBE_ERR_CONFIG;
1553 }
1554
1555 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1556 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1557
1558 /* store the TCP/UDP port masks, bit reversed from port layout */
1559 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1560
1561 /* write both the same so that UDP and TCP use the same mask */
1562 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1563 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1564
1565 /* store source and destination IP masks (big-enian) */
1566 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1567 ~input_mask->formatted.src_ip[0]);
1568 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1569 ~input_mask->formatted.dst_ip[0]);
1570
1571 return 0;
1572 }
1573
1574 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1575 union ixgbe_atr_input *input,
1576 u16 soft_id, u8 queue)
1577 {
1578 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1579
1580 /* currently IPv6 is not supported, must be programmed with 0 */
1581 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1582 input->formatted.src_ip[0]);
1583 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1584 input->formatted.src_ip[1]);
1585 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1586 input->formatted.src_ip[2]);
1587
1588 /* record the source address (big-endian) */
1589 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1590
1591 /* record the first 32 bits of the destination address (big-endian) */
1592 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1593
1594 /* record source and destination port (little-endian)*/
1595 fdirport = ntohs(input->formatted.dst_port);
1596 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1597 fdirport |= ntohs(input->formatted.src_port);
1598 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1599
1600 /* record vlan (little-endian) and flex_bytes(big-endian) */
1601 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1602 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1603 fdirvlan |= ntohs(input->formatted.vlan_id);
1604 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1605
1606 /* configure FDIRHASH register */
1607 fdirhash = input->formatted.bkt_hash;
1608 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1609 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1610
1611 /*
1612 * flush all previous writes to make certain registers are
1613 * programmed prior to issuing the command
1614 */
1615 IXGBE_WRITE_FLUSH(hw);
1616
1617 /* configure FDIRCMD register */
1618 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1619 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1620 if (queue == IXGBE_FDIR_DROP_QUEUE)
1621 fdircmd |= IXGBE_FDIRCMD_DROP;
1622 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1623 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1624 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1625
1626 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1627
1628 return 0;
1629 }
1630
1631 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1632 union ixgbe_atr_input *input,
1633 u16 soft_id)
1634 {
1635 u32 fdirhash;
1636 u32 fdircmd = 0;
1637 u32 retry_count;
1638 s32 err = 0;
1639
1640 /* configure FDIRHASH register */
1641 fdirhash = input->formatted.bkt_hash;
1642 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1643 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1644
1645 /* flush hash to HW */
1646 IXGBE_WRITE_FLUSH(hw);
1647
1648 /* Query if filter is present */
1649 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1650
1651 for (retry_count = 10; retry_count; retry_count--) {
1652 /* allow 10us for query to process */
1653 udelay(10);
1654 /* verify query completed successfully */
1655 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1656 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1657 break;
1658 }
1659
1660 if (!retry_count)
1661 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1662
1663 /* if filter exists in hardware then remove it */
1664 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1665 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1666 IXGBE_WRITE_FLUSH(hw);
1667 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1668 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1669 }
1670
1671 return err;
1672 }
1673
1674 /**
1675 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1676 * @hw: pointer to hardware structure
1677 * @reg: analog register to read
1678 * @val: read value
1679 *
1680 * Performs read operation to Omer analog register specified.
1681 **/
1682 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1683 {
1684 u32 core_ctl;
1685
1686 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1687 (reg << 8));
1688 IXGBE_WRITE_FLUSH(hw);
1689 udelay(10);
1690 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1691 *val = (u8)core_ctl;
1692
1693 return 0;
1694 }
1695
1696 /**
1697 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1698 * @hw: pointer to hardware structure
1699 * @reg: atlas register to write
1700 * @val: value to write
1701 *
1702 * Performs write operation to Omer analog register specified.
1703 **/
1704 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1705 {
1706 u32 core_ctl;
1707
1708 core_ctl = (reg << 8) | val;
1709 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1710 IXGBE_WRITE_FLUSH(hw);
1711 udelay(10);
1712
1713 return 0;
1714 }
1715
1716 /**
1717 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1718 * @hw: pointer to hardware structure
1719 *
1720 * Starts the hardware using the generic start_hw function
1721 * and the generation start_hw function.
1722 * Then performs revision-specific operations, if any.
1723 **/
1724 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1725 {
1726 s32 ret_val = 0;
1727
1728 ret_val = ixgbe_start_hw_generic(hw);
1729 if (ret_val != 0)
1730 goto out;
1731
1732 ret_val = ixgbe_start_hw_gen2(hw);
1733 if (ret_val != 0)
1734 goto out;
1735
1736 /* We need to run link autotry after the driver loads */
1737 hw->mac.autotry_restart = true;
1738 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1739
1740 if (ret_val == 0)
1741 ret_val = ixgbe_verify_fw_version_82599(hw);
1742 out:
1743 return ret_val;
1744 }
1745
1746 /**
1747 * ixgbe_identify_phy_82599 - Get physical layer module
1748 * @hw: pointer to hardware structure
1749 *
1750 * Determines the physical layer module found on the current adapter.
1751 * If PHY already detected, maintains current PHY type in hw struct,
1752 * otherwise executes the PHY detection routine.
1753 **/
1754 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1755 {
1756 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1757
1758 /* Detect PHY if not unknown - returns success if already detected. */
1759 status = ixgbe_identify_phy_generic(hw);
1760 if (status != 0) {
1761 /* 82599 10GBASE-T requires an external PHY */
1762 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1763 goto out;
1764 else
1765 status = ixgbe_identify_sfp_module_generic(hw);
1766 }
1767
1768 /* Set PHY type none if no PHY detected */
1769 if (hw->phy.type == ixgbe_phy_unknown) {
1770 hw->phy.type = ixgbe_phy_none;
1771 status = 0;
1772 }
1773
1774 /* Return error if SFP module has been detected but is not supported */
1775 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1776 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1777
1778 out:
1779 return status;
1780 }
1781
1782 /**
1783 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1784 * @hw: pointer to hardware structure
1785 *
1786 * Determines physical layer capabilities of the current configuration.
1787 **/
1788 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1789 {
1790 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1791 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1792 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1793 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1794 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1795 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1796 u16 ext_ability = 0;
1797 u8 comp_codes_10g = 0;
1798 u8 comp_codes_1g = 0;
1799
1800 hw->phy.ops.identify(hw);
1801
1802 switch (hw->phy.type) {
1803 case ixgbe_phy_tn:
1804 case ixgbe_phy_cu_unknown:
1805 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1806 &ext_ability);
1807 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1808 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1809 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1810 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1811 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1812 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1813 goto out;
1814 default:
1815 break;
1816 }
1817
1818 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1819 case IXGBE_AUTOC_LMS_1G_AN:
1820 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1821 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1822 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1823 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1824 goto out;
1825 } else
1826 /* SFI mode so read SFP module */
1827 goto sfp_check;
1828 break;
1829 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1830 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1831 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1832 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1833 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1834 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1835 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1836 goto out;
1837 break;
1838 case IXGBE_AUTOC_LMS_10G_SERIAL:
1839 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1840 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1841 goto out;
1842 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1843 goto sfp_check;
1844 break;
1845 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1846 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1847 if (autoc & IXGBE_AUTOC_KX_SUPP)
1848 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1849 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1850 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1851 if (autoc & IXGBE_AUTOC_KR_SUPP)
1852 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1853 goto out;
1854 break;
1855 default:
1856 goto out;
1857 break;
1858 }
1859
1860 sfp_check:
1861 /* SFP check must be done last since DA modules are sometimes used to
1862 * test KR mode - we need to id KR mode correctly before SFP module.
1863 * Call identify_sfp because the pluggable module may have changed */
1864 hw->phy.ops.identify_sfp(hw);
1865 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1866 goto out;
1867
1868 switch (hw->phy.type) {
1869 case ixgbe_phy_sfp_passive_tyco:
1870 case ixgbe_phy_sfp_passive_unknown:
1871 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1872 break;
1873 case ixgbe_phy_sfp_ftl_active:
1874 case ixgbe_phy_sfp_active_unknown:
1875 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1876 break;
1877 case ixgbe_phy_sfp_avago:
1878 case ixgbe_phy_sfp_ftl:
1879 case ixgbe_phy_sfp_intel:
1880 case ixgbe_phy_sfp_unknown:
1881 hw->phy.ops.read_i2c_eeprom(hw,
1882 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1883 hw->phy.ops.read_i2c_eeprom(hw,
1884 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1885 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1886 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1887 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1888 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1889 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1890 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1891 break;
1892 default:
1893 break;
1894 }
1895
1896 out:
1897 return physical_layer;
1898 }
1899
1900 /**
1901 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1902 * @hw: pointer to hardware structure
1903 * @regval: register value to write to RXCTRL
1904 *
1905 * Enables the Rx DMA unit for 82599
1906 **/
1907 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1908 {
1909 #define IXGBE_MAX_SECRX_POLL 30
1910 int i;
1911 int secrxreg;
1912
1913 /*
1914 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1915 * If traffic is incoming before we enable the Rx unit, it could hang
1916 * the Rx DMA unit. Therefore, make sure the security engine is
1917 * completely disabled prior to enabling the Rx unit.
1918 */
1919 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1920 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1921 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1922 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1923 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1924 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1925 break;
1926 else
1927 /* Use interrupt-safe sleep just in case */
1928 udelay(10);
1929 }
1930
1931 /* For informational purposes only */
1932 if (i >= IXGBE_MAX_SECRX_POLL)
1933 hw_dbg(hw, "Rx unit being enabled before security "
1934 "path fully disabled. Continuing with init.\n");
1935
1936 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1937 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1938 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1939 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1940 IXGBE_WRITE_FLUSH(hw);
1941
1942 return 0;
1943 }
1944
1945 /**
1946 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1947 * @hw: pointer to hardware structure
1948 *
1949 * Verifies that installed the firmware version is 0.6 or higher
1950 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1951 *
1952 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1953 * if the FW version is not supported.
1954 **/
1955 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1956 {
1957 s32 status = IXGBE_ERR_EEPROM_VERSION;
1958 u16 fw_offset, fw_ptp_cfg_offset;
1959 u16 fw_version = 0;
1960
1961 /* firmware check is only necessary for SFI devices */
1962 if (hw->phy.media_type != ixgbe_media_type_fiber) {
1963 status = 0;
1964 goto fw_version_out;
1965 }
1966
1967 /* get the offset to the Firmware Module block */
1968 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
1969
1970 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
1971 goto fw_version_out;
1972
1973 /* get the offset to the Pass Through Patch Configuration block */
1974 hw->eeprom.ops.read(hw, (fw_offset +
1975 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
1976 &fw_ptp_cfg_offset);
1977
1978 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
1979 goto fw_version_out;
1980
1981 /* get the firmware version */
1982 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
1983 IXGBE_FW_PATCH_VERSION_4),
1984 &fw_version);
1985
1986 if (fw_version > 0x5)
1987 status = 0;
1988
1989 fw_version_out:
1990 return status;
1991 }
1992
1993 /**
1994 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
1995 * @hw: pointer to hardware structure
1996 *
1997 * Returns true if the LESM FW module is present and enabled. Otherwise
1998 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
1999 **/
2000 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2001 {
2002 bool lesm_enabled = false;
2003 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2004 s32 status;
2005
2006 /* get the offset to the Firmware Module block */
2007 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2008
2009 if ((status != 0) ||
2010 (fw_offset == 0) || (fw_offset == 0xFFFF))
2011 goto out;
2012
2013 /* get the offset to the LESM Parameters block */
2014 status = hw->eeprom.ops.read(hw, (fw_offset +
2015 IXGBE_FW_LESM_PARAMETERS_PTR),
2016 &fw_lesm_param_offset);
2017
2018 if ((status != 0) ||
2019 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2020 goto out;
2021
2022 /* get the lesm state word */
2023 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2024 IXGBE_FW_LESM_STATE_1),
2025 &fw_lesm_state);
2026
2027 if ((status == 0) &&
2028 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2029 lesm_enabled = true;
2030
2031 out:
2032 return lesm_enabled;
2033 }
2034
2035 /**
2036 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2037 * fastest available method
2038 *
2039 * @hw: pointer to hardware structure
2040 * @offset: offset of word in EEPROM to read
2041 * @words: number of words
2042 * @data: word(s) read from the EEPROM
2043 *
2044 * Retrieves 16 bit word(s) read from EEPROM
2045 **/
2046 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2047 u16 words, u16 *data)
2048 {
2049 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2050 s32 ret_val = IXGBE_ERR_CONFIG;
2051
2052 /*
2053 * If EEPROM is detected and can be addressed using 14 bits,
2054 * use EERD otherwise use bit bang
2055 */
2056 if ((eeprom->type == ixgbe_eeprom_spi) &&
2057 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2058 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2059 data);
2060 else
2061 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2062 words,
2063 data);
2064
2065 return ret_val;
2066 }
2067
2068 /**
2069 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2070 * fastest available method
2071 *
2072 * @hw: pointer to hardware structure
2073 * @offset: offset of word in the EEPROM to read
2074 * @data: word read from the EEPROM
2075 *
2076 * Reads a 16 bit word from the EEPROM
2077 **/
2078 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2079 u16 offset, u16 *data)
2080 {
2081 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2082 s32 ret_val = IXGBE_ERR_CONFIG;
2083
2084 /*
2085 * If EEPROM is detected and can be addressed using 14 bits,
2086 * use EERD otherwise use bit bang
2087 */
2088 if ((eeprom->type == ixgbe_eeprom_spi) &&
2089 (offset <= IXGBE_EERD_MAX_ADDR))
2090 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2091 else
2092 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2093
2094 return ret_val;
2095 }
2096
2097 static struct ixgbe_mac_operations mac_ops_82599 = {
2098 .init_hw = &ixgbe_init_hw_generic,
2099 .reset_hw = &ixgbe_reset_hw_82599,
2100 .start_hw = &ixgbe_start_hw_82599,
2101 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2102 .get_media_type = &ixgbe_get_media_type_82599,
2103 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2104 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2105 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2106 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2107 .get_device_caps = &ixgbe_get_device_caps_generic,
2108 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2109 .stop_adapter = &ixgbe_stop_adapter_generic,
2110 .get_bus_info = &ixgbe_get_bus_info_generic,
2111 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2112 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2113 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2114 .setup_link = &ixgbe_setup_mac_link_82599,
2115 .set_rxpba = &ixgbe_set_rxpba_generic,
2116 .check_link = &ixgbe_check_mac_link_generic,
2117 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2118 .led_on = &ixgbe_led_on_generic,
2119 .led_off = &ixgbe_led_off_generic,
2120 .blink_led_start = &ixgbe_blink_led_start_generic,
2121 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2122 .set_rar = &ixgbe_set_rar_generic,
2123 .clear_rar = &ixgbe_clear_rar_generic,
2124 .set_vmdq = &ixgbe_set_vmdq_generic,
2125 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2126 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2127 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2128 .enable_mc = &ixgbe_enable_mc_generic,
2129 .disable_mc = &ixgbe_disable_mc_generic,
2130 .clear_vfta = &ixgbe_clear_vfta_generic,
2131 .set_vfta = &ixgbe_set_vfta_generic,
2132 .fc_enable = &ixgbe_fc_enable_generic,
2133 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2134 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2135 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2136 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2137 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2138 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2139 .release_swfw_sync = &ixgbe_release_swfw_sync,
2140
2141 };
2142
2143 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2144 .init_params = &ixgbe_init_eeprom_params_generic,
2145 .read = &ixgbe_read_eeprom_82599,
2146 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2147 .write = &ixgbe_write_eeprom_generic,
2148 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2149 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2150 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2151 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2152 };
2153
2154 static struct ixgbe_phy_operations phy_ops_82599 = {
2155 .identify = &ixgbe_identify_phy_82599,
2156 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2157 .init = &ixgbe_init_phy_ops_82599,
2158 .reset = &ixgbe_reset_phy_generic,
2159 .read_reg = &ixgbe_read_phy_reg_generic,
2160 .write_reg = &ixgbe_write_phy_reg_generic,
2161 .setup_link = &ixgbe_setup_phy_link_generic,
2162 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2163 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2164 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2165 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2166 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2167 .check_overtemp = &ixgbe_tn_check_overtemp,
2168 };
2169
2170 struct ixgbe_info ixgbe_82599_info = {
2171 .mac = ixgbe_mac_82599EB,
2172 .get_invariants = &ixgbe_get_invariants_82599,
2173 .mac_ops = &mac_ops_82599,
2174 .eeprom_ops = &eeprom_ops_82599,
2175 .phy_ops = &phy_ops_82599,
2176 .mbx_ops = &mbx_ops_generic,
2177 };