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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
blob9edecfa1f0f4ffb556d73cbda06db380f9bdeeb8
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
39
40 #include <linux/init.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/in.h>
43 #include <linux/ip.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/etherdevice.h>
47 #include <linux/delay.h>
48 #include <linux/ethtool.h>
49 #include <linux/platform_device.h>
50 #include <linux/module.h>
51 #include <linux/kernel.h>
52 #include <linux/spinlock.h>
53 #include <linux/workqueue.h>
54 #include <linux/phy.h>
55 #include <linux/mv643xx_eth.h>
56 #include <linux/io.h>
57 #include <linux/types.h>
58 #include <linux/inet_lro.h>
59 #include <linux/slab.h>
60 #include <asm/system.h>
61
62 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
63 static char mv643xx_eth_driver_version[] = "1.4";
64
65
66 /*
67 * Registers shared between all ports.
68 */
69 #define PHY_ADDR 0x0000
70 #define SMI_REG 0x0004
71 #define SMI_BUSY 0x10000000
72 #define SMI_READ_VALID 0x08000000
73 #define SMI_OPCODE_READ 0x04000000
74 #define SMI_OPCODE_WRITE 0x00000000
75 #define ERR_INT_CAUSE 0x0080
76 #define ERR_INT_SMI_DONE 0x00000010
77 #define ERR_INT_MASK 0x0084
78 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
79 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
80 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
81 #define WINDOW_BAR_ENABLE 0x0290
82 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83
84 /*
85 * Main per-port registers. These live at offset 0x0400 for
86 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
87 */
88 #define PORT_CONFIG 0x0000
89 #define UNICAST_PROMISCUOUS_MODE 0x00000001
90 #define PORT_CONFIG_EXT 0x0004
91 #define MAC_ADDR_LOW 0x0014
92 #define MAC_ADDR_HIGH 0x0018
93 #define SDMA_CONFIG 0x001c
94 #define TX_BURST_SIZE_16_64BIT 0x01000000
95 #define TX_BURST_SIZE_4_64BIT 0x00800000
96 #define BLM_TX_NO_SWAP 0x00000020
97 #define BLM_RX_NO_SWAP 0x00000010
98 #define RX_BURST_SIZE_16_64BIT 0x00000008
99 #define RX_BURST_SIZE_4_64BIT 0x00000004
100 #define PORT_SERIAL_CONTROL 0x003c
101 #define SET_MII_SPEED_TO_100 0x01000000
102 #define SET_GMII_SPEED_TO_1000 0x00800000
103 #define SET_FULL_DUPLEX_MODE 0x00200000
104 #define MAX_RX_PACKET_9700BYTE 0x000a0000
105 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
106 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
107 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
108 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
109 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
110 #define FORCE_LINK_PASS 0x00000002
111 #define SERIAL_PORT_ENABLE 0x00000001
112 #define PORT_STATUS 0x0044
113 #define TX_FIFO_EMPTY 0x00000400
114 #define TX_IN_PROGRESS 0x00000080
115 #define PORT_SPEED_MASK 0x00000030
116 #define PORT_SPEED_1000 0x00000010
117 #define PORT_SPEED_100 0x00000020
118 #define PORT_SPEED_10 0x00000000
119 #define FLOW_CONTROL_ENABLED 0x00000008
120 #define FULL_DUPLEX 0x00000004
121 #define LINK_UP 0x00000002
122 #define TXQ_COMMAND 0x0048
123 #define TXQ_FIX_PRIO_CONF 0x004c
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
151
152 /*
153 * Misc per-port registers.
154 */
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
159
160
161 /*
162 * SDMA configuration register default value.
163 */
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
171 BLM_RX_NO_SWAP | \
172 BLM_TX_NO_SWAP | \
173 TX_BURST_SIZE_4_64BIT)
174 #else
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
176 #endif
177
178
179 /*
180 * Misc definitions.
181 */
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 256
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
185
186
187 /*
188 * RX/TX descriptors.
189 */
190 #if defined(__BIG_ENDIAN)
191 struct rx_desc {
192 u16 byte_cnt; /* Descriptor buffer byte count */
193 u16 buf_size; /* Buffer size */
194 u32 cmd_sts; /* Descriptor command status */
195 u32 next_desc_ptr; /* Next descriptor pointer */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 };
198
199 struct tx_desc {
200 u16 byte_cnt; /* buffer byte count */
201 u16 l4i_chk; /* CPU provided TCP checksum */
202 u32 cmd_sts; /* Command/status field */
203 u32 next_desc_ptr; /* Pointer to next descriptor */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 };
206 #elif defined(__LITTLE_ENDIAN)
207 struct rx_desc {
208 u32 cmd_sts; /* Descriptor command status */
209 u16 buf_size; /* Buffer size */
210 u16 byte_cnt; /* Descriptor buffer byte count */
211 u32 buf_ptr; /* Descriptor buffer pointer */
212 u32 next_desc_ptr; /* Next descriptor pointer */
213 };
214
215 struct tx_desc {
216 u32 cmd_sts; /* Command/status field */
217 u16 l4i_chk; /* CPU provided TCP checksum */
218 u16 byte_cnt; /* buffer byte count */
219 u32 buf_ptr; /* pointer to buffer for this descriptor*/
220 u32 next_desc_ptr; /* Pointer to next descriptor */
221 };
222 #else
223 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
224 #endif
225
226 /* RX & TX descriptor command */
227 #define BUFFER_OWNED_BY_DMA 0x80000000
228
229 /* RX & TX descriptor status */
230 #define ERROR_SUMMARY 0x00000001
231
232 /* RX descriptor status */
233 #define LAYER_4_CHECKSUM_OK 0x40000000
234 #define RX_ENABLE_INTERRUPT 0x20000000
235 #define RX_FIRST_DESC 0x08000000
236 #define RX_LAST_DESC 0x04000000
237 #define RX_IP_HDR_OK 0x02000000
238 #define RX_PKT_IS_IPV4 0x01000000
239 #define RX_PKT_IS_ETHERNETV2 0x00800000
240 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
241 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
242 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
243
244 /* TX descriptor command */
245 #define TX_ENABLE_INTERRUPT 0x00800000
246 #define GEN_CRC 0x00400000
247 #define TX_FIRST_DESC 0x00200000
248 #define TX_LAST_DESC 0x00100000
249 #define ZERO_PADDING 0x00080000
250 #define GEN_IP_V4_CHECKSUM 0x00040000
251 #define GEN_TCP_UDP_CHECKSUM 0x00020000
252 #define UDP_FRAME 0x00010000
253 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
254 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
255
256 #define TX_IHL_SHIFT 11
257
258
259 /* global *******************************************************************/
260 struct mv643xx_eth_shared_private {
261 /*
262 * Ethernet controller base address.
263 */
264 void __iomem *base;
265
266 /*
267 * Points at the right SMI instance to use.
268 */
269 struct mv643xx_eth_shared_private *smi;
270
271 /*
272 * Provides access to local SMI interface.
273 */
274 struct mii_bus *smi_bus;
275
276 /*
277 * If we have access to the error interrupt pin (which is
278 * somewhat misnamed as it not only reflects internal errors
279 * but also reflects SMI completion), use that to wait for
280 * SMI access completion instead of polling the SMI busy bit.
281 */
282 int err_interrupt;
283 wait_queue_head_t smi_busy_wait;
284
285 /*
286 * Per-port MBUS window access register value.
287 */
288 u32 win_protect;
289
290 /*
291 * Hardware-specific parameters.
292 */
293 unsigned int t_clk;
294 int extended_rx_coal_limit;
295 int tx_bw_control;
296 int tx_csum_limit;
297 };
298
299 #define TX_BW_CONTROL_ABSENT 0
300 #define TX_BW_CONTROL_OLD_LAYOUT 1
301 #define TX_BW_CONTROL_NEW_LAYOUT 2
302
303 static int mv643xx_eth_open(struct net_device *dev);
304 static int mv643xx_eth_stop(struct net_device *dev);
305
306
307 /* per-port *****************************************************************/
308 struct mib_counters {
309 u64 good_octets_received;
310 u32 bad_octets_received;
311 u32 internal_mac_transmit_err;
312 u32 good_frames_received;
313 u32 bad_frames_received;
314 u32 broadcast_frames_received;
315 u32 multicast_frames_received;
316 u32 frames_64_octets;
317 u32 frames_65_to_127_octets;
318 u32 frames_128_to_255_octets;
319 u32 frames_256_to_511_octets;
320 u32 frames_512_to_1023_octets;
321 u32 frames_1024_to_max_octets;
322 u64 good_octets_sent;
323 u32 good_frames_sent;
324 u32 excessive_collision;
325 u32 multicast_frames_sent;
326 u32 broadcast_frames_sent;
327 u32 unrec_mac_control_received;
328 u32 fc_sent;
329 u32 good_fc_received;
330 u32 bad_fc_received;
331 u32 undersize_received;
332 u32 fragments_received;
333 u32 oversize_received;
334 u32 jabber_received;
335 u32 mac_receive_error;
336 u32 bad_crc_event;
337 u32 collision;
338 u32 late_collision;
339 /* Non MIB hardware counters */
340 u32 rx_discard;
341 u32 rx_overrun;
342 };
343
344 struct lro_counters {
345 u32 lro_aggregated;
346 u32 lro_flushed;
347 u32 lro_no_desc;
348 };
349
350 struct rx_queue {
351 int index;
352
353 int rx_ring_size;
354
355 int rx_desc_count;
356 int rx_curr_desc;
357 int rx_used_desc;
358
359 struct rx_desc *rx_desc_area;
360 dma_addr_t rx_desc_dma;
361 int rx_desc_area_size;
362 struct sk_buff **rx_skb;
363
364 struct net_lro_mgr lro_mgr;
365 struct net_lro_desc lro_arr[8];
366 };
367
368 struct tx_queue {
369 int index;
370
371 int tx_ring_size;
372
373 int tx_desc_count;
374 int tx_curr_desc;
375 int tx_used_desc;
376
377 struct tx_desc *tx_desc_area;
378 dma_addr_t tx_desc_dma;
379 int tx_desc_area_size;
380
381 struct sk_buff_head tx_skb;
382
383 unsigned long tx_packets;
384 unsigned long tx_bytes;
385 unsigned long tx_dropped;
386 };
387
388 struct mv643xx_eth_private {
389 struct mv643xx_eth_shared_private *shared;
390 void __iomem *base;
391 int port_num;
392
393 struct net_device *dev;
394
395 struct phy_device *phy;
396
397 struct timer_list mib_counters_timer;
398 spinlock_t mib_counters_lock;
399 struct mib_counters mib_counters;
400
401 struct lro_counters lro_counters;
402
403 struct work_struct tx_timeout_task;
404
405 struct napi_struct napi;
406 u32 int_mask;
407 u8 oom;
408 u8 work_link;
409 u8 work_tx;
410 u8 work_tx_end;
411 u8 work_rx;
412 u8 work_rx_refill;
413
414 int skb_size;
415 struct sk_buff_head rx_recycle;
416
417 /*
418 * RX state.
419 */
420 int rx_ring_size;
421 unsigned long rx_desc_sram_addr;
422 int rx_desc_sram_size;
423 int rxq_count;
424 struct timer_list rx_oom;
425 struct rx_queue rxq[8];
426
427 /*
428 * TX state.
429 */
430 int tx_ring_size;
431 unsigned long tx_desc_sram_addr;
432 int tx_desc_sram_size;
433 int txq_count;
434 struct tx_queue txq[8];
435 };
436
437
438 /* port register accessors **************************************************/
439 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
440 {
441 return readl(mp->shared->base + offset);
442 }
443
444 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
445 {
446 return readl(mp->base + offset);
447 }
448
449 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
450 {
451 writel(data, mp->shared->base + offset);
452 }
453
454 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
455 {
456 writel(data, mp->base + offset);
457 }
458
459
460 /* rxq/txq helper functions *************************************************/
461 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
462 {
463 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
464 }
465
466 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
467 {
468 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
469 }
470
471 static void rxq_enable(struct rx_queue *rxq)
472 {
473 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
474 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
475 }
476
477 static void rxq_disable(struct rx_queue *rxq)
478 {
479 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
480 u8 mask = 1 << rxq->index;
481
482 wrlp(mp, RXQ_COMMAND, mask << 8);
483 while (rdlp(mp, RXQ_COMMAND) & mask)
484 udelay(10);
485 }
486
487 static void txq_reset_hw_ptr(struct tx_queue *txq)
488 {
489 struct mv643xx_eth_private *mp = txq_to_mp(txq);
490 u32 addr;
491
492 addr = (u32)txq->tx_desc_dma;
493 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
494 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
495 }
496
497 static void txq_enable(struct tx_queue *txq)
498 {
499 struct mv643xx_eth_private *mp = txq_to_mp(txq);
500 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
501 }
502
503 static void txq_disable(struct tx_queue *txq)
504 {
505 struct mv643xx_eth_private *mp = txq_to_mp(txq);
506 u8 mask = 1 << txq->index;
507
508 wrlp(mp, TXQ_COMMAND, mask << 8);
509 while (rdlp(mp, TXQ_COMMAND) & mask)
510 udelay(10);
511 }
512
513 static void txq_maybe_wake(struct tx_queue *txq)
514 {
515 struct mv643xx_eth_private *mp = txq_to_mp(txq);
516 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
517
518 if (netif_tx_queue_stopped(nq)) {
519 __netif_tx_lock(nq, smp_processor_id());
520 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
521 netif_tx_wake_queue(nq);
522 __netif_tx_unlock(nq);
523 }
524 }
525
526
527 /* rx napi ******************************************************************/
528 static int
529 mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
530 u64 *hdr_flags, void *priv)
531 {
532 unsigned long cmd_sts = (unsigned long)priv;
533
534 /*
535 * Make sure that this packet is Ethernet II, is not VLAN
536 * tagged, is IPv4, has a valid IP header, and is TCP.
537 */
538 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
539 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
540 RX_PKT_IS_VLAN_TAGGED)) !=
541 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
542 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
543 return -1;
544
545 skb_reset_network_header(skb);
546 skb_set_transport_header(skb, ip_hdrlen(skb));
547 *iphdr = ip_hdr(skb);
548 *tcph = tcp_hdr(skb);
549 *hdr_flags = LRO_IPV4 | LRO_TCP;
550
551 return 0;
552 }
553
554 static int rxq_process(struct rx_queue *rxq, int budget)
555 {
556 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
557 struct net_device_stats *stats = &mp->dev->stats;
558 int lro_flush_needed;
559 int rx;
560
561 lro_flush_needed = 0;
562 rx = 0;
563 while (rx < budget && rxq->rx_desc_count) {
564 struct rx_desc *rx_desc;
565 unsigned int cmd_sts;
566 struct sk_buff *skb;
567 u16 byte_cnt;
568
569 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
570
571 cmd_sts = rx_desc->cmd_sts;
572 if (cmd_sts & BUFFER_OWNED_BY_DMA)
573 break;
574 rmb();
575
576 skb = rxq->rx_skb[rxq->rx_curr_desc];
577 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
578
579 rxq->rx_curr_desc++;
580 if (rxq->rx_curr_desc == rxq->rx_ring_size)
581 rxq->rx_curr_desc = 0;
582
583 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
584 rx_desc->buf_size, DMA_FROM_DEVICE);
585 rxq->rx_desc_count--;
586 rx++;
587
588 mp->work_rx_refill |= 1 << rxq->index;
589
590 byte_cnt = rx_desc->byte_cnt;
591
592 /*
593 * Update statistics.
594 *
595 * Note that the descriptor byte count includes 2 dummy
596 * bytes automatically inserted by the hardware at the
597 * start of the packet (which we don't count), and a 4
598 * byte CRC at the end of the packet (which we do count).
599 */
600 stats->rx_packets++;
601 stats->rx_bytes += byte_cnt - 2;
602
603 /*
604 * In case we received a packet without first / last bits
605 * on, or the error summary bit is set, the packet needs
606 * to be dropped.
607 */
608 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
609 != (RX_FIRST_DESC | RX_LAST_DESC))
610 goto err;
611
612 /*
613 * The -4 is for the CRC in the trailer of the
614 * received packet
615 */
616 skb_put(skb, byte_cnt - 2 - 4);
617
618 if (cmd_sts & LAYER_4_CHECKSUM_OK)
619 skb->ip_summed = CHECKSUM_UNNECESSARY;
620 skb->protocol = eth_type_trans(skb, mp->dev);
621
622 if (skb->dev->features & NETIF_F_LRO &&
623 skb->ip_summed == CHECKSUM_UNNECESSARY) {
624 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
625 lro_flush_needed = 1;
626 } else
627 netif_receive_skb(skb);
628
629 continue;
630
631 err:
632 stats->rx_dropped++;
633
634 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
635 (RX_FIRST_DESC | RX_LAST_DESC)) {
636 if (net_ratelimit())
637 netdev_err(mp->dev,
638 "received packet spanning multiple descriptors\n");
639 }
640
641 if (cmd_sts & ERROR_SUMMARY)
642 stats->rx_errors++;
643
644 dev_kfree_skb(skb);
645 }
646
647 if (lro_flush_needed)
648 lro_flush_all(&rxq->lro_mgr);
649
650 if (rx < budget)
651 mp->work_rx &= ~(1 << rxq->index);
652
653 return rx;
654 }
655
656 static int rxq_refill(struct rx_queue *rxq, int budget)
657 {
658 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
659 int refilled;
660
661 refilled = 0;
662 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
663 struct sk_buff *skb;
664 int rx;
665 struct rx_desc *rx_desc;
666 int size;
667
668 skb = __skb_dequeue(&mp->rx_recycle);
669 if (skb == NULL)
670 skb = dev_alloc_skb(mp->skb_size);
671
672 if (skb == NULL) {
673 mp->oom = 1;
674 goto oom;
675 }
676
677 if (SKB_DMA_REALIGN)
678 skb_reserve(skb, SKB_DMA_REALIGN);
679
680 refilled++;
681 rxq->rx_desc_count++;
682
683 rx = rxq->rx_used_desc++;
684 if (rxq->rx_used_desc == rxq->rx_ring_size)
685 rxq->rx_used_desc = 0;
686
687 rx_desc = rxq->rx_desc_area + rx;
688
689 size = skb->end - skb->data;
690 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
691 skb->data, size,
692 DMA_FROM_DEVICE);
693 rx_desc->buf_size = size;
694 rxq->rx_skb[rx] = skb;
695 wmb();
696 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
697 wmb();
698
699 /*
700 * The hardware automatically prepends 2 bytes of
701 * dummy data to each received packet, so that the
702 * IP header ends up 16-byte aligned.
703 */
704 skb_reserve(skb, 2);
705 }
706
707 if (refilled < budget)
708 mp->work_rx_refill &= ~(1 << rxq->index);
709
710 oom:
711 return refilled;
712 }
713
714
715 /* tx ***********************************************************************/
716 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
717 {
718 int frag;
719
720 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
721 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
722
723 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
724 return 1;
725 }
726
727 return 0;
728 }
729
730 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
731 {
732 struct mv643xx_eth_private *mp = txq_to_mp(txq);
733 int nr_frags = skb_shinfo(skb)->nr_frags;
734 int frag;
735
736 for (frag = 0; frag < nr_frags; frag++) {
737 skb_frag_t *this_frag;
738 int tx_index;
739 struct tx_desc *desc;
740
741 this_frag = &skb_shinfo(skb)->frags[frag];
742 tx_index = txq->tx_curr_desc++;
743 if (txq->tx_curr_desc == txq->tx_ring_size)
744 txq->tx_curr_desc = 0;
745 desc = &txq->tx_desc_area[tx_index];
746
747 /*
748 * The last fragment will generate an interrupt
749 * which will free the skb on TX completion.
750 */
751 if (frag == nr_frags - 1) {
752 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
753 ZERO_PADDING | TX_LAST_DESC |
754 TX_ENABLE_INTERRUPT;
755 } else {
756 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
757 }
758
759 desc->l4i_chk = 0;
760 desc->byte_cnt = skb_frag_size(this_frag);
761 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
762 this_frag, 0,
763 skb_frag_size(this_frag),
764 DMA_TO_DEVICE);
765 }
766 }
767
768 static inline __be16 sum16_as_be(__sum16 sum)
769 {
770 return (__force __be16)sum;
771 }
772
773 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
774 {
775 struct mv643xx_eth_private *mp = txq_to_mp(txq);
776 int nr_frags = skb_shinfo(skb)->nr_frags;
777 int tx_index;
778 struct tx_desc *desc;
779 u32 cmd_sts;
780 u16 l4i_chk;
781 int length;
782
783 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
784 l4i_chk = 0;
785
786 if (skb->ip_summed == CHECKSUM_PARTIAL) {
787 int hdr_len;
788 int tag_bytes;
789
790 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
791 skb->protocol != htons(ETH_P_8021Q));
792
793 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
794 tag_bytes = hdr_len - ETH_HLEN;
795 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
796 unlikely(tag_bytes & ~12)) {
797 if (skb_checksum_help(skb) == 0)
798 goto no_csum;
799 kfree_skb(skb);
800 return 1;
801 }
802
803 if (tag_bytes & 4)
804 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
805 if (tag_bytes & 8)
806 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
807
808 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
809 GEN_IP_V4_CHECKSUM |
810 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
811
812 switch (ip_hdr(skb)->protocol) {
813 case IPPROTO_UDP:
814 cmd_sts |= UDP_FRAME;
815 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
816 break;
817 case IPPROTO_TCP:
818 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
819 break;
820 default:
821 BUG();
822 }
823 } else {
824 no_csum:
825 /* Errata BTS #50, IHL must be 5 if no HW checksum */
826 cmd_sts |= 5 << TX_IHL_SHIFT;
827 }
828
829 tx_index = txq->tx_curr_desc++;
830 if (txq->tx_curr_desc == txq->tx_ring_size)
831 txq->tx_curr_desc = 0;
832 desc = &txq->tx_desc_area[tx_index];
833
834 if (nr_frags) {
835 txq_submit_frag_skb(txq, skb);
836 length = skb_headlen(skb);
837 } else {
838 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
839 length = skb->len;
840 }
841
842 desc->l4i_chk = l4i_chk;
843 desc->byte_cnt = length;
844 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
845 length, DMA_TO_DEVICE);
846
847 __skb_queue_tail(&txq->tx_skb, skb);
848
849 skb_tx_timestamp(skb);
850
851 /* ensure all other descriptors are written before first cmd_sts */
852 wmb();
853 desc->cmd_sts = cmd_sts;
854
855 /* clear TX_END status */
856 mp->work_tx_end &= ~(1 << txq->index);
857
858 /* ensure all descriptors are written before poking hardware */
859 wmb();
860 txq_enable(txq);
861
862 txq->tx_desc_count += nr_frags + 1;
863
864 return 0;
865 }
866
867 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
868 {
869 struct mv643xx_eth_private *mp = netdev_priv(dev);
870 int length, queue;
871 struct tx_queue *txq;
872 struct netdev_queue *nq;
873
874 queue = skb_get_queue_mapping(skb);
875 txq = mp->txq + queue;
876 nq = netdev_get_tx_queue(dev, queue);
877
878 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
879 txq->tx_dropped++;
880 netdev_printk(KERN_DEBUG, dev,
881 "failed to linearize skb with tiny unaligned fragment\n");
882 return NETDEV_TX_BUSY;
883 }
884
885 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
886 if (net_ratelimit())
887 netdev_err(dev, "tx queue full?!\n");
888 kfree_skb(skb);
889 return NETDEV_TX_OK;
890 }
891
892 length = skb->len;
893
894 if (!txq_submit_skb(txq, skb)) {
895 int entries_left;
896
897 txq->tx_bytes += length;
898 txq->tx_packets++;
899
900 entries_left = txq->tx_ring_size - txq->tx_desc_count;
901 if (entries_left < MAX_SKB_FRAGS + 1)
902 netif_tx_stop_queue(nq);
903 }
904
905 return NETDEV_TX_OK;
906 }
907
908
909 /* tx napi ******************************************************************/
910 static void txq_kick(struct tx_queue *txq)
911 {
912 struct mv643xx_eth_private *mp = txq_to_mp(txq);
913 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
914 u32 hw_desc_ptr;
915 u32 expected_ptr;
916
917 __netif_tx_lock(nq, smp_processor_id());
918
919 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
920 goto out;
921
922 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
923 expected_ptr = (u32)txq->tx_desc_dma +
924 txq->tx_curr_desc * sizeof(struct tx_desc);
925
926 if (hw_desc_ptr != expected_ptr)
927 txq_enable(txq);
928
929 out:
930 __netif_tx_unlock(nq);
931
932 mp->work_tx_end &= ~(1 << txq->index);
933 }
934
935 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
936 {
937 struct mv643xx_eth_private *mp = txq_to_mp(txq);
938 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
939 int reclaimed;
940
941 __netif_tx_lock(nq, smp_processor_id());
942
943 reclaimed = 0;
944 while (reclaimed < budget && txq->tx_desc_count > 0) {
945 int tx_index;
946 struct tx_desc *desc;
947 u32 cmd_sts;
948 struct sk_buff *skb;
949
950 tx_index = txq->tx_used_desc;
951 desc = &txq->tx_desc_area[tx_index];
952 cmd_sts = desc->cmd_sts;
953
954 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
955 if (!force)
956 break;
957 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
958 }
959
960 txq->tx_used_desc = tx_index + 1;
961 if (txq->tx_used_desc == txq->tx_ring_size)
962 txq->tx_used_desc = 0;
963
964 reclaimed++;
965 txq->tx_desc_count--;
966
967 skb = NULL;
968 if (cmd_sts & TX_LAST_DESC)
969 skb = __skb_dequeue(&txq->tx_skb);
970
971 if (cmd_sts & ERROR_SUMMARY) {
972 netdev_info(mp->dev, "tx error\n");
973 mp->dev->stats.tx_errors++;
974 }
975
976 if (cmd_sts & TX_FIRST_DESC) {
977 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
978 desc->byte_cnt, DMA_TO_DEVICE);
979 } else {
980 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
981 desc->byte_cnt, DMA_TO_DEVICE);
982 }
983
984 if (skb != NULL) {
985 if (skb_queue_len(&mp->rx_recycle) <
986 mp->rx_ring_size &&
987 skb_recycle_check(skb, mp->skb_size))
988 __skb_queue_head(&mp->rx_recycle, skb);
989 else
990 dev_kfree_skb(skb);
991 }
992 }
993
994 __netif_tx_unlock(nq);
995
996 if (reclaimed < budget)
997 mp->work_tx &= ~(1 << txq->index);
998
999 return reclaimed;
1000 }
1001
1002
1003 /* tx rate control **********************************************************/
1004 /*
1005 * Set total maximum TX rate (shared by all TX queues for this port)
1006 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1007 */
1008 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1009 {
1010 int token_rate;
1011 int mtu;
1012 int bucket_size;
1013
1014 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1015 if (token_rate > 1023)
1016 token_rate = 1023;
1017
1018 mtu = (mp->dev->mtu + 255) >> 8;
1019 if (mtu > 63)
1020 mtu = 63;
1021
1022 bucket_size = (burst + 255) >> 8;
1023 if (bucket_size > 65535)
1024 bucket_size = 65535;
1025
1026 switch (mp->shared->tx_bw_control) {
1027 case TX_BW_CONTROL_OLD_LAYOUT:
1028 wrlp(mp, TX_BW_RATE, token_rate);
1029 wrlp(mp, TX_BW_MTU, mtu);
1030 wrlp(mp, TX_BW_BURST, bucket_size);
1031 break;
1032 case TX_BW_CONTROL_NEW_LAYOUT:
1033 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1034 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1035 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1036 break;
1037 }
1038 }
1039
1040 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1041 {
1042 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1043 int token_rate;
1044 int bucket_size;
1045
1046 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1047 if (token_rate > 1023)
1048 token_rate = 1023;
1049
1050 bucket_size = (burst + 255) >> 8;
1051 if (bucket_size > 65535)
1052 bucket_size = 65535;
1053
1054 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1055 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1056 }
1057
1058 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1059 {
1060 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1061 int off;
1062 u32 val;
1063
1064 /*
1065 * Turn on fixed priority mode.
1066 */
1067 off = 0;
1068 switch (mp->shared->tx_bw_control) {
1069 case TX_BW_CONTROL_OLD_LAYOUT:
1070 off = TXQ_FIX_PRIO_CONF;
1071 break;
1072 case TX_BW_CONTROL_NEW_LAYOUT:
1073 off = TXQ_FIX_PRIO_CONF_MOVED;
1074 break;
1075 }
1076
1077 if (off) {
1078 val = rdlp(mp, off);
1079 val |= 1 << txq->index;
1080 wrlp(mp, off, val);
1081 }
1082 }
1083
1084
1085 /* mii management interface *************************************************/
1086 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1087 {
1088 struct mv643xx_eth_shared_private *msp = dev_id;
1089
1090 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1091 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1092 wake_up(&msp->smi_busy_wait);
1093 return IRQ_HANDLED;
1094 }
1095
1096 return IRQ_NONE;
1097 }
1098
1099 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1100 {
1101 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1102 }
1103
1104 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1105 {
1106 if (msp->err_interrupt == NO_IRQ) {
1107 int i;
1108
1109 for (i = 0; !smi_is_done(msp); i++) {
1110 if (i == 10)
1111 return -ETIMEDOUT;
1112 msleep(10);
1113 }
1114
1115 return 0;
1116 }
1117
1118 if (!smi_is_done(msp)) {
1119 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1120 msecs_to_jiffies(100));
1121 if (!smi_is_done(msp))
1122 return -ETIMEDOUT;
1123 }
1124
1125 return 0;
1126 }
1127
1128 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1129 {
1130 struct mv643xx_eth_shared_private *msp = bus->priv;
1131 void __iomem *smi_reg = msp->base + SMI_REG;
1132 int ret;
1133
1134 if (smi_wait_ready(msp)) {
1135 pr_warn("SMI bus busy timeout\n");
1136 return -ETIMEDOUT;
1137 }
1138
1139 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1140
1141 if (smi_wait_ready(msp)) {
1142 pr_warn("SMI bus busy timeout\n");
1143 return -ETIMEDOUT;
1144 }
1145
1146 ret = readl(smi_reg);
1147 if (!(ret & SMI_READ_VALID)) {
1148 pr_warn("SMI bus read not valid\n");
1149 return -ENODEV;
1150 }
1151
1152 return ret & 0xffff;
1153 }
1154
1155 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1156 {
1157 struct mv643xx_eth_shared_private *msp = bus->priv;
1158 void __iomem *smi_reg = msp->base + SMI_REG;
1159
1160 if (smi_wait_ready(msp)) {
1161 pr_warn("SMI bus busy timeout\n");
1162 return -ETIMEDOUT;
1163 }
1164
1165 writel(SMI_OPCODE_WRITE | (reg << 21) |
1166 (addr << 16) | (val & 0xffff), smi_reg);
1167
1168 if (smi_wait_ready(msp)) {
1169 pr_warn("SMI bus busy timeout\n");
1170 return -ETIMEDOUT;
1171 }
1172
1173 return 0;
1174 }
1175
1176
1177 /* statistics ***************************************************************/
1178 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1179 {
1180 struct mv643xx_eth_private *mp = netdev_priv(dev);
1181 struct net_device_stats *stats = &dev->stats;
1182 unsigned long tx_packets = 0;
1183 unsigned long tx_bytes = 0;
1184 unsigned long tx_dropped = 0;
1185 int i;
1186
1187 for (i = 0; i < mp->txq_count; i++) {
1188 struct tx_queue *txq = mp->txq + i;
1189
1190 tx_packets += txq->tx_packets;
1191 tx_bytes += txq->tx_bytes;
1192 tx_dropped += txq->tx_dropped;
1193 }
1194
1195 stats->tx_packets = tx_packets;
1196 stats->tx_bytes = tx_bytes;
1197 stats->tx_dropped = tx_dropped;
1198
1199 return stats;
1200 }
1201
1202 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1203 {
1204 u32 lro_aggregated = 0;
1205 u32 lro_flushed = 0;
1206 u32 lro_no_desc = 0;
1207 int i;
1208
1209 for (i = 0; i < mp->rxq_count; i++) {
1210 struct rx_queue *rxq = mp->rxq + i;
1211
1212 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1213 lro_flushed += rxq->lro_mgr.stats.flushed;
1214 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1215 }
1216
1217 mp->lro_counters.lro_aggregated = lro_aggregated;
1218 mp->lro_counters.lro_flushed = lro_flushed;
1219 mp->lro_counters.lro_no_desc = lro_no_desc;
1220 }
1221
1222 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1223 {
1224 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1225 }
1226
1227 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1228 {
1229 int i;
1230
1231 for (i = 0; i < 0x80; i += 4)
1232 mib_read(mp, i);
1233
1234 /* Clear non MIB hw counters also */
1235 rdlp(mp, RX_DISCARD_FRAME_CNT);
1236 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1237 }
1238
1239 static void mib_counters_update(struct mv643xx_eth_private *mp)
1240 {
1241 struct mib_counters *p = &mp->mib_counters;
1242
1243 spin_lock_bh(&mp->mib_counters_lock);
1244 p->good_octets_received += mib_read(mp, 0x00);
1245 p->bad_octets_received += mib_read(mp, 0x08);
1246 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1247 p->good_frames_received += mib_read(mp, 0x10);
1248 p->bad_frames_received += mib_read(mp, 0x14);
1249 p->broadcast_frames_received += mib_read(mp, 0x18);
1250 p->multicast_frames_received += mib_read(mp, 0x1c);
1251 p->frames_64_octets += mib_read(mp, 0x20);
1252 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1253 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1254 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1255 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1256 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1257 p->good_octets_sent += mib_read(mp, 0x38);
1258 p->good_frames_sent += mib_read(mp, 0x40);
1259 p->excessive_collision += mib_read(mp, 0x44);
1260 p->multicast_frames_sent += mib_read(mp, 0x48);
1261 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1262 p->unrec_mac_control_received += mib_read(mp, 0x50);
1263 p->fc_sent += mib_read(mp, 0x54);
1264 p->good_fc_received += mib_read(mp, 0x58);
1265 p->bad_fc_received += mib_read(mp, 0x5c);
1266 p->undersize_received += mib_read(mp, 0x60);
1267 p->fragments_received += mib_read(mp, 0x64);
1268 p->oversize_received += mib_read(mp, 0x68);
1269 p->jabber_received += mib_read(mp, 0x6c);
1270 p->mac_receive_error += mib_read(mp, 0x70);
1271 p->bad_crc_event += mib_read(mp, 0x74);
1272 p->collision += mib_read(mp, 0x78);
1273 p->late_collision += mib_read(mp, 0x7c);
1274 /* Non MIB hardware counters */
1275 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1276 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1277 spin_unlock_bh(&mp->mib_counters_lock);
1278
1279 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1280 }
1281
1282 static void mib_counters_timer_wrapper(unsigned long _mp)
1283 {
1284 struct mv643xx_eth_private *mp = (void *)_mp;
1285
1286 mib_counters_update(mp);
1287 }
1288
1289
1290 /* interrupt coalescing *****************************************************/
1291 /*
1292 * Hardware coalescing parameters are set in units of 64 t_clk
1293 * cycles. I.e.:
1294 *
1295 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1296 *
1297 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1298 *
1299 * In the ->set*() methods, we round the computed register value
1300 * to the nearest integer.
1301 */
1302 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1303 {
1304 u32 val = rdlp(mp, SDMA_CONFIG);
1305 u64 temp;
1306
1307 if (mp->shared->extended_rx_coal_limit)
1308 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1309 else
1310 temp = (val & 0x003fff00) >> 8;
1311
1312 temp *= 64000000;
1313 do_div(temp, mp->shared->t_clk);
1314
1315 return (unsigned int)temp;
1316 }
1317
1318 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1319 {
1320 u64 temp;
1321 u32 val;
1322
1323 temp = (u64)usec * mp->shared->t_clk;
1324 temp += 31999999;
1325 do_div(temp, 64000000);
1326
1327 val = rdlp(mp, SDMA_CONFIG);
1328 if (mp->shared->extended_rx_coal_limit) {
1329 if (temp > 0xffff)
1330 temp = 0xffff;
1331 val &= ~0x023fff80;
1332 val |= (temp & 0x8000) << 10;
1333 val |= (temp & 0x7fff) << 7;
1334 } else {
1335 if (temp > 0x3fff)
1336 temp = 0x3fff;
1337 val &= ~0x003fff00;
1338 val |= (temp & 0x3fff) << 8;
1339 }
1340 wrlp(mp, SDMA_CONFIG, val);
1341 }
1342
1343 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1344 {
1345 u64 temp;
1346
1347 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1348 temp *= 64000000;
1349 do_div(temp, mp->shared->t_clk);
1350
1351 return (unsigned int)temp;
1352 }
1353
1354 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1355 {
1356 u64 temp;
1357
1358 temp = (u64)usec * mp->shared->t_clk;
1359 temp += 31999999;
1360 do_div(temp, 64000000);
1361
1362 if (temp > 0x3fff)
1363 temp = 0x3fff;
1364
1365 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1366 }
1367
1368
1369 /* ethtool ******************************************************************/
1370 struct mv643xx_eth_stats {
1371 char stat_string[ETH_GSTRING_LEN];
1372 int sizeof_stat;
1373 int netdev_off;
1374 int mp_off;
1375 };
1376
1377 #define SSTAT(m) \
1378 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1379 offsetof(struct net_device, stats.m), -1 }
1380
1381 #define MIBSTAT(m) \
1382 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1383 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1384
1385 #define LROSTAT(m) \
1386 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1387 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1388
1389 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1390 SSTAT(rx_packets),
1391 SSTAT(tx_packets),
1392 SSTAT(rx_bytes),
1393 SSTAT(tx_bytes),
1394 SSTAT(rx_errors),
1395 SSTAT(tx_errors),
1396 SSTAT(rx_dropped),
1397 SSTAT(tx_dropped),
1398 MIBSTAT(good_octets_received),
1399 MIBSTAT(bad_octets_received),
1400 MIBSTAT(internal_mac_transmit_err),
1401 MIBSTAT(good_frames_received),
1402 MIBSTAT(bad_frames_received),
1403 MIBSTAT(broadcast_frames_received),
1404 MIBSTAT(multicast_frames_received),
1405 MIBSTAT(frames_64_octets),
1406 MIBSTAT(frames_65_to_127_octets),
1407 MIBSTAT(frames_128_to_255_octets),
1408 MIBSTAT(frames_256_to_511_octets),
1409 MIBSTAT(frames_512_to_1023_octets),
1410 MIBSTAT(frames_1024_to_max_octets),
1411 MIBSTAT(good_octets_sent),
1412 MIBSTAT(good_frames_sent),
1413 MIBSTAT(excessive_collision),
1414 MIBSTAT(multicast_frames_sent),
1415 MIBSTAT(broadcast_frames_sent),
1416 MIBSTAT(unrec_mac_control_received),
1417 MIBSTAT(fc_sent),
1418 MIBSTAT(good_fc_received),
1419 MIBSTAT(bad_fc_received),
1420 MIBSTAT(undersize_received),
1421 MIBSTAT(fragments_received),
1422 MIBSTAT(oversize_received),
1423 MIBSTAT(jabber_received),
1424 MIBSTAT(mac_receive_error),
1425 MIBSTAT(bad_crc_event),
1426 MIBSTAT(collision),
1427 MIBSTAT(late_collision),
1428 MIBSTAT(rx_discard),
1429 MIBSTAT(rx_overrun),
1430 LROSTAT(lro_aggregated),
1431 LROSTAT(lro_flushed),
1432 LROSTAT(lro_no_desc),
1433 };
1434
1435 static int
1436 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1437 struct ethtool_cmd *cmd)
1438 {
1439 int err;
1440
1441 err = phy_read_status(mp->phy);
1442 if (err == 0)
1443 err = phy_ethtool_gset(mp->phy, cmd);
1444
1445 /*
1446 * The MAC does not support 1000baseT_Half.
1447 */
1448 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1449 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1450
1451 return err;
1452 }
1453
1454 static int
1455 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1456 struct ethtool_cmd *cmd)
1457 {
1458 u32 port_status;
1459
1460 port_status = rdlp(mp, PORT_STATUS);
1461
1462 cmd->supported = SUPPORTED_MII;
1463 cmd->advertising = ADVERTISED_MII;
1464 switch (port_status & PORT_SPEED_MASK) {
1465 case PORT_SPEED_10:
1466 ethtool_cmd_speed_set(cmd, SPEED_10);
1467 break;
1468 case PORT_SPEED_100:
1469 ethtool_cmd_speed_set(cmd, SPEED_100);
1470 break;
1471 case PORT_SPEED_1000:
1472 ethtool_cmd_speed_set(cmd, SPEED_1000);
1473 break;
1474 default:
1475 cmd->speed = -1;
1476 break;
1477 }
1478 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1479 cmd->port = PORT_MII;
1480 cmd->phy_address = 0;
1481 cmd->transceiver = XCVR_INTERNAL;
1482 cmd->autoneg = AUTONEG_DISABLE;
1483 cmd->maxtxpkt = 1;
1484 cmd->maxrxpkt = 1;
1485
1486 return 0;
1487 }
1488
1489 static int
1490 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1491 {
1492 struct mv643xx_eth_private *mp = netdev_priv(dev);
1493
1494 if (mp->phy != NULL)
1495 return mv643xx_eth_get_settings_phy(mp, cmd);
1496 else
1497 return mv643xx_eth_get_settings_phyless(mp, cmd);
1498 }
1499
1500 static int
1501 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1502 {
1503 struct mv643xx_eth_private *mp = netdev_priv(dev);
1504
1505 if (mp->phy == NULL)
1506 return -EINVAL;
1507
1508 /*
1509 * The MAC does not support 1000baseT_Half.
1510 */
1511 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1512
1513 return phy_ethtool_sset(mp->phy, cmd);
1514 }
1515
1516 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1517 struct ethtool_drvinfo *drvinfo)
1518 {
1519 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1520 sizeof(drvinfo->driver));
1521 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1522 sizeof(drvinfo->version));
1523 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1524 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1525 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1526 }
1527
1528 static int mv643xx_eth_nway_reset(struct net_device *dev)
1529 {
1530 struct mv643xx_eth_private *mp = netdev_priv(dev);
1531
1532 if (mp->phy == NULL)
1533 return -EINVAL;
1534
1535 return genphy_restart_aneg(mp->phy);
1536 }
1537
1538 static int
1539 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1540 {
1541 struct mv643xx_eth_private *mp = netdev_priv(dev);
1542
1543 ec->rx_coalesce_usecs = get_rx_coal(mp);
1544 ec->tx_coalesce_usecs = get_tx_coal(mp);
1545
1546 return 0;
1547 }
1548
1549 static int
1550 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1551 {
1552 struct mv643xx_eth_private *mp = netdev_priv(dev);
1553
1554 set_rx_coal(mp, ec->rx_coalesce_usecs);
1555 set_tx_coal(mp, ec->tx_coalesce_usecs);
1556
1557 return 0;
1558 }
1559
1560 static void
1561 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1562 {
1563 struct mv643xx_eth_private *mp = netdev_priv(dev);
1564
1565 er->rx_max_pending = 4096;
1566 er->tx_max_pending = 4096;
1567
1568 er->rx_pending = mp->rx_ring_size;
1569 er->tx_pending = mp->tx_ring_size;
1570 }
1571
1572 static int
1573 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1574 {
1575 struct mv643xx_eth_private *mp = netdev_priv(dev);
1576
1577 if (er->rx_mini_pending || er->rx_jumbo_pending)
1578 return -EINVAL;
1579
1580 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1581 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1582
1583 if (netif_running(dev)) {
1584 mv643xx_eth_stop(dev);
1585 if (mv643xx_eth_open(dev)) {
1586 netdev_err(dev,
1587 "fatal error on re-opening device after ring param change\n");
1588 return -ENOMEM;
1589 }
1590 }
1591
1592 return 0;
1593 }
1594
1595
1596 static int
1597 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1598 {
1599 struct mv643xx_eth_private *mp = netdev_priv(dev);
1600 bool rx_csum = features & NETIF_F_RXCSUM;
1601
1602 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1603
1604 return 0;
1605 }
1606
1607 static void mv643xx_eth_get_strings(struct net_device *dev,
1608 uint32_t stringset, uint8_t *data)
1609 {
1610 int i;
1611
1612 if (stringset == ETH_SS_STATS) {
1613 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1614 memcpy(data + i * ETH_GSTRING_LEN,
1615 mv643xx_eth_stats[i].stat_string,
1616 ETH_GSTRING_LEN);
1617 }
1618 }
1619 }
1620
1621 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1622 struct ethtool_stats *stats,
1623 uint64_t *data)
1624 {
1625 struct mv643xx_eth_private *mp = netdev_priv(dev);
1626 int i;
1627
1628 mv643xx_eth_get_stats(dev);
1629 mib_counters_update(mp);
1630 mv643xx_eth_grab_lro_stats(mp);
1631
1632 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1633 const struct mv643xx_eth_stats *stat;
1634 void *p;
1635
1636 stat = mv643xx_eth_stats + i;
1637
1638 if (stat->netdev_off >= 0)
1639 p = ((void *)mp->dev) + stat->netdev_off;
1640 else
1641 p = ((void *)mp) + stat->mp_off;
1642
1643 data[i] = (stat->sizeof_stat == 8) ?
1644 *(uint64_t *)p : *(uint32_t *)p;
1645 }
1646 }
1647
1648 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1649 {
1650 if (sset == ETH_SS_STATS)
1651 return ARRAY_SIZE(mv643xx_eth_stats);
1652
1653 return -EOPNOTSUPP;
1654 }
1655
1656 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1657 .get_settings = mv643xx_eth_get_settings,
1658 .set_settings = mv643xx_eth_set_settings,
1659 .get_drvinfo = mv643xx_eth_get_drvinfo,
1660 .nway_reset = mv643xx_eth_nway_reset,
1661 .get_link = ethtool_op_get_link,
1662 .get_coalesce = mv643xx_eth_get_coalesce,
1663 .set_coalesce = mv643xx_eth_set_coalesce,
1664 .get_ringparam = mv643xx_eth_get_ringparam,
1665 .set_ringparam = mv643xx_eth_set_ringparam,
1666 .get_strings = mv643xx_eth_get_strings,
1667 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1668 .get_sset_count = mv643xx_eth_get_sset_count,
1669 };
1670
1671
1672 /* address handling *********************************************************/
1673 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1674 {
1675 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1676 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1677
1678 addr[0] = (mac_h >> 24) & 0xff;
1679 addr[1] = (mac_h >> 16) & 0xff;
1680 addr[2] = (mac_h >> 8) & 0xff;
1681 addr[3] = mac_h & 0xff;
1682 addr[4] = (mac_l >> 8) & 0xff;
1683 addr[5] = mac_l & 0xff;
1684 }
1685
1686 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1687 {
1688 wrlp(mp, MAC_ADDR_HIGH,
1689 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1690 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1691 }
1692
1693 static u32 uc_addr_filter_mask(struct net_device *dev)
1694 {
1695 struct netdev_hw_addr *ha;
1696 u32 nibbles;
1697
1698 if (dev->flags & IFF_PROMISC)
1699 return 0;
1700
1701 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1702 netdev_for_each_uc_addr(ha, dev) {
1703 if (memcmp(dev->dev_addr, ha->addr, 5))
1704 return 0;
1705 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1706 return 0;
1707
1708 nibbles |= 1 << (ha->addr[5] & 0x0f);
1709 }
1710
1711 return nibbles;
1712 }
1713
1714 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1715 {
1716 struct mv643xx_eth_private *mp = netdev_priv(dev);
1717 u32 port_config;
1718 u32 nibbles;
1719 int i;
1720
1721 uc_addr_set(mp, dev->dev_addr);
1722
1723 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1724
1725 nibbles = uc_addr_filter_mask(dev);
1726 if (!nibbles) {
1727 port_config |= UNICAST_PROMISCUOUS_MODE;
1728 nibbles = 0xffff;
1729 }
1730
1731 for (i = 0; i < 16; i += 4) {
1732 int off = UNICAST_TABLE(mp->port_num) + i;
1733 u32 v;
1734
1735 v = 0;
1736 if (nibbles & 1)
1737 v |= 0x00000001;
1738 if (nibbles & 2)
1739 v |= 0x00000100;
1740 if (nibbles & 4)
1741 v |= 0x00010000;
1742 if (nibbles & 8)
1743 v |= 0x01000000;
1744 nibbles >>= 4;
1745
1746 wrl(mp, off, v);
1747 }
1748
1749 wrlp(mp, PORT_CONFIG, port_config);
1750 }
1751
1752 static int addr_crc(unsigned char *addr)
1753 {
1754 int crc = 0;
1755 int i;
1756
1757 for (i = 0; i < 6; i++) {
1758 int j;
1759
1760 crc = (crc ^ addr[i]) << 8;
1761 for (j = 7; j >= 0; j--) {
1762 if (crc & (0x100 << j))
1763 crc ^= 0x107 << j;
1764 }
1765 }
1766
1767 return crc;
1768 }
1769
1770 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1771 {
1772 struct mv643xx_eth_private *mp = netdev_priv(dev);
1773 u32 *mc_spec;
1774 u32 *mc_other;
1775 struct netdev_hw_addr *ha;
1776 int i;
1777
1778 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1779 int port_num;
1780 u32 accept;
1781
1782 oom:
1783 port_num = mp->port_num;
1784 accept = 0x01010101;
1785 for (i = 0; i < 0x100; i += 4) {
1786 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1787 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1788 }
1789 return;
1790 }
1791
1792 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1793 if (mc_spec == NULL)
1794 goto oom;
1795 mc_other = mc_spec + (0x100 >> 2);
1796
1797 memset(mc_spec, 0, 0x100);
1798 memset(mc_other, 0, 0x100);
1799
1800 netdev_for_each_mc_addr(ha, dev) {
1801 u8 *a = ha->addr;
1802 u32 *table;
1803 int entry;
1804
1805 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1806 table = mc_spec;
1807 entry = a[5];
1808 } else {
1809 table = mc_other;
1810 entry = addr_crc(a);
1811 }
1812
1813 table[entry >> 2] |= 1 << (8 * (entry & 3));
1814 }
1815
1816 for (i = 0; i < 0x100; i += 4) {
1817 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1818 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1819 }
1820
1821 kfree(mc_spec);
1822 }
1823
1824 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1825 {
1826 mv643xx_eth_program_unicast_filter(dev);
1827 mv643xx_eth_program_multicast_filter(dev);
1828 }
1829
1830 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1831 {
1832 struct sockaddr *sa = addr;
1833
1834 if (!is_valid_ether_addr(sa->sa_data))
1835 return -EINVAL;
1836
1837 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1838
1839 netif_addr_lock_bh(dev);
1840 mv643xx_eth_program_unicast_filter(dev);
1841 netif_addr_unlock_bh(dev);
1842
1843 return 0;
1844 }
1845
1846
1847 /* rx/tx queue initialisation ***********************************************/
1848 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1849 {
1850 struct rx_queue *rxq = mp->rxq + index;
1851 struct rx_desc *rx_desc;
1852 int size;
1853 int i;
1854
1855 rxq->index = index;
1856
1857 rxq->rx_ring_size = mp->rx_ring_size;
1858
1859 rxq->rx_desc_count = 0;
1860 rxq->rx_curr_desc = 0;
1861 rxq->rx_used_desc = 0;
1862
1863 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1864
1865 if (index == 0 && size <= mp->rx_desc_sram_size) {
1866 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1867 mp->rx_desc_sram_size);
1868 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1869 } else {
1870 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1871 size, &rxq->rx_desc_dma,
1872 GFP_KERNEL);
1873 }
1874
1875 if (rxq->rx_desc_area == NULL) {
1876 netdev_err(mp->dev,
1877 "can't allocate rx ring (%d bytes)\n", size);
1878 goto out;
1879 }
1880 memset(rxq->rx_desc_area, 0, size);
1881
1882 rxq->rx_desc_area_size = size;
1883 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1884 GFP_KERNEL);
1885 if (rxq->rx_skb == NULL) {
1886 netdev_err(mp->dev, "can't allocate rx skb ring\n");
1887 goto out_free;
1888 }
1889
1890 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1891 for (i = 0; i < rxq->rx_ring_size; i++) {
1892 int nexti;
1893
1894 nexti = i + 1;
1895 if (nexti == rxq->rx_ring_size)
1896 nexti = 0;
1897
1898 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1899 nexti * sizeof(struct rx_desc);
1900 }
1901
1902 rxq->lro_mgr.dev = mp->dev;
1903 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1904 rxq->lro_mgr.features = LRO_F_NAPI;
1905 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1906 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1907 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1908 rxq->lro_mgr.max_aggr = 32;
1909 rxq->lro_mgr.frag_align_pad = 0;
1910 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1911 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1912
1913 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
1914
1915 return 0;
1916
1917
1918 out_free:
1919 if (index == 0 && size <= mp->rx_desc_sram_size)
1920 iounmap(rxq->rx_desc_area);
1921 else
1922 dma_free_coherent(mp->dev->dev.parent, size,
1923 rxq->rx_desc_area,
1924 rxq->rx_desc_dma);
1925
1926 out:
1927 return -ENOMEM;
1928 }
1929
1930 static void rxq_deinit(struct rx_queue *rxq)
1931 {
1932 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1933 int i;
1934
1935 rxq_disable(rxq);
1936
1937 for (i = 0; i < rxq->rx_ring_size; i++) {
1938 if (rxq->rx_skb[i]) {
1939 dev_kfree_skb(rxq->rx_skb[i]);
1940 rxq->rx_desc_count--;
1941 }
1942 }
1943
1944 if (rxq->rx_desc_count) {
1945 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1946 rxq->rx_desc_count);
1947 }
1948
1949 if (rxq->index == 0 &&
1950 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1951 iounmap(rxq->rx_desc_area);
1952 else
1953 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1954 rxq->rx_desc_area, rxq->rx_desc_dma);
1955
1956 kfree(rxq->rx_skb);
1957 }
1958
1959 static int txq_init(struct mv643xx_eth_private *mp, int index)
1960 {
1961 struct tx_queue *txq = mp->txq + index;
1962 struct tx_desc *tx_desc;
1963 int size;
1964 int i;
1965
1966 txq->index = index;
1967
1968 txq->tx_ring_size = mp->tx_ring_size;
1969
1970 txq->tx_desc_count = 0;
1971 txq->tx_curr_desc = 0;
1972 txq->tx_used_desc = 0;
1973
1974 size = txq->tx_ring_size * sizeof(struct tx_desc);
1975
1976 if (index == 0 && size <= mp->tx_desc_sram_size) {
1977 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1978 mp->tx_desc_sram_size);
1979 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1980 } else {
1981 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1982 size, &txq->tx_desc_dma,
1983 GFP_KERNEL);
1984 }
1985
1986 if (txq->tx_desc_area == NULL) {
1987 netdev_err(mp->dev,
1988 "can't allocate tx ring (%d bytes)\n", size);
1989 return -ENOMEM;
1990 }
1991 memset(txq->tx_desc_area, 0, size);
1992
1993 txq->tx_desc_area_size = size;
1994
1995 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1996 for (i = 0; i < txq->tx_ring_size; i++) {
1997 struct tx_desc *txd = tx_desc + i;
1998 int nexti;
1999
2000 nexti = i + 1;
2001 if (nexti == txq->tx_ring_size)
2002 nexti = 0;
2003
2004 txd->cmd_sts = 0;
2005 txd->next_desc_ptr = txq->tx_desc_dma +
2006 nexti * sizeof(struct tx_desc);
2007 }
2008
2009 skb_queue_head_init(&txq->tx_skb);
2010
2011 return 0;
2012 }
2013
2014 static void txq_deinit(struct tx_queue *txq)
2015 {
2016 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2017
2018 txq_disable(txq);
2019 txq_reclaim(txq, txq->tx_ring_size, 1);
2020
2021 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2022
2023 if (txq->index == 0 &&
2024 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2025 iounmap(txq->tx_desc_area);
2026 else
2027 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2028 txq->tx_desc_area, txq->tx_desc_dma);
2029 }
2030
2031
2032 /* netdev ops and related ***************************************************/
2033 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2034 {
2035 u32 int_cause;
2036 u32 int_cause_ext;
2037
2038 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2039 if (int_cause == 0)
2040 return 0;
2041
2042 int_cause_ext = 0;
2043 if (int_cause & INT_EXT) {
2044 int_cause &= ~INT_EXT;
2045 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2046 }
2047
2048 if (int_cause) {
2049 wrlp(mp, INT_CAUSE, ~int_cause);
2050 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2051 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2052 mp->work_rx |= (int_cause & INT_RX) >> 2;
2053 }
2054
2055 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2056 if (int_cause_ext) {
2057 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2058 if (int_cause_ext & INT_EXT_LINK_PHY)
2059 mp->work_link = 1;
2060 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2061 }
2062
2063 return 1;
2064 }
2065
2066 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2067 {
2068 struct net_device *dev = (struct net_device *)dev_id;
2069 struct mv643xx_eth_private *mp = netdev_priv(dev);
2070
2071 if (unlikely(!mv643xx_eth_collect_events(mp)))
2072 return IRQ_NONE;
2073
2074 wrlp(mp, INT_MASK, 0);
2075 napi_schedule(&mp->napi);
2076
2077 return IRQ_HANDLED;
2078 }
2079
2080 static void handle_link_event(struct mv643xx_eth_private *mp)
2081 {
2082 struct net_device *dev = mp->dev;
2083 u32 port_status;
2084 int speed;
2085 int duplex;
2086 int fc;
2087
2088 port_status = rdlp(mp, PORT_STATUS);
2089 if (!(port_status & LINK_UP)) {
2090 if (netif_carrier_ok(dev)) {
2091 int i;
2092
2093 netdev_info(dev, "link down\n");
2094
2095 netif_carrier_off(dev);
2096
2097 for (i = 0; i < mp->txq_count; i++) {
2098 struct tx_queue *txq = mp->txq + i;
2099
2100 txq_reclaim(txq, txq->tx_ring_size, 1);
2101 txq_reset_hw_ptr(txq);
2102 }
2103 }
2104 return;
2105 }
2106
2107 switch (port_status & PORT_SPEED_MASK) {
2108 case PORT_SPEED_10:
2109 speed = 10;
2110 break;
2111 case PORT_SPEED_100:
2112 speed = 100;
2113 break;
2114 case PORT_SPEED_1000:
2115 speed = 1000;
2116 break;
2117 default:
2118 speed = -1;
2119 break;
2120 }
2121 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2122 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2123
2124 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2125 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2126
2127 if (!netif_carrier_ok(dev))
2128 netif_carrier_on(dev);
2129 }
2130
2131 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2132 {
2133 struct mv643xx_eth_private *mp;
2134 int work_done;
2135
2136 mp = container_of(napi, struct mv643xx_eth_private, napi);
2137
2138 if (unlikely(mp->oom)) {
2139 mp->oom = 0;
2140 del_timer(&mp->rx_oom);
2141 }
2142
2143 work_done = 0;
2144 while (work_done < budget) {
2145 u8 queue_mask;
2146 int queue;
2147 int work_tbd;
2148
2149 if (mp->work_link) {
2150 mp->work_link = 0;
2151 handle_link_event(mp);
2152 work_done++;
2153 continue;
2154 }
2155
2156 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2157 if (likely(!mp->oom))
2158 queue_mask |= mp->work_rx_refill;
2159
2160 if (!queue_mask) {
2161 if (mv643xx_eth_collect_events(mp))
2162 continue;
2163 break;
2164 }
2165
2166 queue = fls(queue_mask) - 1;
2167 queue_mask = 1 << queue;
2168
2169 work_tbd = budget - work_done;
2170 if (work_tbd > 16)
2171 work_tbd = 16;
2172
2173 if (mp->work_tx_end & queue_mask) {
2174 txq_kick(mp->txq + queue);
2175 } else if (mp->work_tx & queue_mask) {
2176 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2177 txq_maybe_wake(mp->txq + queue);
2178 } else if (mp->work_rx & queue_mask) {
2179 work_done += rxq_process(mp->rxq + queue, work_tbd);
2180 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2181 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2182 } else {
2183 BUG();
2184 }
2185 }
2186
2187 if (work_done < budget) {
2188 if (mp->oom)
2189 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2190 napi_complete(napi);
2191 wrlp(mp, INT_MASK, mp->int_mask);
2192 }
2193
2194 return work_done;
2195 }
2196
2197 static inline void oom_timer_wrapper(unsigned long data)
2198 {
2199 struct mv643xx_eth_private *mp = (void *)data;
2200
2201 napi_schedule(&mp->napi);
2202 }
2203
2204 static void phy_reset(struct mv643xx_eth_private *mp)
2205 {
2206 int data;
2207
2208 data = phy_read(mp->phy, MII_BMCR);
2209 if (data < 0)
2210 return;
2211
2212 data |= BMCR_RESET;
2213 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2214 return;
2215
2216 do {
2217 data = phy_read(mp->phy, MII_BMCR);
2218 } while (data >= 0 && data & BMCR_RESET);
2219 }
2220
2221 static void port_start(struct mv643xx_eth_private *mp)
2222 {
2223 u32 pscr;
2224 int i;
2225
2226 /*
2227 * Perform PHY reset, if there is a PHY.
2228 */
2229 if (mp->phy != NULL) {
2230 struct ethtool_cmd cmd;
2231
2232 mv643xx_eth_get_settings(mp->dev, &cmd);
2233 phy_reset(mp);
2234 mv643xx_eth_set_settings(mp->dev, &cmd);
2235 }
2236
2237 /*
2238 * Configure basic link parameters.
2239 */
2240 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2241
2242 pscr |= SERIAL_PORT_ENABLE;
2243 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2244
2245 pscr |= DO_NOT_FORCE_LINK_FAIL;
2246 if (mp->phy == NULL)
2247 pscr |= FORCE_LINK_PASS;
2248 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2249
2250 /*
2251 * Configure TX path and queues.
2252 */
2253 tx_set_rate(mp, 1000000000, 16777216);
2254 for (i = 0; i < mp->txq_count; i++) {
2255 struct tx_queue *txq = mp->txq + i;
2256
2257 txq_reset_hw_ptr(txq);
2258 txq_set_rate(txq, 1000000000, 16777216);
2259 txq_set_fixed_prio_mode(txq);
2260 }
2261
2262 /*
2263 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2264 * frames to RX queue #0, and include the pseudo-header when
2265 * calculating receive checksums.
2266 */
2267 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2268
2269 /*
2270 * Treat BPDUs as normal multicasts, and disable partition mode.
2271 */
2272 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2273
2274 /*
2275 * Add configured unicast addresses to address filter table.
2276 */
2277 mv643xx_eth_program_unicast_filter(mp->dev);
2278
2279 /*
2280 * Enable the receive queues.
2281 */
2282 for (i = 0; i < mp->rxq_count; i++) {
2283 struct rx_queue *rxq = mp->rxq + i;
2284 u32 addr;
2285
2286 addr = (u32)rxq->rx_desc_dma;
2287 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2288 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2289
2290 rxq_enable(rxq);
2291 }
2292 }
2293
2294 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2295 {
2296 int skb_size;
2297
2298 /*
2299 * Reserve 2+14 bytes for an ethernet header (the hardware
2300 * automatically prepends 2 bytes of dummy data to each
2301 * received packet), 16 bytes for up to four VLAN tags, and
2302 * 4 bytes for the trailing FCS -- 36 bytes total.
2303 */
2304 skb_size = mp->dev->mtu + 36;
2305
2306 /*
2307 * Make sure that the skb size is a multiple of 8 bytes, as
2308 * the lower three bits of the receive descriptor's buffer
2309 * size field are ignored by the hardware.
2310 */
2311 mp->skb_size = (skb_size + 7) & ~7;
2312
2313 /*
2314 * If NET_SKB_PAD is smaller than a cache line,
2315 * netdev_alloc_skb() will cause skb->data to be misaligned
2316 * to a cache line boundary. If this is the case, include
2317 * some extra space to allow re-aligning the data area.
2318 */
2319 mp->skb_size += SKB_DMA_REALIGN;
2320 }
2321
2322 static int mv643xx_eth_open(struct net_device *dev)
2323 {
2324 struct mv643xx_eth_private *mp = netdev_priv(dev);
2325 int err;
2326 int i;
2327
2328 wrlp(mp, INT_CAUSE, 0);
2329 wrlp(mp, INT_CAUSE_EXT, 0);
2330 rdlp(mp, INT_CAUSE_EXT);
2331
2332 err = request_irq(dev->irq, mv643xx_eth_irq,
2333 IRQF_SHARED, dev->name, dev);
2334 if (err) {
2335 netdev_err(dev, "can't assign irq\n");
2336 return -EAGAIN;
2337 }
2338
2339 mv643xx_eth_recalc_skb_size(mp);
2340
2341 napi_enable(&mp->napi);
2342
2343 skb_queue_head_init(&mp->rx_recycle);
2344
2345 mp->int_mask = INT_EXT;
2346
2347 for (i = 0; i < mp->rxq_count; i++) {
2348 err = rxq_init(mp, i);
2349 if (err) {
2350 while (--i >= 0)
2351 rxq_deinit(mp->rxq + i);
2352 goto out;
2353 }
2354
2355 rxq_refill(mp->rxq + i, INT_MAX);
2356 mp->int_mask |= INT_RX_0 << i;
2357 }
2358
2359 if (mp->oom) {
2360 mp->rx_oom.expires = jiffies + (HZ / 10);
2361 add_timer(&mp->rx_oom);
2362 }
2363
2364 for (i = 0; i < mp->txq_count; i++) {
2365 err = txq_init(mp, i);
2366 if (err) {
2367 while (--i >= 0)
2368 txq_deinit(mp->txq + i);
2369 goto out_free;
2370 }
2371 mp->int_mask |= INT_TX_END_0 << i;
2372 }
2373
2374 port_start(mp);
2375
2376 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2377 wrlp(mp, INT_MASK, mp->int_mask);
2378
2379 return 0;
2380
2381
2382 out_free:
2383 for (i = 0; i < mp->rxq_count; i++)
2384 rxq_deinit(mp->rxq + i);
2385 out:
2386 free_irq(dev->irq, dev);
2387
2388 return err;
2389 }
2390
2391 static void port_reset(struct mv643xx_eth_private *mp)
2392 {
2393 unsigned int data;
2394 int i;
2395
2396 for (i = 0; i < mp->rxq_count; i++)
2397 rxq_disable(mp->rxq + i);
2398 for (i = 0; i < mp->txq_count; i++)
2399 txq_disable(mp->txq + i);
2400
2401 while (1) {
2402 u32 ps = rdlp(mp, PORT_STATUS);
2403
2404 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2405 break;
2406 udelay(10);
2407 }
2408
2409 /* Reset the Enable bit in the Configuration Register */
2410 data = rdlp(mp, PORT_SERIAL_CONTROL);
2411 data &= ~(SERIAL_PORT_ENABLE |
2412 DO_NOT_FORCE_LINK_FAIL |
2413 FORCE_LINK_PASS);
2414 wrlp(mp, PORT_SERIAL_CONTROL, data);
2415 }
2416
2417 static int mv643xx_eth_stop(struct net_device *dev)
2418 {
2419 struct mv643xx_eth_private *mp = netdev_priv(dev);
2420 int i;
2421
2422 wrlp(mp, INT_MASK_EXT, 0x00000000);
2423 wrlp(mp, INT_MASK, 0x00000000);
2424 rdlp(mp, INT_MASK);
2425
2426 napi_disable(&mp->napi);
2427
2428 del_timer_sync(&mp->rx_oom);
2429
2430 netif_carrier_off(dev);
2431
2432 free_irq(dev->irq, dev);
2433
2434 port_reset(mp);
2435 mv643xx_eth_get_stats(dev);
2436 mib_counters_update(mp);
2437 del_timer_sync(&mp->mib_counters_timer);
2438
2439 skb_queue_purge(&mp->rx_recycle);
2440
2441 for (i = 0; i < mp->rxq_count; i++)
2442 rxq_deinit(mp->rxq + i);
2443 for (i = 0; i < mp->txq_count; i++)
2444 txq_deinit(mp->txq + i);
2445
2446 return 0;
2447 }
2448
2449 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2450 {
2451 struct mv643xx_eth_private *mp = netdev_priv(dev);
2452
2453 if (mp->phy != NULL)
2454 return phy_mii_ioctl(mp->phy, ifr, cmd);
2455
2456 return -EOPNOTSUPP;
2457 }
2458
2459 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2460 {
2461 struct mv643xx_eth_private *mp = netdev_priv(dev);
2462
2463 if (new_mtu < 64 || new_mtu > 9500)
2464 return -EINVAL;
2465
2466 dev->mtu = new_mtu;
2467 mv643xx_eth_recalc_skb_size(mp);
2468 tx_set_rate(mp, 1000000000, 16777216);
2469
2470 if (!netif_running(dev))
2471 return 0;
2472
2473 /*
2474 * Stop and then re-open the interface. This will allocate RX
2475 * skbs of the new MTU.
2476 * There is a possible danger that the open will not succeed,
2477 * due to memory being full.
2478 */
2479 mv643xx_eth_stop(dev);
2480 if (mv643xx_eth_open(dev)) {
2481 netdev_err(dev,
2482 "fatal error on re-opening device after MTU change\n");
2483 }
2484
2485 return 0;
2486 }
2487
2488 static void tx_timeout_task(struct work_struct *ugly)
2489 {
2490 struct mv643xx_eth_private *mp;
2491
2492 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2493 if (netif_running(mp->dev)) {
2494 netif_tx_stop_all_queues(mp->dev);
2495 port_reset(mp);
2496 port_start(mp);
2497 netif_tx_wake_all_queues(mp->dev);
2498 }
2499 }
2500
2501 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2502 {
2503 struct mv643xx_eth_private *mp = netdev_priv(dev);
2504
2505 netdev_info(dev, "tx timeout\n");
2506
2507 schedule_work(&mp->tx_timeout_task);
2508 }
2509
2510 #ifdef CONFIG_NET_POLL_CONTROLLER
2511 static void mv643xx_eth_netpoll(struct net_device *dev)
2512 {
2513 struct mv643xx_eth_private *mp = netdev_priv(dev);
2514
2515 wrlp(mp, INT_MASK, 0x00000000);
2516 rdlp(mp, INT_MASK);
2517
2518 mv643xx_eth_irq(dev->irq, dev);
2519
2520 wrlp(mp, INT_MASK, mp->int_mask);
2521 }
2522 #endif
2523
2524
2525 /* platform glue ************************************************************/
2526 static void
2527 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2528 const struct mbus_dram_target_info *dram)
2529 {
2530 void __iomem *base = msp->base;
2531 u32 win_enable;
2532 u32 win_protect;
2533 int i;
2534
2535 for (i = 0; i < 6; i++) {
2536 writel(0, base + WINDOW_BASE(i));
2537 writel(0, base + WINDOW_SIZE(i));
2538 if (i < 4)
2539 writel(0, base + WINDOW_REMAP_HIGH(i));
2540 }
2541
2542 win_enable = 0x3f;
2543 win_protect = 0;
2544
2545 for (i = 0; i < dram->num_cs; i++) {
2546 const struct mbus_dram_window *cs = dram->cs + i;
2547
2548 writel((cs->base & 0xffff0000) |
2549 (cs->mbus_attr << 8) |
2550 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2551 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2552
2553 win_enable &= ~(1 << i);
2554 win_protect |= 3 << (2 * i);
2555 }
2556
2557 writel(win_enable, base + WINDOW_BAR_ENABLE);
2558 msp->win_protect = win_protect;
2559 }
2560
2561 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2562 {
2563 /*
2564 * Check whether we have a 14-bit coal limit field in bits
2565 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2566 * SDMA config register.
2567 */
2568 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2569 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2570 msp->extended_rx_coal_limit = 1;
2571 else
2572 msp->extended_rx_coal_limit = 0;
2573
2574 /*
2575 * Check whether the MAC supports TX rate control, and if
2576 * yes, whether its associated registers are in the old or
2577 * the new place.
2578 */
2579 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2580 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2581 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2582 } else {
2583 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2584 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2585 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2586 else
2587 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2588 }
2589 }
2590
2591 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2592 {
2593 static int mv643xx_eth_version_printed;
2594 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2595 struct mv643xx_eth_shared_private *msp;
2596 const struct mbus_dram_target_info *dram;
2597 struct resource *res;
2598 int ret;
2599
2600 if (!mv643xx_eth_version_printed++)
2601 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2602 mv643xx_eth_driver_version);
2603
2604 ret = -EINVAL;
2605 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2606 if (res == NULL)
2607 goto out;
2608
2609 ret = -ENOMEM;
2610 msp = kzalloc(sizeof(*msp), GFP_KERNEL);
2611 if (msp == NULL)
2612 goto out;
2613
2614 msp->base = ioremap(res->start, resource_size(res));
2615 if (msp->base == NULL)
2616 goto out_free;
2617
2618 /*
2619 * Set up and register SMI bus.
2620 */
2621 if (pd == NULL || pd->shared_smi == NULL) {
2622 msp->smi_bus = mdiobus_alloc();
2623 if (msp->smi_bus == NULL)
2624 goto out_unmap;
2625
2626 msp->smi_bus->priv = msp;
2627 msp->smi_bus->name = "mv643xx_eth smi";
2628 msp->smi_bus->read = smi_bus_read;
2629 msp->smi_bus->write = smi_bus_write,
2630 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
2631 pdev->name, pdev->id);
2632 msp->smi_bus->parent = &pdev->dev;
2633 msp->smi_bus->phy_mask = 0xffffffff;
2634 if (mdiobus_register(msp->smi_bus) < 0)
2635 goto out_free_mii_bus;
2636 msp->smi = msp;
2637 } else {
2638 msp->smi = platform_get_drvdata(pd->shared_smi);
2639 }
2640
2641 msp->err_interrupt = NO_IRQ;
2642 init_waitqueue_head(&msp->smi_busy_wait);
2643
2644 /*
2645 * Check whether the error interrupt is hooked up.
2646 */
2647 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2648 if (res != NULL) {
2649 int err;
2650
2651 err = request_irq(res->start, mv643xx_eth_err_irq,
2652 IRQF_SHARED, "mv643xx_eth", msp);
2653 if (!err) {
2654 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2655 msp->err_interrupt = res->start;
2656 }
2657 }
2658
2659 /*
2660 * (Re-)program MBUS remapping windows if we are asked to.
2661 */
2662 dram = mv_mbus_dram_info();
2663 if (dram)
2664 mv643xx_eth_conf_mbus_windows(msp, dram);
2665
2666 /*
2667 * Detect hardware parameters.
2668 */
2669 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2670 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2671 pd->tx_csum_limit : 9 * 1024;
2672 infer_hw_params(msp);
2673
2674 platform_set_drvdata(pdev, msp);
2675
2676 return 0;
2677
2678 out_free_mii_bus:
2679 mdiobus_free(msp->smi_bus);
2680 out_unmap:
2681 iounmap(msp->base);
2682 out_free:
2683 kfree(msp);
2684 out:
2685 return ret;
2686 }
2687
2688 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2689 {
2690 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2691 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2692
2693 if (pd == NULL || pd->shared_smi == NULL) {
2694 mdiobus_unregister(msp->smi_bus);
2695 mdiobus_free(msp->smi_bus);
2696 }
2697 if (msp->err_interrupt != NO_IRQ)
2698 free_irq(msp->err_interrupt, msp);
2699 iounmap(msp->base);
2700 kfree(msp);
2701
2702 return 0;
2703 }
2704
2705 static struct platform_driver mv643xx_eth_shared_driver = {
2706 .probe = mv643xx_eth_shared_probe,
2707 .remove = mv643xx_eth_shared_remove,
2708 .driver = {
2709 .name = MV643XX_ETH_SHARED_NAME,
2710 .owner = THIS_MODULE,
2711 },
2712 };
2713
2714 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2715 {
2716 int addr_shift = 5 * mp->port_num;
2717 u32 data;
2718
2719 data = rdl(mp, PHY_ADDR);
2720 data &= ~(0x1f << addr_shift);
2721 data |= (phy_addr & 0x1f) << addr_shift;
2722 wrl(mp, PHY_ADDR, data);
2723 }
2724
2725 static int phy_addr_get(struct mv643xx_eth_private *mp)
2726 {
2727 unsigned int data;
2728
2729 data = rdl(mp, PHY_ADDR);
2730
2731 return (data >> (5 * mp->port_num)) & 0x1f;
2732 }
2733
2734 static void set_params(struct mv643xx_eth_private *mp,
2735 struct mv643xx_eth_platform_data *pd)
2736 {
2737 struct net_device *dev = mp->dev;
2738
2739 if (is_valid_ether_addr(pd->mac_addr))
2740 memcpy(dev->dev_addr, pd->mac_addr, 6);
2741 else
2742 uc_addr_get(mp, dev->dev_addr);
2743
2744 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2745 if (pd->rx_queue_size)
2746 mp->rx_ring_size = pd->rx_queue_size;
2747 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2748 mp->rx_desc_sram_size = pd->rx_sram_size;
2749
2750 mp->rxq_count = pd->rx_queue_count ? : 1;
2751
2752 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2753 if (pd->tx_queue_size)
2754 mp->tx_ring_size = pd->tx_queue_size;
2755 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2756 mp->tx_desc_sram_size = pd->tx_sram_size;
2757
2758 mp->txq_count = pd->tx_queue_count ? : 1;
2759 }
2760
2761 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2762 int phy_addr)
2763 {
2764 struct mii_bus *bus = mp->shared->smi->smi_bus;
2765 struct phy_device *phydev;
2766 int start;
2767 int num;
2768 int i;
2769
2770 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2771 start = phy_addr_get(mp) & 0x1f;
2772 num = 32;
2773 } else {
2774 start = phy_addr & 0x1f;
2775 num = 1;
2776 }
2777
2778 phydev = NULL;
2779 for (i = 0; i < num; i++) {
2780 int addr = (start + i) & 0x1f;
2781
2782 if (bus->phy_map[addr] == NULL)
2783 mdiobus_scan(bus, addr);
2784
2785 if (phydev == NULL) {
2786 phydev = bus->phy_map[addr];
2787 if (phydev != NULL)
2788 phy_addr_set(mp, addr);
2789 }
2790 }
2791
2792 return phydev;
2793 }
2794
2795 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2796 {
2797 struct phy_device *phy = mp->phy;
2798
2799 phy_reset(mp);
2800
2801 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
2802
2803 if (speed == 0) {
2804 phy->autoneg = AUTONEG_ENABLE;
2805 phy->speed = 0;
2806 phy->duplex = 0;
2807 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2808 } else {
2809 phy->autoneg = AUTONEG_DISABLE;
2810 phy->advertising = 0;
2811 phy->speed = speed;
2812 phy->duplex = duplex;
2813 }
2814 phy_start_aneg(phy);
2815 }
2816
2817 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2818 {
2819 u32 pscr;
2820
2821 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2822 if (pscr & SERIAL_PORT_ENABLE) {
2823 pscr &= ~SERIAL_PORT_ENABLE;
2824 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2825 }
2826
2827 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2828 if (mp->phy == NULL) {
2829 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2830 if (speed == SPEED_1000)
2831 pscr |= SET_GMII_SPEED_TO_1000;
2832 else if (speed == SPEED_100)
2833 pscr |= SET_MII_SPEED_TO_100;
2834
2835 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2836
2837 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2838 if (duplex == DUPLEX_FULL)
2839 pscr |= SET_FULL_DUPLEX_MODE;
2840 }
2841
2842 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2843 }
2844
2845 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2846 .ndo_open = mv643xx_eth_open,
2847 .ndo_stop = mv643xx_eth_stop,
2848 .ndo_start_xmit = mv643xx_eth_xmit,
2849 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2850 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2851 .ndo_validate_addr = eth_validate_addr,
2852 .ndo_do_ioctl = mv643xx_eth_ioctl,
2853 .ndo_change_mtu = mv643xx_eth_change_mtu,
2854 .ndo_set_features = mv643xx_eth_set_features,
2855 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2856 .ndo_get_stats = mv643xx_eth_get_stats,
2857 #ifdef CONFIG_NET_POLL_CONTROLLER
2858 .ndo_poll_controller = mv643xx_eth_netpoll,
2859 #endif
2860 };
2861
2862 static int mv643xx_eth_probe(struct platform_device *pdev)
2863 {
2864 struct mv643xx_eth_platform_data *pd;
2865 struct mv643xx_eth_private *mp;
2866 struct net_device *dev;
2867 struct resource *res;
2868 int err;
2869
2870 pd = pdev->dev.platform_data;
2871 if (pd == NULL) {
2872 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2873 return -ENODEV;
2874 }
2875
2876 if (pd->shared == NULL) {
2877 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2878 return -ENODEV;
2879 }
2880
2881 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2882 if (!dev)
2883 return -ENOMEM;
2884
2885 mp = netdev_priv(dev);
2886 platform_set_drvdata(pdev, mp);
2887
2888 mp->shared = platform_get_drvdata(pd->shared);
2889 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2890 mp->port_num = pd->port_number;
2891
2892 mp->dev = dev;
2893
2894 set_params(mp, pd);
2895 netif_set_real_num_tx_queues(dev, mp->txq_count);
2896 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2897
2898 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2899 mp->phy = phy_scan(mp, pd->phy_addr);
2900
2901 if (mp->phy != NULL)
2902 phy_init(mp, pd->speed, pd->duplex);
2903
2904 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2905
2906 init_pscr(mp, pd->speed, pd->duplex);
2907
2908
2909 mib_counters_clear(mp);
2910
2911 init_timer(&mp->mib_counters_timer);
2912 mp->mib_counters_timer.data = (unsigned long)mp;
2913 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2914 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2915 add_timer(&mp->mib_counters_timer);
2916
2917 spin_lock_init(&mp->mib_counters_lock);
2918
2919 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2920
2921 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2922
2923 init_timer(&mp->rx_oom);
2924 mp->rx_oom.data = (unsigned long)mp;
2925 mp->rx_oom.function = oom_timer_wrapper;
2926
2927
2928 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2929 BUG_ON(!res);
2930 dev->irq = res->start;
2931
2932 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2933
2934 dev->watchdog_timeo = 2 * HZ;
2935 dev->base_addr = 0;
2936
2937 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
2938 NETIF_F_RXCSUM | NETIF_F_LRO;
2939 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2940 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2941
2942 dev->priv_flags |= IFF_UNICAST_FLT;
2943
2944 SET_NETDEV_DEV(dev, &pdev->dev);
2945
2946 if (mp->shared->win_protect)
2947 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2948
2949 netif_carrier_off(dev);
2950
2951 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2952
2953 set_rx_coal(mp, 250);
2954 set_tx_coal(mp, 0);
2955
2956 err = register_netdev(dev);
2957 if (err)
2958 goto out;
2959
2960 netdev_notice(dev, "port %d with MAC address %pM\n",
2961 mp->port_num, dev->dev_addr);
2962
2963 if (mp->tx_desc_sram_size > 0)
2964 netdev_notice(dev, "configured with sram\n");
2965
2966 return 0;
2967
2968 out:
2969 free_netdev(dev);
2970
2971 return err;
2972 }
2973
2974 static int mv643xx_eth_remove(struct platform_device *pdev)
2975 {
2976 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2977
2978 unregister_netdev(mp->dev);
2979 if (mp->phy != NULL)
2980 phy_detach(mp->phy);
2981 cancel_work_sync(&mp->tx_timeout_task);
2982 free_netdev(mp->dev);
2983
2984 platform_set_drvdata(pdev, NULL);
2985
2986 return 0;
2987 }
2988
2989 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2990 {
2991 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2992
2993 /* Mask all interrupts on ethernet port */
2994 wrlp(mp, INT_MASK, 0);
2995 rdlp(mp, INT_MASK);
2996
2997 if (netif_running(mp->dev))
2998 port_reset(mp);
2999 }
3000
3001 static struct platform_driver mv643xx_eth_driver = {
3002 .probe = mv643xx_eth_probe,
3003 .remove = mv643xx_eth_remove,
3004 .shutdown = mv643xx_eth_shutdown,
3005 .driver = {
3006 .name = MV643XX_ETH_NAME,
3007 .owner = THIS_MODULE,
3008 },
3009 };
3010
3011 static int __init mv643xx_eth_init_module(void)
3012 {
3013 int rc;
3014
3015 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3016 if (!rc) {
3017 rc = platform_driver_register(&mv643xx_eth_driver);
3018 if (rc)
3019 platform_driver_unregister(&mv643xx_eth_shared_driver);
3020 }
3021
3022 return rc;
3023 }
3024 module_init(mv643xx_eth_init_module);
3025
3026 static void __exit mv643xx_eth_cleanup_module(void)
3027 {
3028 platform_driver_unregister(&mv643xx_eth_driver);
3029 platform_driver_unregister(&mv643xx_eth_shared_driver);
3030 }
3031 module_exit(mv643xx_eth_cleanup_module);
3032
3033 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3034 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3035 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3036 MODULE_LICENSE("GPL");
3037 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3038 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);