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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / net / ethernet / nvidia / forcedeth.c
blob4c4e7f4583830ce9231bd1ebef8ab3a1fed99fa2
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 #define FORCEDETH_VERSION "0.64"
46 #define DRV_NAME "forcedeth"
47
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/delay.h>
55 #include <linux/sched.h>
56 #include <linux/spinlock.h>
57 #include <linux/ethtool.h>
58 #include <linux/timer.h>
59 #include <linux/skbuff.h>
60 #include <linux/mii.h>
61 #include <linux/random.h>
62 #include <linux/init.h>
63 #include <linux/if_vlan.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/slab.h>
66 #include <linux/uaccess.h>
67 #include <linux/prefetch.h>
68 #include <linux/u64_stats_sync.h>
69 #include <linux/io.h>
70
71 #include <asm/irq.h>
72 #include <asm/system.h>
73
74 #define TX_WORK_PER_LOOP 64
75 #define RX_WORK_PER_LOOP 64
76
77 /*
78 * Hardware access:
79 */
80
81 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
82 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
83 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
84 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
85 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
86 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
87 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
88 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
89 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
90 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
91 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
92 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
93 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
94 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
95 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
96 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
97 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
98 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
99 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
100 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
101 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
102 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
103 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
104 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
105 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
106 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
107 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
108
109 enum {
110 NvRegIrqStatus = 0x000,
111 #define NVREG_IRQSTAT_MIIEVENT 0x040
112 #define NVREG_IRQSTAT_MASK 0x83ff
113 NvRegIrqMask = 0x004,
114 #define NVREG_IRQ_RX_ERROR 0x0001
115 #define NVREG_IRQ_RX 0x0002
116 #define NVREG_IRQ_RX_NOBUF 0x0004
117 #define NVREG_IRQ_TX_ERR 0x0008
118 #define NVREG_IRQ_TX_OK 0x0010
119 #define NVREG_IRQ_TIMER 0x0020
120 #define NVREG_IRQ_LINK 0x0040
121 #define NVREG_IRQ_RX_FORCED 0x0080
122 #define NVREG_IRQ_TX_FORCED 0x0100
123 #define NVREG_IRQ_RECOVER_ERROR 0x8200
124 #define NVREG_IRQMASK_THROUGHPUT 0x00df
125 #define NVREG_IRQMASK_CPU 0x0060
126 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
127 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
128 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
129
130 NvRegUnknownSetupReg6 = 0x008,
131 #define NVREG_UNKSETUP6_VAL 3
132
133 /*
134 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
135 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
136 */
137 NvRegPollingInterval = 0x00c,
138 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
139 #define NVREG_POLL_DEFAULT_CPU 13
140 NvRegMSIMap0 = 0x020,
141 NvRegMSIMap1 = 0x024,
142 NvRegMSIIrqMask = 0x030,
143 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
144 NvRegMisc1 = 0x080,
145 #define NVREG_MISC1_PAUSE_TX 0x01
146 #define NVREG_MISC1_HD 0x02
147 #define NVREG_MISC1_FORCE 0x3b0f3c
148
149 NvRegMacReset = 0x34,
150 #define NVREG_MAC_RESET_ASSERT 0x0F3
151 NvRegTransmitterControl = 0x084,
152 #define NVREG_XMITCTL_START 0x01
153 #define NVREG_XMITCTL_MGMT_ST 0x40000000
154 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
155 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
156 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
157 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
158 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
159 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
160 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
161 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
162 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
163 #define NVREG_XMITCTL_DATA_START 0x00100000
164 #define NVREG_XMITCTL_DATA_READY 0x00010000
165 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
166 NvRegTransmitterStatus = 0x088,
167 #define NVREG_XMITSTAT_BUSY 0x01
168
169 NvRegPacketFilterFlags = 0x8c,
170 #define NVREG_PFF_PAUSE_RX 0x08
171 #define NVREG_PFF_ALWAYS 0x7F0000
172 #define NVREG_PFF_PROMISC 0x80
173 #define NVREG_PFF_MYADDR 0x20
174 #define NVREG_PFF_LOOPBACK 0x10
175
176 NvRegOffloadConfig = 0x90,
177 #define NVREG_OFFLOAD_HOMEPHY 0x601
178 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
179 NvRegReceiverControl = 0x094,
180 #define NVREG_RCVCTL_START 0x01
181 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
182 NvRegReceiverStatus = 0x98,
183 #define NVREG_RCVSTAT_BUSY 0x01
184
185 NvRegSlotTime = 0x9c,
186 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
187 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
188 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
189 #define NVREG_SLOTTIME_HALF 0x0000ff00
190 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
191 #define NVREG_SLOTTIME_MASK 0x000000ff
192
193 NvRegTxDeferral = 0xA0,
194 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
195 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
196 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
198 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
199 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
200 NvRegRxDeferral = 0xA4,
201 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
202 NvRegMacAddrA = 0xA8,
203 NvRegMacAddrB = 0xAC,
204 NvRegMulticastAddrA = 0xB0,
205 #define NVREG_MCASTADDRA_FORCE 0x01
206 NvRegMulticastAddrB = 0xB4,
207 NvRegMulticastMaskA = 0xB8,
208 #define NVREG_MCASTMASKA_NONE 0xffffffff
209 NvRegMulticastMaskB = 0xBC,
210 #define NVREG_MCASTMASKB_NONE 0xffff
211
212 NvRegPhyInterface = 0xC0,
213 #define PHY_RGMII 0x10000000
214 NvRegBackOffControl = 0xC4,
215 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
216 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
217 #define NVREG_BKOFFCTRL_SELECT 24
218 #define NVREG_BKOFFCTRL_GEAR 12
219
220 NvRegTxRingPhysAddr = 0x100,
221 NvRegRxRingPhysAddr = 0x104,
222 NvRegRingSizes = 0x108,
223 #define NVREG_RINGSZ_TXSHIFT 0
224 #define NVREG_RINGSZ_RXSHIFT 16
225 NvRegTransmitPoll = 0x10c,
226 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
227 NvRegLinkSpeed = 0x110,
228 #define NVREG_LINKSPEED_FORCE 0x10000
229 #define NVREG_LINKSPEED_10 1000
230 #define NVREG_LINKSPEED_100 100
231 #define NVREG_LINKSPEED_1000 50
232 #define NVREG_LINKSPEED_MASK (0xFFF)
233 NvRegUnknownSetupReg5 = 0x130,
234 #define NVREG_UNKSETUP5_BIT31 (1<<31)
235 NvRegTxWatermark = 0x13c,
236 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
237 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
238 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
239 NvRegTxRxControl = 0x144,
240 #define NVREG_TXRXCTL_KICK 0x0001
241 #define NVREG_TXRXCTL_BIT1 0x0002
242 #define NVREG_TXRXCTL_BIT2 0x0004
243 #define NVREG_TXRXCTL_IDLE 0x0008
244 #define NVREG_TXRXCTL_RESET 0x0010
245 #define NVREG_TXRXCTL_RXCHECK 0x0400
246 #define NVREG_TXRXCTL_DESC_1 0
247 #define NVREG_TXRXCTL_DESC_2 0x002100
248 #define NVREG_TXRXCTL_DESC_3 0xc02200
249 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
250 #define NVREG_TXRXCTL_VLANINS 0x00080
251 NvRegTxRingPhysAddrHigh = 0x148,
252 NvRegRxRingPhysAddrHigh = 0x14C,
253 NvRegTxPauseFrame = 0x170,
254 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
256 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
257 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
258 NvRegTxPauseFrameLimit = 0x174,
259 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
260 NvRegMIIStatus = 0x180,
261 #define NVREG_MIISTAT_ERROR 0x0001
262 #define NVREG_MIISTAT_LINKCHANGE 0x0008
263 #define NVREG_MIISTAT_MASK_RW 0x0007
264 #define NVREG_MIISTAT_MASK_ALL 0x000f
265 NvRegMIIMask = 0x184,
266 #define NVREG_MII_LINKCHANGE 0x0008
267
268 NvRegAdapterControl = 0x188,
269 #define NVREG_ADAPTCTL_START 0x02
270 #define NVREG_ADAPTCTL_LINKUP 0x04
271 #define NVREG_ADAPTCTL_PHYVALID 0x40000
272 #define NVREG_ADAPTCTL_RUNNING 0x100000
273 #define NVREG_ADAPTCTL_PHYSHIFT 24
274 NvRegMIISpeed = 0x18c,
275 #define NVREG_MIISPEED_BIT8 (1<<8)
276 #define NVREG_MIIDELAY 5
277 NvRegMIIControl = 0x190,
278 #define NVREG_MIICTL_INUSE 0x08000
279 #define NVREG_MIICTL_WRITE 0x00400
280 #define NVREG_MIICTL_ADDRSHIFT 5
281 NvRegMIIData = 0x194,
282 NvRegTxUnicast = 0x1a0,
283 NvRegTxMulticast = 0x1a4,
284 NvRegTxBroadcast = 0x1a8,
285 NvRegWakeUpFlags = 0x200,
286 #define NVREG_WAKEUPFLAGS_VAL 0x7770
287 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
288 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
289 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
290 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
291 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
292 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
293 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
294 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
295 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
296 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
297
298 NvRegMgmtUnitGetVersion = 0x204,
299 #define NVREG_MGMTUNITGETVERSION 0x01
300 NvRegMgmtUnitVersion = 0x208,
301 #define NVREG_MGMTUNITVERSION 0x08
302 NvRegPowerCap = 0x268,
303 #define NVREG_POWERCAP_D3SUPP (1<<30)
304 #define NVREG_POWERCAP_D2SUPP (1<<26)
305 #define NVREG_POWERCAP_D1SUPP (1<<25)
306 NvRegPowerState = 0x26c,
307 #define NVREG_POWERSTATE_POWEREDUP 0x8000
308 #define NVREG_POWERSTATE_VALID 0x0100
309 #define NVREG_POWERSTATE_MASK 0x0003
310 #define NVREG_POWERSTATE_D0 0x0000
311 #define NVREG_POWERSTATE_D1 0x0001
312 #define NVREG_POWERSTATE_D2 0x0002
313 #define NVREG_POWERSTATE_D3 0x0003
314 NvRegMgmtUnitControl = 0x278,
315 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
316 NvRegTxCnt = 0x280,
317 NvRegTxZeroReXmt = 0x284,
318 NvRegTxOneReXmt = 0x288,
319 NvRegTxManyReXmt = 0x28c,
320 NvRegTxLateCol = 0x290,
321 NvRegTxUnderflow = 0x294,
322 NvRegTxLossCarrier = 0x298,
323 NvRegTxExcessDef = 0x29c,
324 NvRegTxRetryErr = 0x2a0,
325 NvRegRxFrameErr = 0x2a4,
326 NvRegRxExtraByte = 0x2a8,
327 NvRegRxLateCol = 0x2ac,
328 NvRegRxRunt = 0x2b0,
329 NvRegRxFrameTooLong = 0x2b4,
330 NvRegRxOverflow = 0x2b8,
331 NvRegRxFCSErr = 0x2bc,
332 NvRegRxFrameAlignErr = 0x2c0,
333 NvRegRxLenErr = 0x2c4,
334 NvRegRxUnicast = 0x2c8,
335 NvRegRxMulticast = 0x2cc,
336 NvRegRxBroadcast = 0x2d0,
337 NvRegTxDef = 0x2d4,
338 NvRegTxFrame = 0x2d8,
339 NvRegRxCnt = 0x2dc,
340 NvRegTxPause = 0x2e0,
341 NvRegRxPause = 0x2e4,
342 NvRegRxDropFrame = 0x2e8,
343 NvRegVlanControl = 0x300,
344 #define NVREG_VLANCONTROL_ENABLE 0x2000
345 NvRegMSIXMap0 = 0x3e0,
346 NvRegMSIXMap1 = 0x3e4,
347 NvRegMSIXIrqStatus = 0x3f0,
348
349 NvRegPowerState2 = 0x600,
350 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
351 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
352 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
353 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
354 };
355
356 /* Big endian: should work, but is untested */
357 struct ring_desc {
358 __le32 buf;
359 __le32 flaglen;
360 };
361
362 struct ring_desc_ex {
363 __le32 bufhigh;
364 __le32 buflow;
365 __le32 txvlan;
366 __le32 flaglen;
367 };
368
369 union ring_type {
370 struct ring_desc *orig;
371 struct ring_desc_ex *ex;
372 };
373
374 #define FLAG_MASK_V1 0xffff0000
375 #define FLAG_MASK_V2 0xffffc000
376 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
377 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
378
379 #define NV_TX_LASTPACKET (1<<16)
380 #define NV_TX_RETRYERROR (1<<19)
381 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
382 #define NV_TX_FORCED_INTERRUPT (1<<24)
383 #define NV_TX_DEFERRED (1<<26)
384 #define NV_TX_CARRIERLOST (1<<27)
385 #define NV_TX_LATECOLLISION (1<<28)
386 #define NV_TX_UNDERFLOW (1<<29)
387 #define NV_TX_ERROR (1<<30)
388 #define NV_TX_VALID (1<<31)
389
390 #define NV_TX2_LASTPACKET (1<<29)
391 #define NV_TX2_RETRYERROR (1<<18)
392 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
393 #define NV_TX2_FORCED_INTERRUPT (1<<30)
394 #define NV_TX2_DEFERRED (1<<25)
395 #define NV_TX2_CARRIERLOST (1<<26)
396 #define NV_TX2_LATECOLLISION (1<<27)
397 #define NV_TX2_UNDERFLOW (1<<28)
398 /* error and valid are the same for both */
399 #define NV_TX2_ERROR (1<<30)
400 #define NV_TX2_VALID (1<<31)
401 #define NV_TX2_TSO (1<<28)
402 #define NV_TX2_TSO_SHIFT 14
403 #define NV_TX2_TSO_MAX_SHIFT 14
404 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
405 #define NV_TX2_CHECKSUM_L3 (1<<27)
406 #define NV_TX2_CHECKSUM_L4 (1<<26)
407
408 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
409
410 #define NV_RX_DESCRIPTORVALID (1<<16)
411 #define NV_RX_MISSEDFRAME (1<<17)
412 #define NV_RX_SUBSTRACT1 (1<<18)
413 #define NV_RX_ERROR1 (1<<23)
414 #define NV_RX_ERROR2 (1<<24)
415 #define NV_RX_ERROR3 (1<<25)
416 #define NV_RX_ERROR4 (1<<26)
417 #define NV_RX_CRCERR (1<<27)
418 #define NV_RX_OVERFLOW (1<<28)
419 #define NV_RX_FRAMINGERR (1<<29)
420 #define NV_RX_ERROR (1<<30)
421 #define NV_RX_AVAIL (1<<31)
422 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
423
424 #define NV_RX2_CHECKSUMMASK (0x1C000000)
425 #define NV_RX2_CHECKSUM_IP (0x10000000)
426 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
427 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
428 #define NV_RX2_DESCRIPTORVALID (1<<29)
429 #define NV_RX2_SUBSTRACT1 (1<<25)
430 #define NV_RX2_ERROR1 (1<<18)
431 #define NV_RX2_ERROR2 (1<<19)
432 #define NV_RX2_ERROR3 (1<<20)
433 #define NV_RX2_ERROR4 (1<<21)
434 #define NV_RX2_CRCERR (1<<22)
435 #define NV_RX2_OVERFLOW (1<<23)
436 #define NV_RX2_FRAMINGERR (1<<24)
437 /* error and avail are the same for both */
438 #define NV_RX2_ERROR (1<<30)
439 #define NV_RX2_AVAIL (1<<31)
440 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
441
442 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
443 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
444
445 /* Miscellaneous hardware related defines: */
446 #define NV_PCI_REGSZ_VER1 0x270
447 #define NV_PCI_REGSZ_VER2 0x2d4
448 #define NV_PCI_REGSZ_VER3 0x604
449 #define NV_PCI_REGSZ_MAX 0x604
450
451 /* various timeout delays: all in usec */
452 #define NV_TXRX_RESET_DELAY 4
453 #define NV_TXSTOP_DELAY1 10
454 #define NV_TXSTOP_DELAY1MAX 500000
455 #define NV_TXSTOP_DELAY2 100
456 #define NV_RXSTOP_DELAY1 10
457 #define NV_RXSTOP_DELAY1MAX 500000
458 #define NV_RXSTOP_DELAY2 100
459 #define NV_SETUP5_DELAY 5
460 #define NV_SETUP5_DELAYMAX 50000
461 #define NV_POWERUP_DELAY 5
462 #define NV_POWERUP_DELAYMAX 5000
463 #define NV_MIIBUSY_DELAY 50
464 #define NV_MIIPHY_DELAY 10
465 #define NV_MIIPHY_DELAYMAX 10000
466 #define NV_MAC_RESET_DELAY 64
467
468 #define NV_WAKEUPPATTERNS 5
469 #define NV_WAKEUPMASKENTRIES 4
470
471 /* General driver defaults */
472 #define NV_WATCHDOG_TIMEO (5*HZ)
473
474 #define RX_RING_DEFAULT 512
475 #define TX_RING_DEFAULT 256
476 #define RX_RING_MIN 128
477 #define TX_RING_MIN 64
478 #define RING_MAX_DESC_VER_1 1024
479 #define RING_MAX_DESC_VER_2_3 16384
480
481 /* rx/tx mac addr + type + vlan + align + slack*/
482 #define NV_RX_HEADERS (64)
483 /* even more slack. */
484 #define NV_RX_ALLOC_PAD (64)
485
486 /* maximum mtu size */
487 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
488 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
489
490 #define OOM_REFILL (1+HZ/20)
491 #define POLL_WAIT (1+HZ/100)
492 #define LINK_TIMEOUT (3*HZ)
493 #define STATS_INTERVAL (10*HZ)
494
495 /*
496 * desc_ver values:
497 * The nic supports three different descriptor types:
498 * - DESC_VER_1: Original
499 * - DESC_VER_2: support for jumbo frames.
500 * - DESC_VER_3: 64-bit format.
501 */
502 #define DESC_VER_1 1
503 #define DESC_VER_2 2
504 #define DESC_VER_3 3
505
506 /* PHY defines */
507 #define PHY_OUI_MARVELL 0x5043
508 #define PHY_OUI_CICADA 0x03f1
509 #define PHY_OUI_VITESSE 0x01c1
510 #define PHY_OUI_REALTEK 0x0732
511 #define PHY_OUI_REALTEK2 0x0020
512 #define PHYID1_OUI_MASK 0x03ff
513 #define PHYID1_OUI_SHFT 6
514 #define PHYID2_OUI_MASK 0xfc00
515 #define PHYID2_OUI_SHFT 10
516 #define PHYID2_MODEL_MASK 0x03f0
517 #define PHY_MODEL_REALTEK_8211 0x0110
518 #define PHY_REV_MASK 0x0001
519 #define PHY_REV_REALTEK_8211B 0x0000
520 #define PHY_REV_REALTEK_8211C 0x0001
521 #define PHY_MODEL_REALTEK_8201 0x0200
522 #define PHY_MODEL_MARVELL_E3016 0x0220
523 #define PHY_MARVELL_E3016_INITMASK 0x0300
524 #define PHY_CICADA_INIT1 0x0f000
525 #define PHY_CICADA_INIT2 0x0e00
526 #define PHY_CICADA_INIT3 0x01000
527 #define PHY_CICADA_INIT4 0x0200
528 #define PHY_CICADA_INIT5 0x0004
529 #define PHY_CICADA_INIT6 0x02000
530 #define PHY_VITESSE_INIT_REG1 0x1f
531 #define PHY_VITESSE_INIT_REG2 0x10
532 #define PHY_VITESSE_INIT_REG3 0x11
533 #define PHY_VITESSE_INIT_REG4 0x12
534 #define PHY_VITESSE_INIT_MSK1 0xc
535 #define PHY_VITESSE_INIT_MSK2 0x0180
536 #define PHY_VITESSE_INIT1 0x52b5
537 #define PHY_VITESSE_INIT2 0xaf8a
538 #define PHY_VITESSE_INIT3 0x8
539 #define PHY_VITESSE_INIT4 0x8f8a
540 #define PHY_VITESSE_INIT5 0xaf86
541 #define PHY_VITESSE_INIT6 0x8f86
542 #define PHY_VITESSE_INIT7 0xaf82
543 #define PHY_VITESSE_INIT8 0x0100
544 #define PHY_VITESSE_INIT9 0x8f82
545 #define PHY_VITESSE_INIT10 0x0
546 #define PHY_REALTEK_INIT_REG1 0x1f
547 #define PHY_REALTEK_INIT_REG2 0x19
548 #define PHY_REALTEK_INIT_REG3 0x13
549 #define PHY_REALTEK_INIT_REG4 0x14
550 #define PHY_REALTEK_INIT_REG5 0x18
551 #define PHY_REALTEK_INIT_REG6 0x11
552 #define PHY_REALTEK_INIT_REG7 0x01
553 #define PHY_REALTEK_INIT1 0x0000
554 #define PHY_REALTEK_INIT2 0x8e00
555 #define PHY_REALTEK_INIT3 0x0001
556 #define PHY_REALTEK_INIT4 0xad17
557 #define PHY_REALTEK_INIT5 0xfb54
558 #define PHY_REALTEK_INIT6 0xf5c7
559 #define PHY_REALTEK_INIT7 0x1000
560 #define PHY_REALTEK_INIT8 0x0003
561 #define PHY_REALTEK_INIT9 0x0008
562 #define PHY_REALTEK_INIT10 0x0005
563 #define PHY_REALTEK_INIT11 0x0200
564 #define PHY_REALTEK_INIT_MSK1 0x0003
565
566 #define PHY_GIGABIT 0x0100
567
568 #define PHY_TIMEOUT 0x1
569 #define PHY_ERROR 0x2
570
571 #define PHY_100 0x1
572 #define PHY_1000 0x2
573 #define PHY_HALF 0x100
574
575 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
576 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
577 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
578 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
579 #define NV_PAUSEFRAME_RX_REQ 0x0010
580 #define NV_PAUSEFRAME_TX_REQ 0x0020
581 #define NV_PAUSEFRAME_AUTONEG 0x0040
582
583 /* MSI/MSI-X defines */
584 #define NV_MSI_X_MAX_VECTORS 8
585 #define NV_MSI_X_VECTORS_MASK 0x000f
586 #define NV_MSI_CAPABLE 0x0010
587 #define NV_MSI_X_CAPABLE 0x0020
588 #define NV_MSI_ENABLED 0x0040
589 #define NV_MSI_X_ENABLED 0x0080
590
591 #define NV_MSI_X_VECTOR_ALL 0x0
592 #define NV_MSI_X_VECTOR_RX 0x0
593 #define NV_MSI_X_VECTOR_TX 0x1
594 #define NV_MSI_X_VECTOR_OTHER 0x2
595
596 #define NV_MSI_PRIV_OFFSET 0x68
597 #define NV_MSI_PRIV_VALUE 0xffffffff
598
599 #define NV_RESTART_TX 0x1
600 #define NV_RESTART_RX 0x2
601
602 #define NV_TX_LIMIT_COUNT 16
603
604 #define NV_DYNAMIC_THRESHOLD 4
605 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
606
607 /* statistics */
608 struct nv_ethtool_str {
609 char name[ETH_GSTRING_LEN];
610 };
611
612 static const struct nv_ethtool_str nv_estats_str[] = {
613 { "tx_bytes" }, /* includes Ethernet FCS CRC */
614 { "tx_zero_rexmt" },
615 { "tx_one_rexmt" },
616 { "tx_many_rexmt" },
617 { "tx_late_collision" },
618 { "tx_fifo_errors" },
619 { "tx_carrier_errors" },
620 { "tx_excess_deferral" },
621 { "tx_retry_error" },
622 { "rx_frame_error" },
623 { "rx_extra_byte" },
624 { "rx_late_collision" },
625 { "rx_runt" },
626 { "rx_frame_too_long" },
627 { "rx_over_errors" },
628 { "rx_crc_errors" },
629 { "rx_frame_align_error" },
630 { "rx_length_error" },
631 { "rx_unicast" },
632 { "rx_multicast" },
633 { "rx_broadcast" },
634 { "rx_packets" },
635 { "rx_errors_total" },
636 { "tx_errors_total" },
637
638 /* version 2 stats */
639 { "tx_deferral" },
640 { "tx_packets" },
641 { "rx_bytes" }, /* includes Ethernet FCS CRC */
642 { "tx_pause" },
643 { "rx_pause" },
644 { "rx_drop_frame" },
645
646 /* version 3 stats */
647 { "tx_unicast" },
648 { "tx_multicast" },
649 { "tx_broadcast" }
650 };
651
652 struct nv_ethtool_stats {
653 u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
654 u64 tx_zero_rexmt;
655 u64 tx_one_rexmt;
656 u64 tx_many_rexmt;
657 u64 tx_late_collision;
658 u64 tx_fifo_errors;
659 u64 tx_carrier_errors;
660 u64 tx_excess_deferral;
661 u64 tx_retry_error;
662 u64 rx_frame_error;
663 u64 rx_extra_byte;
664 u64 rx_late_collision;
665 u64 rx_runt;
666 u64 rx_frame_too_long;
667 u64 rx_over_errors;
668 u64 rx_crc_errors;
669 u64 rx_frame_align_error;
670 u64 rx_length_error;
671 u64 rx_unicast;
672 u64 rx_multicast;
673 u64 rx_broadcast;
674 u64 rx_packets; /* should be ifconfig->rx_packets */
675 u64 rx_errors_total;
676 u64 tx_errors_total;
677
678 /* version 2 stats */
679 u64 tx_deferral;
680 u64 tx_packets; /* should be ifconfig->tx_packets */
681 u64 rx_bytes; /* should be ifconfig->rx_bytes + 4*rx_packets */
682 u64 tx_pause;
683 u64 rx_pause;
684 u64 rx_drop_frame;
685
686 /* version 3 stats */
687 u64 tx_unicast;
688 u64 tx_multicast;
689 u64 tx_broadcast;
690 };
691
692 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
693 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
694 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
695
696 /* diagnostics */
697 #define NV_TEST_COUNT_BASE 3
698 #define NV_TEST_COUNT_EXTENDED 4
699
700 static const struct nv_ethtool_str nv_etests_str[] = {
701 { "link (online/offline)" },
702 { "register (offline) " },
703 { "interrupt (offline) " },
704 { "loopback (offline) " }
705 };
706
707 struct register_test {
708 __u32 reg;
709 __u32 mask;
710 };
711
712 static const struct register_test nv_registers_test[] = {
713 { NvRegUnknownSetupReg6, 0x01 },
714 { NvRegMisc1, 0x03c },
715 { NvRegOffloadConfig, 0x03ff },
716 { NvRegMulticastAddrA, 0xffffffff },
717 { NvRegTxWatermark, 0x0ff },
718 { NvRegWakeUpFlags, 0x07777 },
719 { 0, 0 }
720 };
721
722 struct nv_skb_map {
723 struct sk_buff *skb;
724 dma_addr_t dma;
725 unsigned int dma_len:31;
726 unsigned int dma_single:1;
727 struct ring_desc_ex *first_tx_desc;
728 struct nv_skb_map *next_tx_ctx;
729 };
730
731 /*
732 * SMP locking:
733 * All hardware access under netdev_priv(dev)->lock, except the performance
734 * critical parts:
735 * - rx is (pseudo-) lockless: it relies on the single-threading provided
736 * by the arch code for interrupts.
737 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
738 * needs netdev_priv(dev)->lock :-(
739 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
740 *
741 * Hardware stats updates are protected by hwstats_lock:
742 * - updated by nv_do_stats_poll (timer). This is meant to avoid
743 * integer wraparound in the NIC stats registers, at low frequency
744 * (0.1 Hz)
745 * - updated by nv_get_ethtool_stats + nv_get_stats64
746 *
747 * Software stats are accessed only through 64b synchronization points
748 * and are not subject to other synchronization techniques (single
749 * update thread on the TX or RX paths).
750 */
751
752 /* in dev: base, irq */
753 struct fe_priv {
754 spinlock_t lock;
755
756 struct net_device *dev;
757 struct napi_struct napi;
758
759 /* hardware stats are updated in syscall and timer */
760 spinlock_t hwstats_lock;
761 struct nv_ethtool_stats estats;
762
763 int in_shutdown;
764 u32 linkspeed;
765 int duplex;
766 int autoneg;
767 int fixed_mode;
768 int phyaddr;
769 int wolenabled;
770 unsigned int phy_oui;
771 unsigned int phy_model;
772 unsigned int phy_rev;
773 u16 gigabit;
774 int intr_test;
775 int recover_error;
776 int quiet_count;
777
778 /* General data: RO fields */
779 dma_addr_t ring_addr;
780 struct pci_dev *pci_dev;
781 u32 orig_mac[2];
782 u32 events;
783 u32 irqmask;
784 u32 desc_ver;
785 u32 txrxctl_bits;
786 u32 vlanctl_bits;
787 u32 driver_data;
788 u32 device_id;
789 u32 register_size;
790 u32 mac_in_use;
791 int mgmt_version;
792 int mgmt_sema;
793
794 void __iomem *base;
795
796 /* rx specific fields.
797 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
798 */
799 union ring_type get_rx, put_rx, first_rx, last_rx;
800 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
801 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
802 struct nv_skb_map *rx_skb;
803
804 union ring_type rx_ring;
805 unsigned int rx_buf_sz;
806 unsigned int pkt_limit;
807 struct timer_list oom_kick;
808 struct timer_list nic_poll;
809 struct timer_list stats_poll;
810 u32 nic_poll_irq;
811 int rx_ring_size;
812
813 /* RX software stats */
814 struct u64_stats_sync swstats_rx_syncp;
815 u64 stat_rx_packets;
816 u64 stat_rx_bytes; /* not always available in HW */
817 u64 stat_rx_missed_errors;
818 u64 stat_rx_dropped;
819
820 /* media detection workaround.
821 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
822 */
823 int need_linktimer;
824 unsigned long link_timeout;
825 /*
826 * tx specific fields.
827 */
828 union ring_type get_tx, put_tx, first_tx, last_tx;
829 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
830 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
831 struct nv_skb_map *tx_skb;
832
833 union ring_type tx_ring;
834 u32 tx_flags;
835 int tx_ring_size;
836 int tx_limit;
837 u32 tx_pkts_in_progress;
838 struct nv_skb_map *tx_change_owner;
839 struct nv_skb_map *tx_end_flip;
840 int tx_stop;
841
842 /* TX software stats */
843 struct u64_stats_sync swstats_tx_syncp;
844 u64 stat_tx_packets; /* not always available in HW */
845 u64 stat_tx_bytes;
846 u64 stat_tx_dropped;
847
848 /* msi/msi-x fields */
849 u32 msi_flags;
850 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
851
852 /* flow control */
853 u32 pause_flags;
854
855 /* power saved state */
856 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
857
858 /* for different msi-x irq type */
859 char name_rx[IFNAMSIZ + 3]; /* -rx */
860 char name_tx[IFNAMSIZ + 3]; /* -tx */
861 char name_other[IFNAMSIZ + 6]; /* -other */
862 };
863
864 /*
865 * Maximum number of loops until we assume that a bit in the irq mask
866 * is stuck. Overridable with module param.
867 */
868 static int max_interrupt_work = 4;
869
870 /*
871 * Optimization can be either throuput mode or cpu mode
872 *
873 * Throughput Mode: Every tx and rx packet will generate an interrupt.
874 * CPU Mode: Interrupts are controlled by a timer.
875 */
876 enum {
877 NV_OPTIMIZATION_MODE_THROUGHPUT,
878 NV_OPTIMIZATION_MODE_CPU,
879 NV_OPTIMIZATION_MODE_DYNAMIC
880 };
881 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
882
883 /*
884 * Poll interval for timer irq
885 *
886 * This interval determines how frequent an interrupt is generated.
887 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
888 * Min = 0, and Max = 65535
889 */
890 static int poll_interval = -1;
891
892 /*
893 * MSI interrupts
894 */
895 enum {
896 NV_MSI_INT_DISABLED,
897 NV_MSI_INT_ENABLED
898 };
899 static int msi = NV_MSI_INT_ENABLED;
900
901 /*
902 * MSIX interrupts
903 */
904 enum {
905 NV_MSIX_INT_DISABLED,
906 NV_MSIX_INT_ENABLED
907 };
908 static int msix = NV_MSIX_INT_ENABLED;
909
910 /*
911 * DMA 64bit
912 */
913 enum {
914 NV_DMA_64BIT_DISABLED,
915 NV_DMA_64BIT_ENABLED
916 };
917 static int dma_64bit = NV_DMA_64BIT_ENABLED;
918
919 /*
920 * Debug output control for tx_timeout
921 */
922 static bool debug_tx_timeout = false;
923
924 /*
925 * Crossover Detection
926 * Realtek 8201 phy + some OEM boards do not work properly.
927 */
928 enum {
929 NV_CROSSOVER_DETECTION_DISABLED,
930 NV_CROSSOVER_DETECTION_ENABLED
931 };
932 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
933
934 /*
935 * Power down phy when interface is down (persists through reboot;
936 * older Linux and other OSes may not power it up again)
937 */
938 static int phy_power_down;
939
940 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
941 {
942 return netdev_priv(dev);
943 }
944
945 static inline u8 __iomem *get_hwbase(struct net_device *dev)
946 {
947 return ((struct fe_priv *)netdev_priv(dev))->base;
948 }
949
950 static inline void pci_push(u8 __iomem *base)
951 {
952 /* force out pending posted writes */
953 readl(base);
954 }
955
956 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
957 {
958 return le32_to_cpu(prd->flaglen)
959 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
960 }
961
962 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
963 {
964 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
965 }
966
967 static bool nv_optimized(struct fe_priv *np)
968 {
969 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
970 return false;
971 return true;
972 }
973
974 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
975 int delay, int delaymax)
976 {
977 u8 __iomem *base = get_hwbase(dev);
978
979 pci_push(base);
980 do {
981 udelay(delay);
982 delaymax -= delay;
983 if (delaymax < 0)
984 return 1;
985 } while ((readl(base + offset) & mask) != target);
986 return 0;
987 }
988
989 #define NV_SETUP_RX_RING 0x01
990 #define NV_SETUP_TX_RING 0x02
991
992 static inline u32 dma_low(dma_addr_t addr)
993 {
994 return addr;
995 }
996
997 static inline u32 dma_high(dma_addr_t addr)
998 {
999 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
1000 }
1001
1002 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
1003 {
1004 struct fe_priv *np = get_nvpriv(dev);
1005 u8 __iomem *base = get_hwbase(dev);
1006
1007 if (!nv_optimized(np)) {
1008 if (rxtx_flags & NV_SETUP_RX_RING)
1009 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1010 if (rxtx_flags & NV_SETUP_TX_RING)
1011 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1012 } else {
1013 if (rxtx_flags & NV_SETUP_RX_RING) {
1014 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1015 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1016 }
1017 if (rxtx_flags & NV_SETUP_TX_RING) {
1018 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1019 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1020 }
1021 }
1022 }
1023
1024 static void free_rings(struct net_device *dev)
1025 {
1026 struct fe_priv *np = get_nvpriv(dev);
1027
1028 if (!nv_optimized(np)) {
1029 if (np->rx_ring.orig)
1030 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1031 np->rx_ring.orig, np->ring_addr);
1032 } else {
1033 if (np->rx_ring.ex)
1034 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1035 np->rx_ring.ex, np->ring_addr);
1036 }
1037 kfree(np->rx_skb);
1038 kfree(np->tx_skb);
1039 }
1040
1041 static int using_multi_irqs(struct net_device *dev)
1042 {
1043 struct fe_priv *np = get_nvpriv(dev);
1044
1045 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1046 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1047 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1048 return 0;
1049 else
1050 return 1;
1051 }
1052
1053 static void nv_txrx_gate(struct net_device *dev, bool gate)
1054 {
1055 struct fe_priv *np = get_nvpriv(dev);
1056 u8 __iomem *base = get_hwbase(dev);
1057 u32 powerstate;
1058
1059 if (!np->mac_in_use &&
1060 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1061 powerstate = readl(base + NvRegPowerState2);
1062 if (gate)
1063 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1064 else
1065 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1066 writel(powerstate, base + NvRegPowerState2);
1067 }
1068 }
1069
1070 static void nv_enable_irq(struct net_device *dev)
1071 {
1072 struct fe_priv *np = get_nvpriv(dev);
1073
1074 if (!using_multi_irqs(dev)) {
1075 if (np->msi_flags & NV_MSI_X_ENABLED)
1076 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1077 else
1078 enable_irq(np->pci_dev->irq);
1079 } else {
1080 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1081 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1082 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1083 }
1084 }
1085
1086 static void nv_disable_irq(struct net_device *dev)
1087 {
1088 struct fe_priv *np = get_nvpriv(dev);
1089
1090 if (!using_multi_irqs(dev)) {
1091 if (np->msi_flags & NV_MSI_X_ENABLED)
1092 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1093 else
1094 disable_irq(np->pci_dev->irq);
1095 } else {
1096 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1097 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1098 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1099 }
1100 }
1101
1102 /* In MSIX mode, a write to irqmask behaves as XOR */
1103 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1104 {
1105 u8 __iomem *base = get_hwbase(dev);
1106
1107 writel(mask, base + NvRegIrqMask);
1108 }
1109
1110 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1111 {
1112 struct fe_priv *np = get_nvpriv(dev);
1113 u8 __iomem *base = get_hwbase(dev);
1114
1115 if (np->msi_flags & NV_MSI_X_ENABLED) {
1116 writel(mask, base + NvRegIrqMask);
1117 } else {
1118 if (np->msi_flags & NV_MSI_ENABLED)
1119 writel(0, base + NvRegMSIIrqMask);
1120 writel(0, base + NvRegIrqMask);
1121 }
1122 }
1123
1124 static void nv_napi_enable(struct net_device *dev)
1125 {
1126 struct fe_priv *np = get_nvpriv(dev);
1127
1128 napi_enable(&np->napi);
1129 }
1130
1131 static void nv_napi_disable(struct net_device *dev)
1132 {
1133 struct fe_priv *np = get_nvpriv(dev);
1134
1135 napi_disable(&np->napi);
1136 }
1137
1138 #define MII_READ (-1)
1139 /* mii_rw: read/write a register on the PHY.
1140 *
1141 * Caller must guarantee serialization
1142 */
1143 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1144 {
1145 u8 __iomem *base = get_hwbase(dev);
1146 u32 reg;
1147 int retval;
1148
1149 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1150
1151 reg = readl(base + NvRegMIIControl);
1152 if (reg & NVREG_MIICTL_INUSE) {
1153 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1154 udelay(NV_MIIBUSY_DELAY);
1155 }
1156
1157 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1158 if (value != MII_READ) {
1159 writel(value, base + NvRegMIIData);
1160 reg |= NVREG_MIICTL_WRITE;
1161 }
1162 writel(reg, base + NvRegMIIControl);
1163
1164 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1165 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1166 retval = -1;
1167 } else if (value != MII_READ) {
1168 /* it was a write operation - fewer failures are detectable */
1169 retval = 0;
1170 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1171 retval = -1;
1172 } else {
1173 retval = readl(base + NvRegMIIData);
1174 }
1175
1176 return retval;
1177 }
1178
1179 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1180 {
1181 struct fe_priv *np = netdev_priv(dev);
1182 u32 miicontrol;
1183 unsigned int tries = 0;
1184
1185 miicontrol = BMCR_RESET | bmcr_setup;
1186 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1187 return -1;
1188
1189 /* wait for 500ms */
1190 msleep(500);
1191
1192 /* must wait till reset is deasserted */
1193 while (miicontrol & BMCR_RESET) {
1194 usleep_range(10000, 20000);
1195 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1196 /* FIXME: 100 tries seem excessive */
1197 if (tries++ > 100)
1198 return -1;
1199 }
1200 return 0;
1201 }
1202
1203 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1204 {
1205 static const struct {
1206 int reg;
1207 int init;
1208 } ri[] = {
1209 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1210 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1211 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1212 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1213 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1214 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1215 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1216 };
1217 int i;
1218
1219 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1220 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1221 return PHY_ERROR;
1222 }
1223
1224 return 0;
1225 }
1226
1227 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1228 {
1229 u32 reg;
1230 u8 __iomem *base = get_hwbase(dev);
1231 u32 powerstate = readl(base + NvRegPowerState2);
1232
1233 /* need to perform hw phy reset */
1234 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1235 writel(powerstate, base + NvRegPowerState2);
1236 msleep(25);
1237
1238 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1239 writel(powerstate, base + NvRegPowerState2);
1240 msleep(25);
1241
1242 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1243 reg |= PHY_REALTEK_INIT9;
1244 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1245 return PHY_ERROR;
1246 if (mii_rw(dev, np->phyaddr,
1247 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1248 return PHY_ERROR;
1249 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1250 if (!(reg & PHY_REALTEK_INIT11)) {
1251 reg |= PHY_REALTEK_INIT11;
1252 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1253 return PHY_ERROR;
1254 }
1255 if (mii_rw(dev, np->phyaddr,
1256 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1257 return PHY_ERROR;
1258
1259 return 0;
1260 }
1261
1262 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1263 {
1264 u32 phy_reserved;
1265
1266 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1267 phy_reserved = mii_rw(dev, np->phyaddr,
1268 PHY_REALTEK_INIT_REG6, MII_READ);
1269 phy_reserved |= PHY_REALTEK_INIT7;
1270 if (mii_rw(dev, np->phyaddr,
1271 PHY_REALTEK_INIT_REG6, phy_reserved))
1272 return PHY_ERROR;
1273 }
1274
1275 return 0;
1276 }
1277
1278 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1279 {
1280 u32 phy_reserved;
1281
1282 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1283 if (mii_rw(dev, np->phyaddr,
1284 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1285 return PHY_ERROR;
1286 phy_reserved = mii_rw(dev, np->phyaddr,
1287 PHY_REALTEK_INIT_REG2, MII_READ);
1288 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1289 phy_reserved |= PHY_REALTEK_INIT3;
1290 if (mii_rw(dev, np->phyaddr,
1291 PHY_REALTEK_INIT_REG2, phy_reserved))
1292 return PHY_ERROR;
1293 if (mii_rw(dev, np->phyaddr,
1294 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1295 return PHY_ERROR;
1296 }
1297
1298 return 0;
1299 }
1300
1301 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1302 u32 phyinterface)
1303 {
1304 u32 phy_reserved;
1305
1306 if (phyinterface & PHY_RGMII) {
1307 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1308 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1309 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1310 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1311 return PHY_ERROR;
1312 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1313 phy_reserved |= PHY_CICADA_INIT5;
1314 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1315 return PHY_ERROR;
1316 }
1317 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1318 phy_reserved |= PHY_CICADA_INIT6;
1319 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1320 return PHY_ERROR;
1321
1322 return 0;
1323 }
1324
1325 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1326 {
1327 u32 phy_reserved;
1328
1329 if (mii_rw(dev, np->phyaddr,
1330 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1331 return PHY_ERROR;
1332 if (mii_rw(dev, np->phyaddr,
1333 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1334 return PHY_ERROR;
1335 phy_reserved = mii_rw(dev, np->phyaddr,
1336 PHY_VITESSE_INIT_REG4, MII_READ);
1337 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1338 return PHY_ERROR;
1339 phy_reserved = mii_rw(dev, np->phyaddr,
1340 PHY_VITESSE_INIT_REG3, MII_READ);
1341 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1342 phy_reserved |= PHY_VITESSE_INIT3;
1343 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1344 return PHY_ERROR;
1345 if (mii_rw(dev, np->phyaddr,
1346 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1347 return PHY_ERROR;
1348 if (mii_rw(dev, np->phyaddr,
1349 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1350 return PHY_ERROR;
1351 phy_reserved = mii_rw(dev, np->phyaddr,
1352 PHY_VITESSE_INIT_REG4, MII_READ);
1353 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1354 phy_reserved |= PHY_VITESSE_INIT3;
1355 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1356 return PHY_ERROR;
1357 phy_reserved = mii_rw(dev, np->phyaddr,
1358 PHY_VITESSE_INIT_REG3, MII_READ);
1359 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1360 return PHY_ERROR;
1361 if (mii_rw(dev, np->phyaddr,
1362 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1363 return PHY_ERROR;
1364 if (mii_rw(dev, np->phyaddr,
1365 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1366 return PHY_ERROR;
1367 phy_reserved = mii_rw(dev, np->phyaddr,
1368 PHY_VITESSE_INIT_REG4, MII_READ);
1369 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1370 return PHY_ERROR;
1371 phy_reserved = mii_rw(dev, np->phyaddr,
1372 PHY_VITESSE_INIT_REG3, MII_READ);
1373 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1374 phy_reserved |= PHY_VITESSE_INIT8;
1375 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1376 return PHY_ERROR;
1377 if (mii_rw(dev, np->phyaddr,
1378 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1379 return PHY_ERROR;
1380 if (mii_rw(dev, np->phyaddr,
1381 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1382 return PHY_ERROR;
1383
1384 return 0;
1385 }
1386
1387 static int phy_init(struct net_device *dev)
1388 {
1389 struct fe_priv *np = get_nvpriv(dev);
1390 u8 __iomem *base = get_hwbase(dev);
1391 u32 phyinterface;
1392 u32 mii_status, mii_control, mii_control_1000, reg;
1393
1394 /* phy errata for E3016 phy */
1395 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1396 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1397 reg &= ~PHY_MARVELL_E3016_INITMASK;
1398 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1399 netdev_info(dev, "%s: phy write to errata reg failed\n",
1400 pci_name(np->pci_dev));
1401 return PHY_ERROR;
1402 }
1403 }
1404 if (np->phy_oui == PHY_OUI_REALTEK) {
1405 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1406 np->phy_rev == PHY_REV_REALTEK_8211B) {
1407 if (init_realtek_8211b(dev, np)) {
1408 netdev_info(dev, "%s: phy init failed\n",
1409 pci_name(np->pci_dev));
1410 return PHY_ERROR;
1411 }
1412 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1413 np->phy_rev == PHY_REV_REALTEK_8211C) {
1414 if (init_realtek_8211c(dev, np)) {
1415 netdev_info(dev, "%s: phy init failed\n",
1416 pci_name(np->pci_dev));
1417 return PHY_ERROR;
1418 }
1419 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1420 if (init_realtek_8201(dev, np)) {
1421 netdev_info(dev, "%s: phy init failed\n",
1422 pci_name(np->pci_dev));
1423 return PHY_ERROR;
1424 }
1425 }
1426 }
1427
1428 /* set advertise register */
1429 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1430 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1431 ADVERTISE_100HALF | ADVERTISE_100FULL |
1432 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1433 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1434 netdev_info(dev, "%s: phy write to advertise failed\n",
1435 pci_name(np->pci_dev));
1436 return PHY_ERROR;
1437 }
1438
1439 /* get phy interface type */
1440 phyinterface = readl(base + NvRegPhyInterface);
1441
1442 /* see if gigabit phy */
1443 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1444 if (mii_status & PHY_GIGABIT) {
1445 np->gigabit = PHY_GIGABIT;
1446 mii_control_1000 = mii_rw(dev, np->phyaddr,
1447 MII_CTRL1000, MII_READ);
1448 mii_control_1000 &= ~ADVERTISE_1000HALF;
1449 if (phyinterface & PHY_RGMII)
1450 mii_control_1000 |= ADVERTISE_1000FULL;
1451 else
1452 mii_control_1000 &= ~ADVERTISE_1000FULL;
1453
1454 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1455 netdev_info(dev, "%s: phy init failed\n",
1456 pci_name(np->pci_dev));
1457 return PHY_ERROR;
1458 }
1459 } else
1460 np->gigabit = 0;
1461
1462 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1463 mii_control |= BMCR_ANENABLE;
1464
1465 if (np->phy_oui == PHY_OUI_REALTEK &&
1466 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1467 np->phy_rev == PHY_REV_REALTEK_8211C) {
1468 /* start autoneg since we already performed hw reset above */
1469 mii_control |= BMCR_ANRESTART;
1470 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1471 netdev_info(dev, "%s: phy init failed\n",
1472 pci_name(np->pci_dev));
1473 return PHY_ERROR;
1474 }
1475 } else {
1476 /* reset the phy
1477 * (certain phys need bmcr to be setup with reset)
1478 */
1479 if (phy_reset(dev, mii_control)) {
1480 netdev_info(dev, "%s: phy reset failed\n",
1481 pci_name(np->pci_dev));
1482 return PHY_ERROR;
1483 }
1484 }
1485
1486 /* phy vendor specific configuration */
1487 if ((np->phy_oui == PHY_OUI_CICADA)) {
1488 if (init_cicada(dev, np, phyinterface)) {
1489 netdev_info(dev, "%s: phy init failed\n",
1490 pci_name(np->pci_dev));
1491 return PHY_ERROR;
1492 }
1493 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1494 if (init_vitesse(dev, np)) {
1495 netdev_info(dev, "%s: phy init failed\n",
1496 pci_name(np->pci_dev));
1497 return PHY_ERROR;
1498 }
1499 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1500 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1501 np->phy_rev == PHY_REV_REALTEK_8211B) {
1502 /* reset could have cleared these out, set them back */
1503 if (init_realtek_8211b(dev, np)) {
1504 netdev_info(dev, "%s: phy init failed\n",
1505 pci_name(np->pci_dev));
1506 return PHY_ERROR;
1507 }
1508 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1509 if (init_realtek_8201(dev, np) ||
1510 init_realtek_8201_cross(dev, np)) {
1511 netdev_info(dev, "%s: phy init failed\n",
1512 pci_name(np->pci_dev));
1513 return PHY_ERROR;
1514 }
1515 }
1516 }
1517
1518 /* some phys clear out pause advertisement on reset, set it back */
1519 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1520
1521 /* restart auto negotiation, power down phy */
1522 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1523 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1524 if (phy_power_down)
1525 mii_control |= BMCR_PDOWN;
1526 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1527 return PHY_ERROR;
1528
1529 return 0;
1530 }
1531
1532 static void nv_start_rx(struct net_device *dev)
1533 {
1534 struct fe_priv *np = netdev_priv(dev);
1535 u8 __iomem *base = get_hwbase(dev);
1536 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1537
1538 /* Already running? Stop it. */
1539 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1540 rx_ctrl &= ~NVREG_RCVCTL_START;
1541 writel(rx_ctrl, base + NvRegReceiverControl);
1542 pci_push(base);
1543 }
1544 writel(np->linkspeed, base + NvRegLinkSpeed);
1545 pci_push(base);
1546 rx_ctrl |= NVREG_RCVCTL_START;
1547 if (np->mac_in_use)
1548 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1549 writel(rx_ctrl, base + NvRegReceiverControl);
1550 pci_push(base);
1551 }
1552
1553 static void nv_stop_rx(struct net_device *dev)
1554 {
1555 struct fe_priv *np = netdev_priv(dev);
1556 u8 __iomem *base = get_hwbase(dev);
1557 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1558
1559 if (!np->mac_in_use)
1560 rx_ctrl &= ~NVREG_RCVCTL_START;
1561 else
1562 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1563 writel(rx_ctrl, base + NvRegReceiverControl);
1564 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1565 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1566 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1567 __func__);
1568
1569 udelay(NV_RXSTOP_DELAY2);
1570 if (!np->mac_in_use)
1571 writel(0, base + NvRegLinkSpeed);
1572 }
1573
1574 static void nv_start_tx(struct net_device *dev)
1575 {
1576 struct fe_priv *np = netdev_priv(dev);
1577 u8 __iomem *base = get_hwbase(dev);
1578 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1579
1580 tx_ctrl |= NVREG_XMITCTL_START;
1581 if (np->mac_in_use)
1582 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1583 writel(tx_ctrl, base + NvRegTransmitterControl);
1584 pci_push(base);
1585 }
1586
1587 static void nv_stop_tx(struct net_device *dev)
1588 {
1589 struct fe_priv *np = netdev_priv(dev);
1590 u8 __iomem *base = get_hwbase(dev);
1591 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1592
1593 if (!np->mac_in_use)
1594 tx_ctrl &= ~NVREG_XMITCTL_START;
1595 else
1596 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1597 writel(tx_ctrl, base + NvRegTransmitterControl);
1598 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1599 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1600 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1601 __func__);
1602
1603 udelay(NV_TXSTOP_DELAY2);
1604 if (!np->mac_in_use)
1605 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1606 base + NvRegTransmitPoll);
1607 }
1608
1609 static void nv_start_rxtx(struct net_device *dev)
1610 {
1611 nv_start_rx(dev);
1612 nv_start_tx(dev);
1613 }
1614
1615 static void nv_stop_rxtx(struct net_device *dev)
1616 {
1617 nv_stop_rx(dev);
1618 nv_stop_tx(dev);
1619 }
1620
1621 static void nv_txrx_reset(struct net_device *dev)
1622 {
1623 struct fe_priv *np = netdev_priv(dev);
1624 u8 __iomem *base = get_hwbase(dev);
1625
1626 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1627 pci_push(base);
1628 udelay(NV_TXRX_RESET_DELAY);
1629 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1630 pci_push(base);
1631 }
1632
1633 static void nv_mac_reset(struct net_device *dev)
1634 {
1635 struct fe_priv *np = netdev_priv(dev);
1636 u8 __iomem *base = get_hwbase(dev);
1637 u32 temp1, temp2, temp3;
1638
1639 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1640 pci_push(base);
1641
1642 /* save registers since they will be cleared on reset */
1643 temp1 = readl(base + NvRegMacAddrA);
1644 temp2 = readl(base + NvRegMacAddrB);
1645 temp3 = readl(base + NvRegTransmitPoll);
1646
1647 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1648 pci_push(base);
1649 udelay(NV_MAC_RESET_DELAY);
1650 writel(0, base + NvRegMacReset);
1651 pci_push(base);
1652 udelay(NV_MAC_RESET_DELAY);
1653
1654 /* restore saved registers */
1655 writel(temp1, base + NvRegMacAddrA);
1656 writel(temp2, base + NvRegMacAddrB);
1657 writel(temp3, base + NvRegTransmitPoll);
1658
1659 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1660 pci_push(base);
1661 }
1662
1663 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1664 static void nv_update_stats(struct net_device *dev)
1665 {
1666 struct fe_priv *np = netdev_priv(dev);
1667 u8 __iomem *base = get_hwbase(dev);
1668
1669 /* If it happens that this is run in top-half context, then
1670 * replace the spin_lock of hwstats_lock with
1671 * spin_lock_irqsave() in calling functions. */
1672 WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1673 assert_spin_locked(&np->hwstats_lock);
1674
1675 /* query hardware */
1676 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1677 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1678 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1679 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1680 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1681 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1682 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1683 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1684 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1685 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1686 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1687 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1688 np->estats.rx_runt += readl(base + NvRegRxRunt);
1689 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1690 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1691 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1692 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1693 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1694 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1695 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1696 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1697 np->estats.rx_packets =
1698 np->estats.rx_unicast +
1699 np->estats.rx_multicast +
1700 np->estats.rx_broadcast;
1701 np->estats.rx_errors_total =
1702 np->estats.rx_crc_errors +
1703 np->estats.rx_over_errors +
1704 np->estats.rx_frame_error +
1705 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1706 np->estats.rx_late_collision +
1707 np->estats.rx_runt +
1708 np->estats.rx_frame_too_long;
1709 np->estats.tx_errors_total =
1710 np->estats.tx_late_collision +
1711 np->estats.tx_fifo_errors +
1712 np->estats.tx_carrier_errors +
1713 np->estats.tx_excess_deferral +
1714 np->estats.tx_retry_error;
1715
1716 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1717 np->estats.tx_deferral += readl(base + NvRegTxDef);
1718 np->estats.tx_packets += readl(base + NvRegTxFrame);
1719 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1720 np->estats.tx_pause += readl(base + NvRegTxPause);
1721 np->estats.rx_pause += readl(base + NvRegRxPause);
1722 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1723 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1724 }
1725
1726 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1727 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1728 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1729 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1730 }
1731 }
1732
1733 /*
1734 * nv_get_stats64: dev->ndo_get_stats64 function
1735 * Get latest stats value from the nic.
1736 * Called with read_lock(&dev_base_lock) held for read -
1737 * only synchronized against unregister_netdevice.
1738 */
1739 static struct rtnl_link_stats64*
1740 nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1741 __acquires(&netdev_priv(dev)->hwstats_lock)
1742 __releases(&netdev_priv(dev)->hwstats_lock)
1743 {
1744 struct fe_priv *np = netdev_priv(dev);
1745 unsigned int syncp_start;
1746
1747 /*
1748 * Note: because HW stats are not always available and for
1749 * consistency reasons, the following ifconfig stats are
1750 * managed by software: rx_bytes, tx_bytes, rx_packets and
1751 * tx_packets. The related hardware stats reported by ethtool
1752 * should be equivalent to these ifconfig stats, with 4
1753 * additional bytes per packet (Ethernet FCS CRC), except for
1754 * tx_packets when TSO kicks in.
1755 */
1756
1757 /* software stats */
1758 do {
1759 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_rx_syncp);
1760 storage->rx_packets = np->stat_rx_packets;
1761 storage->rx_bytes = np->stat_rx_bytes;
1762 storage->rx_dropped = np->stat_rx_dropped;
1763 storage->rx_missed_errors = np->stat_rx_missed_errors;
1764 } while (u64_stats_fetch_retry_bh(&np->swstats_rx_syncp, syncp_start));
1765
1766 do {
1767 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_tx_syncp);
1768 storage->tx_packets = np->stat_tx_packets;
1769 storage->tx_bytes = np->stat_tx_bytes;
1770 storage->tx_dropped = np->stat_tx_dropped;
1771 } while (u64_stats_fetch_retry_bh(&np->swstats_tx_syncp, syncp_start));
1772
1773 /* If the nic supports hw counters then retrieve latest values */
1774 if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1775 spin_lock_bh(&np->hwstats_lock);
1776
1777 nv_update_stats(dev);
1778
1779 /* generic stats */
1780 storage->rx_errors = np->estats.rx_errors_total;
1781 storage->tx_errors = np->estats.tx_errors_total;
1782
1783 /* meaningful only when NIC supports stats v3 */
1784 storage->multicast = np->estats.rx_multicast;
1785
1786 /* detailed rx_errors */
1787 storage->rx_length_errors = np->estats.rx_length_error;
1788 storage->rx_over_errors = np->estats.rx_over_errors;
1789 storage->rx_crc_errors = np->estats.rx_crc_errors;
1790 storage->rx_frame_errors = np->estats.rx_frame_align_error;
1791 storage->rx_fifo_errors = np->estats.rx_drop_frame;
1792
1793 /* detailed tx_errors */
1794 storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1795 storage->tx_fifo_errors = np->estats.tx_fifo_errors;
1796
1797 spin_unlock_bh(&np->hwstats_lock);
1798 }
1799
1800 return storage;
1801 }
1802
1803 /*
1804 * nv_alloc_rx: fill rx ring entries.
1805 * Return 1 if the allocations for the skbs failed and the
1806 * rx engine is without Available descriptors
1807 */
1808 static int nv_alloc_rx(struct net_device *dev)
1809 {
1810 struct fe_priv *np = netdev_priv(dev);
1811 struct ring_desc *less_rx;
1812
1813 less_rx = np->get_rx.orig;
1814 if (less_rx-- == np->first_rx.orig)
1815 less_rx = np->last_rx.orig;
1816
1817 while (np->put_rx.orig != less_rx) {
1818 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1819 if (skb) {
1820 np->put_rx_ctx->skb = skb;
1821 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1822 skb->data,
1823 skb_tailroom(skb),
1824 PCI_DMA_FROMDEVICE);
1825 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1826 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1827 wmb();
1828 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1829 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1830 np->put_rx.orig = np->first_rx.orig;
1831 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1832 np->put_rx_ctx = np->first_rx_ctx;
1833 } else {
1834 u64_stats_update_begin(&np->swstats_rx_syncp);
1835 np->stat_rx_dropped++;
1836 u64_stats_update_end(&np->swstats_rx_syncp);
1837 return 1;
1838 }
1839 }
1840 return 0;
1841 }
1842
1843 static int nv_alloc_rx_optimized(struct net_device *dev)
1844 {
1845 struct fe_priv *np = netdev_priv(dev);
1846 struct ring_desc_ex *less_rx;
1847
1848 less_rx = np->get_rx.ex;
1849 if (less_rx-- == np->first_rx.ex)
1850 less_rx = np->last_rx.ex;
1851
1852 while (np->put_rx.ex != less_rx) {
1853 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1854 if (skb) {
1855 np->put_rx_ctx->skb = skb;
1856 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1857 skb->data,
1858 skb_tailroom(skb),
1859 PCI_DMA_FROMDEVICE);
1860 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1861 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1862 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1863 wmb();
1864 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1865 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1866 np->put_rx.ex = np->first_rx.ex;
1867 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1868 np->put_rx_ctx = np->first_rx_ctx;
1869 } else {
1870 u64_stats_update_begin(&np->swstats_rx_syncp);
1871 np->stat_rx_dropped++;
1872 u64_stats_update_end(&np->swstats_rx_syncp);
1873 return 1;
1874 }
1875 }
1876 return 0;
1877 }
1878
1879 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1880 static void nv_do_rx_refill(unsigned long data)
1881 {
1882 struct net_device *dev = (struct net_device *) data;
1883 struct fe_priv *np = netdev_priv(dev);
1884
1885 /* Just reschedule NAPI rx processing */
1886 napi_schedule(&np->napi);
1887 }
1888
1889 static void nv_init_rx(struct net_device *dev)
1890 {
1891 struct fe_priv *np = netdev_priv(dev);
1892 int i;
1893
1894 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1895
1896 if (!nv_optimized(np))
1897 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1898 else
1899 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1900 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1901 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1902
1903 for (i = 0; i < np->rx_ring_size; i++) {
1904 if (!nv_optimized(np)) {
1905 np->rx_ring.orig[i].flaglen = 0;
1906 np->rx_ring.orig[i].buf = 0;
1907 } else {
1908 np->rx_ring.ex[i].flaglen = 0;
1909 np->rx_ring.ex[i].txvlan = 0;
1910 np->rx_ring.ex[i].bufhigh = 0;
1911 np->rx_ring.ex[i].buflow = 0;
1912 }
1913 np->rx_skb[i].skb = NULL;
1914 np->rx_skb[i].dma = 0;
1915 }
1916 }
1917
1918 static void nv_init_tx(struct net_device *dev)
1919 {
1920 struct fe_priv *np = netdev_priv(dev);
1921 int i;
1922
1923 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1924
1925 if (!nv_optimized(np))
1926 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1927 else
1928 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1929 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1930 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1931 netdev_reset_queue(np->dev);
1932 np->tx_pkts_in_progress = 0;
1933 np->tx_change_owner = NULL;
1934 np->tx_end_flip = NULL;
1935 np->tx_stop = 0;
1936
1937 for (i = 0; i < np->tx_ring_size; i++) {
1938 if (!nv_optimized(np)) {
1939 np->tx_ring.orig[i].flaglen = 0;
1940 np->tx_ring.orig[i].buf = 0;
1941 } else {
1942 np->tx_ring.ex[i].flaglen = 0;
1943 np->tx_ring.ex[i].txvlan = 0;
1944 np->tx_ring.ex[i].bufhigh = 0;
1945 np->tx_ring.ex[i].buflow = 0;
1946 }
1947 np->tx_skb[i].skb = NULL;
1948 np->tx_skb[i].dma = 0;
1949 np->tx_skb[i].dma_len = 0;
1950 np->tx_skb[i].dma_single = 0;
1951 np->tx_skb[i].first_tx_desc = NULL;
1952 np->tx_skb[i].next_tx_ctx = NULL;
1953 }
1954 }
1955
1956 static int nv_init_ring(struct net_device *dev)
1957 {
1958 struct fe_priv *np = netdev_priv(dev);
1959
1960 nv_init_tx(dev);
1961 nv_init_rx(dev);
1962
1963 if (!nv_optimized(np))
1964 return nv_alloc_rx(dev);
1965 else
1966 return nv_alloc_rx_optimized(dev);
1967 }
1968
1969 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1970 {
1971 if (tx_skb->dma) {
1972 if (tx_skb->dma_single)
1973 pci_unmap_single(np->pci_dev, tx_skb->dma,
1974 tx_skb->dma_len,
1975 PCI_DMA_TODEVICE);
1976 else
1977 pci_unmap_page(np->pci_dev, tx_skb->dma,
1978 tx_skb->dma_len,
1979 PCI_DMA_TODEVICE);
1980 tx_skb->dma = 0;
1981 }
1982 }
1983
1984 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1985 {
1986 nv_unmap_txskb(np, tx_skb);
1987 if (tx_skb->skb) {
1988 dev_kfree_skb_any(tx_skb->skb);
1989 tx_skb->skb = NULL;
1990 return 1;
1991 }
1992 return 0;
1993 }
1994
1995 static void nv_drain_tx(struct net_device *dev)
1996 {
1997 struct fe_priv *np = netdev_priv(dev);
1998 unsigned int i;
1999
2000 for (i = 0; i < np->tx_ring_size; i++) {
2001 if (!nv_optimized(np)) {
2002 np->tx_ring.orig[i].flaglen = 0;
2003 np->tx_ring.orig[i].buf = 0;
2004 } else {
2005 np->tx_ring.ex[i].flaglen = 0;
2006 np->tx_ring.ex[i].txvlan = 0;
2007 np->tx_ring.ex[i].bufhigh = 0;
2008 np->tx_ring.ex[i].buflow = 0;
2009 }
2010 if (nv_release_txskb(np, &np->tx_skb[i])) {
2011 u64_stats_update_begin(&np->swstats_tx_syncp);
2012 np->stat_tx_dropped++;
2013 u64_stats_update_end(&np->swstats_tx_syncp);
2014 }
2015 np->tx_skb[i].dma = 0;
2016 np->tx_skb[i].dma_len = 0;
2017 np->tx_skb[i].dma_single = 0;
2018 np->tx_skb[i].first_tx_desc = NULL;
2019 np->tx_skb[i].next_tx_ctx = NULL;
2020 }
2021 np->tx_pkts_in_progress = 0;
2022 np->tx_change_owner = NULL;
2023 np->tx_end_flip = NULL;
2024 }
2025
2026 static void nv_drain_rx(struct net_device *dev)
2027 {
2028 struct fe_priv *np = netdev_priv(dev);
2029 int i;
2030
2031 for (i = 0; i < np->rx_ring_size; i++) {
2032 if (!nv_optimized(np)) {
2033 np->rx_ring.orig[i].flaglen = 0;
2034 np->rx_ring.orig[i].buf = 0;
2035 } else {
2036 np->rx_ring.ex[i].flaglen = 0;
2037 np->rx_ring.ex[i].txvlan = 0;
2038 np->rx_ring.ex[i].bufhigh = 0;
2039 np->rx_ring.ex[i].buflow = 0;
2040 }
2041 wmb();
2042 if (np->rx_skb[i].skb) {
2043 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2044 (skb_end_pointer(np->rx_skb[i].skb) -
2045 np->rx_skb[i].skb->data),
2046 PCI_DMA_FROMDEVICE);
2047 dev_kfree_skb(np->rx_skb[i].skb);
2048 np->rx_skb[i].skb = NULL;
2049 }
2050 }
2051 }
2052
2053 static void nv_drain_rxtx(struct net_device *dev)
2054 {
2055 nv_drain_tx(dev);
2056 nv_drain_rx(dev);
2057 }
2058
2059 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2060 {
2061 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2062 }
2063
2064 static void nv_legacybackoff_reseed(struct net_device *dev)
2065 {
2066 u8 __iomem *base = get_hwbase(dev);
2067 u32 reg;
2068 u32 low;
2069 int tx_status = 0;
2070
2071 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2072 get_random_bytes(&low, sizeof(low));
2073 reg |= low & NVREG_SLOTTIME_MASK;
2074
2075 /* Need to stop tx before change takes effect.
2076 * Caller has already gained np->lock.
2077 */
2078 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2079 if (tx_status)
2080 nv_stop_tx(dev);
2081 nv_stop_rx(dev);
2082 writel(reg, base + NvRegSlotTime);
2083 if (tx_status)
2084 nv_start_tx(dev);
2085 nv_start_rx(dev);
2086 }
2087
2088 /* Gear Backoff Seeds */
2089 #define BACKOFF_SEEDSET_ROWS 8
2090 #define BACKOFF_SEEDSET_LFSRS 15
2091
2092 /* Known Good seed sets */
2093 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2094 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2095 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2096 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2097 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2098 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2099 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2100 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2101 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2102
2103 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2104 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2105 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2106 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2107 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2108 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2109 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2110 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2111 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2112
2113 static void nv_gear_backoff_reseed(struct net_device *dev)
2114 {
2115 u8 __iomem *base = get_hwbase(dev);
2116 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2117 u32 temp, seedset, combinedSeed;
2118 int i;
2119
2120 /* Setup seed for free running LFSR */
2121 /* We are going to read the time stamp counter 3 times
2122 and swizzle bits around to increase randomness */
2123 get_random_bytes(&miniseed1, sizeof(miniseed1));
2124 miniseed1 &= 0x0fff;
2125 if (miniseed1 == 0)
2126 miniseed1 = 0xabc;
2127
2128 get_random_bytes(&miniseed2, sizeof(miniseed2));
2129 miniseed2 &= 0x0fff;
2130 if (miniseed2 == 0)
2131 miniseed2 = 0xabc;
2132 miniseed2_reversed =
2133 ((miniseed2 & 0xF00) >> 8) |
2134 (miniseed2 & 0x0F0) |
2135 ((miniseed2 & 0x00F) << 8);
2136
2137 get_random_bytes(&miniseed3, sizeof(miniseed3));
2138 miniseed3 &= 0x0fff;
2139 if (miniseed3 == 0)
2140 miniseed3 = 0xabc;
2141 miniseed3_reversed =
2142 ((miniseed3 & 0xF00) >> 8) |
2143 (miniseed3 & 0x0F0) |
2144 ((miniseed3 & 0x00F) << 8);
2145
2146 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2147 (miniseed2 ^ miniseed3_reversed);
2148
2149 /* Seeds can not be zero */
2150 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2151 combinedSeed |= 0x08;
2152 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2153 combinedSeed |= 0x8000;
2154
2155 /* No need to disable tx here */
2156 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2157 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2158 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2159 writel(temp, base + NvRegBackOffControl);
2160
2161 /* Setup seeds for all gear LFSRs. */
2162 get_random_bytes(&seedset, sizeof(seedset));
2163 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2164 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2165 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2166 temp |= main_seedset[seedset][i-1] & 0x3ff;
2167 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2168 writel(temp, base + NvRegBackOffControl);
2169 }
2170 }
2171
2172 /*
2173 * nv_start_xmit: dev->hard_start_xmit function
2174 * Called with netif_tx_lock held.
2175 */
2176 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2177 {
2178 struct fe_priv *np = netdev_priv(dev);
2179 u32 tx_flags = 0;
2180 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2181 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2182 unsigned int i;
2183 u32 offset = 0;
2184 u32 bcnt;
2185 u32 size = skb_headlen(skb);
2186 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2187 u32 empty_slots;
2188 struct ring_desc *put_tx;
2189 struct ring_desc *start_tx;
2190 struct ring_desc *prev_tx;
2191 struct nv_skb_map *prev_tx_ctx;
2192 unsigned long flags;
2193
2194 /* add fragments to entries count */
2195 for (i = 0; i < fragments; i++) {
2196 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2197
2198 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2199 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2200 }
2201
2202 spin_lock_irqsave(&np->lock, flags);
2203 empty_slots = nv_get_empty_tx_slots(np);
2204 if (unlikely(empty_slots <= entries)) {
2205 netif_stop_queue(dev);
2206 np->tx_stop = 1;
2207 spin_unlock_irqrestore(&np->lock, flags);
2208 return NETDEV_TX_BUSY;
2209 }
2210 spin_unlock_irqrestore(&np->lock, flags);
2211
2212 start_tx = put_tx = np->put_tx.orig;
2213
2214 /* setup the header buffer */
2215 do {
2216 prev_tx = put_tx;
2217 prev_tx_ctx = np->put_tx_ctx;
2218 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2219 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2220 PCI_DMA_TODEVICE);
2221 np->put_tx_ctx->dma_len = bcnt;
2222 np->put_tx_ctx->dma_single = 1;
2223 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2224 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2225
2226 tx_flags = np->tx_flags;
2227 offset += bcnt;
2228 size -= bcnt;
2229 if (unlikely(put_tx++ == np->last_tx.orig))
2230 put_tx = np->first_tx.orig;
2231 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2232 np->put_tx_ctx = np->first_tx_ctx;
2233 } while (size);
2234
2235 /* setup the fragments */
2236 for (i = 0; i < fragments; i++) {
2237 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2238 u32 frag_size = skb_frag_size(frag);
2239 offset = 0;
2240
2241 do {
2242 prev_tx = put_tx;
2243 prev_tx_ctx = np->put_tx_ctx;
2244 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2245 np->put_tx_ctx->dma = skb_frag_dma_map(
2246 &np->pci_dev->dev,
2247 frag, offset,
2248 bcnt,
2249 DMA_TO_DEVICE);
2250 np->put_tx_ctx->dma_len = bcnt;
2251 np->put_tx_ctx->dma_single = 0;
2252 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2253 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2254
2255 offset += bcnt;
2256 frag_size -= bcnt;
2257 if (unlikely(put_tx++ == np->last_tx.orig))
2258 put_tx = np->first_tx.orig;
2259 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2260 np->put_tx_ctx = np->first_tx_ctx;
2261 } while (frag_size);
2262 }
2263
2264 /* set last fragment flag */
2265 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2266
2267 /* save skb in this slot's context area */
2268 prev_tx_ctx->skb = skb;
2269
2270 if (skb_is_gso(skb))
2271 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2272 else
2273 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2274 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2275
2276 spin_lock_irqsave(&np->lock, flags);
2277
2278 /* set tx flags */
2279 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2280
2281 netdev_sent_queue(np->dev, skb->len);
2282
2283 np->put_tx.orig = put_tx;
2284
2285 spin_unlock_irqrestore(&np->lock, flags);
2286
2287 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2288 return NETDEV_TX_OK;
2289 }
2290
2291 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2292 struct net_device *dev)
2293 {
2294 struct fe_priv *np = netdev_priv(dev);
2295 u32 tx_flags = 0;
2296 u32 tx_flags_extra;
2297 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2298 unsigned int i;
2299 u32 offset = 0;
2300 u32 bcnt;
2301 u32 size = skb_headlen(skb);
2302 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2303 u32 empty_slots;
2304 struct ring_desc_ex *put_tx;
2305 struct ring_desc_ex *start_tx;
2306 struct ring_desc_ex *prev_tx;
2307 struct nv_skb_map *prev_tx_ctx;
2308 struct nv_skb_map *start_tx_ctx;
2309 unsigned long flags;
2310
2311 /* add fragments to entries count */
2312 for (i = 0; i < fragments; i++) {
2313 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2314
2315 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2316 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2317 }
2318
2319 spin_lock_irqsave(&np->lock, flags);
2320 empty_slots = nv_get_empty_tx_slots(np);
2321 if (unlikely(empty_slots <= entries)) {
2322 netif_stop_queue(dev);
2323 np->tx_stop = 1;
2324 spin_unlock_irqrestore(&np->lock, flags);
2325 return NETDEV_TX_BUSY;
2326 }
2327 spin_unlock_irqrestore(&np->lock, flags);
2328
2329 start_tx = put_tx = np->put_tx.ex;
2330 start_tx_ctx = np->put_tx_ctx;
2331
2332 /* setup the header buffer */
2333 do {
2334 prev_tx = put_tx;
2335 prev_tx_ctx = np->put_tx_ctx;
2336 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2337 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2338 PCI_DMA_TODEVICE);
2339 np->put_tx_ctx->dma_len = bcnt;
2340 np->put_tx_ctx->dma_single = 1;
2341 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2342 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2343 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2344
2345 tx_flags = NV_TX2_VALID;
2346 offset += bcnt;
2347 size -= bcnt;
2348 if (unlikely(put_tx++ == np->last_tx.ex))
2349 put_tx = np->first_tx.ex;
2350 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2351 np->put_tx_ctx = np->first_tx_ctx;
2352 } while (size);
2353
2354 /* setup the fragments */
2355 for (i = 0; i < fragments; i++) {
2356 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2357 u32 frag_size = skb_frag_size(frag);
2358 offset = 0;
2359
2360 do {
2361 prev_tx = put_tx;
2362 prev_tx_ctx = np->put_tx_ctx;
2363 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2364 np->put_tx_ctx->dma = skb_frag_dma_map(
2365 &np->pci_dev->dev,
2366 frag, offset,
2367 bcnt,
2368 DMA_TO_DEVICE);
2369 np->put_tx_ctx->dma_len = bcnt;
2370 np->put_tx_ctx->dma_single = 0;
2371 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2372 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2373 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2374
2375 offset += bcnt;
2376 frag_size -= bcnt;
2377 if (unlikely(put_tx++ == np->last_tx.ex))
2378 put_tx = np->first_tx.ex;
2379 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2380 np->put_tx_ctx = np->first_tx_ctx;
2381 } while (frag_size);
2382 }
2383
2384 /* set last fragment flag */
2385 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2386
2387 /* save skb in this slot's context area */
2388 prev_tx_ctx->skb = skb;
2389
2390 if (skb_is_gso(skb))
2391 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2392 else
2393 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2394 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2395
2396 /* vlan tag */
2397 if (vlan_tx_tag_present(skb))
2398 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2399 vlan_tx_tag_get(skb));
2400 else
2401 start_tx->txvlan = 0;
2402
2403 spin_lock_irqsave(&np->lock, flags);
2404
2405 if (np->tx_limit) {
2406 /* Limit the number of outstanding tx. Setup all fragments, but
2407 * do not set the VALID bit on the first descriptor. Save a pointer
2408 * to that descriptor and also for next skb_map element.
2409 */
2410
2411 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2412 if (!np->tx_change_owner)
2413 np->tx_change_owner = start_tx_ctx;
2414
2415 /* remove VALID bit */
2416 tx_flags &= ~NV_TX2_VALID;
2417 start_tx_ctx->first_tx_desc = start_tx;
2418 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2419 np->tx_end_flip = np->put_tx_ctx;
2420 } else {
2421 np->tx_pkts_in_progress++;
2422 }
2423 }
2424
2425 /* set tx flags */
2426 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2427
2428 netdev_sent_queue(np->dev, skb->len);
2429
2430 np->put_tx.ex = put_tx;
2431
2432 spin_unlock_irqrestore(&np->lock, flags);
2433
2434 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2435 return NETDEV_TX_OK;
2436 }
2437
2438 static inline void nv_tx_flip_ownership(struct net_device *dev)
2439 {
2440 struct fe_priv *np = netdev_priv(dev);
2441
2442 np->tx_pkts_in_progress--;
2443 if (np->tx_change_owner) {
2444 np->tx_change_owner->first_tx_desc->flaglen |=
2445 cpu_to_le32(NV_TX2_VALID);
2446 np->tx_pkts_in_progress++;
2447
2448 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2449 if (np->tx_change_owner == np->tx_end_flip)
2450 np->tx_change_owner = NULL;
2451
2452 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2453 }
2454 }
2455
2456 /*
2457 * nv_tx_done: check for completed packets, release the skbs.
2458 *
2459 * Caller must own np->lock.
2460 */
2461 static int nv_tx_done(struct net_device *dev, int limit)
2462 {
2463 struct fe_priv *np = netdev_priv(dev);
2464 u32 flags;
2465 int tx_work = 0;
2466 struct ring_desc *orig_get_tx = np->get_tx.orig;
2467 unsigned int bytes_compl = 0;
2468
2469 while ((np->get_tx.orig != np->put_tx.orig) &&
2470 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2471 (tx_work < limit)) {
2472
2473 nv_unmap_txskb(np, np->get_tx_ctx);
2474
2475 if (np->desc_ver == DESC_VER_1) {
2476 if (flags & NV_TX_LASTPACKET) {
2477 if (flags & NV_TX_ERROR) {
2478 if ((flags & NV_TX_RETRYERROR)
2479 && !(flags & NV_TX_RETRYCOUNT_MASK))
2480 nv_legacybackoff_reseed(dev);
2481 } else {
2482 u64_stats_update_begin(&np->swstats_tx_syncp);
2483 np->stat_tx_packets++;
2484 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2485 u64_stats_update_end(&np->swstats_tx_syncp);
2486 }
2487 bytes_compl += np->get_tx_ctx->skb->len;
2488 dev_kfree_skb_any(np->get_tx_ctx->skb);
2489 np->get_tx_ctx->skb = NULL;
2490 tx_work++;
2491 }
2492 } else {
2493 if (flags & NV_TX2_LASTPACKET) {
2494 if (flags & NV_TX2_ERROR) {
2495 if ((flags & NV_TX2_RETRYERROR)
2496 && !(flags & NV_TX2_RETRYCOUNT_MASK))
2497 nv_legacybackoff_reseed(dev);
2498 } else {
2499 u64_stats_update_begin(&np->swstats_tx_syncp);
2500 np->stat_tx_packets++;
2501 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2502 u64_stats_update_end(&np->swstats_tx_syncp);
2503 }
2504 bytes_compl += np->get_tx_ctx->skb->len;
2505 dev_kfree_skb_any(np->get_tx_ctx->skb);
2506 np->get_tx_ctx->skb = NULL;
2507 tx_work++;
2508 }
2509 }
2510 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2511 np->get_tx.orig = np->first_tx.orig;
2512 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2513 np->get_tx_ctx = np->first_tx_ctx;
2514 }
2515
2516 netdev_completed_queue(np->dev, tx_work, bytes_compl);
2517
2518 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2519 np->tx_stop = 0;
2520 netif_wake_queue(dev);
2521 }
2522 return tx_work;
2523 }
2524
2525 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2526 {
2527 struct fe_priv *np = netdev_priv(dev);
2528 u32 flags;
2529 int tx_work = 0;
2530 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2531 unsigned long bytes_cleaned = 0;
2532
2533 while ((np->get_tx.ex != np->put_tx.ex) &&
2534 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2535 (tx_work < limit)) {
2536
2537 nv_unmap_txskb(np, np->get_tx_ctx);
2538
2539 if (flags & NV_TX2_LASTPACKET) {
2540 if (flags & NV_TX2_ERROR) {
2541 if ((flags & NV_TX2_RETRYERROR)
2542 && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2543 if (np->driver_data & DEV_HAS_GEAR_MODE)
2544 nv_gear_backoff_reseed(dev);
2545 else
2546 nv_legacybackoff_reseed(dev);
2547 }
2548 } else {
2549 u64_stats_update_begin(&np->swstats_tx_syncp);
2550 np->stat_tx_packets++;
2551 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2552 u64_stats_update_end(&np->swstats_tx_syncp);
2553 }
2554
2555 bytes_cleaned += np->get_tx_ctx->skb->len;
2556 dev_kfree_skb_any(np->get_tx_ctx->skb);
2557 np->get_tx_ctx->skb = NULL;
2558 tx_work++;
2559
2560 if (np->tx_limit)
2561 nv_tx_flip_ownership(dev);
2562 }
2563
2564 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2565 np->get_tx.ex = np->first_tx.ex;
2566 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2567 np->get_tx_ctx = np->first_tx_ctx;
2568 }
2569
2570 netdev_completed_queue(np->dev, tx_work, bytes_cleaned);
2571
2572 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2573 np->tx_stop = 0;
2574 netif_wake_queue(dev);
2575 }
2576 return tx_work;
2577 }
2578
2579 /*
2580 * nv_tx_timeout: dev->tx_timeout function
2581 * Called with netif_tx_lock held.
2582 */
2583 static void nv_tx_timeout(struct net_device *dev)
2584 {
2585 struct fe_priv *np = netdev_priv(dev);
2586 u8 __iomem *base = get_hwbase(dev);
2587 u32 status;
2588 union ring_type put_tx;
2589 int saved_tx_limit;
2590
2591 if (np->msi_flags & NV_MSI_X_ENABLED)
2592 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2593 else
2594 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2595
2596 netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2597
2598 if (unlikely(debug_tx_timeout)) {
2599 int i;
2600
2601 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2602 netdev_info(dev, "Dumping tx registers\n");
2603 for (i = 0; i <= np->register_size; i += 32) {
2604 netdev_info(dev,
2605 "%3x: %08x %08x %08x %08x "
2606 "%08x %08x %08x %08x\n",
2607 i,
2608 readl(base + i + 0), readl(base + i + 4),
2609 readl(base + i + 8), readl(base + i + 12),
2610 readl(base + i + 16), readl(base + i + 20),
2611 readl(base + i + 24), readl(base + i + 28));
2612 }
2613 netdev_info(dev, "Dumping tx ring\n");
2614 for (i = 0; i < np->tx_ring_size; i += 4) {
2615 if (!nv_optimized(np)) {
2616 netdev_info(dev,
2617 "%03x: %08x %08x // %08x %08x "
2618 "// %08x %08x // %08x %08x\n",
2619 i,
2620 le32_to_cpu(np->tx_ring.orig[i].buf),
2621 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2622 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2623 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2624 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2625 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2626 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2627 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2628 } else {
2629 netdev_info(dev,
2630 "%03x: %08x %08x %08x "
2631 "// %08x %08x %08x "
2632 "// %08x %08x %08x "
2633 "// %08x %08x %08x\n",
2634 i,
2635 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2636 le32_to_cpu(np->tx_ring.ex[i].buflow),
2637 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2638 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2639 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2640 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2641 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2642 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2643 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2644 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2645 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2646 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2647 }
2648 }
2649 }
2650
2651 spin_lock_irq(&np->lock);
2652
2653 /* 1) stop tx engine */
2654 nv_stop_tx(dev);
2655
2656 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2657 saved_tx_limit = np->tx_limit;
2658 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2659 np->tx_stop = 0; /* prevent waking tx queue */
2660 if (!nv_optimized(np))
2661 nv_tx_done(dev, np->tx_ring_size);
2662 else
2663 nv_tx_done_optimized(dev, np->tx_ring_size);
2664
2665 /* save current HW position */
2666 if (np->tx_change_owner)
2667 put_tx.ex = np->tx_change_owner->first_tx_desc;
2668 else
2669 put_tx = np->put_tx;
2670
2671 /* 3) clear all tx state */
2672 nv_drain_tx(dev);
2673 nv_init_tx(dev);
2674
2675 /* 4) restore state to current HW position */
2676 np->get_tx = np->put_tx = put_tx;
2677 np->tx_limit = saved_tx_limit;
2678
2679 /* 5) restart tx engine */
2680 nv_start_tx(dev);
2681 netif_wake_queue(dev);
2682 spin_unlock_irq(&np->lock);
2683 }
2684
2685 /*
2686 * Called when the nic notices a mismatch between the actual data len on the
2687 * wire and the len indicated in the 802 header
2688 */
2689 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2690 {
2691 int hdrlen; /* length of the 802 header */
2692 int protolen; /* length as stored in the proto field */
2693
2694 /* 1) calculate len according to header */
2695 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2696 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2697 hdrlen = VLAN_HLEN;
2698 } else {
2699 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2700 hdrlen = ETH_HLEN;
2701 }
2702 if (protolen > ETH_DATA_LEN)
2703 return datalen; /* Value in proto field not a len, no checks possible */
2704
2705 protolen += hdrlen;
2706 /* consistency checks: */
2707 if (datalen > ETH_ZLEN) {
2708 if (datalen >= protolen) {
2709 /* more data on wire than in 802 header, trim of
2710 * additional data.
2711 */
2712 return protolen;
2713 } else {
2714 /* less data on wire than mentioned in header.
2715 * Discard the packet.
2716 */
2717 return -1;
2718 }
2719 } else {
2720 /* short packet. Accept only if 802 values are also short */
2721 if (protolen > ETH_ZLEN) {
2722 return -1;
2723 }
2724 return datalen;
2725 }
2726 }
2727
2728 static int nv_rx_process(struct net_device *dev, int limit)
2729 {
2730 struct fe_priv *np = netdev_priv(dev);
2731 u32 flags;
2732 int rx_work = 0;
2733 struct sk_buff *skb;
2734 int len;
2735
2736 while ((np->get_rx.orig != np->put_rx.orig) &&
2737 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2738 (rx_work < limit)) {
2739
2740 /*
2741 * the packet is for us - immediately tear down the pci mapping.
2742 * TODO: check if a prefetch of the first cacheline improves
2743 * the performance.
2744 */
2745 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2746 np->get_rx_ctx->dma_len,
2747 PCI_DMA_FROMDEVICE);
2748 skb = np->get_rx_ctx->skb;
2749 np->get_rx_ctx->skb = NULL;
2750
2751 /* look at what we actually got: */
2752 if (np->desc_ver == DESC_VER_1) {
2753 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2754 len = flags & LEN_MASK_V1;
2755 if (unlikely(flags & NV_RX_ERROR)) {
2756 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2757 len = nv_getlen(dev, skb->data, len);
2758 if (len < 0) {
2759 dev_kfree_skb(skb);
2760 goto next_pkt;
2761 }
2762 }
2763 /* framing errors are soft errors */
2764 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2765 if (flags & NV_RX_SUBSTRACT1)
2766 len--;
2767 }
2768 /* the rest are hard errors */
2769 else {
2770 if (flags & NV_RX_MISSEDFRAME) {
2771 u64_stats_update_begin(&np->swstats_rx_syncp);
2772 np->stat_rx_missed_errors++;
2773 u64_stats_update_end(&np->swstats_rx_syncp);
2774 }
2775 dev_kfree_skb(skb);
2776 goto next_pkt;
2777 }
2778 }
2779 } else {
2780 dev_kfree_skb(skb);
2781 goto next_pkt;
2782 }
2783 } else {
2784 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2785 len = flags & LEN_MASK_V2;
2786 if (unlikely(flags & NV_RX2_ERROR)) {
2787 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2788 len = nv_getlen(dev, skb->data, len);
2789 if (len < 0) {
2790 dev_kfree_skb(skb);
2791 goto next_pkt;
2792 }
2793 }
2794 /* framing errors are soft errors */
2795 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2796 if (flags & NV_RX2_SUBSTRACT1)
2797 len--;
2798 }
2799 /* the rest are hard errors */
2800 else {
2801 dev_kfree_skb(skb);
2802 goto next_pkt;
2803 }
2804 }
2805 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2806 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2807 skb->ip_summed = CHECKSUM_UNNECESSARY;
2808 } else {
2809 dev_kfree_skb(skb);
2810 goto next_pkt;
2811 }
2812 }
2813 /* got a valid packet - forward it to the network core */
2814 skb_put(skb, len);
2815 skb->protocol = eth_type_trans(skb, dev);
2816 napi_gro_receive(&np->napi, skb);
2817 u64_stats_update_begin(&np->swstats_rx_syncp);
2818 np->stat_rx_packets++;
2819 np->stat_rx_bytes += len;
2820 u64_stats_update_end(&np->swstats_rx_syncp);
2821 next_pkt:
2822 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2823 np->get_rx.orig = np->first_rx.orig;
2824 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2825 np->get_rx_ctx = np->first_rx_ctx;
2826
2827 rx_work++;
2828 }
2829
2830 return rx_work;
2831 }
2832
2833 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2834 {
2835 struct fe_priv *np = netdev_priv(dev);
2836 u32 flags;
2837 u32 vlanflags = 0;
2838 int rx_work = 0;
2839 struct sk_buff *skb;
2840 int len;
2841
2842 while ((np->get_rx.ex != np->put_rx.ex) &&
2843 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2844 (rx_work < limit)) {
2845
2846 /*
2847 * the packet is for us - immediately tear down the pci mapping.
2848 * TODO: check if a prefetch of the first cacheline improves
2849 * the performance.
2850 */
2851 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2852 np->get_rx_ctx->dma_len,
2853 PCI_DMA_FROMDEVICE);
2854 skb = np->get_rx_ctx->skb;
2855 np->get_rx_ctx->skb = NULL;
2856
2857 /* look at what we actually got: */
2858 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2859 len = flags & LEN_MASK_V2;
2860 if (unlikely(flags & NV_RX2_ERROR)) {
2861 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2862 len = nv_getlen(dev, skb->data, len);
2863 if (len < 0) {
2864 dev_kfree_skb(skb);
2865 goto next_pkt;
2866 }
2867 }
2868 /* framing errors are soft errors */
2869 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2870 if (flags & NV_RX2_SUBSTRACT1)
2871 len--;
2872 }
2873 /* the rest are hard errors */
2874 else {
2875 dev_kfree_skb(skb);
2876 goto next_pkt;
2877 }
2878 }
2879
2880 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2881 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2882 skb->ip_summed = CHECKSUM_UNNECESSARY;
2883
2884 /* got a valid packet - forward it to the network core */
2885 skb_put(skb, len);
2886 skb->protocol = eth_type_trans(skb, dev);
2887 prefetch(skb->data);
2888
2889 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2890
2891 /*
2892 * There's need to check for NETIF_F_HW_VLAN_RX here.
2893 * Even if vlan rx accel is disabled,
2894 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2895 */
2896 if (dev->features & NETIF_F_HW_VLAN_RX &&
2897 vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2898 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2899
2900 __vlan_hwaccel_put_tag(skb, vid);
2901 }
2902 napi_gro_receive(&np->napi, skb);
2903 u64_stats_update_begin(&np->swstats_rx_syncp);
2904 np->stat_rx_packets++;
2905 np->stat_rx_bytes += len;
2906 u64_stats_update_end(&np->swstats_rx_syncp);
2907 } else {
2908 dev_kfree_skb(skb);
2909 }
2910 next_pkt:
2911 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2912 np->get_rx.ex = np->first_rx.ex;
2913 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2914 np->get_rx_ctx = np->first_rx_ctx;
2915
2916 rx_work++;
2917 }
2918
2919 return rx_work;
2920 }
2921
2922 static void set_bufsize(struct net_device *dev)
2923 {
2924 struct fe_priv *np = netdev_priv(dev);
2925
2926 if (dev->mtu <= ETH_DATA_LEN)
2927 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2928 else
2929 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2930 }
2931
2932 /*
2933 * nv_change_mtu: dev->change_mtu function
2934 * Called with dev_base_lock held for read.
2935 */
2936 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2937 {
2938 struct fe_priv *np = netdev_priv(dev);
2939 int old_mtu;
2940
2941 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2942 return -EINVAL;
2943
2944 old_mtu = dev->mtu;
2945 dev->mtu = new_mtu;
2946
2947 /* return early if the buffer sizes will not change */
2948 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2949 return 0;
2950 if (old_mtu == new_mtu)
2951 return 0;
2952
2953 /* synchronized against open : rtnl_lock() held by caller */
2954 if (netif_running(dev)) {
2955 u8 __iomem *base = get_hwbase(dev);
2956 /*
2957 * It seems that the nic preloads valid ring entries into an
2958 * internal buffer. The procedure for flushing everything is
2959 * guessed, there is probably a simpler approach.
2960 * Changing the MTU is a rare event, it shouldn't matter.
2961 */
2962 nv_disable_irq(dev);
2963 nv_napi_disable(dev);
2964 netif_tx_lock_bh(dev);
2965 netif_addr_lock(dev);
2966 spin_lock(&np->lock);
2967 /* stop engines */
2968 nv_stop_rxtx(dev);
2969 nv_txrx_reset(dev);
2970 /* drain rx queue */
2971 nv_drain_rxtx(dev);
2972 /* reinit driver view of the rx queue */
2973 set_bufsize(dev);
2974 if (nv_init_ring(dev)) {
2975 if (!np->in_shutdown)
2976 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2977 }
2978 /* reinit nic view of the rx queue */
2979 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2980 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2981 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2982 base + NvRegRingSizes);
2983 pci_push(base);
2984 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2985 pci_push(base);
2986
2987 /* restart rx engine */
2988 nv_start_rxtx(dev);
2989 spin_unlock(&np->lock);
2990 netif_addr_unlock(dev);
2991 netif_tx_unlock_bh(dev);
2992 nv_napi_enable(dev);
2993 nv_enable_irq(dev);
2994 }
2995 return 0;
2996 }
2997
2998 static void nv_copy_mac_to_hw(struct net_device *dev)
2999 {
3000 u8 __iomem *base = get_hwbase(dev);
3001 u32 mac[2];
3002
3003 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3004 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3005 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3006
3007 writel(mac[0], base + NvRegMacAddrA);
3008 writel(mac[1], base + NvRegMacAddrB);
3009 }
3010
3011 /*
3012 * nv_set_mac_address: dev->set_mac_address function
3013 * Called with rtnl_lock() held.
3014 */
3015 static int nv_set_mac_address(struct net_device *dev, void *addr)
3016 {
3017 struct fe_priv *np = netdev_priv(dev);
3018 struct sockaddr *macaddr = (struct sockaddr *)addr;
3019
3020 if (!is_valid_ether_addr(macaddr->sa_data))
3021 return -EADDRNOTAVAIL;
3022
3023 /* synchronized against open : rtnl_lock() held by caller */
3024 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3025
3026 if (netif_running(dev)) {
3027 netif_tx_lock_bh(dev);
3028 netif_addr_lock(dev);
3029 spin_lock_irq(&np->lock);
3030
3031 /* stop rx engine */
3032 nv_stop_rx(dev);
3033
3034 /* set mac address */
3035 nv_copy_mac_to_hw(dev);
3036
3037 /* restart rx engine */
3038 nv_start_rx(dev);
3039 spin_unlock_irq(&np->lock);
3040 netif_addr_unlock(dev);
3041 netif_tx_unlock_bh(dev);
3042 } else {
3043 nv_copy_mac_to_hw(dev);
3044 }
3045 return 0;
3046 }
3047
3048 /*
3049 * nv_set_multicast: dev->set_multicast function
3050 * Called with netif_tx_lock held.
3051 */
3052 static void nv_set_multicast(struct net_device *dev)
3053 {
3054 struct fe_priv *np = netdev_priv(dev);
3055 u8 __iomem *base = get_hwbase(dev);
3056 u32 addr[2];
3057 u32 mask[2];
3058 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3059
3060 memset(addr, 0, sizeof(addr));
3061 memset(mask, 0, sizeof(mask));
3062
3063 if (dev->flags & IFF_PROMISC) {
3064 pff |= NVREG_PFF_PROMISC;
3065 } else {
3066 pff |= NVREG_PFF_MYADDR;
3067
3068 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3069 u32 alwaysOff[2];
3070 u32 alwaysOn[2];
3071
3072 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3073 if (dev->flags & IFF_ALLMULTI) {
3074 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3075 } else {
3076 struct netdev_hw_addr *ha;
3077
3078 netdev_for_each_mc_addr(ha, dev) {
3079 unsigned char *hw_addr = ha->addr;
3080 u32 a, b;
3081
3082 a = le32_to_cpu(*(__le32 *) hw_addr);
3083 b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
3084 alwaysOn[0] &= a;
3085 alwaysOff[0] &= ~a;
3086 alwaysOn[1] &= b;
3087 alwaysOff[1] &= ~b;
3088 }
3089 }
3090 addr[0] = alwaysOn[0];
3091 addr[1] = alwaysOn[1];
3092 mask[0] = alwaysOn[0] | alwaysOff[0];
3093 mask[1] = alwaysOn[1] | alwaysOff[1];
3094 } else {
3095 mask[0] = NVREG_MCASTMASKA_NONE;
3096 mask[1] = NVREG_MCASTMASKB_NONE;
3097 }
3098 }
3099 addr[0] |= NVREG_MCASTADDRA_FORCE;
3100 pff |= NVREG_PFF_ALWAYS;
3101 spin_lock_irq(&np->lock);
3102 nv_stop_rx(dev);
3103 writel(addr[0], base + NvRegMulticastAddrA);
3104 writel(addr[1], base + NvRegMulticastAddrB);
3105 writel(mask[0], base + NvRegMulticastMaskA);
3106 writel(mask[1], base + NvRegMulticastMaskB);
3107 writel(pff, base + NvRegPacketFilterFlags);
3108 nv_start_rx(dev);
3109 spin_unlock_irq(&np->lock);
3110 }
3111
3112 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3113 {
3114 struct fe_priv *np = netdev_priv(dev);
3115 u8 __iomem *base = get_hwbase(dev);
3116
3117 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3118
3119 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3120 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3121 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3122 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3123 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3124 } else {
3125 writel(pff, base + NvRegPacketFilterFlags);
3126 }
3127 }
3128 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3129 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3130 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3131 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3132 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3133 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3134 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3135 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3136 /* limit the number of tx pause frames to a default of 8 */
3137 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3138 }
3139 writel(pause_enable, base + NvRegTxPauseFrame);
3140 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3141 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3142 } else {
3143 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3144 writel(regmisc, base + NvRegMisc1);
3145 }
3146 }
3147 }
3148
3149 static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3150 {
3151 struct fe_priv *np = netdev_priv(dev);
3152 u8 __iomem *base = get_hwbase(dev);
3153 u32 phyreg, txreg;
3154 int mii_status;
3155
3156 np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3157 np->duplex = duplex;
3158
3159 /* see if gigabit phy */
3160 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3161 if (mii_status & PHY_GIGABIT) {
3162 np->gigabit = PHY_GIGABIT;
3163 phyreg = readl(base + NvRegSlotTime);
3164 phyreg &= ~(0x3FF00);
3165 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3166 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3167 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3168 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3169 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3170 phyreg |= NVREG_SLOTTIME_1000_FULL;
3171 writel(phyreg, base + NvRegSlotTime);
3172 }
3173
3174 phyreg = readl(base + NvRegPhyInterface);
3175 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3176 if (np->duplex == 0)
3177 phyreg |= PHY_HALF;
3178 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3179 phyreg |= PHY_100;
3180 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3181 NVREG_LINKSPEED_1000)
3182 phyreg |= PHY_1000;
3183 writel(phyreg, base + NvRegPhyInterface);
3184
3185 if (phyreg & PHY_RGMII) {
3186 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3187 NVREG_LINKSPEED_1000)
3188 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3189 else
3190 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3191 } else {
3192 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3193 }
3194 writel(txreg, base + NvRegTxDeferral);
3195
3196 if (np->desc_ver == DESC_VER_1) {
3197 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3198 } else {
3199 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3200 NVREG_LINKSPEED_1000)
3201 txreg = NVREG_TX_WM_DESC2_3_1000;
3202 else
3203 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3204 }
3205 writel(txreg, base + NvRegTxWatermark);
3206
3207 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3208 base + NvRegMisc1);
3209 pci_push(base);
3210 writel(np->linkspeed, base + NvRegLinkSpeed);
3211 pci_push(base);
3212
3213 return;
3214 }
3215
3216 /**
3217 * nv_update_linkspeed: Setup the MAC according to the link partner
3218 * @dev: Network device to be configured
3219 *
3220 * The function queries the PHY and checks if there is a link partner.
3221 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3222 * set to 10 MBit HD.
3223 *
3224 * The function returns 0 if there is no link partner and 1 if there is
3225 * a good link partner.
3226 */
3227 static int nv_update_linkspeed(struct net_device *dev)
3228 {
3229 struct fe_priv *np = netdev_priv(dev);
3230 u8 __iomem *base = get_hwbase(dev);
3231 int adv = 0;
3232 int lpa = 0;
3233 int adv_lpa, adv_pause, lpa_pause;
3234 int newls = np->linkspeed;
3235 int newdup = np->duplex;
3236 int mii_status;
3237 u32 bmcr;
3238 int retval = 0;
3239 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3240 u32 txrxFlags = 0;
3241 u32 phy_exp;
3242
3243 /* If device loopback is enabled, set carrier on and enable max link
3244 * speed.
3245 */
3246 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3247 if (bmcr & BMCR_LOOPBACK) {
3248 if (netif_running(dev)) {
3249 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3250 if (!netif_carrier_ok(dev))
3251 netif_carrier_on(dev);
3252 }
3253 return 1;
3254 }
3255
3256 /* BMSR_LSTATUS is latched, read it twice:
3257 * we want the current value.
3258 */
3259 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3260 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3261
3262 if (!(mii_status & BMSR_LSTATUS)) {
3263 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3264 newdup = 0;
3265 retval = 0;
3266 goto set_speed;
3267 }
3268
3269 if (np->autoneg == 0) {
3270 if (np->fixed_mode & LPA_100FULL) {
3271 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3272 newdup = 1;
3273 } else if (np->fixed_mode & LPA_100HALF) {
3274 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3275 newdup = 0;
3276 } else if (np->fixed_mode & LPA_10FULL) {
3277 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3278 newdup = 1;
3279 } else {
3280 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3281 newdup = 0;
3282 }
3283 retval = 1;
3284 goto set_speed;
3285 }
3286 /* check auto negotiation is complete */
3287 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3288 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3289 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3290 newdup = 0;
3291 retval = 0;
3292 goto set_speed;
3293 }
3294
3295 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3296 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3297
3298 retval = 1;
3299 if (np->gigabit == PHY_GIGABIT) {
3300 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3301 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3302
3303 if ((control_1000 & ADVERTISE_1000FULL) &&
3304 (status_1000 & LPA_1000FULL)) {
3305 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3306 newdup = 1;
3307 goto set_speed;
3308 }
3309 }
3310
3311 /* FIXME: handle parallel detection properly */
3312 adv_lpa = lpa & adv;
3313 if (adv_lpa & LPA_100FULL) {
3314 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3315 newdup = 1;
3316 } else if (adv_lpa & LPA_100HALF) {
3317 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3318 newdup = 0;
3319 } else if (adv_lpa & LPA_10FULL) {
3320 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3321 newdup = 1;
3322 } else if (adv_lpa & LPA_10HALF) {
3323 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3324 newdup = 0;
3325 } else {
3326 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3327 newdup = 0;
3328 }
3329
3330 set_speed:
3331 if (np->duplex == newdup && np->linkspeed == newls)
3332 return retval;
3333
3334 np->duplex = newdup;
3335 np->linkspeed = newls;
3336
3337 /* The transmitter and receiver must be restarted for safe update */
3338 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3339 txrxFlags |= NV_RESTART_TX;
3340 nv_stop_tx(dev);
3341 }
3342 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3343 txrxFlags |= NV_RESTART_RX;
3344 nv_stop_rx(dev);
3345 }
3346
3347 if (np->gigabit == PHY_GIGABIT) {
3348 phyreg = readl(base + NvRegSlotTime);
3349 phyreg &= ~(0x3FF00);
3350 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3351 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3352 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3353 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3354 phyreg |= NVREG_SLOTTIME_1000_FULL;
3355 writel(phyreg, base + NvRegSlotTime);
3356 }
3357
3358 phyreg = readl(base + NvRegPhyInterface);
3359 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3360 if (np->duplex == 0)
3361 phyreg |= PHY_HALF;
3362 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3363 phyreg |= PHY_100;
3364 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3365 phyreg |= PHY_1000;
3366 writel(phyreg, base + NvRegPhyInterface);
3367
3368 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3369 if (phyreg & PHY_RGMII) {
3370 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3371 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3372 } else {
3373 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3374 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3375 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3376 else
3377 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3378 } else {
3379 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3380 }
3381 }
3382 } else {
3383 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3384 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3385 else
3386 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3387 }
3388 writel(txreg, base + NvRegTxDeferral);
3389
3390 if (np->desc_ver == DESC_VER_1) {
3391 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3392 } else {
3393 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3394 txreg = NVREG_TX_WM_DESC2_3_1000;
3395 else
3396 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3397 }
3398 writel(txreg, base + NvRegTxWatermark);
3399
3400 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3401 base + NvRegMisc1);
3402 pci_push(base);
3403 writel(np->linkspeed, base + NvRegLinkSpeed);
3404 pci_push(base);
3405
3406 pause_flags = 0;
3407 /* setup pause frame */
3408 if (np->duplex != 0) {
3409 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3410 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3411 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3412
3413 switch (adv_pause) {
3414 case ADVERTISE_PAUSE_CAP:
3415 if (lpa_pause & LPA_PAUSE_CAP) {
3416 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3417 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3418 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3419 }
3420 break;
3421 case ADVERTISE_PAUSE_ASYM:
3422 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3423 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3424 break;
3425 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3426 if (lpa_pause & LPA_PAUSE_CAP) {
3427 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3428 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3429 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3430 }
3431 if (lpa_pause == LPA_PAUSE_ASYM)
3432 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3433 break;
3434 }
3435 } else {
3436 pause_flags = np->pause_flags;
3437 }
3438 }
3439 nv_update_pause(dev, pause_flags);
3440
3441 if (txrxFlags & NV_RESTART_TX)
3442 nv_start_tx(dev);
3443 if (txrxFlags & NV_RESTART_RX)
3444 nv_start_rx(dev);
3445
3446 return retval;
3447 }
3448
3449 static void nv_linkchange(struct net_device *dev)
3450 {
3451 if (nv_update_linkspeed(dev)) {
3452 if (!netif_carrier_ok(dev)) {
3453 netif_carrier_on(dev);
3454 netdev_info(dev, "link up\n");
3455 nv_txrx_gate(dev, false);
3456 nv_start_rx(dev);
3457 }
3458 } else {
3459 if (netif_carrier_ok(dev)) {
3460 netif_carrier_off(dev);
3461 netdev_info(dev, "link down\n");
3462 nv_txrx_gate(dev, true);
3463 nv_stop_rx(dev);
3464 }
3465 }
3466 }
3467
3468 static void nv_link_irq(struct net_device *dev)
3469 {
3470 u8 __iomem *base = get_hwbase(dev);
3471 u32 miistat;
3472
3473 miistat = readl(base + NvRegMIIStatus);
3474 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3475
3476 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3477 nv_linkchange(dev);
3478 }
3479
3480 static void nv_msi_workaround(struct fe_priv *np)
3481 {
3482
3483 /* Need to toggle the msi irq mask within the ethernet device,
3484 * otherwise, future interrupts will not be detected.
3485 */
3486 if (np->msi_flags & NV_MSI_ENABLED) {
3487 u8 __iomem *base = np->base;
3488
3489 writel(0, base + NvRegMSIIrqMask);
3490 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3491 }
3492 }
3493
3494 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3495 {
3496 struct fe_priv *np = netdev_priv(dev);
3497
3498 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3499 if (total_work > NV_DYNAMIC_THRESHOLD) {
3500 /* transition to poll based interrupts */
3501 np->quiet_count = 0;
3502 if (np->irqmask != NVREG_IRQMASK_CPU) {
3503 np->irqmask = NVREG_IRQMASK_CPU;
3504 return 1;
3505 }
3506 } else {
3507 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3508 np->quiet_count++;
3509 } else {
3510 /* reached a period of low activity, switch
3511 to per tx/rx packet interrupts */
3512 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3513 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3514 return 1;
3515 }
3516 }
3517 }
3518 }
3519 return 0;
3520 }
3521
3522 static irqreturn_t nv_nic_irq(int foo, void *data)
3523 {
3524 struct net_device *dev = (struct net_device *) data;
3525 struct fe_priv *np = netdev_priv(dev);
3526 u8 __iomem *base = get_hwbase(dev);
3527
3528 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3529 np->events = readl(base + NvRegIrqStatus);
3530 writel(np->events, base + NvRegIrqStatus);
3531 } else {
3532 np->events = readl(base + NvRegMSIXIrqStatus);
3533 writel(np->events, base + NvRegMSIXIrqStatus);
3534 }
3535 if (!(np->events & np->irqmask))
3536 return IRQ_NONE;
3537
3538 nv_msi_workaround(np);
3539
3540 if (napi_schedule_prep(&np->napi)) {
3541 /*
3542 * Disable further irq's (msix not enabled with napi)
3543 */
3544 writel(0, base + NvRegIrqMask);
3545 __napi_schedule(&np->napi);
3546 }
3547
3548 return IRQ_HANDLED;
3549 }
3550
3551 /**
3552 * All _optimized functions are used to help increase performance
3553 * (reduce CPU and increase throughput). They use descripter version 3,
3554 * compiler directives, and reduce memory accesses.
3555 */
3556 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3557 {
3558 struct net_device *dev = (struct net_device *) data;
3559 struct fe_priv *np = netdev_priv(dev);
3560 u8 __iomem *base = get_hwbase(dev);
3561
3562 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3563 np->events = readl(base + NvRegIrqStatus);
3564 writel(np->events, base + NvRegIrqStatus);
3565 } else {
3566 np->events = readl(base + NvRegMSIXIrqStatus);
3567 writel(np->events, base + NvRegMSIXIrqStatus);
3568 }
3569 if (!(np->events & np->irqmask))
3570 return IRQ_NONE;
3571
3572 nv_msi_workaround(np);
3573
3574 if (napi_schedule_prep(&np->napi)) {
3575 /*
3576 * Disable further irq's (msix not enabled with napi)
3577 */
3578 writel(0, base + NvRegIrqMask);
3579 __napi_schedule(&np->napi);
3580 }
3581
3582 return IRQ_HANDLED;
3583 }
3584
3585 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3586 {
3587 struct net_device *dev = (struct net_device *) data;
3588 struct fe_priv *np = netdev_priv(dev);
3589 u8 __iomem *base = get_hwbase(dev);
3590 u32 events;
3591 int i;
3592 unsigned long flags;
3593
3594 for (i = 0;; i++) {
3595 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3596 writel(events, base + NvRegMSIXIrqStatus);
3597 netdev_dbg(dev, "tx irq events: %08x\n", events);
3598 if (!(events & np->irqmask))
3599 break;
3600
3601 spin_lock_irqsave(&np->lock, flags);
3602 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3603 spin_unlock_irqrestore(&np->lock, flags);
3604
3605 if (unlikely(i > max_interrupt_work)) {
3606 spin_lock_irqsave(&np->lock, flags);
3607 /* disable interrupts on the nic */
3608 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3609 pci_push(base);
3610
3611 if (!np->in_shutdown) {
3612 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3613 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3614 }
3615 spin_unlock_irqrestore(&np->lock, flags);
3616 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3617 __func__, i);
3618 break;
3619 }
3620
3621 }
3622
3623 return IRQ_RETVAL(i);
3624 }
3625
3626 static int nv_napi_poll(struct napi_struct *napi, int budget)
3627 {
3628 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3629 struct net_device *dev = np->dev;
3630 u8 __iomem *base = get_hwbase(dev);
3631 unsigned long flags;
3632 int retcode;
3633 int rx_count, tx_work = 0, rx_work = 0;
3634
3635 do {
3636 if (!nv_optimized(np)) {
3637 spin_lock_irqsave(&np->lock, flags);
3638 tx_work += nv_tx_done(dev, np->tx_ring_size);
3639 spin_unlock_irqrestore(&np->lock, flags);
3640
3641 rx_count = nv_rx_process(dev, budget - rx_work);
3642 retcode = nv_alloc_rx(dev);
3643 } else {
3644 spin_lock_irqsave(&np->lock, flags);
3645 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3646 spin_unlock_irqrestore(&np->lock, flags);
3647
3648 rx_count = nv_rx_process_optimized(dev,
3649 budget - rx_work);
3650 retcode = nv_alloc_rx_optimized(dev);
3651 }
3652 } while (retcode == 0 &&
3653 rx_count > 0 && (rx_work += rx_count) < budget);
3654
3655 if (retcode) {
3656 spin_lock_irqsave(&np->lock, flags);
3657 if (!np->in_shutdown)
3658 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3659 spin_unlock_irqrestore(&np->lock, flags);
3660 }
3661
3662 nv_change_interrupt_mode(dev, tx_work + rx_work);
3663
3664 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3665 spin_lock_irqsave(&np->lock, flags);
3666 nv_link_irq(dev);
3667 spin_unlock_irqrestore(&np->lock, flags);
3668 }
3669 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3670 spin_lock_irqsave(&np->lock, flags);
3671 nv_linkchange(dev);
3672 spin_unlock_irqrestore(&np->lock, flags);
3673 np->link_timeout = jiffies + LINK_TIMEOUT;
3674 }
3675 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3676 spin_lock_irqsave(&np->lock, flags);
3677 if (!np->in_shutdown) {
3678 np->nic_poll_irq = np->irqmask;
3679 np->recover_error = 1;
3680 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3681 }
3682 spin_unlock_irqrestore(&np->lock, flags);
3683 napi_complete(napi);
3684 return rx_work;
3685 }
3686
3687 if (rx_work < budget) {
3688 /* re-enable interrupts
3689 (msix not enabled in napi) */
3690 napi_complete(napi);
3691
3692 writel(np->irqmask, base + NvRegIrqMask);
3693 }
3694 return rx_work;
3695 }
3696
3697 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3698 {
3699 struct net_device *dev = (struct net_device *) data;
3700 struct fe_priv *np = netdev_priv(dev);
3701 u8 __iomem *base = get_hwbase(dev);
3702 u32 events;
3703 int i;
3704 unsigned long flags;
3705
3706 for (i = 0;; i++) {
3707 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3708 writel(events, base + NvRegMSIXIrqStatus);
3709 netdev_dbg(dev, "rx irq events: %08x\n", events);
3710 if (!(events & np->irqmask))
3711 break;
3712
3713 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3714 if (unlikely(nv_alloc_rx_optimized(dev))) {
3715 spin_lock_irqsave(&np->lock, flags);
3716 if (!np->in_shutdown)
3717 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3718 spin_unlock_irqrestore(&np->lock, flags);
3719 }
3720 }
3721
3722 if (unlikely(i > max_interrupt_work)) {
3723 spin_lock_irqsave(&np->lock, flags);
3724 /* disable interrupts on the nic */
3725 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3726 pci_push(base);
3727
3728 if (!np->in_shutdown) {
3729 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3730 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3731 }
3732 spin_unlock_irqrestore(&np->lock, flags);
3733 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3734 __func__, i);
3735 break;
3736 }
3737 }
3738
3739 return IRQ_RETVAL(i);
3740 }
3741
3742 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3743 {
3744 struct net_device *dev = (struct net_device *) data;
3745 struct fe_priv *np = netdev_priv(dev);
3746 u8 __iomem *base = get_hwbase(dev);
3747 u32 events;
3748 int i;
3749 unsigned long flags;
3750
3751 for (i = 0;; i++) {
3752 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3753 writel(events, base + NvRegMSIXIrqStatus);
3754 netdev_dbg(dev, "irq events: %08x\n", events);
3755 if (!(events & np->irqmask))
3756 break;
3757
3758 /* check tx in case we reached max loop limit in tx isr */
3759 spin_lock_irqsave(&np->lock, flags);
3760 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3761 spin_unlock_irqrestore(&np->lock, flags);
3762
3763 if (events & NVREG_IRQ_LINK) {
3764 spin_lock_irqsave(&np->lock, flags);
3765 nv_link_irq(dev);
3766 spin_unlock_irqrestore(&np->lock, flags);
3767 }
3768 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3769 spin_lock_irqsave(&np->lock, flags);
3770 nv_linkchange(dev);
3771 spin_unlock_irqrestore(&np->lock, flags);
3772 np->link_timeout = jiffies + LINK_TIMEOUT;
3773 }
3774 if (events & NVREG_IRQ_RECOVER_ERROR) {
3775 spin_lock_irq(&np->lock);
3776 /* disable interrupts on the nic */
3777 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3778 pci_push(base);
3779
3780 if (!np->in_shutdown) {
3781 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3782 np->recover_error = 1;
3783 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3784 }
3785 spin_unlock_irq(&np->lock);
3786 break;
3787 }
3788 if (unlikely(i > max_interrupt_work)) {
3789 spin_lock_irqsave(&np->lock, flags);
3790 /* disable interrupts on the nic */
3791 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3792 pci_push(base);
3793
3794 if (!np->in_shutdown) {
3795 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3796 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3797 }
3798 spin_unlock_irqrestore(&np->lock, flags);
3799 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3800 __func__, i);
3801 break;
3802 }
3803
3804 }
3805
3806 return IRQ_RETVAL(i);
3807 }
3808
3809 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3810 {
3811 struct net_device *dev = (struct net_device *) data;
3812 struct fe_priv *np = netdev_priv(dev);
3813 u8 __iomem *base = get_hwbase(dev);
3814 u32 events;
3815
3816 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3817 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3818 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3819 } else {
3820 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3821 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3822 }
3823 pci_push(base);
3824 if (!(events & NVREG_IRQ_TIMER))
3825 return IRQ_RETVAL(0);
3826
3827 nv_msi_workaround(np);
3828
3829 spin_lock(&np->lock);
3830 np->intr_test = 1;
3831 spin_unlock(&np->lock);
3832
3833 return IRQ_RETVAL(1);
3834 }
3835
3836 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3837 {
3838 u8 __iomem *base = get_hwbase(dev);
3839 int i;
3840 u32 msixmap = 0;
3841
3842 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3843 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3844 * the remaining 8 interrupts.
3845 */
3846 for (i = 0; i < 8; i++) {
3847 if ((irqmask >> i) & 0x1)
3848 msixmap |= vector << (i << 2);
3849 }
3850 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3851
3852 msixmap = 0;
3853 for (i = 0; i < 8; i++) {
3854 if ((irqmask >> (i + 8)) & 0x1)
3855 msixmap |= vector << (i << 2);
3856 }
3857 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3858 }
3859
3860 static int nv_request_irq(struct net_device *dev, int intr_test)
3861 {
3862 struct fe_priv *np = get_nvpriv(dev);
3863 u8 __iomem *base = get_hwbase(dev);
3864 int ret = 1;
3865 int i;
3866 irqreturn_t (*handler)(int foo, void *data);
3867
3868 if (intr_test) {
3869 handler = nv_nic_irq_test;
3870 } else {
3871 if (nv_optimized(np))
3872 handler = nv_nic_irq_optimized;
3873 else
3874 handler = nv_nic_irq;
3875 }
3876
3877 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3878 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3879 np->msi_x_entry[i].entry = i;
3880 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3881 if (ret == 0) {
3882 np->msi_flags |= NV_MSI_X_ENABLED;
3883 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3884 /* Request irq for rx handling */
3885 sprintf(np->name_rx, "%s-rx", dev->name);
3886 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3887 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3888 netdev_info(dev,
3889 "request_irq failed for rx %d\n",
3890 ret);
3891 pci_disable_msix(np->pci_dev);
3892 np->msi_flags &= ~NV_MSI_X_ENABLED;
3893 goto out_err;
3894 }
3895 /* Request irq for tx handling */
3896 sprintf(np->name_tx, "%s-tx", dev->name);
3897 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3898 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3899 netdev_info(dev,
3900 "request_irq failed for tx %d\n",
3901 ret);
3902 pci_disable_msix(np->pci_dev);
3903 np->msi_flags &= ~NV_MSI_X_ENABLED;
3904 goto out_free_rx;
3905 }
3906 /* Request irq for link and timer handling */
3907 sprintf(np->name_other, "%s-other", dev->name);
3908 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3909 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3910 netdev_info(dev,
3911 "request_irq failed for link %d\n",
3912 ret);
3913 pci_disable_msix(np->pci_dev);
3914 np->msi_flags &= ~NV_MSI_X_ENABLED;
3915 goto out_free_tx;
3916 }
3917 /* map interrupts to their respective vector */
3918 writel(0, base + NvRegMSIXMap0);
3919 writel(0, base + NvRegMSIXMap1);
3920 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3921 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3922 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3923 } else {
3924 /* Request irq for all interrupts */
3925 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3926 netdev_info(dev,
3927 "request_irq failed %d\n",
3928 ret);
3929 pci_disable_msix(np->pci_dev);
3930 np->msi_flags &= ~NV_MSI_X_ENABLED;
3931 goto out_err;
3932 }
3933
3934 /* map interrupts to vector 0 */
3935 writel(0, base + NvRegMSIXMap0);
3936 writel(0, base + NvRegMSIXMap1);
3937 }
3938 netdev_info(dev, "MSI-X enabled\n");
3939 }
3940 }
3941 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3942 ret = pci_enable_msi(np->pci_dev);
3943 if (ret == 0) {
3944 np->msi_flags |= NV_MSI_ENABLED;
3945 dev->irq = np->pci_dev->irq;
3946 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3947 netdev_info(dev, "request_irq failed %d\n",
3948 ret);
3949 pci_disable_msi(np->pci_dev);
3950 np->msi_flags &= ~NV_MSI_ENABLED;
3951 dev->irq = np->pci_dev->irq;
3952 goto out_err;
3953 }
3954
3955 /* map interrupts to vector 0 */
3956 writel(0, base + NvRegMSIMap0);
3957 writel(0, base + NvRegMSIMap1);
3958 /* enable msi vector 0 */
3959 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3960 netdev_info(dev, "MSI enabled\n");
3961 }
3962 }
3963 if (ret != 0) {
3964 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3965 goto out_err;
3966
3967 }
3968
3969 return 0;
3970 out_free_tx:
3971 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3972 out_free_rx:
3973 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3974 out_err:
3975 return 1;
3976 }
3977
3978 static void nv_free_irq(struct net_device *dev)
3979 {
3980 struct fe_priv *np = get_nvpriv(dev);
3981 int i;
3982
3983 if (np->msi_flags & NV_MSI_X_ENABLED) {
3984 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3985 free_irq(np->msi_x_entry[i].vector, dev);
3986 pci_disable_msix(np->pci_dev);
3987 np->msi_flags &= ~NV_MSI_X_ENABLED;
3988 } else {
3989 free_irq(np->pci_dev->irq, dev);
3990 if (np->msi_flags & NV_MSI_ENABLED) {
3991 pci_disable_msi(np->pci_dev);
3992 np->msi_flags &= ~NV_MSI_ENABLED;
3993 }
3994 }
3995 }
3996
3997 static void nv_do_nic_poll(unsigned long data)
3998 {
3999 struct net_device *dev = (struct net_device *) data;
4000 struct fe_priv *np = netdev_priv(dev);
4001 u8 __iomem *base = get_hwbase(dev);
4002 u32 mask = 0;
4003
4004 /*
4005 * First disable irq(s) and then
4006 * reenable interrupts on the nic, we have to do this before calling
4007 * nv_nic_irq because that may decide to do otherwise
4008 */
4009
4010 if (!using_multi_irqs(dev)) {
4011 if (np->msi_flags & NV_MSI_X_ENABLED)
4012 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4013 else
4014 disable_irq_lockdep(np->pci_dev->irq);
4015 mask = np->irqmask;
4016 } else {
4017 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4018 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4019 mask |= NVREG_IRQ_RX_ALL;
4020 }
4021 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4022 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4023 mask |= NVREG_IRQ_TX_ALL;
4024 }
4025 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4026 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4027 mask |= NVREG_IRQ_OTHER;
4028 }
4029 }
4030 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4031
4032 if (np->recover_error) {
4033 np->recover_error = 0;
4034 netdev_info(dev, "MAC in recoverable error state\n");
4035 if (netif_running(dev)) {
4036 netif_tx_lock_bh(dev);
4037 netif_addr_lock(dev);
4038 spin_lock(&np->lock);
4039 /* stop engines */
4040 nv_stop_rxtx(dev);
4041 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4042 nv_mac_reset(dev);
4043 nv_txrx_reset(dev);
4044 /* drain rx queue */
4045 nv_drain_rxtx(dev);
4046 /* reinit driver view of the rx queue */
4047 set_bufsize(dev);
4048 if (nv_init_ring(dev)) {
4049 if (!np->in_shutdown)
4050 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4051 }
4052 /* reinit nic view of the rx queue */
4053 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4054 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4055 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4056 base + NvRegRingSizes);
4057 pci_push(base);
4058 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4059 pci_push(base);
4060 /* clear interrupts */
4061 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4062 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4063 else
4064 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4065
4066 /* restart rx engine */
4067 nv_start_rxtx(dev);
4068 spin_unlock(&np->lock);
4069 netif_addr_unlock(dev);
4070 netif_tx_unlock_bh(dev);
4071 }
4072 }
4073
4074 writel(mask, base + NvRegIrqMask);
4075 pci_push(base);
4076
4077 if (!using_multi_irqs(dev)) {
4078 np->nic_poll_irq = 0;
4079 if (nv_optimized(np))
4080 nv_nic_irq_optimized(0, dev);
4081 else
4082 nv_nic_irq(0, dev);
4083 if (np->msi_flags & NV_MSI_X_ENABLED)
4084 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4085 else
4086 enable_irq_lockdep(np->pci_dev->irq);
4087 } else {
4088 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4089 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4090 nv_nic_irq_rx(0, dev);
4091 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4092 }
4093 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4094 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4095 nv_nic_irq_tx(0, dev);
4096 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4097 }
4098 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4099 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4100 nv_nic_irq_other(0, dev);
4101 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4102 }
4103 }
4104
4105 }
4106
4107 #ifdef CONFIG_NET_POLL_CONTROLLER
4108 static void nv_poll_controller(struct net_device *dev)
4109 {
4110 nv_do_nic_poll((unsigned long) dev);
4111 }
4112 #endif
4113
4114 static void nv_do_stats_poll(unsigned long data)
4115 __acquires(&netdev_priv(dev)->hwstats_lock)
4116 __releases(&netdev_priv(dev)->hwstats_lock)
4117 {
4118 struct net_device *dev = (struct net_device *) data;
4119 struct fe_priv *np = netdev_priv(dev);
4120
4121 /* If lock is currently taken, the stats are being refreshed
4122 * and hence fresh enough */
4123 if (spin_trylock(&np->hwstats_lock)) {
4124 nv_update_stats(dev);
4125 spin_unlock(&np->hwstats_lock);
4126 }
4127
4128 if (!np->in_shutdown)
4129 mod_timer(&np->stats_poll,
4130 round_jiffies(jiffies + STATS_INTERVAL));
4131 }
4132
4133 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4134 {
4135 struct fe_priv *np = netdev_priv(dev);
4136 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4137 strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4138 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4139 }
4140
4141 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4142 {
4143 struct fe_priv *np = netdev_priv(dev);
4144 wolinfo->supported = WAKE_MAGIC;
4145
4146 spin_lock_irq(&np->lock);
4147 if (np->wolenabled)
4148 wolinfo->wolopts = WAKE_MAGIC;
4149 spin_unlock_irq(&np->lock);
4150 }
4151
4152 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4153 {
4154 struct fe_priv *np = netdev_priv(dev);
4155 u8 __iomem *base = get_hwbase(dev);
4156 u32 flags = 0;
4157
4158 if (wolinfo->wolopts == 0) {
4159 np->wolenabled = 0;
4160 } else if (wolinfo->wolopts & WAKE_MAGIC) {
4161 np->wolenabled = 1;
4162 flags = NVREG_WAKEUPFLAGS_ENABLE;
4163 }
4164 if (netif_running(dev)) {
4165 spin_lock_irq(&np->lock);
4166 writel(flags, base + NvRegWakeUpFlags);
4167 spin_unlock_irq(&np->lock);
4168 }
4169 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4170 return 0;
4171 }
4172
4173 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4174 {
4175 struct fe_priv *np = netdev_priv(dev);
4176 u32 speed;
4177 int adv;
4178
4179 spin_lock_irq(&np->lock);
4180 ecmd->port = PORT_MII;
4181 if (!netif_running(dev)) {
4182 /* We do not track link speed / duplex setting if the
4183 * interface is disabled. Force a link check */
4184 if (nv_update_linkspeed(dev)) {
4185 if (!netif_carrier_ok(dev))
4186 netif_carrier_on(dev);
4187 } else {
4188 if (netif_carrier_ok(dev))
4189 netif_carrier_off(dev);
4190 }
4191 }
4192
4193 if (netif_carrier_ok(dev)) {
4194 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4195 case NVREG_LINKSPEED_10:
4196 speed = SPEED_10;
4197 break;
4198 case NVREG_LINKSPEED_100:
4199 speed = SPEED_100;
4200 break;
4201 case NVREG_LINKSPEED_1000:
4202 speed = SPEED_1000;
4203 break;
4204 default:
4205 speed = -1;
4206 break;
4207 }
4208 ecmd->duplex = DUPLEX_HALF;
4209 if (np->duplex)
4210 ecmd->duplex = DUPLEX_FULL;
4211 } else {
4212 speed = -1;
4213 ecmd->duplex = -1;
4214 }
4215 ethtool_cmd_speed_set(ecmd, speed);
4216 ecmd->autoneg = np->autoneg;
4217
4218 ecmd->advertising = ADVERTISED_MII;
4219 if (np->autoneg) {
4220 ecmd->advertising |= ADVERTISED_Autoneg;
4221 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4222 if (adv & ADVERTISE_10HALF)
4223 ecmd->advertising |= ADVERTISED_10baseT_Half;
4224 if (adv & ADVERTISE_10FULL)
4225 ecmd->advertising |= ADVERTISED_10baseT_Full;
4226 if (adv & ADVERTISE_100HALF)
4227 ecmd->advertising |= ADVERTISED_100baseT_Half;
4228 if (adv & ADVERTISE_100FULL)
4229 ecmd->advertising |= ADVERTISED_100baseT_Full;
4230 if (np->gigabit == PHY_GIGABIT) {
4231 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4232 if (adv & ADVERTISE_1000FULL)
4233 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4234 }
4235 }
4236 ecmd->supported = (SUPPORTED_Autoneg |
4237 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4238 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4239 SUPPORTED_MII);
4240 if (np->gigabit == PHY_GIGABIT)
4241 ecmd->supported |= SUPPORTED_1000baseT_Full;
4242
4243 ecmd->phy_address = np->phyaddr;
4244 ecmd->transceiver = XCVR_EXTERNAL;
4245
4246 /* ignore maxtxpkt, maxrxpkt for now */
4247 spin_unlock_irq(&np->lock);
4248 return 0;
4249 }
4250
4251 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4252 {
4253 struct fe_priv *np = netdev_priv(dev);
4254 u32 speed = ethtool_cmd_speed(ecmd);
4255
4256 if (ecmd->port != PORT_MII)
4257 return -EINVAL;
4258 if (ecmd->transceiver != XCVR_EXTERNAL)
4259 return -EINVAL;
4260 if (ecmd->phy_address != np->phyaddr) {
4261 /* TODO: support switching between multiple phys. Should be
4262 * trivial, but not enabled due to lack of test hardware. */
4263 return -EINVAL;
4264 }
4265 if (ecmd->autoneg == AUTONEG_ENABLE) {
4266 u32 mask;
4267
4268 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4269 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4270 if (np->gigabit == PHY_GIGABIT)
4271 mask |= ADVERTISED_1000baseT_Full;
4272
4273 if ((ecmd->advertising & mask) == 0)
4274 return -EINVAL;
4275
4276 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4277 /* Note: autonegotiation disable, speed 1000 intentionally
4278 * forbidden - no one should need that. */
4279
4280 if (speed != SPEED_10 && speed != SPEED_100)
4281 return -EINVAL;
4282 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4283 return -EINVAL;
4284 } else {
4285 return -EINVAL;
4286 }
4287
4288 netif_carrier_off(dev);
4289 if (netif_running(dev)) {
4290 unsigned long flags;
4291
4292 nv_disable_irq(dev);
4293 netif_tx_lock_bh(dev);
4294 netif_addr_lock(dev);
4295 /* with plain spinlock lockdep complains */
4296 spin_lock_irqsave(&np->lock, flags);
4297 /* stop engines */
4298 /* FIXME:
4299 * this can take some time, and interrupts are disabled
4300 * due to spin_lock_irqsave, but let's hope no daemon
4301 * is going to change the settings very often...
4302 * Worst case:
4303 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4304 * + some minor delays, which is up to a second approximately
4305 */
4306 nv_stop_rxtx(dev);
4307 spin_unlock_irqrestore(&np->lock, flags);
4308 netif_addr_unlock(dev);
4309 netif_tx_unlock_bh(dev);
4310 }
4311
4312 if (ecmd->autoneg == AUTONEG_ENABLE) {
4313 int adv, bmcr;
4314
4315 np->autoneg = 1;
4316
4317 /* advertise only what has been requested */
4318 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4319 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4320 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4321 adv |= ADVERTISE_10HALF;
4322 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4323 adv |= ADVERTISE_10FULL;
4324 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4325 adv |= ADVERTISE_100HALF;
4326 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4327 adv |= ADVERTISE_100FULL;
4328 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4329 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4330 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4331 adv |= ADVERTISE_PAUSE_ASYM;
4332 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4333
4334 if (np->gigabit == PHY_GIGABIT) {
4335 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4336 adv &= ~ADVERTISE_1000FULL;
4337 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4338 adv |= ADVERTISE_1000FULL;
4339 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4340 }
4341
4342 if (netif_running(dev))
4343 netdev_info(dev, "link down\n");
4344 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4345 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4346 bmcr |= BMCR_ANENABLE;
4347 /* reset the phy in order for settings to stick,
4348 * and cause autoneg to start */
4349 if (phy_reset(dev, bmcr)) {
4350 netdev_info(dev, "phy reset failed\n");
4351 return -EINVAL;
4352 }
4353 } else {
4354 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4355 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4356 }
4357 } else {
4358 int adv, bmcr;
4359
4360 np->autoneg = 0;
4361
4362 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4363 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4364 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4365 adv |= ADVERTISE_10HALF;
4366 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4367 adv |= ADVERTISE_10FULL;
4368 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4369 adv |= ADVERTISE_100HALF;
4370 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4371 adv |= ADVERTISE_100FULL;
4372 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4373 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4374 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4375 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4376 }
4377 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4378 adv |= ADVERTISE_PAUSE_ASYM;
4379 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4380 }
4381 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4382 np->fixed_mode = adv;
4383
4384 if (np->gigabit == PHY_GIGABIT) {
4385 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4386 adv &= ~ADVERTISE_1000FULL;
4387 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4388 }
4389
4390 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4391 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4392 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4393 bmcr |= BMCR_FULLDPLX;
4394 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4395 bmcr |= BMCR_SPEED100;
4396 if (np->phy_oui == PHY_OUI_MARVELL) {
4397 /* reset the phy in order for forced mode settings to stick */
4398 if (phy_reset(dev, bmcr)) {
4399 netdev_info(dev, "phy reset failed\n");
4400 return -EINVAL;
4401 }
4402 } else {
4403 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4404 if (netif_running(dev)) {
4405 /* Wait a bit and then reconfigure the nic. */
4406 udelay(10);
4407 nv_linkchange(dev);
4408 }
4409 }
4410 }
4411
4412 if (netif_running(dev)) {
4413 nv_start_rxtx(dev);
4414 nv_enable_irq(dev);
4415 }
4416
4417 return 0;
4418 }
4419
4420 #define FORCEDETH_REGS_VER 1
4421
4422 static int nv_get_regs_len(struct net_device *dev)
4423 {
4424 struct fe_priv *np = netdev_priv(dev);
4425 return np->register_size;
4426 }
4427
4428 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4429 {
4430 struct fe_priv *np = netdev_priv(dev);
4431 u8 __iomem *base = get_hwbase(dev);
4432 u32 *rbuf = buf;
4433 int i;
4434
4435 regs->version = FORCEDETH_REGS_VER;
4436 spin_lock_irq(&np->lock);
4437 for (i = 0; i <= np->register_size/sizeof(u32); i++)
4438 rbuf[i] = readl(base + i*sizeof(u32));
4439 spin_unlock_irq(&np->lock);
4440 }
4441
4442 static int nv_nway_reset(struct net_device *dev)
4443 {
4444 struct fe_priv *np = netdev_priv(dev);
4445 int ret;
4446
4447 if (np->autoneg) {
4448 int bmcr;
4449
4450 netif_carrier_off(dev);
4451 if (netif_running(dev)) {
4452 nv_disable_irq(dev);
4453 netif_tx_lock_bh(dev);
4454 netif_addr_lock(dev);
4455 spin_lock(&np->lock);
4456 /* stop engines */
4457 nv_stop_rxtx(dev);
4458 spin_unlock(&np->lock);
4459 netif_addr_unlock(dev);
4460 netif_tx_unlock_bh(dev);
4461 netdev_info(dev, "link down\n");
4462 }
4463
4464 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4465 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4466 bmcr |= BMCR_ANENABLE;
4467 /* reset the phy in order for settings to stick*/
4468 if (phy_reset(dev, bmcr)) {
4469 netdev_info(dev, "phy reset failed\n");
4470 return -EINVAL;
4471 }
4472 } else {
4473 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4474 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4475 }
4476
4477 if (netif_running(dev)) {
4478 nv_start_rxtx(dev);
4479 nv_enable_irq(dev);
4480 }
4481 ret = 0;
4482 } else {
4483 ret = -EINVAL;
4484 }
4485
4486 return ret;
4487 }
4488
4489 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4490 {
4491 struct fe_priv *np = netdev_priv(dev);
4492
4493 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4494 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4495
4496 ring->rx_pending = np->rx_ring_size;
4497 ring->tx_pending = np->tx_ring_size;
4498 }
4499
4500 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4501 {
4502 struct fe_priv *np = netdev_priv(dev);
4503 u8 __iomem *base = get_hwbase(dev);
4504 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4505 dma_addr_t ring_addr;
4506
4507 if (ring->rx_pending < RX_RING_MIN ||
4508 ring->tx_pending < TX_RING_MIN ||
4509 ring->rx_mini_pending != 0 ||
4510 ring->rx_jumbo_pending != 0 ||
4511 (np->desc_ver == DESC_VER_1 &&
4512 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4513 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4514 (np->desc_ver != DESC_VER_1 &&
4515 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4516 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4517 return -EINVAL;
4518 }
4519
4520 /* allocate new rings */
4521 if (!nv_optimized(np)) {
4522 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4523 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4524 &ring_addr);
4525 } else {
4526 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4527 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4528 &ring_addr);
4529 }
4530 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4531 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4532 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4533 /* fall back to old rings */
4534 if (!nv_optimized(np)) {
4535 if (rxtx_ring)
4536 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4537 rxtx_ring, ring_addr);
4538 } else {
4539 if (rxtx_ring)
4540 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4541 rxtx_ring, ring_addr);
4542 }
4543
4544 kfree(rx_skbuff);
4545 kfree(tx_skbuff);
4546 goto exit;
4547 }
4548
4549 if (netif_running(dev)) {
4550 nv_disable_irq(dev);
4551 nv_napi_disable(dev);
4552 netif_tx_lock_bh(dev);
4553 netif_addr_lock(dev);
4554 spin_lock(&np->lock);
4555 /* stop engines */
4556 nv_stop_rxtx(dev);
4557 nv_txrx_reset(dev);
4558 /* drain queues */
4559 nv_drain_rxtx(dev);
4560 /* delete queues */
4561 free_rings(dev);
4562 }
4563
4564 /* set new values */
4565 np->rx_ring_size = ring->rx_pending;
4566 np->tx_ring_size = ring->tx_pending;
4567
4568 if (!nv_optimized(np)) {
4569 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4570 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4571 } else {
4572 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4573 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4574 }
4575 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4576 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4577 np->ring_addr = ring_addr;
4578
4579 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4580 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4581
4582 if (netif_running(dev)) {
4583 /* reinit driver view of the queues */
4584 set_bufsize(dev);
4585 if (nv_init_ring(dev)) {
4586 if (!np->in_shutdown)
4587 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4588 }
4589
4590 /* reinit nic view of the queues */
4591 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4592 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4593 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4594 base + NvRegRingSizes);
4595 pci_push(base);
4596 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4597 pci_push(base);
4598
4599 /* restart engines */
4600 nv_start_rxtx(dev);
4601 spin_unlock(&np->lock);
4602 netif_addr_unlock(dev);
4603 netif_tx_unlock_bh(dev);
4604 nv_napi_enable(dev);
4605 nv_enable_irq(dev);
4606 }
4607 return 0;
4608 exit:
4609 return -ENOMEM;
4610 }
4611
4612 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4613 {
4614 struct fe_priv *np = netdev_priv(dev);
4615
4616 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4617 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4618 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4619 }
4620
4621 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4622 {
4623 struct fe_priv *np = netdev_priv(dev);
4624 int adv, bmcr;
4625
4626 if ((!np->autoneg && np->duplex == 0) ||
4627 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4628 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4629 return -EINVAL;
4630 }
4631 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4632 netdev_info(dev, "hardware does not support tx pause frames\n");
4633 return -EINVAL;
4634 }
4635
4636 netif_carrier_off(dev);
4637 if (netif_running(dev)) {
4638 nv_disable_irq(dev);
4639 netif_tx_lock_bh(dev);
4640 netif_addr_lock(dev);
4641 spin_lock(&np->lock);
4642 /* stop engines */
4643 nv_stop_rxtx(dev);
4644 spin_unlock(&np->lock);
4645 netif_addr_unlock(dev);
4646 netif_tx_unlock_bh(dev);
4647 }
4648
4649 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4650 if (pause->rx_pause)
4651 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4652 if (pause->tx_pause)
4653 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4654
4655 if (np->autoneg && pause->autoneg) {
4656 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4657
4658 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4659 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4660 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4661 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4662 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4663 adv |= ADVERTISE_PAUSE_ASYM;
4664 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4665
4666 if (netif_running(dev))
4667 netdev_info(dev, "link down\n");
4668 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4669 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4670 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4671 } else {
4672 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4673 if (pause->rx_pause)
4674 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4675 if (pause->tx_pause)
4676 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4677
4678 if (!netif_running(dev))
4679 nv_update_linkspeed(dev);
4680 else
4681 nv_update_pause(dev, np->pause_flags);
4682 }
4683
4684 if (netif_running(dev)) {
4685 nv_start_rxtx(dev);
4686 nv_enable_irq(dev);
4687 }
4688 return 0;
4689 }
4690
4691 static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4692 {
4693 struct fe_priv *np = netdev_priv(dev);
4694 unsigned long flags;
4695 u32 miicontrol;
4696 int err, retval = 0;
4697
4698 spin_lock_irqsave(&np->lock, flags);
4699 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4700 if (features & NETIF_F_LOOPBACK) {
4701 if (miicontrol & BMCR_LOOPBACK) {
4702 spin_unlock_irqrestore(&np->lock, flags);
4703 netdev_info(dev, "Loopback already enabled\n");
4704 return 0;
4705 }
4706 nv_disable_irq(dev);
4707 /* Turn on loopback mode */
4708 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4709 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4710 if (err) {
4711 retval = PHY_ERROR;
4712 spin_unlock_irqrestore(&np->lock, flags);
4713 phy_init(dev);
4714 } else {
4715 if (netif_running(dev)) {
4716 /* Force 1000 Mbps full-duplex */
4717 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4718 1);
4719 /* Force link up */
4720 netif_carrier_on(dev);
4721 }
4722 spin_unlock_irqrestore(&np->lock, flags);
4723 netdev_info(dev,
4724 "Internal PHY loopback mode enabled.\n");
4725 }
4726 } else {
4727 if (!(miicontrol & BMCR_LOOPBACK)) {
4728 spin_unlock_irqrestore(&np->lock, flags);
4729 netdev_info(dev, "Loopback already disabled\n");
4730 return 0;
4731 }
4732 nv_disable_irq(dev);
4733 /* Turn off loopback */
4734 spin_unlock_irqrestore(&np->lock, flags);
4735 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4736 phy_init(dev);
4737 }
4738 msleep(500);
4739 spin_lock_irqsave(&np->lock, flags);
4740 nv_enable_irq(dev);
4741 spin_unlock_irqrestore(&np->lock, flags);
4742
4743 return retval;
4744 }
4745
4746 static netdev_features_t nv_fix_features(struct net_device *dev,
4747 netdev_features_t features)
4748 {
4749 /* vlan is dependent on rx checksum offload */
4750 if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4751 features |= NETIF_F_RXCSUM;
4752
4753 return features;
4754 }
4755
4756 static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4757 {
4758 struct fe_priv *np = get_nvpriv(dev);
4759
4760 spin_lock_irq(&np->lock);
4761
4762 if (features & NETIF_F_HW_VLAN_RX)
4763 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4764 else
4765 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4766
4767 if (features & NETIF_F_HW_VLAN_TX)
4768 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4769 else
4770 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4771
4772 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4773
4774 spin_unlock_irq(&np->lock);
4775 }
4776
4777 static int nv_set_features(struct net_device *dev, netdev_features_t features)
4778 {
4779 struct fe_priv *np = netdev_priv(dev);
4780 u8 __iomem *base = get_hwbase(dev);
4781 netdev_features_t changed = dev->features ^ features;
4782 int retval;
4783
4784 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4785 retval = nv_set_loopback(dev, features);
4786 if (retval != 0)
4787 return retval;
4788 }
4789
4790 if (changed & NETIF_F_RXCSUM) {
4791 spin_lock_irq(&np->lock);
4792
4793 if (features & NETIF_F_RXCSUM)
4794 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4795 else
4796 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4797
4798 if (netif_running(dev))
4799 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4800
4801 spin_unlock_irq(&np->lock);
4802 }
4803
4804 if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
4805 nv_vlan_mode(dev, features);
4806
4807 return 0;
4808 }
4809
4810 static int nv_get_sset_count(struct net_device *dev, int sset)
4811 {
4812 struct fe_priv *np = netdev_priv(dev);
4813
4814 switch (sset) {
4815 case ETH_SS_TEST:
4816 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4817 return NV_TEST_COUNT_EXTENDED;
4818 else
4819 return NV_TEST_COUNT_BASE;
4820 case ETH_SS_STATS:
4821 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4822 return NV_DEV_STATISTICS_V3_COUNT;
4823 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4824 return NV_DEV_STATISTICS_V2_COUNT;
4825 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4826 return NV_DEV_STATISTICS_V1_COUNT;
4827 else
4828 return 0;
4829 default:
4830 return -EOPNOTSUPP;
4831 }
4832 }
4833
4834 static void nv_get_ethtool_stats(struct net_device *dev,
4835 struct ethtool_stats *estats, u64 *buffer)
4836 __acquires(&netdev_priv(dev)->hwstats_lock)
4837 __releases(&netdev_priv(dev)->hwstats_lock)
4838 {
4839 struct fe_priv *np = netdev_priv(dev);
4840
4841 spin_lock_bh(&np->hwstats_lock);
4842 nv_update_stats(dev);
4843 memcpy(buffer, &np->estats,
4844 nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4845 spin_unlock_bh(&np->hwstats_lock);
4846 }
4847
4848 static int nv_link_test(struct net_device *dev)
4849 {
4850 struct fe_priv *np = netdev_priv(dev);
4851 int mii_status;
4852
4853 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4854 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4855
4856 /* check phy link status */
4857 if (!(mii_status & BMSR_LSTATUS))
4858 return 0;
4859 else
4860 return 1;
4861 }
4862
4863 static int nv_register_test(struct net_device *dev)
4864 {
4865 u8 __iomem *base = get_hwbase(dev);
4866 int i = 0;
4867 u32 orig_read, new_read;
4868
4869 do {
4870 orig_read = readl(base + nv_registers_test[i].reg);
4871
4872 /* xor with mask to toggle bits */
4873 orig_read ^= nv_registers_test[i].mask;
4874
4875 writel(orig_read, base + nv_registers_test[i].reg);
4876
4877 new_read = readl(base + nv_registers_test[i].reg);
4878
4879 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4880 return 0;
4881
4882 /* restore original value */
4883 orig_read ^= nv_registers_test[i].mask;
4884 writel(orig_read, base + nv_registers_test[i].reg);
4885
4886 } while (nv_registers_test[++i].reg != 0);
4887
4888 return 1;
4889 }
4890
4891 static int nv_interrupt_test(struct net_device *dev)
4892 {
4893 struct fe_priv *np = netdev_priv(dev);
4894 u8 __iomem *base = get_hwbase(dev);
4895 int ret = 1;
4896 int testcnt;
4897 u32 save_msi_flags, save_poll_interval = 0;
4898
4899 if (netif_running(dev)) {
4900 /* free current irq */
4901 nv_free_irq(dev);
4902 save_poll_interval = readl(base+NvRegPollingInterval);
4903 }
4904
4905 /* flag to test interrupt handler */
4906 np->intr_test = 0;
4907
4908 /* setup test irq */
4909 save_msi_flags = np->msi_flags;
4910 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4911 np->msi_flags |= 0x001; /* setup 1 vector */
4912 if (nv_request_irq(dev, 1))
4913 return 0;
4914
4915 /* setup timer interrupt */
4916 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4917 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4918
4919 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4920
4921 /* wait for at least one interrupt */
4922 msleep(100);
4923
4924 spin_lock_irq(&np->lock);
4925
4926 /* flag should be set within ISR */
4927 testcnt = np->intr_test;
4928 if (!testcnt)
4929 ret = 2;
4930
4931 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4932 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4933 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4934 else
4935 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4936
4937 spin_unlock_irq(&np->lock);
4938
4939 nv_free_irq(dev);
4940
4941 np->msi_flags = save_msi_flags;
4942
4943 if (netif_running(dev)) {
4944 writel(save_poll_interval, base + NvRegPollingInterval);
4945 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4946 /* restore original irq */
4947 if (nv_request_irq(dev, 0))
4948 return 0;
4949 }
4950
4951 return ret;
4952 }
4953
4954 static int nv_loopback_test(struct net_device *dev)
4955 {
4956 struct fe_priv *np = netdev_priv(dev);
4957 u8 __iomem *base = get_hwbase(dev);
4958 struct sk_buff *tx_skb, *rx_skb;
4959 dma_addr_t test_dma_addr;
4960 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4961 u32 flags;
4962 int len, i, pkt_len;
4963 u8 *pkt_data;
4964 u32 filter_flags = 0;
4965 u32 misc1_flags = 0;
4966 int ret = 1;
4967
4968 if (netif_running(dev)) {
4969 nv_disable_irq(dev);
4970 filter_flags = readl(base + NvRegPacketFilterFlags);
4971 misc1_flags = readl(base + NvRegMisc1);
4972 } else {
4973 nv_txrx_reset(dev);
4974 }
4975
4976 /* reinit driver view of the rx queue */
4977 set_bufsize(dev);
4978 nv_init_ring(dev);
4979
4980 /* setup hardware for loopback */
4981 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4982 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4983
4984 /* reinit nic view of the rx queue */
4985 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4986 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4987 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4988 base + NvRegRingSizes);
4989 pci_push(base);
4990
4991 /* restart rx engine */
4992 nv_start_rxtx(dev);
4993
4994 /* setup packet for tx */
4995 pkt_len = ETH_DATA_LEN;
4996 tx_skb = dev_alloc_skb(pkt_len);
4997 if (!tx_skb) {
4998 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4999 ret = 0;
5000 goto out;
5001 }
5002 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5003 skb_tailroom(tx_skb),
5004 PCI_DMA_FROMDEVICE);
5005 pkt_data = skb_put(tx_skb, pkt_len);
5006 for (i = 0; i < pkt_len; i++)
5007 pkt_data[i] = (u8)(i & 0xff);
5008
5009 if (!nv_optimized(np)) {
5010 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5011 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5012 } else {
5013 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5014 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5015 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5016 }
5017 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5018 pci_push(get_hwbase(dev));
5019
5020 msleep(500);
5021
5022 /* check for rx of the packet */
5023 if (!nv_optimized(np)) {
5024 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5025 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5026
5027 } else {
5028 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5029 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5030 }
5031
5032 if (flags & NV_RX_AVAIL) {
5033 ret = 0;
5034 } else if (np->desc_ver == DESC_VER_1) {
5035 if (flags & NV_RX_ERROR)
5036 ret = 0;
5037 } else {
5038 if (flags & NV_RX2_ERROR)
5039 ret = 0;
5040 }
5041
5042 if (ret) {
5043 if (len != pkt_len) {
5044 ret = 0;
5045 } else {
5046 rx_skb = np->rx_skb[0].skb;
5047 for (i = 0; i < pkt_len; i++) {
5048 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5049 ret = 0;
5050 break;
5051 }
5052 }
5053 }
5054 }
5055
5056 pci_unmap_single(np->pci_dev, test_dma_addr,
5057 (skb_end_pointer(tx_skb) - tx_skb->data),
5058 PCI_DMA_TODEVICE);
5059 dev_kfree_skb_any(tx_skb);
5060 out:
5061 /* stop engines */
5062 nv_stop_rxtx(dev);
5063 nv_txrx_reset(dev);
5064 /* drain rx queue */
5065 nv_drain_rxtx(dev);
5066
5067 if (netif_running(dev)) {
5068 writel(misc1_flags, base + NvRegMisc1);
5069 writel(filter_flags, base + NvRegPacketFilterFlags);
5070 nv_enable_irq(dev);
5071 }
5072
5073 return ret;
5074 }
5075
5076 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5077 {
5078 struct fe_priv *np = netdev_priv(dev);
5079 u8 __iomem *base = get_hwbase(dev);
5080 int result;
5081 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5082
5083 if (!nv_link_test(dev)) {
5084 test->flags |= ETH_TEST_FL_FAILED;
5085 buffer[0] = 1;
5086 }
5087
5088 if (test->flags & ETH_TEST_FL_OFFLINE) {
5089 if (netif_running(dev)) {
5090 netif_stop_queue(dev);
5091 nv_napi_disable(dev);
5092 netif_tx_lock_bh(dev);
5093 netif_addr_lock(dev);
5094 spin_lock_irq(&np->lock);
5095 nv_disable_hw_interrupts(dev, np->irqmask);
5096 if (!(np->msi_flags & NV_MSI_X_ENABLED))
5097 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5098 else
5099 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5100 /* stop engines */
5101 nv_stop_rxtx(dev);
5102 nv_txrx_reset(dev);
5103 /* drain rx queue */
5104 nv_drain_rxtx(dev);
5105 spin_unlock_irq(&np->lock);
5106 netif_addr_unlock(dev);
5107 netif_tx_unlock_bh(dev);
5108 }
5109
5110 if (!nv_register_test(dev)) {
5111 test->flags |= ETH_TEST_FL_FAILED;
5112 buffer[1] = 1;
5113 }
5114
5115 result = nv_interrupt_test(dev);
5116 if (result != 1) {
5117 test->flags |= ETH_TEST_FL_FAILED;
5118 buffer[2] = 1;
5119 }
5120 if (result == 0) {
5121 /* bail out */
5122 return;
5123 }
5124
5125 if (!nv_loopback_test(dev)) {
5126 test->flags |= ETH_TEST_FL_FAILED;
5127 buffer[3] = 1;
5128 }
5129
5130 if (netif_running(dev)) {
5131 /* reinit driver view of the rx queue */
5132 set_bufsize(dev);
5133 if (nv_init_ring(dev)) {
5134 if (!np->in_shutdown)
5135 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5136 }
5137 /* reinit nic view of the rx queue */
5138 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5139 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5140 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5141 base + NvRegRingSizes);
5142 pci_push(base);
5143 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5144 pci_push(base);
5145 /* restart rx engine */
5146 nv_start_rxtx(dev);
5147 netif_start_queue(dev);
5148 nv_napi_enable(dev);
5149 nv_enable_hw_interrupts(dev, np->irqmask);
5150 }
5151 }
5152 }
5153
5154 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5155 {
5156 switch (stringset) {
5157 case ETH_SS_STATS:
5158 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5159 break;
5160 case ETH_SS_TEST:
5161 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5162 break;
5163 }
5164 }
5165
5166 static const struct ethtool_ops ops = {
5167 .get_drvinfo = nv_get_drvinfo,
5168 .get_link = ethtool_op_get_link,
5169 .get_wol = nv_get_wol,
5170 .set_wol = nv_set_wol,
5171 .get_settings = nv_get_settings,
5172 .set_settings = nv_set_settings,
5173 .get_regs_len = nv_get_regs_len,
5174 .get_regs = nv_get_regs,
5175 .nway_reset = nv_nway_reset,
5176 .get_ringparam = nv_get_ringparam,
5177 .set_ringparam = nv_set_ringparam,
5178 .get_pauseparam = nv_get_pauseparam,
5179 .set_pauseparam = nv_set_pauseparam,
5180 .get_strings = nv_get_strings,
5181 .get_ethtool_stats = nv_get_ethtool_stats,
5182 .get_sset_count = nv_get_sset_count,
5183 .self_test = nv_self_test,
5184 };
5185
5186 /* The mgmt unit and driver use a semaphore to access the phy during init */
5187 static int nv_mgmt_acquire_sema(struct net_device *dev)
5188 {
5189 struct fe_priv *np = netdev_priv(dev);
5190 u8 __iomem *base = get_hwbase(dev);
5191 int i;
5192 u32 tx_ctrl, mgmt_sema;
5193
5194 for (i = 0; i < 10; i++) {
5195 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5196 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5197 break;
5198 msleep(500);
5199 }
5200
5201 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5202 return 0;
5203
5204 for (i = 0; i < 2; i++) {
5205 tx_ctrl = readl(base + NvRegTransmitterControl);
5206 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5207 writel(tx_ctrl, base + NvRegTransmitterControl);
5208
5209 /* verify that semaphore was acquired */
5210 tx_ctrl = readl(base + NvRegTransmitterControl);
5211 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5212 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5213 np->mgmt_sema = 1;
5214 return 1;
5215 } else
5216 udelay(50);
5217 }
5218
5219 return 0;
5220 }
5221
5222 static void nv_mgmt_release_sema(struct net_device *dev)
5223 {
5224 struct fe_priv *np = netdev_priv(dev);
5225 u8 __iomem *base = get_hwbase(dev);
5226 u32 tx_ctrl;
5227
5228 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5229 if (np->mgmt_sema) {
5230 tx_ctrl = readl(base + NvRegTransmitterControl);
5231 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5232 writel(tx_ctrl, base + NvRegTransmitterControl);
5233 }
5234 }
5235 }
5236
5237
5238 static int nv_mgmt_get_version(struct net_device *dev)
5239 {
5240 struct fe_priv *np = netdev_priv(dev);
5241 u8 __iomem *base = get_hwbase(dev);
5242 u32 data_ready = readl(base + NvRegTransmitterControl);
5243 u32 data_ready2 = 0;
5244 unsigned long start;
5245 int ready = 0;
5246
5247 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5248 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5249 start = jiffies;
5250 while (time_before(jiffies, start + 5*HZ)) {
5251 data_ready2 = readl(base + NvRegTransmitterControl);
5252 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5253 ready = 1;
5254 break;
5255 }
5256 schedule_timeout_uninterruptible(1);
5257 }
5258
5259 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5260 return 0;
5261
5262 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5263
5264 return 1;
5265 }
5266
5267 static int nv_open(struct net_device *dev)
5268 {
5269 struct fe_priv *np = netdev_priv(dev);
5270 u8 __iomem *base = get_hwbase(dev);
5271 int ret = 1;
5272 int oom, i;
5273 u32 low;
5274
5275 /* power up phy */
5276 mii_rw(dev, np->phyaddr, MII_BMCR,
5277 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5278
5279 nv_txrx_gate(dev, false);
5280 /* erase previous misconfiguration */
5281 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5282 nv_mac_reset(dev);
5283 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5284 writel(0, base + NvRegMulticastAddrB);
5285 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5286 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5287 writel(0, base + NvRegPacketFilterFlags);
5288
5289 writel(0, base + NvRegTransmitterControl);
5290 writel(0, base + NvRegReceiverControl);
5291
5292 writel(0, base + NvRegAdapterControl);
5293
5294 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5295 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5296
5297 /* initialize descriptor rings */
5298 set_bufsize(dev);
5299 oom = nv_init_ring(dev);
5300
5301 writel(0, base + NvRegLinkSpeed);
5302 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5303 nv_txrx_reset(dev);
5304 writel(0, base + NvRegUnknownSetupReg6);
5305
5306 np->in_shutdown = 0;
5307
5308 /* give hw rings */
5309 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5310 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5311 base + NvRegRingSizes);
5312
5313 writel(np->linkspeed, base + NvRegLinkSpeed);
5314 if (np->desc_ver == DESC_VER_1)
5315 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5316 else
5317 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5318 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5319 writel(np->vlanctl_bits, base + NvRegVlanControl);
5320 pci_push(base);
5321 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5322 if (reg_delay(dev, NvRegUnknownSetupReg5,
5323 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5324 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5325 netdev_info(dev,
5326 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5327
5328 writel(0, base + NvRegMIIMask);
5329 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5330 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5331
5332 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5333 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5334 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5335 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5336
5337 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5338
5339 get_random_bytes(&low, sizeof(low));
5340 low &= NVREG_SLOTTIME_MASK;
5341 if (np->desc_ver == DESC_VER_1) {
5342 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5343 } else {
5344 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5345 /* setup legacy backoff */
5346 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5347 } else {
5348 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5349 nv_gear_backoff_reseed(dev);
5350 }
5351 }
5352 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5353 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5354 if (poll_interval == -1) {
5355 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5356 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5357 else
5358 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5359 } else
5360 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5361 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5362 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5363 base + NvRegAdapterControl);
5364 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5365 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5366 if (np->wolenabled)
5367 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5368
5369 i = readl(base + NvRegPowerState);
5370 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5371 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5372
5373 pci_push(base);
5374 udelay(10);
5375 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5376
5377 nv_disable_hw_interrupts(dev, np->irqmask);
5378 pci_push(base);
5379 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5380 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5381 pci_push(base);
5382
5383 if (nv_request_irq(dev, 0))
5384 goto out_drain;
5385
5386 /* ask for interrupts */
5387 nv_enable_hw_interrupts(dev, np->irqmask);
5388
5389 spin_lock_irq(&np->lock);
5390 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5391 writel(0, base + NvRegMulticastAddrB);
5392 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5393 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5394 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5395 /* One manual link speed update: Interrupts are enabled, future link
5396 * speed changes cause interrupts and are handled by nv_link_irq().
5397 */
5398 {
5399 u32 miistat;
5400 miistat = readl(base + NvRegMIIStatus);
5401 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5402 }
5403 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5404 * to init hw */
5405 np->linkspeed = 0;
5406 ret = nv_update_linkspeed(dev);
5407 nv_start_rxtx(dev);
5408 netif_start_queue(dev);
5409 nv_napi_enable(dev);
5410
5411 if (ret) {
5412 netif_carrier_on(dev);
5413 } else {
5414 netdev_info(dev, "no link during initialization\n");
5415 netif_carrier_off(dev);
5416 }
5417 if (oom)
5418 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5419
5420 /* start statistics timer */
5421 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5422 mod_timer(&np->stats_poll,
5423 round_jiffies(jiffies + STATS_INTERVAL));
5424
5425 spin_unlock_irq(&np->lock);
5426
5427 /* If the loopback feature was set while the device was down, make sure
5428 * that it's set correctly now.
5429 */
5430 if (dev->features & NETIF_F_LOOPBACK)
5431 nv_set_loopback(dev, dev->features);
5432
5433 return 0;
5434 out_drain:
5435 nv_drain_rxtx(dev);
5436 return ret;
5437 }
5438
5439 static int nv_close(struct net_device *dev)
5440 {
5441 struct fe_priv *np = netdev_priv(dev);
5442 u8 __iomem *base;
5443
5444 spin_lock_irq(&np->lock);
5445 np->in_shutdown = 1;
5446 spin_unlock_irq(&np->lock);
5447 nv_napi_disable(dev);
5448 synchronize_irq(np->pci_dev->irq);
5449
5450 del_timer_sync(&np->oom_kick);
5451 del_timer_sync(&np->nic_poll);
5452 del_timer_sync(&np->stats_poll);
5453
5454 netif_stop_queue(dev);
5455 spin_lock_irq(&np->lock);
5456 nv_stop_rxtx(dev);
5457 nv_txrx_reset(dev);
5458
5459 /* disable interrupts on the nic or we will lock up */
5460 base = get_hwbase(dev);
5461 nv_disable_hw_interrupts(dev, np->irqmask);
5462 pci_push(base);
5463
5464 spin_unlock_irq(&np->lock);
5465
5466 nv_free_irq(dev);
5467
5468 nv_drain_rxtx(dev);
5469
5470 if (np->wolenabled || !phy_power_down) {
5471 nv_txrx_gate(dev, false);
5472 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5473 nv_start_rx(dev);
5474 } else {
5475 /* power down phy */
5476 mii_rw(dev, np->phyaddr, MII_BMCR,
5477 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5478 nv_txrx_gate(dev, true);
5479 }
5480
5481 /* FIXME: power down nic */
5482
5483 return 0;
5484 }
5485
5486 static const struct net_device_ops nv_netdev_ops = {
5487 .ndo_open = nv_open,
5488 .ndo_stop = nv_close,
5489 .ndo_get_stats64 = nv_get_stats64,
5490 .ndo_start_xmit = nv_start_xmit,
5491 .ndo_tx_timeout = nv_tx_timeout,
5492 .ndo_change_mtu = nv_change_mtu,
5493 .ndo_fix_features = nv_fix_features,
5494 .ndo_set_features = nv_set_features,
5495 .ndo_validate_addr = eth_validate_addr,
5496 .ndo_set_mac_address = nv_set_mac_address,
5497 .ndo_set_rx_mode = nv_set_multicast,
5498 #ifdef CONFIG_NET_POLL_CONTROLLER
5499 .ndo_poll_controller = nv_poll_controller,
5500 #endif
5501 };
5502
5503 static const struct net_device_ops nv_netdev_ops_optimized = {
5504 .ndo_open = nv_open,
5505 .ndo_stop = nv_close,
5506 .ndo_get_stats64 = nv_get_stats64,
5507 .ndo_start_xmit = nv_start_xmit_optimized,
5508 .ndo_tx_timeout = nv_tx_timeout,
5509 .ndo_change_mtu = nv_change_mtu,
5510 .ndo_fix_features = nv_fix_features,
5511 .ndo_set_features = nv_set_features,
5512 .ndo_validate_addr = eth_validate_addr,
5513 .ndo_set_mac_address = nv_set_mac_address,
5514 .ndo_set_rx_mode = nv_set_multicast,
5515 #ifdef CONFIG_NET_POLL_CONTROLLER
5516 .ndo_poll_controller = nv_poll_controller,
5517 #endif
5518 };
5519
5520 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5521 {
5522 struct net_device *dev;
5523 struct fe_priv *np;
5524 unsigned long addr;
5525 u8 __iomem *base;
5526 int err, i;
5527 u32 powerstate, txreg;
5528 u32 phystate_orig = 0, phystate;
5529 int phyinitialized = 0;
5530 static int printed_version;
5531
5532 if (!printed_version++)
5533 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5534 FORCEDETH_VERSION);
5535
5536 dev = alloc_etherdev(sizeof(struct fe_priv));
5537 err = -ENOMEM;
5538 if (!dev)
5539 goto out;
5540
5541 np = netdev_priv(dev);
5542 np->dev = dev;
5543 np->pci_dev = pci_dev;
5544 spin_lock_init(&np->lock);
5545 spin_lock_init(&np->hwstats_lock);
5546 SET_NETDEV_DEV(dev, &pci_dev->dev);
5547
5548 init_timer(&np->oom_kick);
5549 np->oom_kick.data = (unsigned long) dev;
5550 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
5551 init_timer(&np->nic_poll);
5552 np->nic_poll.data = (unsigned long) dev;
5553 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5554 init_timer_deferrable(&np->stats_poll);
5555 np->stats_poll.data = (unsigned long) dev;
5556 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
5557
5558 err = pci_enable_device(pci_dev);
5559 if (err)
5560 goto out_free;
5561
5562 pci_set_master(pci_dev);
5563
5564 err = pci_request_regions(pci_dev, DRV_NAME);
5565 if (err < 0)
5566 goto out_disable;
5567
5568 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5569 np->register_size = NV_PCI_REGSZ_VER3;
5570 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5571 np->register_size = NV_PCI_REGSZ_VER2;
5572 else
5573 np->register_size = NV_PCI_REGSZ_VER1;
5574
5575 err = -EINVAL;
5576 addr = 0;
5577 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5578 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5579 pci_resource_len(pci_dev, i) >= np->register_size) {
5580 addr = pci_resource_start(pci_dev, i);
5581 break;
5582 }
5583 }
5584 if (i == DEVICE_COUNT_RESOURCE) {
5585 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5586 goto out_relreg;
5587 }
5588
5589 /* copy of driver data */
5590 np->driver_data = id->driver_data;
5591 /* copy of device id */
5592 np->device_id = id->device;
5593
5594 /* handle different descriptor versions */
5595 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5596 /* packet format 3: supports 40-bit addressing */
5597 np->desc_ver = DESC_VER_3;
5598 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5599 if (dma_64bit) {
5600 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5601 dev_info(&pci_dev->dev,
5602 "64-bit DMA failed, using 32-bit addressing\n");
5603 else
5604 dev->features |= NETIF_F_HIGHDMA;
5605 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5606 dev_info(&pci_dev->dev,
5607 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5608 }
5609 }
5610 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5611 /* packet format 2: supports jumbo frames */
5612 np->desc_ver = DESC_VER_2;
5613 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5614 } else {
5615 /* original packet format */
5616 np->desc_ver = DESC_VER_1;
5617 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5618 }
5619
5620 np->pkt_limit = NV_PKTLIMIT_1;
5621 if (id->driver_data & DEV_HAS_LARGEDESC)
5622 np->pkt_limit = NV_PKTLIMIT_2;
5623
5624 if (id->driver_data & DEV_HAS_CHECKSUM) {
5625 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5626 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5627 NETIF_F_TSO | NETIF_F_RXCSUM;
5628 }
5629
5630 np->vlanctl_bits = 0;
5631 if (id->driver_data & DEV_HAS_VLAN) {
5632 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5633 dev->hw_features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5634 }
5635
5636 dev->features |= dev->hw_features;
5637
5638 /* Add loopback capability to the device. */
5639 dev->hw_features |= NETIF_F_LOOPBACK;
5640
5641 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5642 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5643 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5644 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5645 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5646 }
5647
5648 err = -ENOMEM;
5649 np->base = ioremap(addr, np->register_size);
5650 if (!np->base)
5651 goto out_relreg;
5652 dev->base_addr = (unsigned long)np->base;
5653
5654 dev->irq = pci_dev->irq;
5655
5656 np->rx_ring_size = RX_RING_DEFAULT;
5657 np->tx_ring_size = TX_RING_DEFAULT;
5658
5659 if (!nv_optimized(np)) {
5660 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5661 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5662 &np->ring_addr);
5663 if (!np->rx_ring.orig)
5664 goto out_unmap;
5665 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5666 } else {
5667 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5668 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5669 &np->ring_addr);
5670 if (!np->rx_ring.ex)
5671 goto out_unmap;
5672 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5673 }
5674 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5675 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5676 if (!np->rx_skb || !np->tx_skb)
5677 goto out_freering;
5678
5679 if (!nv_optimized(np))
5680 dev->netdev_ops = &nv_netdev_ops;
5681 else
5682 dev->netdev_ops = &nv_netdev_ops_optimized;
5683
5684 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5685 SET_ETHTOOL_OPS(dev, &ops);
5686 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5687
5688 pci_set_drvdata(pci_dev, dev);
5689
5690 /* read the mac address */
5691 base = get_hwbase(dev);
5692 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5693 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5694
5695 /* check the workaround bit for correct mac address order */
5696 txreg = readl(base + NvRegTransmitPoll);
5697 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5698 /* mac address is already in correct order */
5699 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5700 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5701 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5702 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5703 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5704 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5705 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5706 /* mac address is already in correct order */
5707 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5708 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5709 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5710 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5711 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5712 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5713 /*
5714 * Set orig mac address back to the reversed version.
5715 * This flag will be cleared during low power transition.
5716 * Therefore, we should always put back the reversed address.
5717 */
5718 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5719 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5720 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5721 } else {
5722 /* need to reverse mac address to correct order */
5723 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5724 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5725 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5726 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5727 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5728 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5729 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5730 dev_dbg(&pci_dev->dev,
5731 "%s: set workaround bit for reversed mac addr\n",
5732 __func__);
5733 }
5734 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5735
5736 if (!is_valid_ether_addr(dev->perm_addr)) {
5737 /*
5738 * Bad mac address. At least one bios sets the mac address
5739 * to 01:23:45:67:89:ab
5740 */
5741 dev_err(&pci_dev->dev,
5742 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5743 dev->dev_addr);
5744 random_ether_addr(dev->dev_addr);
5745 dev_err(&pci_dev->dev,
5746 "Using random MAC address: %pM\n", dev->dev_addr);
5747 }
5748
5749 /* set mac address */
5750 nv_copy_mac_to_hw(dev);
5751
5752 /* disable WOL */
5753 writel(0, base + NvRegWakeUpFlags);
5754 np->wolenabled = 0;
5755 device_set_wakeup_enable(&pci_dev->dev, false);
5756
5757 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5758
5759 /* take phy and nic out of low power mode */
5760 powerstate = readl(base + NvRegPowerState2);
5761 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5762 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5763 pci_dev->revision >= 0xA3)
5764 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5765 writel(powerstate, base + NvRegPowerState2);
5766 }
5767
5768 if (np->desc_ver == DESC_VER_1)
5769 np->tx_flags = NV_TX_VALID;
5770 else
5771 np->tx_flags = NV_TX2_VALID;
5772
5773 np->msi_flags = 0;
5774 if ((id->driver_data & DEV_HAS_MSI) && msi)
5775 np->msi_flags |= NV_MSI_CAPABLE;
5776
5777 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5778 /* msix has had reported issues when modifying irqmask
5779 as in the case of napi, therefore, disable for now
5780 */
5781 #if 0
5782 np->msi_flags |= NV_MSI_X_CAPABLE;
5783 #endif
5784 }
5785
5786 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5787 np->irqmask = NVREG_IRQMASK_CPU;
5788 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5789 np->msi_flags |= 0x0001;
5790 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5791 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5792 /* start off in throughput mode */
5793 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5794 /* remove support for msix mode */
5795 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5796 } else {
5797 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5798 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5799 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5800 np->msi_flags |= 0x0003;
5801 }
5802
5803 if (id->driver_data & DEV_NEED_TIMERIRQ)
5804 np->irqmask |= NVREG_IRQ_TIMER;
5805 if (id->driver_data & DEV_NEED_LINKTIMER) {
5806 np->need_linktimer = 1;
5807 np->link_timeout = jiffies + LINK_TIMEOUT;
5808 } else {
5809 np->need_linktimer = 0;
5810 }
5811
5812 /* Limit the number of tx's outstanding for hw bug */
5813 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5814 np->tx_limit = 1;
5815 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5816 pci_dev->revision >= 0xA2)
5817 np->tx_limit = 0;
5818 }
5819
5820 /* clear phy state and temporarily halt phy interrupts */
5821 writel(0, base + NvRegMIIMask);
5822 phystate = readl(base + NvRegAdapterControl);
5823 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5824 phystate_orig = 1;
5825 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5826 writel(phystate, base + NvRegAdapterControl);
5827 }
5828 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5829
5830 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5831 /* management unit running on the mac? */
5832 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5833 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5834 nv_mgmt_acquire_sema(dev) &&
5835 nv_mgmt_get_version(dev)) {
5836 np->mac_in_use = 1;
5837 if (np->mgmt_version > 0)
5838 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5839 /* management unit setup the phy already? */
5840 if (np->mac_in_use &&
5841 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5842 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5843 /* phy is inited by mgmt unit */
5844 phyinitialized = 1;
5845 } else {
5846 /* we need to init the phy */
5847 }
5848 }
5849 }
5850
5851 /* find a suitable phy */
5852 for (i = 1; i <= 32; i++) {
5853 int id1, id2;
5854 int phyaddr = i & 0x1F;
5855
5856 spin_lock_irq(&np->lock);
5857 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5858 spin_unlock_irq(&np->lock);
5859 if (id1 < 0 || id1 == 0xffff)
5860 continue;
5861 spin_lock_irq(&np->lock);
5862 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5863 spin_unlock_irq(&np->lock);
5864 if (id2 < 0 || id2 == 0xffff)
5865 continue;
5866
5867 np->phy_model = id2 & PHYID2_MODEL_MASK;
5868 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5869 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5870 np->phyaddr = phyaddr;
5871 np->phy_oui = id1 | id2;
5872
5873 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5874 if (np->phy_oui == PHY_OUI_REALTEK2)
5875 np->phy_oui = PHY_OUI_REALTEK;
5876 /* Setup phy revision for Realtek */
5877 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5878 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5879
5880 break;
5881 }
5882 if (i == 33) {
5883 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5884 goto out_error;
5885 }
5886
5887 if (!phyinitialized) {
5888 /* reset it */
5889 phy_init(dev);
5890 } else {
5891 /* see if it is a gigabit phy */
5892 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5893 if (mii_status & PHY_GIGABIT)
5894 np->gigabit = PHY_GIGABIT;
5895 }
5896
5897 /* set default link speed settings */
5898 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5899 np->duplex = 0;
5900 np->autoneg = 1;
5901
5902 err = register_netdev(dev);
5903 if (err) {
5904 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5905 goto out_error;
5906 }
5907
5908 if (id->driver_data & DEV_HAS_VLAN)
5909 nv_vlan_mode(dev, dev->features);
5910
5911 netif_carrier_off(dev);
5912
5913 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5914 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5915
5916 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5917 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5918 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5919 "csum " : "",
5920 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5921 "vlan " : "",
5922 dev->features & (NETIF_F_LOOPBACK) ?
5923 "loopback " : "",
5924 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5925 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5926 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5927 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5928 np->need_linktimer ? "lnktim " : "",
5929 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5930 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5931 np->desc_ver);
5932
5933 return 0;
5934
5935 out_error:
5936 if (phystate_orig)
5937 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5938 pci_set_drvdata(pci_dev, NULL);
5939 out_freering:
5940 free_rings(dev);
5941 out_unmap:
5942 iounmap(get_hwbase(dev));
5943 out_relreg:
5944 pci_release_regions(pci_dev);
5945 out_disable:
5946 pci_disable_device(pci_dev);
5947 out_free:
5948 free_netdev(dev);
5949 out:
5950 return err;
5951 }
5952
5953 static void nv_restore_phy(struct net_device *dev)
5954 {
5955 struct fe_priv *np = netdev_priv(dev);
5956 u16 phy_reserved, mii_control;
5957
5958 if (np->phy_oui == PHY_OUI_REALTEK &&
5959 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5960 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5961 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5962 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5963 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5964 phy_reserved |= PHY_REALTEK_INIT8;
5965 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5966 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5967
5968 /* restart auto negotiation */
5969 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5970 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5971 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5972 }
5973 }
5974
5975 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5976 {
5977 struct net_device *dev = pci_get_drvdata(pci_dev);
5978 struct fe_priv *np = netdev_priv(dev);
5979 u8 __iomem *base = get_hwbase(dev);
5980
5981 /* special op: write back the misordered MAC address - otherwise
5982 * the next nv_probe would see a wrong address.
5983 */
5984 writel(np->orig_mac[0], base + NvRegMacAddrA);
5985 writel(np->orig_mac[1], base + NvRegMacAddrB);
5986 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5987 base + NvRegTransmitPoll);
5988 }
5989
5990 static void __devexit nv_remove(struct pci_dev *pci_dev)
5991 {
5992 struct net_device *dev = pci_get_drvdata(pci_dev);
5993
5994 unregister_netdev(dev);
5995
5996 nv_restore_mac_addr(pci_dev);
5997
5998 /* restore any phy related changes */
5999 nv_restore_phy(dev);
6000
6001 nv_mgmt_release_sema(dev);
6002
6003 /* free all structures */
6004 free_rings(dev);
6005 iounmap(get_hwbase(dev));
6006 pci_release_regions(pci_dev);
6007 pci_disable_device(pci_dev);
6008 free_netdev(dev);
6009 pci_set_drvdata(pci_dev, NULL);
6010 }
6011
6012 #ifdef CONFIG_PM_SLEEP
6013 static int nv_suspend(struct device *device)
6014 {
6015 struct pci_dev *pdev = to_pci_dev(device);
6016 struct net_device *dev = pci_get_drvdata(pdev);
6017 struct fe_priv *np = netdev_priv(dev);
6018 u8 __iomem *base = get_hwbase(dev);
6019 int i;
6020
6021 if (netif_running(dev)) {
6022 /* Gross. */
6023 nv_close(dev);
6024 }
6025 netif_device_detach(dev);
6026
6027 /* save non-pci configuration space */
6028 for (i = 0; i <= np->register_size/sizeof(u32); i++)
6029 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6030
6031 return 0;
6032 }
6033
6034 static int nv_resume(struct device *device)
6035 {
6036 struct pci_dev *pdev = to_pci_dev(device);
6037 struct net_device *dev = pci_get_drvdata(pdev);
6038 struct fe_priv *np = netdev_priv(dev);
6039 u8 __iomem *base = get_hwbase(dev);
6040 int i, rc = 0;
6041
6042 /* restore non-pci configuration space */
6043 for (i = 0; i <= np->register_size/sizeof(u32); i++)
6044 writel(np->saved_config_space[i], base+i*sizeof(u32));
6045
6046 if (np->driver_data & DEV_NEED_MSI_FIX)
6047 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6048
6049 /* restore phy state, including autoneg */
6050 phy_init(dev);
6051
6052 netif_device_attach(dev);
6053 if (netif_running(dev)) {
6054 rc = nv_open(dev);
6055 nv_set_multicast(dev);
6056 }
6057 return rc;
6058 }
6059
6060 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6061 #define NV_PM_OPS (&nv_pm_ops)
6062
6063 #else
6064 #define NV_PM_OPS NULL
6065 #endif /* CONFIG_PM_SLEEP */
6066
6067 #ifdef CONFIG_PM
6068 static void nv_shutdown(struct pci_dev *pdev)
6069 {
6070 struct net_device *dev = pci_get_drvdata(pdev);
6071 struct fe_priv *np = netdev_priv(dev);
6072
6073 if (netif_running(dev))
6074 nv_close(dev);
6075
6076 /*
6077 * Restore the MAC so a kernel started by kexec won't get confused.
6078 * If we really go for poweroff, we must not restore the MAC,
6079 * otherwise the MAC for WOL will be reversed at least on some boards.
6080 */
6081 if (system_state != SYSTEM_POWER_OFF)
6082 nv_restore_mac_addr(pdev);
6083
6084 pci_disable_device(pdev);
6085 /*
6086 * Apparently it is not possible to reinitialise from D3 hot,
6087 * only put the device into D3 if we really go for poweroff.
6088 */
6089 if (system_state == SYSTEM_POWER_OFF) {
6090 pci_wake_from_d3(pdev, np->wolenabled);
6091 pci_set_power_state(pdev, PCI_D3hot);
6092 }
6093 }
6094 #else
6095 #define nv_shutdown NULL
6096 #endif /* CONFIG_PM */
6097
6098 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
6099 { /* nForce Ethernet Controller */
6100 PCI_DEVICE(0x10DE, 0x01C3),
6101 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6102 },
6103 { /* nForce2 Ethernet Controller */
6104 PCI_DEVICE(0x10DE, 0x0066),
6105 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6106 },
6107 { /* nForce3 Ethernet Controller */
6108 PCI_DEVICE(0x10DE, 0x00D6),
6109 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6110 },
6111 { /* nForce3 Ethernet Controller */
6112 PCI_DEVICE(0x10DE, 0x0086),
6113 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6114 },
6115 { /* nForce3 Ethernet Controller */
6116 PCI_DEVICE(0x10DE, 0x008C),
6117 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6118 },
6119 { /* nForce3 Ethernet Controller */
6120 PCI_DEVICE(0x10DE, 0x00E6),
6121 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6122 },
6123 { /* nForce3 Ethernet Controller */
6124 PCI_DEVICE(0x10DE, 0x00DF),
6125 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6126 },
6127 { /* CK804 Ethernet Controller */
6128 PCI_DEVICE(0x10DE, 0x0056),
6129 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6130 },
6131 { /* CK804 Ethernet Controller */
6132 PCI_DEVICE(0x10DE, 0x0057),
6133 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6134 },
6135 { /* MCP04 Ethernet Controller */
6136 PCI_DEVICE(0x10DE, 0x0037),
6137 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6138 },
6139 { /* MCP04 Ethernet Controller */
6140 PCI_DEVICE(0x10DE, 0x0038),
6141 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6142 },
6143 { /* MCP51 Ethernet Controller */
6144 PCI_DEVICE(0x10DE, 0x0268),
6145 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6146 },
6147 { /* MCP51 Ethernet Controller */
6148 PCI_DEVICE(0x10DE, 0x0269),
6149 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6150 },
6151 { /* MCP55 Ethernet Controller */
6152 PCI_DEVICE(0x10DE, 0x0372),
6153 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6154 },
6155 { /* MCP55 Ethernet Controller */
6156 PCI_DEVICE(0x10DE, 0x0373),
6157 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6158 },
6159 { /* MCP61 Ethernet Controller */
6160 PCI_DEVICE(0x10DE, 0x03E5),
6161 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6162 },
6163 { /* MCP61 Ethernet Controller */
6164 PCI_DEVICE(0x10DE, 0x03E6),
6165 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6166 },
6167 { /* MCP61 Ethernet Controller */
6168 PCI_DEVICE(0x10DE, 0x03EE),
6169 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6170 },
6171 { /* MCP61 Ethernet Controller */
6172 PCI_DEVICE(0x10DE, 0x03EF),
6173 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6174 },
6175 { /* MCP65 Ethernet Controller */
6176 PCI_DEVICE(0x10DE, 0x0450),
6177 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6178 },
6179 { /* MCP65 Ethernet Controller */
6180 PCI_DEVICE(0x10DE, 0x0451),
6181 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6182 },
6183 { /* MCP65 Ethernet Controller */
6184 PCI_DEVICE(0x10DE, 0x0452),
6185 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6186 },
6187 { /* MCP65 Ethernet Controller */
6188 PCI_DEVICE(0x10DE, 0x0453),
6189 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6190 },
6191 { /* MCP67 Ethernet Controller */
6192 PCI_DEVICE(0x10DE, 0x054C),
6193 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6194 },
6195 { /* MCP67 Ethernet Controller */
6196 PCI_DEVICE(0x10DE, 0x054D),
6197 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6198 },
6199 { /* MCP67 Ethernet Controller */
6200 PCI_DEVICE(0x10DE, 0x054E),
6201 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6202 },
6203 { /* MCP67 Ethernet Controller */
6204 PCI_DEVICE(0x10DE, 0x054F),
6205 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6206 },
6207 { /* MCP73 Ethernet Controller */
6208 PCI_DEVICE(0x10DE, 0x07DC),
6209 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6210 },
6211 { /* MCP73 Ethernet Controller */
6212 PCI_DEVICE(0x10DE, 0x07DD),
6213 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6214 },
6215 { /* MCP73 Ethernet Controller */
6216 PCI_DEVICE(0x10DE, 0x07DE),
6217 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6218 },
6219 { /* MCP73 Ethernet Controller */
6220 PCI_DEVICE(0x10DE, 0x07DF),
6221 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6222 },
6223 { /* MCP77 Ethernet Controller */
6224 PCI_DEVICE(0x10DE, 0x0760),
6225 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6226 },
6227 { /* MCP77 Ethernet Controller */
6228 PCI_DEVICE(0x10DE, 0x0761),
6229 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6230 },
6231 { /* MCP77 Ethernet Controller */
6232 PCI_DEVICE(0x10DE, 0x0762),
6233 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6234 },
6235 { /* MCP77 Ethernet Controller */
6236 PCI_DEVICE(0x10DE, 0x0763),
6237 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6238 },
6239 { /* MCP79 Ethernet Controller */
6240 PCI_DEVICE(0x10DE, 0x0AB0),
6241 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6242 },
6243 { /* MCP79 Ethernet Controller */
6244 PCI_DEVICE(0x10DE, 0x0AB1),
6245 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6246 },
6247 { /* MCP79 Ethernet Controller */
6248 PCI_DEVICE(0x10DE, 0x0AB2),
6249 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6250 },
6251 { /* MCP79 Ethernet Controller */
6252 PCI_DEVICE(0x10DE, 0x0AB3),
6253 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6254 },
6255 { /* MCP89 Ethernet Controller */
6256 PCI_DEVICE(0x10DE, 0x0D7D),
6257 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6258 },
6259 {0,},
6260 };
6261
6262 static struct pci_driver driver = {
6263 .name = DRV_NAME,
6264 .id_table = pci_tbl,
6265 .probe = nv_probe,
6266 .remove = __devexit_p(nv_remove),
6267 .shutdown = nv_shutdown,
6268 .driver.pm = NV_PM_OPS,
6269 };
6270
6271 static int __init init_nic(void)
6272 {
6273 return pci_register_driver(&driver);
6274 }
6275
6276 static void __exit exit_nic(void)
6277 {
6278 pci_unregister_driver(&driver);
6279 }
6280
6281 module_param(max_interrupt_work, int, 0);
6282 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6283 module_param(optimization_mode, int, 0);
6284 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6285 module_param(poll_interval, int, 0);
6286 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6287 module_param(msi, int, 0);
6288 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6289 module_param(msix, int, 0);
6290 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6291 module_param(dma_64bit, int, 0);
6292 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6293 module_param(phy_cross, int, 0);
6294 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6295 module_param(phy_power_down, int, 0);
6296 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6297 module_param(debug_tx_timeout, bool, 0);
6298 MODULE_PARM_DESC(debug_tx_timeout,
6299 "Dump tx related registers and ring when tx_timeout happens");
6300
6301 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6302 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6303 MODULE_LICENSE("GPL");
6304
6305 MODULE_DEVICE_TABLE(pci, pci_tbl);
6306
6307 module_init(init_nic);
6308 module_exit(exit_nic);