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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / net / ethernet / qlogic / qlge / qlge.h
blobb8478aab050e76efa2b734572b3f866f98da321f
1 /*
2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qlge for copyright and licensing details.
6 */
7 #ifndef _QLGE_H_
8 #define _QLGE_H_
9
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/rtnetlink.h>
14 #include <linux/if_vlan.h>
15
16 /*
17 * General definitions...
18 */
19 #define DRV_NAME "qlge"
20 #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
21 #define DRV_VERSION "v1.00.00.29.00.00-01"
22
23 #define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */
24
25 #define QLGE_VENDOR_ID 0x1077
26 #define QLGE_DEVICE_ID_8012 0x8012
27 #define QLGE_DEVICE_ID_8000 0x8000
28 #define MAX_CPUS 8
29 #define MAX_TX_RINGS MAX_CPUS
30 #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
31
32 #define NUM_TX_RING_ENTRIES 256
33 #define NUM_RX_RING_ENTRIES 256
34
35 #define NUM_SMALL_BUFFERS 512
36 #define NUM_LARGE_BUFFERS 512
37 #define DB_PAGE_SIZE 4096
38
39 /* Calculate the number of (4k) pages required to
40 * contain a buffer queue of the given length.
41 */
42 #define MAX_DB_PAGES_PER_BQ(x) \
43 (((x * sizeof(u64)) / DB_PAGE_SIZE) + \
44 (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
45
46 #define RX_RING_SHADOW_SPACE (sizeof(u64) + \
47 MAX_DB_PAGES_PER_BQ(NUM_SMALL_BUFFERS) * sizeof(u64) + \
48 MAX_DB_PAGES_PER_BQ(NUM_LARGE_BUFFERS) * sizeof(u64))
49 #define LARGE_BUFFER_MAX_SIZE 8192
50 #define LARGE_BUFFER_MIN_SIZE 2048
51
52 #define MAX_CQ 128
53 #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
54 #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
55 #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
56 #define UDELAY_COUNT 3
57 #define UDELAY_DELAY 100
58
59
60 #define TX_DESC_PER_IOCB 8
61
62 #if ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2) > 0
63 #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
64 #else /* all other page sizes */
65 #define TX_DESC_PER_OAL 0
66 #endif
67
68 /* Word shifting for converting 64-bit
69 * address to a series of 16-bit words.
70 * This is used for some MPI firmware
71 * mailbox commands.
72 */
73 #define LSW(x) ((u16)(x))
74 #define MSW(x) ((u16)((u32)(x) >> 16))
75 #define LSD(x) ((u32)((u64)(x)))
76 #define MSD(x) ((u32)((((u64)(x)) >> 32)))
77
78 /* MPI test register definitions. This register
79 * is used for determining alternate NIC function's
80 * PCI->func number.
81 */
82 enum {
83 MPI_TEST_FUNC_PORT_CFG = 0x1002,
84 MPI_TEST_FUNC_PRB_CTL = 0x100e,
85 MPI_TEST_FUNC_PRB_EN = 0x18a20000,
86 MPI_TEST_FUNC_RST_STS = 0x100a,
87 MPI_TEST_FUNC_RST_FRC = 0x00000003,
88 MPI_TEST_NIC_FUNC_MASK = 0x00000007,
89 MPI_TEST_NIC1_FUNCTION_ENABLE = (1 << 0),
90 MPI_TEST_NIC1_FUNCTION_MASK = 0x0000000e,
91 MPI_TEST_NIC1_FUNC_SHIFT = 1,
92 MPI_TEST_NIC2_FUNCTION_ENABLE = (1 << 4),
93 MPI_TEST_NIC2_FUNCTION_MASK = 0x000000e0,
94 MPI_TEST_NIC2_FUNC_SHIFT = 5,
95 MPI_TEST_FC1_FUNCTION_ENABLE = (1 << 8),
96 MPI_TEST_FC1_FUNCTION_MASK = 0x00000e00,
97 MPI_TEST_FC1_FUNCTION_SHIFT = 9,
98 MPI_TEST_FC2_FUNCTION_ENABLE = (1 << 12),
99 MPI_TEST_FC2_FUNCTION_MASK = 0x0000e000,
100 MPI_TEST_FC2_FUNCTION_SHIFT = 13,
101
102 MPI_NIC_READ = 0x00000000,
103 MPI_NIC_REG_BLOCK = 0x00020000,
104 MPI_NIC_FUNCTION_SHIFT = 6,
105 };
106
107 /*
108 * Processor Address Register (PROC_ADDR) bit definitions.
109 */
110 enum {
111
112 /* Misc. stuff */
113 MAILBOX_COUNT = 16,
114 MAILBOX_TIMEOUT = 5,
115
116 PROC_ADDR_RDY = (1 << 31),
117 PROC_ADDR_R = (1 << 30),
118 PROC_ADDR_ERR = (1 << 29),
119 PROC_ADDR_DA = (1 << 28),
120 PROC_ADDR_FUNC0_MBI = 0x00001180,
121 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
122 PROC_ADDR_FUNC0_CTL = 0x000011a1,
123 PROC_ADDR_FUNC2_MBI = 0x00001280,
124 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
125 PROC_ADDR_FUNC2_CTL = 0x000012a1,
126 PROC_ADDR_MPI_RISC = 0x00000000,
127 PROC_ADDR_MDE = 0x00010000,
128 PROC_ADDR_REGBLOCK = 0x00020000,
129 PROC_ADDR_RISC_REG = 0x00030000,
130 };
131
132 /*
133 * System Register (SYS) bit definitions.
134 */
135 enum {
136 SYS_EFE = (1 << 0),
137 SYS_FAE = (1 << 1),
138 SYS_MDC = (1 << 2),
139 SYS_DST = (1 << 3),
140 SYS_DWC = (1 << 4),
141 SYS_EVW = (1 << 5),
142 SYS_OMP_DLY_MASK = 0x3f000000,
143 /*
144 * There are no values defined as of edit #15.
145 */
146 SYS_ODI = (1 << 14),
147 };
148
149 /*
150 * Reset/Failover Register (RST_FO) bit definitions.
151 */
152 enum {
153 RST_FO_TFO = (1 << 0),
154 RST_FO_RR_MASK = 0x00060000,
155 RST_FO_RR_CQ_CAM = 0x00000000,
156 RST_FO_RR_DROP = 0x00000002,
157 RST_FO_RR_DQ = 0x00000004,
158 RST_FO_RR_RCV_FUNC_CQ = 0x00000006,
159 RST_FO_FRB = (1 << 12),
160 RST_FO_MOP = (1 << 13),
161 RST_FO_REG = (1 << 14),
162 RST_FO_FR = (1 << 15),
163 };
164
165 /*
166 * Function Specific Control Register (FSC) bit definitions.
167 */
168 enum {
169 FSC_DBRST_MASK = 0x00070000,
170 FSC_DBRST_256 = 0x00000000,
171 FSC_DBRST_512 = 0x00000001,
172 FSC_DBRST_768 = 0x00000002,
173 FSC_DBRST_1024 = 0x00000003,
174 FSC_DBL_MASK = 0x00180000,
175 FSC_DBL_DBRST = 0x00000000,
176 FSC_DBL_MAX_PLD = 0x00000008,
177 FSC_DBL_MAX_BRST = 0x00000010,
178 FSC_DBL_128_BYTES = 0x00000018,
179 FSC_EC = (1 << 5),
180 FSC_EPC_MASK = 0x00c00000,
181 FSC_EPC_INBOUND = (1 << 6),
182 FSC_EPC_OUTBOUND = (1 << 7),
183 FSC_VM_PAGESIZE_MASK = 0x07000000,
184 FSC_VM_PAGE_2K = 0x00000100,
185 FSC_VM_PAGE_4K = 0x00000200,
186 FSC_VM_PAGE_8K = 0x00000300,
187 FSC_VM_PAGE_64K = 0x00000600,
188 FSC_SH = (1 << 11),
189 FSC_DSB = (1 << 12),
190 FSC_STE = (1 << 13),
191 FSC_FE = (1 << 15),
192 };
193
194 /*
195 * Host Command Status Register (CSR) bit definitions.
196 */
197 enum {
198 CSR_ERR_STS_MASK = 0x0000003f,
199 /*
200 * There are no valued defined as of edit #15.
201 */
202 CSR_RR = (1 << 8),
203 CSR_HRI = (1 << 9),
204 CSR_RP = (1 << 10),
205 CSR_CMD_PARM_SHIFT = 22,
206 CSR_CMD_NOP = 0x00000000,
207 CSR_CMD_SET_RST = 0x10000000,
208 CSR_CMD_CLR_RST = 0x20000000,
209 CSR_CMD_SET_PAUSE = 0x30000000,
210 CSR_CMD_CLR_PAUSE = 0x40000000,
211 CSR_CMD_SET_H2R_INT = 0x50000000,
212 CSR_CMD_CLR_H2R_INT = 0x60000000,
213 CSR_CMD_PAR_EN = 0x70000000,
214 CSR_CMD_SET_BAD_PAR = 0x80000000,
215 CSR_CMD_CLR_BAD_PAR = 0x90000000,
216 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
217 };
218
219 /*
220 * Configuration Register (CFG) bit definitions.
221 */
222 enum {
223 CFG_LRQ = (1 << 0),
224 CFG_DRQ = (1 << 1),
225 CFG_LR = (1 << 2),
226 CFG_DR = (1 << 3),
227 CFG_LE = (1 << 5),
228 CFG_LCQ = (1 << 6),
229 CFG_DCQ = (1 << 7),
230 CFG_Q_SHIFT = 8,
231 CFG_Q_MASK = 0x7f000000,
232 };
233
234 /*
235 * Status Register (STS) bit definitions.
236 */
237 enum {
238 STS_FE = (1 << 0),
239 STS_PI = (1 << 1),
240 STS_PL0 = (1 << 2),
241 STS_PL1 = (1 << 3),
242 STS_PI0 = (1 << 4),
243 STS_PI1 = (1 << 5),
244 STS_FUNC_ID_MASK = 0x000000c0,
245 STS_FUNC_ID_SHIFT = 6,
246 STS_F0E = (1 << 8),
247 STS_F1E = (1 << 9),
248 STS_F2E = (1 << 10),
249 STS_F3E = (1 << 11),
250 STS_NFE = (1 << 12),
251 };
252
253 /*
254 * Interrupt Enable Register (INTR_EN) bit definitions.
255 */
256 enum {
257 INTR_EN_INTR_MASK = 0x007f0000,
258 INTR_EN_TYPE_MASK = 0x03000000,
259 INTR_EN_TYPE_ENABLE = 0x00000100,
260 INTR_EN_TYPE_DISABLE = 0x00000200,
261 INTR_EN_TYPE_READ = 0x00000300,
262 INTR_EN_IHD = (1 << 13),
263 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
264 INTR_EN_EI = (1 << 14),
265 INTR_EN_EN = (1 << 15),
266 };
267
268 /*
269 * Interrupt Mask Register (INTR_MASK) bit definitions.
270 */
271 enum {
272 INTR_MASK_PI = (1 << 0),
273 INTR_MASK_HL0 = (1 << 1),
274 INTR_MASK_LH0 = (1 << 2),
275 INTR_MASK_HL1 = (1 << 3),
276 INTR_MASK_LH1 = (1 << 4),
277 INTR_MASK_SE = (1 << 5),
278 INTR_MASK_LSC = (1 << 6),
279 INTR_MASK_MC = (1 << 7),
280 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
281 };
282
283 /*
284 * Register (REV_ID) bit definitions.
285 */
286 enum {
287 REV_ID_MASK = 0x0000000f,
288 REV_ID_NICROLL_SHIFT = 0,
289 REV_ID_NICREV_SHIFT = 4,
290 REV_ID_XGROLL_SHIFT = 8,
291 REV_ID_XGREV_SHIFT = 12,
292 REV_ID_CHIPREV_SHIFT = 28,
293 };
294
295 /*
296 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
297 */
298 enum {
299 FRC_ECC_ERR_VW = (1 << 12),
300 FRC_ECC_ERR_VB = (1 << 13),
301 FRC_ECC_ERR_NI = (1 << 14),
302 FRC_ECC_ERR_NO = (1 << 15),
303 FRC_ECC_PFE_SHIFT = 16,
304 FRC_ECC_ERR_DO = (1 << 18),
305 FRC_ECC_P14 = (1 << 19),
306 };
307
308 /*
309 * Error Status Register (ERR_STS) bit definitions.
310 */
311 enum {
312 ERR_STS_NOF = (1 << 0),
313 ERR_STS_NIF = (1 << 1),
314 ERR_STS_DRP = (1 << 2),
315 ERR_STS_XGP = (1 << 3),
316 ERR_STS_FOU = (1 << 4),
317 ERR_STS_FOC = (1 << 5),
318 ERR_STS_FOF = (1 << 6),
319 ERR_STS_FIU = (1 << 7),
320 ERR_STS_FIC = (1 << 8),
321 ERR_STS_FIF = (1 << 9),
322 ERR_STS_MOF = (1 << 10),
323 ERR_STS_TA = (1 << 11),
324 ERR_STS_MA = (1 << 12),
325 ERR_STS_MPE = (1 << 13),
326 ERR_STS_SCE = (1 << 14),
327 ERR_STS_STE = (1 << 15),
328 ERR_STS_FOW = (1 << 16),
329 ERR_STS_UE = (1 << 17),
330 ERR_STS_MCH = (1 << 26),
331 ERR_STS_LOC_SHIFT = 27,
332 };
333
334 /*
335 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
336 */
337 enum {
338 RAM_DBG_ADDR_FW = (1 << 30),
339 RAM_DBG_ADDR_FR = (1 << 31),
340 };
341
342 /*
343 * Semaphore Register (SEM) bit definitions.
344 */
345 enum {
346 /*
347 * Example:
348 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
349 */
350 SEM_CLEAR = 0,
351 SEM_SET = 1,
352 SEM_FORCE = 3,
353 SEM_XGMAC0_SHIFT = 0,
354 SEM_XGMAC1_SHIFT = 2,
355 SEM_ICB_SHIFT = 4,
356 SEM_MAC_ADDR_SHIFT = 6,
357 SEM_FLASH_SHIFT = 8,
358 SEM_PROBE_SHIFT = 10,
359 SEM_RT_IDX_SHIFT = 12,
360 SEM_PROC_REG_SHIFT = 14,
361 SEM_XGMAC0_MASK = 0x00030000,
362 SEM_XGMAC1_MASK = 0x000c0000,
363 SEM_ICB_MASK = 0x00300000,
364 SEM_MAC_ADDR_MASK = 0x00c00000,
365 SEM_FLASH_MASK = 0x03000000,
366 SEM_PROBE_MASK = 0x0c000000,
367 SEM_RT_IDX_MASK = 0x30000000,
368 SEM_PROC_REG_MASK = 0xc0000000,
369 };
370
371 /*
372 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
373 */
374 enum {
375 XGMAC_ADDR_RDY = (1 << 31),
376 XGMAC_ADDR_R = (1 << 30),
377 XGMAC_ADDR_XME = (1 << 29),
378
379 /* XGMAC control registers */
380 PAUSE_SRC_LO = 0x00000100,
381 PAUSE_SRC_HI = 0x00000104,
382 GLOBAL_CFG = 0x00000108,
383 GLOBAL_CFG_RESET = (1 << 0),
384 GLOBAL_CFG_JUMBO = (1 << 6),
385 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
386 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
387 TX_CFG = 0x0000010c,
388 TX_CFG_RESET = (1 << 0),
389 TX_CFG_EN = (1 << 1),
390 TX_CFG_PREAM = (1 << 2),
391 RX_CFG = 0x00000110,
392 RX_CFG_RESET = (1 << 0),
393 RX_CFG_EN = (1 << 1),
394 RX_CFG_PREAM = (1 << 2),
395 FLOW_CTL = 0x0000011c,
396 PAUSE_OPCODE = 0x00000120,
397 PAUSE_TIMER = 0x00000124,
398 PAUSE_FRM_DEST_LO = 0x00000128,
399 PAUSE_FRM_DEST_HI = 0x0000012c,
400 MAC_TX_PARAMS = 0x00000134,
401 MAC_TX_PARAMS_JUMBO = (1 << 31),
402 MAC_TX_PARAMS_SIZE_SHIFT = 16,
403 MAC_RX_PARAMS = 0x00000138,
404 MAC_SYS_INT = 0x00000144,
405 MAC_SYS_INT_MASK = 0x00000148,
406 MAC_MGMT_INT = 0x0000014c,
407 MAC_MGMT_IN_MASK = 0x00000150,
408 EXT_ARB_MODE = 0x000001fc,
409
410 /* XGMAC TX statistics registers */
411 TX_PKTS = 0x00000200,
412 TX_BYTES = 0x00000208,
413 TX_MCAST_PKTS = 0x00000210,
414 TX_BCAST_PKTS = 0x00000218,
415 TX_UCAST_PKTS = 0x00000220,
416 TX_CTL_PKTS = 0x00000228,
417 TX_PAUSE_PKTS = 0x00000230,
418 TX_64_PKT = 0x00000238,
419 TX_65_TO_127_PKT = 0x00000240,
420 TX_128_TO_255_PKT = 0x00000248,
421 TX_256_511_PKT = 0x00000250,
422 TX_512_TO_1023_PKT = 0x00000258,
423 TX_1024_TO_1518_PKT = 0x00000260,
424 TX_1519_TO_MAX_PKT = 0x00000268,
425 TX_UNDERSIZE_PKT = 0x00000270,
426 TX_OVERSIZE_PKT = 0x00000278,
427
428 /* XGMAC statistics control registers */
429 RX_HALF_FULL_DET = 0x000002a0,
430 TX_HALF_FULL_DET = 0x000002a4,
431 RX_OVERFLOW_DET = 0x000002a8,
432 TX_OVERFLOW_DET = 0x000002ac,
433 RX_HALF_FULL_MASK = 0x000002b0,
434 TX_HALF_FULL_MASK = 0x000002b4,
435 RX_OVERFLOW_MASK = 0x000002b8,
436 TX_OVERFLOW_MASK = 0x000002bc,
437 STAT_CNT_CTL = 0x000002c0,
438 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
439 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
440 AUX_RX_HALF_FULL_DET = 0x000002d0,
441 AUX_TX_HALF_FULL_DET = 0x000002d4,
442 AUX_RX_OVERFLOW_DET = 0x000002d8,
443 AUX_TX_OVERFLOW_DET = 0x000002dc,
444 AUX_RX_HALF_FULL_MASK = 0x000002f0,
445 AUX_TX_HALF_FULL_MASK = 0x000002f4,
446 AUX_RX_OVERFLOW_MASK = 0x000002f8,
447 AUX_TX_OVERFLOW_MASK = 0x000002fc,
448
449 /* XGMAC RX statistics registers */
450 RX_BYTES = 0x00000300,
451 RX_BYTES_OK = 0x00000308,
452 RX_PKTS = 0x00000310,
453 RX_PKTS_OK = 0x00000318,
454 RX_BCAST_PKTS = 0x00000320,
455 RX_MCAST_PKTS = 0x00000328,
456 RX_UCAST_PKTS = 0x00000330,
457 RX_UNDERSIZE_PKTS = 0x00000338,
458 RX_OVERSIZE_PKTS = 0x00000340,
459 RX_JABBER_PKTS = 0x00000348,
460 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
461 RX_DROP_EVENTS = 0x00000358,
462 RX_FCERR_PKTS = 0x00000360,
463 RX_ALIGN_ERR = 0x00000368,
464 RX_SYMBOL_ERR = 0x00000370,
465 RX_MAC_ERR = 0x00000378,
466 RX_CTL_PKTS = 0x00000380,
467 RX_PAUSE_PKTS = 0x00000388,
468 RX_64_PKTS = 0x00000390,
469 RX_65_TO_127_PKTS = 0x00000398,
470 RX_128_255_PKTS = 0x000003a0,
471 RX_256_511_PKTS = 0x000003a8,
472 RX_512_TO_1023_PKTS = 0x000003b0,
473 RX_1024_TO_1518_PKTS = 0x000003b8,
474 RX_1519_TO_MAX_PKTS = 0x000003c0,
475 RX_LEN_ERR_PKTS = 0x000003c8,
476
477 /* XGMAC MDIO control registers */
478 MDIO_TX_DATA = 0x00000400,
479 MDIO_RX_DATA = 0x00000410,
480 MDIO_CMD = 0x00000420,
481 MDIO_PHY_ADDR = 0x00000430,
482 MDIO_PORT = 0x00000440,
483 MDIO_STATUS = 0x00000450,
484
485 XGMAC_REGISTER_END = 0x00000740,
486 };
487
488 /*
489 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
490 */
491 enum {
492 ETS_QUEUE_SHIFT = 29,
493 ETS_REF = (1 << 26),
494 ETS_RS = (1 << 27),
495 ETS_P = (1 << 28),
496 ETS_FC_COS_SHIFT = 23,
497 };
498
499 /*
500 * Flash Address Register (FLASH_ADDR) bit definitions.
501 */
502 enum {
503 FLASH_ADDR_RDY = (1 << 31),
504 FLASH_ADDR_R = (1 << 30),
505 FLASH_ADDR_ERR = (1 << 29),
506 };
507
508 /*
509 * Stop CQ Processing Register (CQ_STOP) bit definitions.
510 */
511 enum {
512 CQ_STOP_QUEUE_MASK = (0x007f0000),
513 CQ_STOP_TYPE_MASK = (0x03000000),
514 CQ_STOP_TYPE_START = 0x00000100,
515 CQ_STOP_TYPE_STOP = 0x00000200,
516 CQ_STOP_TYPE_READ = 0x00000300,
517 CQ_STOP_EN = (1 << 15),
518 };
519
520 /*
521 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
522 */
523 enum {
524 MAC_ADDR_IDX_SHIFT = 4,
525 MAC_ADDR_TYPE_SHIFT = 16,
526 MAC_ADDR_TYPE_COUNT = 10,
527 MAC_ADDR_TYPE_MASK = 0x000f0000,
528 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
529 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
530 MAC_ADDR_TYPE_VLAN = 0x00020000,
531 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
532 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
533 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
534 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
535 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
536 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
537 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
538 MAC_ADDR_ADR = (1 << 25),
539 MAC_ADDR_RS = (1 << 26),
540 MAC_ADDR_E = (1 << 27),
541 MAC_ADDR_MR = (1 << 30),
542 MAC_ADDR_MW = (1 << 31),
543 MAX_MULTICAST_ENTRIES = 32,
544
545 /* Entry count and words per entry
546 * for each address type in the filter.
547 */
548 MAC_ADDR_MAX_CAM_ENTRIES = 512,
549 MAC_ADDR_MAX_CAM_WCOUNT = 3,
550 MAC_ADDR_MAX_MULTICAST_ENTRIES = 32,
551 MAC_ADDR_MAX_MULTICAST_WCOUNT = 2,
552 MAC_ADDR_MAX_VLAN_ENTRIES = 4096,
553 MAC_ADDR_MAX_VLAN_WCOUNT = 1,
554 MAC_ADDR_MAX_MCAST_FLTR_ENTRIES = 4096,
555 MAC_ADDR_MAX_MCAST_FLTR_WCOUNT = 1,
556 MAC_ADDR_MAX_FC_MAC_ENTRIES = 4,
557 MAC_ADDR_MAX_FC_MAC_WCOUNT = 2,
558 MAC_ADDR_MAX_MGMT_MAC_ENTRIES = 8,
559 MAC_ADDR_MAX_MGMT_MAC_WCOUNT = 2,
560 MAC_ADDR_MAX_MGMT_VLAN_ENTRIES = 16,
561 MAC_ADDR_MAX_MGMT_VLAN_WCOUNT = 1,
562 MAC_ADDR_MAX_MGMT_V4_ENTRIES = 4,
563 MAC_ADDR_MAX_MGMT_V4_WCOUNT = 1,
564 MAC_ADDR_MAX_MGMT_V6_ENTRIES = 4,
565 MAC_ADDR_MAX_MGMT_V6_WCOUNT = 4,
566 MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES = 4,
567 MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT = 1,
568 };
569
570 /*
571 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
572 */
573 enum {
574 SPLT_HDR_EP = (1 << 31),
575 };
576
577 /*
578 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
579 */
580 enum {
581 FC_RCV_CFG_ECT = (1 << 15),
582 FC_RCV_CFG_DFH = (1 << 20),
583 FC_RCV_CFG_DVF = (1 << 21),
584 FC_RCV_CFG_RCE = (1 << 27),
585 FC_RCV_CFG_RFE = (1 << 28),
586 FC_RCV_CFG_TEE = (1 << 29),
587 FC_RCV_CFG_TCE = (1 << 30),
588 FC_RCV_CFG_TFE = (1 << 31),
589 };
590
591 /*
592 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
593 */
594 enum {
595 NIC_RCV_CFG_PPE = (1 << 0),
596 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
597 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
598 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
599 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
600 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
601 NIC_RCV_CFG_RV = (1 << 3),
602 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
603 NIC_RCV_CFG_DFQ_SHIFT = 8,
604 NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */
605 };
606
607 /*
608 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
609 */
610 enum {
611 MGMT_RCV_CFG_ARP = (1 << 0),
612 MGMT_RCV_CFG_DHC = (1 << 1),
613 MGMT_RCV_CFG_DHS = (1 << 2),
614 MGMT_RCV_CFG_NP = (1 << 3),
615 MGMT_RCV_CFG_I6N = (1 << 4),
616 MGMT_RCV_CFG_I6R = (1 << 5),
617 MGMT_RCV_CFG_DH6 = (1 << 6),
618 MGMT_RCV_CFG_UD1 = (1 << 7),
619 MGMT_RCV_CFG_UD0 = (1 << 8),
620 MGMT_RCV_CFG_BCT = (1 << 9),
621 MGMT_RCV_CFG_MCT = (1 << 10),
622 MGMT_RCV_CFG_DM = (1 << 11),
623 MGMT_RCV_CFG_RM = (1 << 12),
624 MGMT_RCV_CFG_STL = (1 << 13),
625 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
626 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
627 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
628 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
629 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
630 };
631
632 /*
633 * Routing Index Register (RT_IDX) bit definitions.
634 */
635 enum {
636 RT_IDX_IDX_SHIFT = 8,
637 RT_IDX_TYPE_MASK = 0x000f0000,
638 RT_IDX_TYPE_SHIFT = 16,
639 RT_IDX_TYPE_RT = 0x00000000,
640 RT_IDX_TYPE_RT_INV = 0x00010000,
641 RT_IDX_TYPE_NICQ = 0x00020000,
642 RT_IDX_TYPE_NICQ_INV = 0x00030000,
643 RT_IDX_DST_MASK = 0x00700000,
644 RT_IDX_DST_RSS = 0x00000000,
645 RT_IDX_DST_CAM_Q = 0x00100000,
646 RT_IDX_DST_COS_Q = 0x00200000,
647 RT_IDX_DST_DFLT_Q = 0x00300000,
648 RT_IDX_DST_DEST_Q = 0x00400000,
649 RT_IDX_RS = (1 << 26),
650 RT_IDX_E = (1 << 27),
651 RT_IDX_MR = (1 << 30),
652 RT_IDX_MW = (1 << 31),
653
654 /* Nic Queue format - type 2 bits */
655 RT_IDX_BCAST = (1 << 0),
656 RT_IDX_MCAST = (1 << 1),
657 RT_IDX_MCAST_MATCH = (1 << 2),
658 RT_IDX_MCAST_REG_MATCH = (1 << 3),
659 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
660 RT_IDX_FC_MACH = (1 << 5),
661 RT_IDX_ETH_FCOE = (1 << 6),
662 RT_IDX_CAM_HIT = (1 << 7),
663 RT_IDX_CAM_BIT0 = (1 << 8),
664 RT_IDX_CAM_BIT1 = (1 << 9),
665 RT_IDX_VLAN_TAG = (1 << 10),
666 RT_IDX_VLAN_MATCH = (1 << 11),
667 RT_IDX_VLAN_FILTER = (1 << 12),
668 RT_IDX_ETH_SKIP1 = (1 << 13),
669 RT_IDX_ETH_SKIP2 = (1 << 14),
670 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
671 RT_IDX_802_3 = (1 << 16),
672 RT_IDX_LLDP = (1 << 17),
673 RT_IDX_UNUSED018 = (1 << 18),
674 RT_IDX_UNUSED019 = (1 << 19),
675 RT_IDX_UNUSED20 = (1 << 20),
676 RT_IDX_UNUSED21 = (1 << 21),
677 RT_IDX_ERR = (1 << 22),
678 RT_IDX_VALID = (1 << 23),
679 RT_IDX_TU_CSUM_ERR = (1 << 24),
680 RT_IDX_IP_CSUM_ERR = (1 << 25),
681 RT_IDX_MAC_ERR = (1 << 26),
682 RT_IDX_RSS_TCP6 = (1 << 27),
683 RT_IDX_RSS_TCP4 = (1 << 28),
684 RT_IDX_RSS_IPV6 = (1 << 29),
685 RT_IDX_RSS_IPV4 = (1 << 30),
686 RT_IDX_RSS_MATCH = (1 << 31),
687
688 /* Hierarchy for the NIC Queue Mask */
689 RT_IDX_ALL_ERR_SLOT = 0,
690 RT_IDX_MAC_ERR_SLOT = 0,
691 RT_IDX_IP_CSUM_ERR_SLOT = 1,
692 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
693 RT_IDX_BCAST_SLOT = 3,
694 RT_IDX_MCAST_MATCH_SLOT = 4,
695 RT_IDX_ALLMULTI_SLOT = 5,
696 RT_IDX_UNUSED6_SLOT = 6,
697 RT_IDX_UNUSED7_SLOT = 7,
698 RT_IDX_RSS_MATCH_SLOT = 8,
699 RT_IDX_RSS_IPV4_SLOT = 8,
700 RT_IDX_RSS_IPV6_SLOT = 9,
701 RT_IDX_RSS_TCP4_SLOT = 10,
702 RT_IDX_RSS_TCP6_SLOT = 11,
703 RT_IDX_CAM_HIT_SLOT = 12,
704 RT_IDX_UNUSED013 = 13,
705 RT_IDX_UNUSED014 = 14,
706 RT_IDX_PROMISCUOUS_SLOT = 15,
707 RT_IDX_MAX_RT_SLOTS = 8,
708 RT_IDX_MAX_NIC_SLOTS = 16,
709 };
710
711 /*
712 * Serdes Address Register (XG_SERDES_ADDR) bit definitions.
713 */
714 enum {
715 XG_SERDES_ADDR_RDY = (1 << 31),
716 XG_SERDES_ADDR_R = (1 << 30),
717
718 XG_SERDES_ADDR_STS = 0x00001E06,
719 XG_SERDES_ADDR_XFI1_PWR_UP = 0x00000005,
720 XG_SERDES_ADDR_XFI2_PWR_UP = 0x0000000a,
721 XG_SERDES_ADDR_XAUI_PWR_DOWN = 0x00000001,
722
723 /* Serdes coredump definitions. */
724 XG_SERDES_XAUI_AN_START = 0x00000000,
725 XG_SERDES_XAUI_AN_END = 0x00000034,
726 XG_SERDES_XAUI_HSS_PCS_START = 0x00000800,
727 XG_SERDES_XAUI_HSS_PCS_END = 0x0000880,
728 XG_SERDES_XFI_AN_START = 0x00001000,
729 XG_SERDES_XFI_AN_END = 0x00001034,
730 XG_SERDES_XFI_TRAIN_START = 0x10001050,
731 XG_SERDES_XFI_TRAIN_END = 0x1000107C,
732 XG_SERDES_XFI_HSS_PCS_START = 0x00001800,
733 XG_SERDES_XFI_HSS_PCS_END = 0x00001838,
734 XG_SERDES_XFI_HSS_TX_START = 0x00001c00,
735 XG_SERDES_XFI_HSS_TX_END = 0x00001c1f,
736 XG_SERDES_XFI_HSS_RX_START = 0x00001c40,
737 XG_SERDES_XFI_HSS_RX_END = 0x00001c5f,
738 XG_SERDES_XFI_HSS_PLL_START = 0x00001e00,
739 XG_SERDES_XFI_HSS_PLL_END = 0x00001e1f,
740 };
741
742 /*
743 * NIC Probe Mux Address Register (PRB_MX_ADDR) bit definitions.
744 */
745 enum {
746 PRB_MX_ADDR_ARE = (1 << 16),
747 PRB_MX_ADDR_UP = (1 << 15),
748 PRB_MX_ADDR_SWP = (1 << 14),
749
750 /* Module select values. */
751 PRB_MX_ADDR_MAX_MODS = 21,
752 PRB_MX_ADDR_MOD_SEL_SHIFT = 9,
753 PRB_MX_ADDR_MOD_SEL_TBD = 0,
754 PRB_MX_ADDR_MOD_SEL_IDE1 = 1,
755 PRB_MX_ADDR_MOD_SEL_IDE2 = 2,
756 PRB_MX_ADDR_MOD_SEL_FRB = 3,
757 PRB_MX_ADDR_MOD_SEL_ODE1 = 4,
758 PRB_MX_ADDR_MOD_SEL_ODE2 = 5,
759 PRB_MX_ADDR_MOD_SEL_DA1 = 6,
760 PRB_MX_ADDR_MOD_SEL_DA2 = 7,
761 PRB_MX_ADDR_MOD_SEL_IMP1 = 8,
762 PRB_MX_ADDR_MOD_SEL_IMP2 = 9,
763 PRB_MX_ADDR_MOD_SEL_OMP1 = 10,
764 PRB_MX_ADDR_MOD_SEL_OMP2 = 11,
765 PRB_MX_ADDR_MOD_SEL_ORS1 = 12,
766 PRB_MX_ADDR_MOD_SEL_ORS2 = 13,
767 PRB_MX_ADDR_MOD_SEL_REG = 14,
768 PRB_MX_ADDR_MOD_SEL_MAC1 = 16,
769 PRB_MX_ADDR_MOD_SEL_MAC2 = 17,
770 PRB_MX_ADDR_MOD_SEL_VQM1 = 18,
771 PRB_MX_ADDR_MOD_SEL_VQM2 = 19,
772 PRB_MX_ADDR_MOD_SEL_MOP = 20,
773 /* Bit fields indicating which modules
774 * are valid for each clock domain.
775 */
776 PRB_MX_ADDR_VALID_SYS_MOD = 0x000f7ff7,
777 PRB_MX_ADDR_VALID_PCI_MOD = 0x000040c1,
778 PRB_MX_ADDR_VALID_XGM_MOD = 0x00037309,
779 PRB_MX_ADDR_VALID_FC_MOD = 0x00003001,
780 PRB_MX_ADDR_VALID_TOTAL = 34,
781
782 /* Clock domain values. */
783 PRB_MX_ADDR_CLOCK_SHIFT = 6,
784 PRB_MX_ADDR_SYS_CLOCK = 0,
785 PRB_MX_ADDR_PCI_CLOCK = 2,
786 PRB_MX_ADDR_FC_CLOCK = 5,
787 PRB_MX_ADDR_XGM_CLOCK = 6,
788
789 PRB_MX_ADDR_MAX_MUX = 64,
790 };
791
792 /*
793 * Control Register Set Map
794 */
795 enum {
796 PROC_ADDR = 0, /* Use semaphore */
797 PROC_DATA = 0x04, /* Use semaphore */
798 SYS = 0x08,
799 RST_FO = 0x0c,
800 FSC = 0x10,
801 CSR = 0x14,
802 LED = 0x18,
803 ICB_RID = 0x1c, /* Use semaphore */
804 ICB_L = 0x20, /* Use semaphore */
805 ICB_H = 0x24, /* Use semaphore */
806 CFG = 0x28,
807 BIOS_ADDR = 0x2c,
808 STS = 0x30,
809 INTR_EN = 0x34,
810 INTR_MASK = 0x38,
811 ISR1 = 0x3c,
812 ISR2 = 0x40,
813 ISR3 = 0x44,
814 ISR4 = 0x48,
815 REV_ID = 0x4c,
816 FRC_ECC_ERR = 0x50,
817 ERR_STS = 0x54,
818 RAM_DBG_ADDR = 0x58,
819 RAM_DBG_DATA = 0x5c,
820 ECC_ERR_CNT = 0x60,
821 SEM = 0x64,
822 GPIO_1 = 0x68, /* Use semaphore */
823 GPIO_2 = 0x6c, /* Use semaphore */
824 GPIO_3 = 0x70, /* Use semaphore */
825 RSVD2 = 0x74,
826 XGMAC_ADDR = 0x78, /* Use semaphore */
827 XGMAC_DATA = 0x7c, /* Use semaphore */
828 NIC_ETS = 0x80,
829 CNA_ETS = 0x84,
830 FLASH_ADDR = 0x88, /* Use semaphore */
831 FLASH_DATA = 0x8c, /* Use semaphore */
832 CQ_STOP = 0x90,
833 PAGE_TBL_RID = 0x94,
834 WQ_PAGE_TBL_LO = 0x98,
835 WQ_PAGE_TBL_HI = 0x9c,
836 CQ_PAGE_TBL_LO = 0xa0,
837 CQ_PAGE_TBL_HI = 0xa4,
838 MAC_ADDR_IDX = 0xa8, /* Use semaphore */
839 MAC_ADDR_DATA = 0xac, /* Use semaphore */
840 COS_DFLT_CQ1 = 0xb0,
841 COS_DFLT_CQ2 = 0xb4,
842 ETYPE_SKIP1 = 0xb8,
843 ETYPE_SKIP2 = 0xbc,
844 SPLT_HDR = 0xc0,
845 FC_PAUSE_THRES = 0xc4,
846 NIC_PAUSE_THRES = 0xc8,
847 FC_ETHERTYPE = 0xcc,
848 FC_RCV_CFG = 0xd0,
849 NIC_RCV_CFG = 0xd4,
850 FC_COS_TAGS = 0xd8,
851 NIC_COS_TAGS = 0xdc,
852 MGMT_RCV_CFG = 0xe0,
853 RT_IDX = 0xe4,
854 RT_DATA = 0xe8,
855 RSVD7 = 0xec,
856 XG_SERDES_ADDR = 0xf0,
857 XG_SERDES_DATA = 0xf4,
858 PRB_MX_ADDR = 0xf8, /* Use semaphore */
859 PRB_MX_DATA = 0xfc, /* Use semaphore */
860 };
861
862 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
863 #define SMALL_BUFFER_SIZE 256
864 #define SMALL_BUF_MAP_SIZE SMALL_BUFFER_SIZE
865 #define SPLT_SETTING FSC_DBRST_1024
866 #define SPLT_LEN 0
867 #define QLGE_SB_PAD 0
868 #else
869 #define SMALL_BUFFER_SIZE 512
870 #define SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2)
871 #define SPLT_SETTING FSC_SH
872 #define SPLT_LEN (SPLT_HDR_EP | \
873 min(SMALL_BUF_MAP_SIZE, 1023))
874 #define QLGE_SB_PAD 32
875 #endif
876
877 /*
878 * CAM output format.
879 */
880 enum {
881 CAM_OUT_ROUTE_FC = 0,
882 CAM_OUT_ROUTE_NIC = 1,
883 CAM_OUT_FUNC_SHIFT = 2,
884 CAM_OUT_RV = (1 << 4),
885 CAM_OUT_SH = (1 << 15),
886 CAM_OUT_CQ_ID_SHIFT = 5,
887 };
888
889 /*
890 * Mailbox definitions
891 */
892 enum {
893 /* Asynchronous Event Notifications */
894 AEN_SYS_ERR = 0x00008002,
895 AEN_LINK_UP = 0x00008011,
896 AEN_LINK_DOWN = 0x00008012,
897 AEN_IDC_CMPLT = 0x00008100,
898 AEN_IDC_REQ = 0x00008101,
899 AEN_IDC_EXT = 0x00008102,
900 AEN_DCBX_CHG = 0x00008110,
901 AEN_AEN_LOST = 0x00008120,
902 AEN_AEN_SFP_IN = 0x00008130,
903 AEN_AEN_SFP_OUT = 0x00008131,
904 AEN_FW_INIT_DONE = 0x00008400,
905 AEN_FW_INIT_FAIL = 0x00008401,
906
907 /* Mailbox Command Opcodes. */
908 MB_CMD_NOP = 0x00000000,
909 MB_CMD_EX_FW = 0x00000002,
910 MB_CMD_MB_TEST = 0x00000006,
911 MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */
912 MB_CMD_ABOUT_FW = 0x00000008,
913 MB_CMD_COPY_RISC_RAM = 0x0000000a,
914 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
915 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
916 MB_CMD_WRITE_RAM = 0x0000000d,
917 MB_CMD_INIT_RISC_RAM = 0x0000000e,
918 MB_CMD_READ_RAM = 0x0000000f,
919 MB_CMD_STOP_FW = 0x00000014,
920 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
921 MB_CMD_WRITE_SFP = 0x00000030,
922 MB_CMD_READ_SFP = 0x00000031,
923 MB_CMD_INIT_FW = 0x00000060,
924 MB_CMD_GET_IFCB = 0x00000061,
925 MB_CMD_GET_FW_STATE = 0x00000069,
926 MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */
927 MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */
928 MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */
929 MB_WOL_DISABLE = 0,
930 MB_WOL_MAGIC_PKT = (1 << 1),
931 MB_WOL_FLTR = (1 << 2),
932 MB_WOL_UCAST = (1 << 3),
933 MB_WOL_MCAST = (1 << 4),
934 MB_WOL_BCAST = (1 << 5),
935 MB_WOL_LINK_UP = (1 << 6),
936 MB_WOL_LINK_DOWN = (1 << 7),
937 MB_WOL_MODE_ON = (1 << 16), /* Wake on Lan Mode on */
938 MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */
939 MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
940 MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */
941 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
942 MB_CMD_SET_WOL_IMMED = 0x00000115,
943 MB_CMD_PORT_RESET = 0x00000120,
944 MB_CMD_SET_PORT_CFG = 0x00000122,
945 MB_CMD_GET_PORT_CFG = 0x00000123,
946 MB_CMD_GET_LINK_STS = 0x00000124,
947 MB_CMD_SET_LED_CFG = 0x00000125, /* Set LED Configuration Register */
948 QL_LED_BLINK = 0x03e803e8,
949 MB_CMD_GET_LED_CFG = 0x00000126, /* Get LED Configuration Register */
950 MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160, /* Set Mgmnt Traffic Control */
951 MB_SET_MPI_TFK_STOP = (1 << 0),
952 MB_SET_MPI_TFK_RESUME = (1 << 1),
953 MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161, /* Get Mgmnt Traffic Control */
954 MB_GET_MPI_TFK_STOPPED = (1 << 0),
955 MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1),
956 /* Sub-commands for IDC request.
957 * This describes the reason for the
958 * IDC request.
959 */
960 MB_CMD_IOP_NONE = 0x0000,
961 MB_CMD_IOP_PREP_UPDATE_MPI = 0x0001,
962 MB_CMD_IOP_COMP_UPDATE_MPI = 0x0002,
963 MB_CMD_IOP_PREP_LINK_DOWN = 0x0010,
964 MB_CMD_IOP_DVR_START = 0x0100,
965 MB_CMD_IOP_FLASH_ACC = 0x0101,
966 MB_CMD_IOP_RESTART_MPI = 0x0102,
967 MB_CMD_IOP_CORE_DUMP_MPI = 0x0103,
968
969 /* Mailbox Command Status. */
970 MB_CMD_STS_GOOD = 0x00004000, /* Success. */
971 MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */
972 MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */
973 MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */
974 MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */
975 MB_CMD_STS_ERR = 0x00004005, /* System Error. */
976 MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */
977 };
978
979 struct mbox_params {
980 u32 mbox_in[MAILBOX_COUNT];
981 u32 mbox_out[MAILBOX_COUNT];
982 int in_count;
983 int out_count;
984 };
985
986 struct flash_params_8012 {
987 u8 dev_id_str[4];
988 __le16 size;
989 __le16 csum;
990 __le16 ver;
991 __le16 sub_dev_id;
992 u8 mac_addr[6];
993 __le16 res;
994 };
995
996 /* 8000 device's flash is a different structure
997 * at a different offset in flash.
998 */
999 #define FUNC0_FLASH_OFFSET 0x140200
1000 #define FUNC1_FLASH_OFFSET 0x140600
1001
1002 /* Flash related data structures. */
1003 struct flash_params_8000 {
1004 u8 dev_id_str[4]; /* "8000" */
1005 __le16 ver;
1006 __le16 size;
1007 __le16 csum;
1008 __le16 reserved0;
1009 __le16 total_size;
1010 __le16 entry_count;
1011 u8 data_type0;
1012 u8 data_size0;
1013 u8 mac_addr[6];
1014 u8 data_type1;
1015 u8 data_size1;
1016 u8 mac_addr1[6];
1017 u8 data_type2;
1018 u8 data_size2;
1019 __le16 vlan_id;
1020 u8 data_type3;
1021 u8 data_size3;
1022 __le16 last;
1023 u8 reserved1[464];
1024 __le16 subsys_ven_id;
1025 __le16 subsys_dev_id;
1026 u8 reserved2[4];
1027 };
1028
1029 union flash_params {
1030 struct flash_params_8012 flash_params_8012;
1031 struct flash_params_8000 flash_params_8000;
1032 };
1033
1034 /*
1035 * doorbell space for the rx ring context
1036 */
1037 struct rx_doorbell_context {
1038 u32 cnsmr_idx; /* 0x00 */
1039 u32 valid; /* 0x04 */
1040 u32 reserved[4]; /* 0x08-0x14 */
1041 u32 lbq_prod_idx; /* 0x18 */
1042 u32 sbq_prod_idx; /* 0x1c */
1043 };
1044
1045 /*
1046 * doorbell space for the tx ring context
1047 */
1048 struct tx_doorbell_context {
1049 u32 prod_idx; /* 0x00 */
1050 u32 valid; /* 0x04 */
1051 u32 reserved[4]; /* 0x08-0x14 */
1052 u32 lbq_prod_idx; /* 0x18 */
1053 u32 sbq_prod_idx; /* 0x1c */
1054 };
1055
1056 /* DATA STRUCTURES SHARED WITH HARDWARE. */
1057 struct tx_buf_desc {
1058 __le64 addr;
1059 __le32 len;
1060 #define TX_DESC_LEN_MASK 0x000fffff
1061 #define TX_DESC_C 0x40000000
1062 #define TX_DESC_E 0x80000000
1063 } __packed;
1064
1065 /*
1066 * IOCB Definitions...
1067 */
1068
1069 #define OPCODE_OB_MAC_IOCB 0x01
1070 #define OPCODE_OB_MAC_TSO_IOCB 0x02
1071 #define OPCODE_IB_MAC_IOCB 0x20
1072 #define OPCODE_IB_MPI_IOCB 0x21
1073 #define OPCODE_IB_AE_IOCB 0x3f
1074
1075 struct ob_mac_iocb_req {
1076 u8 opcode;
1077 u8 flags1;
1078 #define OB_MAC_IOCB_REQ_OI 0x01
1079 #define OB_MAC_IOCB_REQ_I 0x02
1080 #define OB_MAC_IOCB_REQ_D 0x08
1081 #define OB_MAC_IOCB_REQ_F 0x10
1082 u8 flags2;
1083 u8 flags3;
1084 #define OB_MAC_IOCB_DFP 0x02
1085 #define OB_MAC_IOCB_V 0x04
1086 __le32 reserved1[2];
1087 __le16 frame_len;
1088 #define OB_MAC_IOCB_LEN_MASK 0x3ffff
1089 __le16 reserved2;
1090 u32 tid;
1091 u32 txq_idx;
1092 __le32 reserved3;
1093 __le16 vlan_tci;
1094 __le16 reserved4;
1095 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1096 } __packed;
1097
1098 struct ob_mac_iocb_rsp {
1099 u8 opcode; /* */
1100 u8 flags1; /* */
1101 #define OB_MAC_IOCB_RSP_OI 0x01 /* */
1102 #define OB_MAC_IOCB_RSP_I 0x02 /* */
1103 #define OB_MAC_IOCB_RSP_E 0x08 /* */
1104 #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
1105 #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
1106 #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
1107 u8 flags2; /* */
1108 u8 flags3; /* */
1109 #define OB_MAC_IOCB_RSP_B 0x80 /* */
1110 u32 tid;
1111 u32 txq_idx;
1112 __le32 reserved[13];
1113 } __packed;
1114
1115 struct ob_mac_tso_iocb_req {
1116 u8 opcode;
1117 u8 flags1;
1118 #define OB_MAC_TSO_IOCB_OI 0x01
1119 #define OB_MAC_TSO_IOCB_I 0x02
1120 #define OB_MAC_TSO_IOCB_D 0x08
1121 #define OB_MAC_TSO_IOCB_IP4 0x40
1122 #define OB_MAC_TSO_IOCB_IP6 0x80
1123 u8 flags2;
1124 #define OB_MAC_TSO_IOCB_LSO 0x20
1125 #define OB_MAC_TSO_IOCB_UC 0x40
1126 #define OB_MAC_TSO_IOCB_TC 0x80
1127 u8 flags3;
1128 #define OB_MAC_TSO_IOCB_IC 0x01
1129 #define OB_MAC_TSO_IOCB_DFP 0x02
1130 #define OB_MAC_TSO_IOCB_V 0x04
1131 __le32 reserved1[2];
1132 __le32 frame_len;
1133 u32 tid;
1134 u32 txq_idx;
1135 __le16 total_hdrs_len;
1136 __le16 net_trans_offset;
1137 #define OB_MAC_TRANSPORT_HDR_SHIFT 6
1138 __le16 vlan_tci;
1139 __le16 mss;
1140 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1141 } __packed;
1142
1143 struct ob_mac_tso_iocb_rsp {
1144 u8 opcode;
1145 u8 flags1;
1146 #define OB_MAC_TSO_IOCB_RSP_OI 0x01
1147 #define OB_MAC_TSO_IOCB_RSP_I 0x02
1148 #define OB_MAC_TSO_IOCB_RSP_E 0x08
1149 #define OB_MAC_TSO_IOCB_RSP_S 0x10
1150 #define OB_MAC_TSO_IOCB_RSP_L 0x20
1151 #define OB_MAC_TSO_IOCB_RSP_P 0x40
1152 u8 flags2; /* */
1153 u8 flags3; /* */
1154 #define OB_MAC_TSO_IOCB_RSP_B 0x8000
1155 u32 tid;
1156 u32 txq_idx;
1157 __le32 reserved2[13];
1158 } __packed;
1159
1160 struct ib_mac_iocb_rsp {
1161 u8 opcode; /* 0x20 */
1162 u8 flags1;
1163 #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
1164 #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
1165 #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */
1166 #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
1167 #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
1168 #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
1169 #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
1170 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
1171 #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
1172 #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
1173 #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
1174 #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
1175 u8 flags2;
1176 #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
1177 #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
1178 #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
1179 #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1180 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1181 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1182 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1183 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1184 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1185 #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
1186 #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
1187 #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
1188 u8 flags3;
1189 #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
1190 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
1191 #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
1192 #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
1193 #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
1194 #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
1195 #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
1196 #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
1197 #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
1198 #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
1199 #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
1200 __le32 data_len; /* */
1201 __le64 data_addr; /* */
1202 __le32 rss; /* */
1203 __le16 vlan_id; /* 12 bits */
1204 #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
1205 #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
1206 #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
1207
1208 __le16 reserved1;
1209 __le32 reserved2[6];
1210 u8 reserved3[3];
1211 u8 flags4;
1212 #define IB_MAC_IOCB_RSP_HV 0x20
1213 #define IB_MAC_IOCB_RSP_HS 0x40
1214 #define IB_MAC_IOCB_RSP_HL 0x80
1215 __le32 hdr_len; /* */
1216 __le64 hdr_addr; /* */
1217 } __packed;
1218
1219 struct ib_ae_iocb_rsp {
1220 u8 opcode;
1221 u8 flags1;
1222 #define IB_AE_IOCB_RSP_OI 0x01
1223 #define IB_AE_IOCB_RSP_I 0x02
1224 u8 event;
1225 #define LINK_UP_EVENT 0x00
1226 #define LINK_DOWN_EVENT 0x01
1227 #define CAM_LOOKUP_ERR_EVENT 0x06
1228 #define SOFT_ECC_ERROR_EVENT 0x07
1229 #define MGMT_ERR_EVENT 0x08
1230 #define TEN_GIG_MAC_EVENT 0x09
1231 #define GPI0_H2L_EVENT 0x10
1232 #define GPI0_L2H_EVENT 0x20
1233 #define GPI1_H2L_EVENT 0x11
1234 #define GPI1_L2H_EVENT 0x21
1235 #define PCI_ERR_ANON_BUF_RD 0x40
1236 u8 q_id;
1237 __le32 reserved[15];
1238 } __packed;
1239
1240 /*
1241 * These three structures are for generic
1242 * handling of ib and ob iocbs.
1243 */
1244 struct ql_net_rsp_iocb {
1245 u8 opcode;
1246 u8 flags0;
1247 __le16 length;
1248 __le32 tid;
1249 __le32 reserved[14];
1250 } __packed;
1251
1252 struct net_req_iocb {
1253 u8 opcode;
1254 u8 flags0;
1255 __le16 flags1;
1256 __le32 tid;
1257 __le32 reserved1[30];
1258 } __packed;
1259
1260 /*
1261 * tx ring initialization control block for chip.
1262 * It is defined as:
1263 * "Work Queue Initialization Control Block"
1264 */
1265 struct wqicb {
1266 __le16 len;
1267 #define Q_LEN_V (1 << 4)
1268 #define Q_LEN_CPP_CONT 0x0000
1269 #define Q_LEN_CPP_16 0x0001
1270 #define Q_LEN_CPP_32 0x0002
1271 #define Q_LEN_CPP_64 0x0003
1272 #define Q_LEN_CPP_512 0x0006
1273 __le16 flags;
1274 #define Q_PRI_SHIFT 1
1275 #define Q_FLAGS_LC 0x1000
1276 #define Q_FLAGS_LB 0x2000
1277 #define Q_FLAGS_LI 0x4000
1278 #define Q_FLAGS_LO 0x8000
1279 __le16 cq_id_rss;
1280 #define Q_CQ_ID_RSS_RV 0x8000
1281 __le16 rid;
1282 __le64 addr;
1283 __le64 cnsmr_idx_addr;
1284 } __packed;
1285
1286 /*
1287 * rx ring initialization control block for chip.
1288 * It is defined as:
1289 * "Completion Queue Initialization Control Block"
1290 */
1291 struct cqicb {
1292 u8 msix_vect;
1293 u8 reserved1;
1294 u8 reserved2;
1295 u8 flags;
1296 #define FLAGS_LV 0x08
1297 #define FLAGS_LS 0x10
1298 #define FLAGS_LL 0x20
1299 #define FLAGS_LI 0x40
1300 #define FLAGS_LC 0x80
1301 __le16 len;
1302 #define LEN_V (1 << 4)
1303 #define LEN_CPP_CONT 0x0000
1304 #define LEN_CPP_32 0x0001
1305 #define LEN_CPP_64 0x0002
1306 #define LEN_CPP_128 0x0003
1307 __le16 rid;
1308 __le64 addr;
1309 __le64 prod_idx_addr;
1310 __le16 pkt_delay;
1311 __le16 irq_delay;
1312 __le64 lbq_addr;
1313 __le16 lbq_buf_size;
1314 __le16 lbq_len; /* entry count */
1315 __le64 sbq_addr;
1316 __le16 sbq_buf_size;
1317 __le16 sbq_len; /* entry count */
1318 } __packed;
1319
1320 struct ricb {
1321 u8 base_cq;
1322 #define RSS_L4K 0x80
1323 u8 flags;
1324 #define RSS_L6K 0x01
1325 #define RSS_LI 0x02
1326 #define RSS_LB 0x04
1327 #define RSS_LM 0x08
1328 #define RSS_RI4 0x10
1329 #define RSS_RT4 0x20
1330 #define RSS_RI6 0x40
1331 #define RSS_RT6 0x80
1332 __le16 mask;
1333 u8 hash_cq_id[1024];
1334 __le32 ipv6_hash_key[10];
1335 __le32 ipv4_hash_key[4];
1336 } __packed;
1337
1338 /* SOFTWARE/DRIVER DATA STRUCTURES. */
1339
1340 struct oal {
1341 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1342 };
1343
1344 struct map_list {
1345 DEFINE_DMA_UNMAP_ADDR(mapaddr);
1346 DEFINE_DMA_UNMAP_LEN(maplen);
1347 };
1348
1349 struct tx_ring_desc {
1350 struct sk_buff *skb;
1351 struct ob_mac_iocb_req *queue_entry;
1352 u32 index;
1353 struct oal oal;
1354 struct map_list map[MAX_SKB_FRAGS + 2];
1355 int map_cnt;
1356 struct tx_ring_desc *next;
1357 };
1358
1359 struct page_chunk {
1360 struct page *page; /* master page */
1361 char *va; /* virt addr for this chunk */
1362 u64 map; /* mapping for master */
1363 unsigned int offset; /* offset for this chunk */
1364 unsigned int last_flag; /* flag set for last chunk in page */
1365 };
1366
1367 struct bq_desc {
1368 union {
1369 struct page_chunk pg_chunk;
1370 struct sk_buff *skb;
1371 } p;
1372 __le64 *addr;
1373 u32 index;
1374 DEFINE_DMA_UNMAP_ADDR(mapaddr);
1375 DEFINE_DMA_UNMAP_LEN(maplen);
1376 };
1377
1378 #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1379
1380 struct tx_ring {
1381 /*
1382 * queue info.
1383 */
1384 struct wqicb wqicb; /* structure used to inform chip of new queue */
1385 void *wq_base; /* pci_alloc:virtual addr for tx */
1386 dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */
1387 __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */
1388 dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */
1389 u32 wq_size; /* size in bytes of queue area */
1390 u32 wq_len; /* number of entries in queue */
1391 void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */
1392 void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */
1393 u16 prod_idx; /* current value for prod idx */
1394 u16 cq_id; /* completion (rx) queue for tx completions */
1395 u8 wq_id; /* queue id for this entry */
1396 u8 reserved1[3];
1397 struct tx_ring_desc *q; /* descriptor list for the queue */
1398 spinlock_t lock;
1399 atomic_t tx_count; /* counts down for every outstanding IO */
1400 atomic_t queue_stopped; /* Turns queue off when full. */
1401 struct delayed_work tx_work;
1402 struct ql_adapter *qdev;
1403 u64 tx_packets;
1404 u64 tx_bytes;
1405 u64 tx_errors;
1406 };
1407
1408 /*
1409 * Type of inbound queue.
1410 */
1411 enum {
1412 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */
1413 TX_Q = 3, /* Handles outbound completions. */
1414 RX_Q = 4, /* Handles inbound completions. */
1415 };
1416
1417 struct rx_ring {
1418 struct cqicb cqicb; /* The chip's completion queue init control block. */
1419
1420 /* Completion queue elements. */
1421 void *cq_base;
1422 dma_addr_t cq_base_dma;
1423 u32 cq_size;
1424 u32 cq_len;
1425 u16 cq_id;
1426 __le32 *prod_idx_sh_reg; /* Shadowed producer register. */
1427 dma_addr_t prod_idx_sh_reg_dma;
1428 void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */
1429 u32 cnsmr_idx; /* current sw idx */
1430 struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */
1431 void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */
1432
1433 /* Large buffer queue elements. */
1434 u32 lbq_len; /* entry count */
1435 u32 lbq_size; /* size in bytes of queue */
1436 u32 lbq_buf_size;
1437 void *lbq_base;
1438 dma_addr_t lbq_base_dma;
1439 void *lbq_base_indirect;
1440 dma_addr_t lbq_base_indirect_dma;
1441 struct page_chunk pg_chunk; /* current page for chunks */
1442 struct bq_desc *lbq; /* array of control blocks */
1443 void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */
1444 u32 lbq_prod_idx; /* current sw prod idx */
1445 u32 lbq_curr_idx; /* next entry we expect */
1446 u32 lbq_clean_idx; /* beginning of new descs */
1447 u32 lbq_free_cnt; /* free buffer desc cnt */
1448
1449 /* Small buffer queue elements. */
1450 u32 sbq_len; /* entry count */
1451 u32 sbq_size; /* size in bytes of queue */
1452 u32 sbq_buf_size;
1453 void *sbq_base;
1454 dma_addr_t sbq_base_dma;
1455 void *sbq_base_indirect;
1456 dma_addr_t sbq_base_indirect_dma;
1457 struct bq_desc *sbq; /* array of control blocks */
1458 void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */
1459 u32 sbq_prod_idx; /* current sw prod idx */
1460 u32 sbq_curr_idx; /* next entry we expect */
1461 u32 sbq_clean_idx; /* beginning of new descs */
1462 u32 sbq_free_cnt; /* free buffer desc cnt */
1463
1464 /* Misc. handler elements. */
1465 u32 type; /* Type of queue, tx, rx. */
1466 u32 irq; /* Which vector this ring is assigned. */
1467 u32 cpu; /* Which CPU this should run on. */
1468 char name[IFNAMSIZ + 5];
1469 struct napi_struct napi;
1470 u8 reserved;
1471 struct ql_adapter *qdev;
1472 u64 rx_packets;
1473 u64 rx_multicast;
1474 u64 rx_bytes;
1475 u64 rx_dropped;
1476 u64 rx_errors;
1477 };
1478
1479 /*
1480 * RSS Initialization Control Block
1481 */
1482 struct hash_id {
1483 u8 value[4];
1484 };
1485
1486 struct nic_stats {
1487 /*
1488 * These stats come from offset 200h to 278h
1489 * in the XGMAC register.
1490 */
1491 u64 tx_pkts;
1492 u64 tx_bytes;
1493 u64 tx_mcast_pkts;
1494 u64 tx_bcast_pkts;
1495 u64 tx_ucast_pkts;
1496 u64 tx_ctl_pkts;
1497 u64 tx_pause_pkts;
1498 u64 tx_64_pkt;
1499 u64 tx_65_to_127_pkt;
1500 u64 tx_128_to_255_pkt;
1501 u64 tx_256_511_pkt;
1502 u64 tx_512_to_1023_pkt;
1503 u64 tx_1024_to_1518_pkt;
1504 u64 tx_1519_to_max_pkt;
1505 u64 tx_undersize_pkt;
1506 u64 tx_oversize_pkt;
1507
1508 /*
1509 * These stats come from offset 300h to 3C8h
1510 * in the XGMAC register.
1511 */
1512 u64 rx_bytes;
1513 u64 rx_bytes_ok;
1514 u64 rx_pkts;
1515 u64 rx_pkts_ok;
1516 u64 rx_bcast_pkts;
1517 u64 rx_mcast_pkts;
1518 u64 rx_ucast_pkts;
1519 u64 rx_undersize_pkts;
1520 u64 rx_oversize_pkts;
1521 u64 rx_jabber_pkts;
1522 u64 rx_undersize_fcerr_pkts;
1523 u64 rx_drop_events;
1524 u64 rx_fcerr_pkts;
1525 u64 rx_align_err;
1526 u64 rx_symbol_err;
1527 u64 rx_mac_err;
1528 u64 rx_ctl_pkts;
1529 u64 rx_pause_pkts;
1530 u64 rx_64_pkts;
1531 u64 rx_65_to_127_pkts;
1532 u64 rx_128_255_pkts;
1533 u64 rx_256_511_pkts;
1534 u64 rx_512_to_1023_pkts;
1535 u64 rx_1024_to_1518_pkts;
1536 u64 rx_1519_to_max_pkts;
1537 u64 rx_len_err_pkts;
1538 /*
1539 * These stats come from offset 500h to 5C8h
1540 * in the XGMAC register.
1541 */
1542 u64 tx_cbfc_pause_frames0;
1543 u64 tx_cbfc_pause_frames1;
1544 u64 tx_cbfc_pause_frames2;
1545 u64 tx_cbfc_pause_frames3;
1546 u64 tx_cbfc_pause_frames4;
1547 u64 tx_cbfc_pause_frames5;
1548 u64 tx_cbfc_pause_frames6;
1549 u64 tx_cbfc_pause_frames7;
1550 u64 rx_cbfc_pause_frames0;
1551 u64 rx_cbfc_pause_frames1;
1552 u64 rx_cbfc_pause_frames2;
1553 u64 rx_cbfc_pause_frames3;
1554 u64 rx_cbfc_pause_frames4;
1555 u64 rx_cbfc_pause_frames5;
1556 u64 rx_cbfc_pause_frames6;
1557 u64 rx_cbfc_pause_frames7;
1558 u64 rx_nic_fifo_drop;
1559 };
1560
1561 /* Firmware coredump internal register address/length pairs. */
1562 enum {
1563 MPI_CORE_REGS_ADDR = 0x00030000,
1564 MPI_CORE_REGS_CNT = 127,
1565 MPI_CORE_SH_REGS_CNT = 16,
1566 TEST_REGS_ADDR = 0x00001000,
1567 TEST_REGS_CNT = 23,
1568 RMII_REGS_ADDR = 0x00001040,
1569 RMII_REGS_CNT = 64,
1570 FCMAC1_REGS_ADDR = 0x00001080,
1571 FCMAC2_REGS_ADDR = 0x000010c0,
1572 FCMAC_REGS_CNT = 64,
1573 FC1_MBX_REGS_ADDR = 0x00001100,
1574 FC2_MBX_REGS_ADDR = 0x00001240,
1575 FC_MBX_REGS_CNT = 64,
1576 IDE_REGS_ADDR = 0x00001140,
1577 IDE_REGS_CNT = 64,
1578 NIC1_MBX_REGS_ADDR = 0x00001180,
1579 NIC2_MBX_REGS_ADDR = 0x00001280,
1580 NIC_MBX_REGS_CNT = 64,
1581 SMBUS_REGS_ADDR = 0x00001200,
1582 SMBUS_REGS_CNT = 64,
1583 I2C_REGS_ADDR = 0x00001fc0,
1584 I2C_REGS_CNT = 64,
1585 MEMC_REGS_ADDR = 0x00003000,
1586 MEMC_REGS_CNT = 256,
1587 PBUS_REGS_ADDR = 0x00007c00,
1588 PBUS_REGS_CNT = 256,
1589 MDE_REGS_ADDR = 0x00010000,
1590 MDE_REGS_CNT = 6,
1591 CODE_RAM_ADDR = 0x00020000,
1592 CODE_RAM_CNT = 0x2000,
1593 MEMC_RAM_ADDR = 0x00100000,
1594 MEMC_RAM_CNT = 0x2000,
1595 };
1596
1597 #define MPI_COREDUMP_COOKIE 0x5555aaaa
1598 struct mpi_coredump_global_header {
1599 u32 cookie;
1600 u8 idString[16];
1601 u32 timeLo;
1602 u32 timeHi;
1603 u32 imageSize;
1604 u32 headerSize;
1605 u8 info[220];
1606 };
1607
1608 struct mpi_coredump_segment_header {
1609 u32 cookie;
1610 u32 segNum;
1611 u32 segSize;
1612 u32 extra;
1613 u8 description[16];
1614 };
1615
1616 /* Firmware coredump header segment numbers. */
1617 enum {
1618 CORE_SEG_NUM = 1,
1619 TEST_LOGIC_SEG_NUM = 2,
1620 RMII_SEG_NUM = 3,
1621 FCMAC1_SEG_NUM = 4,
1622 FCMAC2_SEG_NUM = 5,
1623 FC1_MBOX_SEG_NUM = 6,
1624 IDE_SEG_NUM = 7,
1625 NIC1_MBOX_SEG_NUM = 8,
1626 SMBUS_SEG_NUM = 9,
1627 FC2_MBOX_SEG_NUM = 10,
1628 NIC2_MBOX_SEG_NUM = 11,
1629 I2C_SEG_NUM = 12,
1630 MEMC_SEG_NUM = 13,
1631 PBUS_SEG_NUM = 14,
1632 MDE_SEG_NUM = 15,
1633 NIC1_CONTROL_SEG_NUM = 16,
1634 NIC2_CONTROL_SEG_NUM = 17,
1635 NIC1_XGMAC_SEG_NUM = 18,
1636 NIC2_XGMAC_SEG_NUM = 19,
1637 WCS_RAM_SEG_NUM = 20,
1638 MEMC_RAM_SEG_NUM = 21,
1639 XAUI_AN_SEG_NUM = 22,
1640 XAUI_HSS_PCS_SEG_NUM = 23,
1641 XFI_AN_SEG_NUM = 24,
1642 XFI_TRAIN_SEG_NUM = 25,
1643 XFI_HSS_PCS_SEG_NUM = 26,
1644 XFI_HSS_TX_SEG_NUM = 27,
1645 XFI_HSS_RX_SEG_NUM = 28,
1646 XFI_HSS_PLL_SEG_NUM = 29,
1647 MISC_NIC_INFO_SEG_NUM = 30,
1648 INTR_STATES_SEG_NUM = 31,
1649 CAM_ENTRIES_SEG_NUM = 32,
1650 ROUTING_WORDS_SEG_NUM = 33,
1651 ETS_SEG_NUM = 34,
1652 PROBE_DUMP_SEG_NUM = 35,
1653 ROUTING_INDEX_SEG_NUM = 36,
1654 MAC_PROTOCOL_SEG_NUM = 37,
1655 XAUI2_AN_SEG_NUM = 38,
1656 XAUI2_HSS_PCS_SEG_NUM = 39,
1657 XFI2_AN_SEG_NUM = 40,
1658 XFI2_TRAIN_SEG_NUM = 41,
1659 XFI2_HSS_PCS_SEG_NUM = 42,
1660 XFI2_HSS_TX_SEG_NUM = 43,
1661 XFI2_HSS_RX_SEG_NUM = 44,
1662 XFI2_HSS_PLL_SEG_NUM = 45,
1663 SEM_REGS_SEG_NUM = 50
1664
1665 };
1666
1667 /* There are 64 generic NIC registers. */
1668 #define NIC_REGS_DUMP_WORD_COUNT 64
1669 /* XGMAC word count. */
1670 #define XGMAC_DUMP_WORD_COUNT (XGMAC_REGISTER_END / 4)
1671 /* Word counts for the SERDES blocks. */
1672 #define XG_SERDES_XAUI_AN_COUNT 14
1673 #define XG_SERDES_XAUI_HSS_PCS_COUNT 33
1674 #define XG_SERDES_XFI_AN_COUNT 14
1675 #define XG_SERDES_XFI_TRAIN_COUNT 12
1676 #define XG_SERDES_XFI_HSS_PCS_COUNT 15
1677 #define XG_SERDES_XFI_HSS_TX_COUNT 32
1678 #define XG_SERDES_XFI_HSS_RX_COUNT 32
1679 #define XG_SERDES_XFI_HSS_PLL_COUNT 32
1680
1681 /* There are 2 CNA ETS and 8 NIC ETS registers. */
1682 #define ETS_REGS_DUMP_WORD_COUNT 10
1683
1684 /* Each probe mux entry stores the probe type plus 64 entries
1685 * that are each each 64-bits in length. There are a total of
1686 * 34 (PRB_MX_ADDR_VALID_TOTAL) valid probes.
1687 */
1688 #define PRB_MX_ADDR_PRB_WORD_COUNT (1 + (PRB_MX_ADDR_MAX_MUX * 2))
1689 #define PRB_MX_DUMP_TOT_COUNT (PRB_MX_ADDR_PRB_WORD_COUNT * \
1690 PRB_MX_ADDR_VALID_TOTAL)
1691 /* Each routing entry consists of 4 32-bit words.
1692 * They are route type, index, index word, and result.
1693 * There are 2 route blocks with 8 entries each and
1694 * 2 NIC blocks with 16 entries each.
1695 * The totol entries is 48 with 4 words each.
1696 */
1697 #define RT_IDX_DUMP_ENTRIES 48
1698 #define RT_IDX_DUMP_WORDS_PER_ENTRY 4
1699 #define RT_IDX_DUMP_TOT_WORDS (RT_IDX_DUMP_ENTRIES * \
1700 RT_IDX_DUMP_WORDS_PER_ENTRY)
1701 /* There are 10 address blocks in filter, each with
1702 * different entry counts and different word-count-per-entry.
1703 */
1704 #define MAC_ADDR_DUMP_ENTRIES \
1705 ((MAC_ADDR_MAX_CAM_ENTRIES * MAC_ADDR_MAX_CAM_WCOUNT) + \
1706 (MAC_ADDR_MAX_MULTICAST_ENTRIES * MAC_ADDR_MAX_MULTICAST_WCOUNT) + \
1707 (MAC_ADDR_MAX_VLAN_ENTRIES * MAC_ADDR_MAX_VLAN_WCOUNT) + \
1708 (MAC_ADDR_MAX_MCAST_FLTR_ENTRIES * MAC_ADDR_MAX_MCAST_FLTR_WCOUNT) + \
1709 (MAC_ADDR_MAX_FC_MAC_ENTRIES * MAC_ADDR_MAX_FC_MAC_WCOUNT) + \
1710 (MAC_ADDR_MAX_MGMT_MAC_ENTRIES * MAC_ADDR_MAX_MGMT_MAC_WCOUNT) + \
1711 (MAC_ADDR_MAX_MGMT_VLAN_ENTRIES * MAC_ADDR_MAX_MGMT_VLAN_WCOUNT) + \
1712 (MAC_ADDR_MAX_MGMT_V4_ENTRIES * MAC_ADDR_MAX_MGMT_V4_WCOUNT) + \
1713 (MAC_ADDR_MAX_MGMT_V6_ENTRIES * MAC_ADDR_MAX_MGMT_V6_WCOUNT) + \
1714 (MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES * MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT))
1715 #define MAC_ADDR_DUMP_WORDS_PER_ENTRY 2
1716 #define MAC_ADDR_DUMP_TOT_WORDS (MAC_ADDR_DUMP_ENTRIES * \
1717 MAC_ADDR_DUMP_WORDS_PER_ENTRY)
1718 /* Maximum of 4 functions whose semaphore registeres are
1719 * in the coredump.
1720 */
1721 #define MAX_SEMAPHORE_FUNCTIONS 4
1722 /* Defines for access the MPI shadow registers. */
1723 #define RISC_124 0x0003007c
1724 #define RISC_127 0x0003007f
1725 #define SHADOW_OFFSET 0xb0000000
1726 #define SHADOW_REG_SHIFT 20
1727
1728 struct ql_nic_misc {
1729 u32 rx_ring_count;
1730 u32 tx_ring_count;
1731 u32 intr_count;
1732 u32 function;
1733 };
1734
1735 struct ql_reg_dump {
1736
1737 /* segment 0 */
1738 struct mpi_coredump_global_header mpi_global_header;
1739
1740 /* segment 16 */
1741 struct mpi_coredump_segment_header nic_regs_seg_hdr;
1742 u32 nic_regs[64];
1743
1744 /* segment 30 */
1745 struct mpi_coredump_segment_header misc_nic_seg_hdr;
1746 struct ql_nic_misc misc_nic_info;
1747
1748 /* segment 31 */
1749 /* one interrupt state for each CQ */
1750 struct mpi_coredump_segment_header intr_states_seg_hdr;
1751 u32 intr_states[MAX_CPUS];
1752
1753 /* segment 32 */
1754 /* 3 cam words each for 16 unicast,
1755 * 2 cam words for each of 32 multicast.
1756 */
1757 struct mpi_coredump_segment_header cam_entries_seg_hdr;
1758 u32 cam_entries[(16 * 3) + (32 * 3)];
1759
1760 /* segment 33 */
1761 struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1762 u32 nic_routing_words[16];
1763
1764 /* segment 34 */
1765 struct mpi_coredump_segment_header ets_seg_hdr;
1766 u32 ets[8+2];
1767 };
1768
1769 struct ql_mpi_coredump {
1770 /* segment 0 */
1771 struct mpi_coredump_global_header mpi_global_header;
1772
1773 /* segment 1 */
1774 struct mpi_coredump_segment_header core_regs_seg_hdr;
1775 u32 mpi_core_regs[MPI_CORE_REGS_CNT];
1776 u32 mpi_core_sh_regs[MPI_CORE_SH_REGS_CNT];
1777
1778 /* segment 2 */
1779 struct mpi_coredump_segment_header test_logic_regs_seg_hdr;
1780 u32 test_logic_regs[TEST_REGS_CNT];
1781
1782 /* segment 3 */
1783 struct mpi_coredump_segment_header rmii_regs_seg_hdr;
1784 u32 rmii_regs[RMII_REGS_CNT];
1785
1786 /* segment 4 */
1787 struct mpi_coredump_segment_header fcmac1_regs_seg_hdr;
1788 u32 fcmac1_regs[FCMAC_REGS_CNT];
1789
1790 /* segment 5 */
1791 struct mpi_coredump_segment_header fcmac2_regs_seg_hdr;
1792 u32 fcmac2_regs[FCMAC_REGS_CNT];
1793
1794 /* segment 6 */
1795 struct mpi_coredump_segment_header fc1_mbx_regs_seg_hdr;
1796 u32 fc1_mbx_regs[FC_MBX_REGS_CNT];
1797
1798 /* segment 7 */
1799 struct mpi_coredump_segment_header ide_regs_seg_hdr;
1800 u32 ide_regs[IDE_REGS_CNT];
1801
1802 /* segment 8 */
1803 struct mpi_coredump_segment_header nic1_mbx_regs_seg_hdr;
1804 u32 nic1_mbx_regs[NIC_MBX_REGS_CNT];
1805
1806 /* segment 9 */
1807 struct mpi_coredump_segment_header smbus_regs_seg_hdr;
1808 u32 smbus_regs[SMBUS_REGS_CNT];
1809
1810 /* segment 10 */
1811 struct mpi_coredump_segment_header fc2_mbx_regs_seg_hdr;
1812 u32 fc2_mbx_regs[FC_MBX_REGS_CNT];
1813
1814 /* segment 11 */
1815 struct mpi_coredump_segment_header nic2_mbx_regs_seg_hdr;
1816 u32 nic2_mbx_regs[NIC_MBX_REGS_CNT];
1817
1818 /* segment 12 */
1819 struct mpi_coredump_segment_header i2c_regs_seg_hdr;
1820 u32 i2c_regs[I2C_REGS_CNT];
1821 /* segment 13 */
1822 struct mpi_coredump_segment_header memc_regs_seg_hdr;
1823 u32 memc_regs[MEMC_REGS_CNT];
1824
1825 /* segment 14 */
1826 struct mpi_coredump_segment_header pbus_regs_seg_hdr;
1827 u32 pbus_regs[PBUS_REGS_CNT];
1828
1829 /* segment 15 */
1830 struct mpi_coredump_segment_header mde_regs_seg_hdr;
1831 u32 mde_regs[MDE_REGS_CNT];
1832
1833 /* segment 16 */
1834 struct mpi_coredump_segment_header nic_regs_seg_hdr;
1835 u32 nic_regs[NIC_REGS_DUMP_WORD_COUNT];
1836
1837 /* segment 17 */
1838 struct mpi_coredump_segment_header nic2_regs_seg_hdr;
1839 u32 nic2_regs[NIC_REGS_DUMP_WORD_COUNT];
1840
1841 /* segment 18 */
1842 struct mpi_coredump_segment_header xgmac1_seg_hdr;
1843 u32 xgmac1[XGMAC_DUMP_WORD_COUNT];
1844
1845 /* segment 19 */
1846 struct mpi_coredump_segment_header xgmac2_seg_hdr;
1847 u32 xgmac2[XGMAC_DUMP_WORD_COUNT];
1848
1849 /* segment 20 */
1850 struct mpi_coredump_segment_header code_ram_seg_hdr;
1851 u32 code_ram[CODE_RAM_CNT];
1852
1853 /* segment 21 */
1854 struct mpi_coredump_segment_header memc_ram_seg_hdr;
1855 u32 memc_ram[MEMC_RAM_CNT];
1856
1857 /* segment 22 */
1858 struct mpi_coredump_segment_header xaui_an_hdr;
1859 u32 serdes_xaui_an[XG_SERDES_XAUI_AN_COUNT];
1860
1861 /* segment 23 */
1862 struct mpi_coredump_segment_header xaui_hss_pcs_hdr;
1863 u32 serdes_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
1864
1865 /* segment 24 */
1866 struct mpi_coredump_segment_header xfi_an_hdr;
1867 u32 serdes_xfi_an[XG_SERDES_XFI_AN_COUNT];
1868
1869 /* segment 25 */
1870 struct mpi_coredump_segment_header xfi_train_hdr;
1871 u32 serdes_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
1872
1873 /* segment 26 */
1874 struct mpi_coredump_segment_header xfi_hss_pcs_hdr;
1875 u32 serdes_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
1876
1877 /* segment 27 */
1878 struct mpi_coredump_segment_header xfi_hss_tx_hdr;
1879 u32 serdes_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
1880
1881 /* segment 28 */
1882 struct mpi_coredump_segment_header xfi_hss_rx_hdr;
1883 u32 serdes_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
1884
1885 /* segment 29 */
1886 struct mpi_coredump_segment_header xfi_hss_pll_hdr;
1887 u32 serdes_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
1888
1889 /* segment 30 */
1890 struct mpi_coredump_segment_header misc_nic_seg_hdr;
1891 struct ql_nic_misc misc_nic_info;
1892
1893 /* segment 31 */
1894 /* one interrupt state for each CQ */
1895 struct mpi_coredump_segment_header intr_states_seg_hdr;
1896 u32 intr_states[MAX_RX_RINGS];
1897
1898 /* segment 32 */
1899 /* 3 cam words each for 16 unicast,
1900 * 2 cam words for each of 32 multicast.
1901 */
1902 struct mpi_coredump_segment_header cam_entries_seg_hdr;
1903 u32 cam_entries[(16 * 3) + (32 * 3)];
1904
1905 /* segment 33 */
1906 struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1907 u32 nic_routing_words[16];
1908 /* segment 34 */
1909 struct mpi_coredump_segment_header ets_seg_hdr;
1910 u32 ets[ETS_REGS_DUMP_WORD_COUNT];
1911
1912 /* segment 35 */
1913 struct mpi_coredump_segment_header probe_dump_seg_hdr;
1914 u32 probe_dump[PRB_MX_DUMP_TOT_COUNT];
1915
1916 /* segment 36 */
1917 struct mpi_coredump_segment_header routing_reg_seg_hdr;
1918 u32 routing_regs[RT_IDX_DUMP_TOT_WORDS];
1919
1920 /* segment 37 */
1921 struct mpi_coredump_segment_header mac_prot_reg_seg_hdr;
1922 u32 mac_prot_regs[MAC_ADDR_DUMP_TOT_WORDS];
1923
1924 /* segment 38 */
1925 struct mpi_coredump_segment_header xaui2_an_hdr;
1926 u32 serdes2_xaui_an[XG_SERDES_XAUI_AN_COUNT];
1927
1928 /* segment 39 */
1929 struct mpi_coredump_segment_header xaui2_hss_pcs_hdr;
1930 u32 serdes2_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
1931
1932 /* segment 40 */
1933 struct mpi_coredump_segment_header xfi2_an_hdr;
1934 u32 serdes2_xfi_an[XG_SERDES_XFI_AN_COUNT];
1935
1936 /* segment 41 */
1937 struct mpi_coredump_segment_header xfi2_train_hdr;
1938 u32 serdes2_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
1939
1940 /* segment 42 */
1941 struct mpi_coredump_segment_header xfi2_hss_pcs_hdr;
1942 u32 serdes2_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
1943
1944 /* segment 43 */
1945 struct mpi_coredump_segment_header xfi2_hss_tx_hdr;
1946 u32 serdes2_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
1947
1948 /* segment 44 */
1949 struct mpi_coredump_segment_header xfi2_hss_rx_hdr;
1950 u32 serdes2_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
1951
1952 /* segment 45 */
1953 struct mpi_coredump_segment_header xfi2_hss_pll_hdr;
1954 u32 serdes2_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
1955
1956 /* segment 50 */
1957 /* semaphore register for all 5 functions */
1958 struct mpi_coredump_segment_header sem_regs_seg_hdr;
1959 u32 sem_regs[MAX_SEMAPHORE_FUNCTIONS];
1960 };
1961
1962 /*
1963 * intr_context structure is used during initialization
1964 * to hook the interrupts. It is also used in a single
1965 * irq environment as a context to the ISR.
1966 */
1967 struct intr_context {
1968 struct ql_adapter *qdev;
1969 u32 intr;
1970 u32 irq_mask; /* Mask of which rings the vector services. */
1971 u32 hooked;
1972 u32 intr_en_mask; /* value/mask used to enable this intr */
1973 u32 intr_dis_mask; /* value/mask used to disable this intr */
1974 u32 intr_read_mask; /* value/mask used to read this intr */
1975 char name[IFNAMSIZ * 2];
1976 atomic_t irq_cnt; /* irq_cnt is used in single vector
1977 * environment. It's incremented for each
1978 * irq handler that is scheduled. When each
1979 * handler finishes it decrements irq_cnt and
1980 * enables interrupts if it's zero. */
1981 irq_handler_t handler;
1982 };
1983
1984 /* adapter flags definitions. */
1985 enum {
1986 QL_ADAPTER_UP = 0, /* Adapter has been brought up. */
1987 QL_LEGACY_ENABLED = 1,
1988 QL_MSI_ENABLED = 2,
1989 QL_MSIX_ENABLED = 3,
1990 QL_DMA64 = 4,
1991 QL_PROMISCUOUS = 5,
1992 QL_ALLMULTI = 6,
1993 QL_PORT_CFG = 7,
1994 QL_CAM_RT_SET = 8,
1995 QL_SELFTEST = 9,
1996 QL_LB_LINK_UP = 10,
1997 QL_FRC_COREDUMP = 11,
1998 QL_EEH_FATAL = 12,
1999 QL_ASIC_RECOVERY = 14, /* We are in ascic recovery. */
2000 };
2001
2002 /* link_status bit definitions */
2003 enum {
2004 STS_LOOPBACK_MASK = 0x00000700,
2005 STS_LOOPBACK_PCS = 0x00000100,
2006 STS_LOOPBACK_HSS = 0x00000200,
2007 STS_LOOPBACK_EXT = 0x00000300,
2008 STS_PAUSE_MASK = 0x000000c0,
2009 STS_PAUSE_STD = 0x00000040,
2010 STS_PAUSE_PRI = 0x00000080,
2011 STS_SPEED_MASK = 0x00000038,
2012 STS_SPEED_100Mb = 0x00000000,
2013 STS_SPEED_1Gb = 0x00000008,
2014 STS_SPEED_10Gb = 0x00000010,
2015 STS_LINK_TYPE_MASK = 0x00000007,
2016 STS_LINK_TYPE_XFI = 0x00000001,
2017 STS_LINK_TYPE_XAUI = 0x00000002,
2018 STS_LINK_TYPE_XFI_BP = 0x00000003,
2019 STS_LINK_TYPE_XAUI_BP = 0x00000004,
2020 STS_LINK_TYPE_10GBASET = 0x00000005,
2021 };
2022
2023 /* link_config bit definitions */
2024 enum {
2025 CFG_JUMBO_FRAME_SIZE = 0x00010000,
2026 CFG_PAUSE_MASK = 0x00000060,
2027 CFG_PAUSE_STD = 0x00000020,
2028 CFG_PAUSE_PRI = 0x00000040,
2029 CFG_DCBX = 0x00000010,
2030 CFG_LOOPBACK_MASK = 0x00000007,
2031 CFG_LOOPBACK_PCS = 0x00000002,
2032 CFG_LOOPBACK_HSS = 0x00000004,
2033 CFG_LOOPBACK_EXT = 0x00000006,
2034 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
2035 };
2036
2037 struct nic_operations {
2038
2039 int (*get_flash) (struct ql_adapter *);
2040 int (*port_initialize) (struct ql_adapter *);
2041 };
2042
2043 /*
2044 * The main Adapter structure definition.
2045 * This structure has all fields relevant to the hardware.
2046 */
2047 struct ql_adapter {
2048 struct ricb ricb;
2049 unsigned long flags;
2050 u32 wol;
2051
2052 struct nic_stats nic_stats;
2053
2054 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
2055
2056 /* PCI Configuration information for this device */
2057 struct pci_dev *pdev;
2058 struct net_device *ndev; /* Parent NET device */
2059
2060 /* Hardware information */
2061 u32 chip_rev_id;
2062 u32 fw_rev_id;
2063 u32 func; /* PCI function for this adapter */
2064 u32 alt_func; /* PCI function for alternate adapter */
2065 u32 port; /* Port number this adapter */
2066
2067 spinlock_t adapter_lock;
2068 spinlock_t hw_lock;
2069 spinlock_t stats_lock;
2070
2071 /* PCI Bus Relative Register Addresses */
2072 void __iomem *reg_base;
2073 void __iomem *doorbell_area;
2074 u32 doorbell_area_size;
2075
2076 u32 msg_enable;
2077
2078 /* Page for Shadow Registers */
2079 void *rx_ring_shadow_reg_area;
2080 dma_addr_t rx_ring_shadow_reg_dma;
2081 void *tx_ring_shadow_reg_area;
2082 dma_addr_t tx_ring_shadow_reg_dma;
2083
2084 u32 mailbox_in;
2085 u32 mailbox_out;
2086 struct mbox_params idc_mbc;
2087 struct mutex mpi_mutex;
2088
2089 int tx_ring_size;
2090 int rx_ring_size;
2091 u32 intr_count;
2092 struct msix_entry *msi_x_entry;
2093 struct intr_context intr_context[MAX_RX_RINGS];
2094
2095 int tx_ring_count; /* One per online CPU. */
2096 u32 rss_ring_count; /* One per irq vector. */
2097 /*
2098 * rx_ring_count =
2099 * (CPU count * outbound completion rx_ring) +
2100 * (irq_vector_cnt * inbound (RSS) completion rx_ring)
2101 */
2102 int rx_ring_count;
2103 int ring_mem_size;
2104 void *ring_mem;
2105
2106 struct rx_ring rx_ring[MAX_RX_RINGS];
2107 struct tx_ring tx_ring[MAX_TX_RINGS];
2108 unsigned int lbq_buf_order;
2109
2110 int rx_csum;
2111 u32 default_rx_queue;
2112
2113 u16 rx_coalesce_usecs; /* cqicb->int_delay */
2114 u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */
2115 u16 tx_coalesce_usecs; /* cqicb->int_delay */
2116 u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */
2117
2118 u32 xg_sem_mask;
2119 u32 port_link_up;
2120 u32 port_init;
2121 u32 link_status;
2122 struct ql_mpi_coredump *mpi_coredump;
2123 u32 core_is_dumped;
2124 u32 link_config;
2125 u32 led_config;
2126 u32 max_frame_size;
2127
2128 union flash_params flash;
2129
2130 struct workqueue_struct *workqueue;
2131 struct delayed_work asic_reset_work;
2132 struct delayed_work mpi_reset_work;
2133 struct delayed_work mpi_work;
2134 struct delayed_work mpi_port_cfg_work;
2135 struct delayed_work mpi_idc_work;
2136 struct delayed_work mpi_core_to_log;
2137 struct completion ide_completion;
2138 const struct nic_operations *nic_ops;
2139 u16 device_id;
2140 struct timer_list timer;
2141 atomic_t lb_count;
2142 /* Keep local copy of current mac address. */
2143 char current_mac_addr[6];
2144 };
2145
2146 /*
2147 * Typical Register accessor for memory mapped device.
2148 */
2149 static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
2150 {
2151 return readl(qdev->reg_base + reg);
2152 }
2153
2154 /*
2155 * Typical Register accessor for memory mapped device.
2156 */
2157 static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
2158 {
2159 writel(val, qdev->reg_base + reg);
2160 }
2161
2162 /*
2163 * Doorbell Registers:
2164 * Doorbell registers are virtual registers in the PCI memory space.
2165 * The space is allocated by the chip during PCI initialization. The
2166 * device driver finds the doorbell address in BAR 3 in PCI config space.
2167 * The registers are used to control outbound and inbound queues. For
2168 * example, the producer index for an outbound queue. Each queue uses
2169 * 1 4k chunk of memory. The lower half of the space is for outbound
2170 * queues. The upper half is for inbound queues.
2171 */
2172 static inline void ql_write_db_reg(u32 val, void __iomem *addr)
2173 {
2174 writel(val, addr);
2175 mmiowb();
2176 }
2177
2178 /*
2179 * Shadow Registers:
2180 * Outbound queues have a consumer index that is maintained by the chip.
2181 * Inbound queues have a producer index that is maintained by the chip.
2182 * For lower overhead, these registers are "shadowed" to host memory
2183 * which allows the device driver to track the queue progress without
2184 * PCI reads. When an entry is placed on an inbound queue, the chip will
2185 * update the relevant index register and then copy the value to the
2186 * shadow register in host memory.
2187 */
2188 static inline u32 ql_read_sh_reg(__le32 *addr)
2189 {
2190 u32 reg;
2191 reg = le32_to_cpu(*addr);
2192 rmb();
2193 return reg;
2194 }
2195
2196 extern char qlge_driver_name[];
2197 extern const char qlge_driver_version[];
2198 extern const struct ethtool_ops qlge_ethtool_ops;
2199
2200 extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
2201 extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
2202 extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
2203 extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
2204 u32 *value);
2205 extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
2206 extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
2207 u16 q_id);
2208 void ql_queue_fw_error(struct ql_adapter *qdev);
2209 void ql_mpi_work(struct work_struct *work);
2210 void ql_mpi_reset_work(struct work_struct *work);
2211 void ql_mpi_core_to_log(struct work_struct *work);
2212 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
2213 void ql_queue_asic_error(struct ql_adapter *qdev);
2214 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr);
2215 void ql_set_ethtool_ops(struct net_device *ndev);
2216 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
2217 void ql_mpi_idc_work(struct work_struct *work);
2218 void ql_mpi_port_cfg_work(struct work_struct *work);
2219 int ql_mb_get_fw_state(struct ql_adapter *qdev);
2220 int ql_cam_route_initialize(struct ql_adapter *qdev);
2221 int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
2222 int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data);
2223 int ql_unpause_mpi_risc(struct ql_adapter *qdev);
2224 int ql_pause_mpi_risc(struct ql_adapter *qdev);
2225 int ql_hard_reset_mpi_risc(struct ql_adapter *qdev);
2226 int ql_soft_reset_mpi_risc(struct ql_adapter *qdev);
2227 int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf,
2228 u32 ram_addr, int word_count);
2229 int ql_core_dump(struct ql_adapter *qdev,
2230 struct ql_mpi_coredump *mpi_coredump);
2231 int ql_mb_about_fw(struct ql_adapter *qdev);
2232 int ql_mb_wol_set_magic(struct ql_adapter *qdev, u32 enable_wol);
2233 int ql_mb_wol_mode(struct ql_adapter *qdev, u32 wol);
2234 int ql_mb_set_led_cfg(struct ql_adapter *qdev, u32 led_config);
2235 int ql_mb_get_led_cfg(struct ql_adapter *qdev);
2236 void ql_link_on(struct ql_adapter *qdev);
2237 void ql_link_off(struct ql_adapter *qdev);
2238 int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
2239 int ql_mb_get_port_cfg(struct ql_adapter *qdev);
2240 int ql_mb_set_port_cfg(struct ql_adapter *qdev);
2241 int ql_wait_fifo_empty(struct ql_adapter *qdev);
2242 void ql_get_dump(struct ql_adapter *qdev, void *buff);
2243 void ql_gen_reg_dump(struct ql_adapter *qdev,
2244 struct ql_reg_dump *mpi_coredump);
2245 netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev);
2246 void ql_check_lb_frame(struct ql_adapter *, struct sk_buff *);
2247 int ql_own_firmware(struct ql_adapter *qdev);
2248 int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget);
2249
2250 /* #define QL_ALL_DUMP */
2251 /* #define QL_REG_DUMP */
2252 /* #define QL_DEV_DUMP */
2253 /* #define QL_CB_DUMP */
2254 /* #define QL_IB_DUMP */
2255 /* #define QL_OB_DUMP */
2256
2257 #ifdef QL_REG_DUMP
2258 extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
2259 extern void ql_dump_routing_entries(struct ql_adapter *qdev);
2260 extern void ql_dump_regs(struct ql_adapter *qdev);
2261 #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
2262 #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
2263 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
2264 #else
2265 #define QL_DUMP_REGS(qdev)
2266 #define QL_DUMP_ROUTE(qdev)
2267 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
2268 #endif
2269
2270 #ifdef QL_STAT_DUMP
2271 extern void ql_dump_stat(struct ql_adapter *qdev);
2272 #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
2273 #else
2274 #define QL_DUMP_STAT(qdev)
2275 #endif
2276
2277 #ifdef QL_DEV_DUMP
2278 extern void ql_dump_qdev(struct ql_adapter *qdev);
2279 #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
2280 #else
2281 #define QL_DUMP_QDEV(qdev)
2282 #endif
2283
2284 #ifdef QL_CB_DUMP
2285 extern void ql_dump_wqicb(struct wqicb *wqicb);
2286 extern void ql_dump_tx_ring(struct tx_ring *tx_ring);
2287 extern void ql_dump_ricb(struct ricb *ricb);
2288 extern void ql_dump_cqicb(struct cqicb *cqicb);
2289 extern void ql_dump_rx_ring(struct rx_ring *rx_ring);
2290 extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
2291 #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
2292 #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
2293 #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
2294 #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
2295 #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
2296 #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
2297 ql_dump_hw_cb(qdev, size, bit, q_id)
2298 #else
2299 #define QL_DUMP_RICB(ricb)
2300 #define QL_DUMP_WQICB(wqicb)
2301 #define QL_DUMP_TX_RING(tx_ring)
2302 #define QL_DUMP_CQICB(cqicb)
2303 #define QL_DUMP_RX_RING(rx_ring)
2304 #define QL_DUMP_HW_CB(qdev, size, bit, q_id)
2305 #endif
2306
2307 #ifdef QL_OB_DUMP
2308 extern void ql_dump_tx_desc(struct tx_buf_desc *tbd);
2309 extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
2310 extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
2311 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
2312 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
2313 #else
2314 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
2315 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
2316 #endif
2317
2318 #ifdef QL_IB_DUMP
2319 extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
2320 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
2321 #else
2322 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
2323 #endif
2324
2325 #ifdef QL_ALL_DUMP
2326 extern void ql_dump_all(struct ql_adapter *qdev);
2327 #define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
2328 #else
2329 #define QL_DUMP_ALL(qdev)
2330 #endif
2331
2332 #endif /* _QLGE_H_ */