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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / net / ethernet / via / via-rhine.c
blob6764d0d236f5fee67fbf04c3ffe4249e1a363ec3
1 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2 /*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28 [link no longer provides useful info -jgarzik]
29
30 */
31
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
34 #define DRV_NAME "via-rhine"
35 #define DRV_VERSION "1.5.0"
36 #define DRV_RELDATE "2010-10-09"
37
38 #include <linux/types.h>
39
40 /* A few user-configurable values.
41 These may be modified when a driver module is loaded. */
42 static int debug = 0;
43 #define RHINE_MSG_DEFAULT \
44 (0x0000)
45
46 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
47 Setting to > 1518 effectively disables this feature. */
48 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
49 defined(CONFIG_SPARC) || defined(__ia64__) || \
50 defined(__sh__) || defined(__mips__)
51 static int rx_copybreak = 1518;
52 #else
53 static int rx_copybreak;
54 #endif
55
56 /* Work-around for broken BIOSes: they are unable to get the chip back out of
57 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
58 static bool avoid_D3;
59
60 /*
61 * In case you are looking for 'options[]' or 'full_duplex[]', they
62 * are gone. Use ethtool(8) instead.
63 */
64
65 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
66 The Rhine has a 64 element 8390-like hash table. */
67 static const int multicast_filter_limit = 32;
68
69
70 /* Operational parameters that are set at compile time. */
71
72 /* Keep the ring sizes a power of two for compile efficiency.
73 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
74 Making the Tx ring too large decreases the effectiveness of channel
75 bonding and packet priority.
76 There are no ill effects from too-large receive rings. */
77 #define TX_RING_SIZE 16
78 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
79 #define RX_RING_SIZE 64
80
81 /* Operational parameters that usually are not changed. */
82
83 /* Time in jiffies before concluding the transmitter is hung. */
84 #define TX_TIMEOUT (2*HZ)
85
86 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
87
88 #include <linux/module.h>
89 #include <linux/moduleparam.h>
90 #include <linux/kernel.h>
91 #include <linux/string.h>
92 #include <linux/timer.h>
93 #include <linux/errno.h>
94 #include <linux/ioport.h>
95 #include <linux/interrupt.h>
96 #include <linux/pci.h>
97 #include <linux/dma-mapping.h>
98 #include <linux/netdevice.h>
99 #include <linux/etherdevice.h>
100 #include <linux/skbuff.h>
101 #include <linux/init.h>
102 #include <linux/delay.h>
103 #include <linux/mii.h>
104 #include <linux/ethtool.h>
105 #include <linux/crc32.h>
106 #include <linux/if_vlan.h>
107 #include <linux/bitops.h>
108 #include <linux/workqueue.h>
109 #include <asm/processor.h> /* Processor type for cache alignment. */
110 #include <asm/io.h>
111 #include <asm/irq.h>
112 #include <asm/uaccess.h>
113 #include <linux/dmi.h>
114
115 /* These identify the driver base version and may not be removed. */
116 static const char version[] __devinitconst =
117 "v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker";
118
119 /* This driver was written to use PCI memory space. Some early versions
120 of the Rhine may only work correctly with I/O space accesses. */
121 #ifdef CONFIG_VIA_RHINE_MMIO
122 #define USE_MMIO
123 #else
124 #endif
125
126 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
127 MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
128 MODULE_LICENSE("GPL");
129
130 module_param(debug, int, 0);
131 module_param(rx_copybreak, int, 0);
132 module_param(avoid_D3, bool, 0);
133 MODULE_PARM_DESC(debug, "VIA Rhine debug message flags");
134 MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
135 MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
136
137 #define MCAM_SIZE 32
138 #define VCAM_SIZE 32
139
140 /*
141 Theory of Operation
142
143 I. Board Compatibility
144
145 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
146 controller.
147
148 II. Board-specific settings
149
150 Boards with this chip are functional only in a bus-master PCI slot.
151
152 Many operational settings are loaded from the EEPROM to the Config word at
153 offset 0x78. For most of these settings, this driver assumes that they are
154 correct.
155 If this driver is compiled to use PCI memory space operations the EEPROM
156 must be configured to enable memory ops.
157
158 III. Driver operation
159
160 IIIa. Ring buffers
161
162 This driver uses two statically allocated fixed-size descriptor lists
163 formed into rings by a branch from the final descriptor to the beginning of
164 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
165
166 IIIb/c. Transmit/Receive Structure
167
168 This driver attempts to use a zero-copy receive and transmit scheme.
169
170 Alas, all data buffers are required to start on a 32 bit boundary, so
171 the driver must often copy transmit packets into bounce buffers.
172
173 The driver allocates full frame size skbuffs for the Rx ring buffers at
174 open() time and passes the skb->data field to the chip as receive data
175 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
176 a fresh skbuff is allocated and the frame is copied to the new skbuff.
177 When the incoming frame is larger, the skbuff is passed directly up the
178 protocol stack. Buffers consumed this way are replaced by newly allocated
179 skbuffs in the last phase of rhine_rx().
180
181 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
182 using a full-sized skbuff for small frames vs. the copying costs of larger
183 frames. New boards are typically used in generously configured machines
184 and the underfilled buffers have negligible impact compared to the benefit of
185 a single allocation size, so the default value of zero results in never
186 copying packets. When copying is done, the cost is usually mitigated by using
187 a combined copy/checksum routine. Copying also preloads the cache, which is
188 most useful with small frames.
189
190 Since the VIA chips are only able to transfer data to buffers on 32 bit
191 boundaries, the IP header at offset 14 in an ethernet frame isn't
192 longword aligned for further processing. Copying these unaligned buffers
193 has the beneficial effect of 16-byte aligning the IP header.
194
195 IIId. Synchronization
196
197 The driver runs as two independent, single-threaded flows of control. One
198 is the send-packet routine, which enforces single-threaded use by the
199 netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
200 which is single threaded by the hardware and interrupt handling software.
201
202 The send packet thread has partial control over the Tx ring. It locks the
203 netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
204 the ring is not available it stops the transmit queue by
205 calling netif_stop_queue.
206
207 The interrupt handler has exclusive control over the Rx ring and records stats
208 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
209 empty by incrementing the dirty_tx mark. If at least half of the entries in
210 the Rx ring are available the transmit queue is woken up if it was stopped.
211
212 IV. Notes
213
214 IVb. References
215
216 Preliminary VT86C100A manual from http://www.via.com.tw/
217 http://www.scyld.com/expert/100mbps.html
218 http://www.scyld.com/expert/NWay.html
219 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
220 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
221
222
223 IVc. Errata
224
225 The VT86C100A manual is not reliable information.
226 The 3043 chip does not handle unaligned transmit or receive buffers, resulting
227 in significant performance degradation for bounce buffer copies on transmit
228 and unaligned IP headers on receive.
229 The chip does not pad to minimum transmit length.
230
231 */
232
233
234 /* This table drives the PCI probe routines. It's mostly boilerplate in all
235 of the drivers, and will likely be provided by some future kernel.
236 Note the matching code -- the first table entry matchs all 56** cards but
237 second only the 1234 card.
238 */
239
240 enum rhine_revs {
241 VT86C100A = 0x00,
242 VTunknown0 = 0x20,
243 VT6102 = 0x40,
244 VT8231 = 0x50, /* Integrated MAC */
245 VT8233 = 0x60, /* Integrated MAC */
246 VT8235 = 0x74, /* Integrated MAC */
247 VT8237 = 0x78, /* Integrated MAC */
248 VTunknown1 = 0x7C,
249 VT6105 = 0x80,
250 VT6105_B0 = 0x83,
251 VT6105L = 0x8A,
252 VT6107 = 0x8C,
253 VTunknown2 = 0x8E,
254 VT6105M = 0x90, /* Management adapter */
255 };
256
257 enum rhine_quirks {
258 rqWOL = 0x0001, /* Wake-On-LAN support */
259 rqForceReset = 0x0002,
260 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
261 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
262 rqRhineI = 0x0100, /* See comment below */
263 };
264 /*
265 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
266 * MMIO as well as for the collision counter and the Tx FIFO underflow
267 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
268 */
269
270 /* Beware of PCI posted writes */
271 #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
272
273 static DEFINE_PCI_DEVICE_TABLE(rhine_pci_tbl) = {
274 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
275 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
276 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
277 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
278 { } /* terminate list */
279 };
280 MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
281
282
283 /* Offsets to the device registers. */
284 enum register_offsets {
285 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
286 ChipCmd1=0x09, TQWake=0x0A,
287 IntrStatus=0x0C, IntrEnable=0x0E,
288 MulticastFilter0=0x10, MulticastFilter1=0x14,
289 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
290 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
291 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
292 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
293 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
294 StickyHW=0x83, IntrStatus2=0x84,
295 CamMask=0x88, CamCon=0x92, CamAddr=0x93,
296 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
297 WOLcrClr1=0xA6, WOLcgClr=0xA7,
298 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
299 };
300
301 /* Bits in ConfigD */
302 enum backoff_bits {
303 BackOptional=0x01, BackModify=0x02,
304 BackCaptureEffect=0x04, BackRandom=0x08
305 };
306
307 /* Bits in the TxConfig (TCR) register */
308 enum tcr_bits {
309 TCR_PQEN=0x01,
310 TCR_LB0=0x02, /* loopback[0] */
311 TCR_LB1=0x04, /* loopback[1] */
312 TCR_OFSET=0x08,
313 TCR_RTGOPT=0x10,
314 TCR_RTFT0=0x20,
315 TCR_RTFT1=0x40,
316 TCR_RTSF=0x80,
317 };
318
319 /* Bits in the CamCon (CAMC) register */
320 enum camcon_bits {
321 CAMC_CAMEN=0x01,
322 CAMC_VCAMSL=0x02,
323 CAMC_CAMWR=0x04,
324 CAMC_CAMRD=0x08,
325 };
326
327 /* Bits in the PCIBusConfig1 (BCR1) register */
328 enum bcr1_bits {
329 BCR1_POT0=0x01,
330 BCR1_POT1=0x02,
331 BCR1_POT2=0x04,
332 BCR1_CTFT0=0x08,
333 BCR1_CTFT1=0x10,
334 BCR1_CTSF=0x20,
335 BCR1_TXQNOBK=0x40, /* for VT6105 */
336 BCR1_VIDFR=0x80, /* for VT6105 */
337 BCR1_MED0=0x40, /* for VT6102 */
338 BCR1_MED1=0x80, /* for VT6102 */
339 };
340
341 #ifdef USE_MMIO
342 /* Registers we check that mmio and reg are the same. */
343 static const int mmio_verify_registers[] = {
344 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
345 0
346 };
347 #endif
348
349 /* Bits in the interrupt status/mask registers. */
350 enum intr_status_bits {
351 IntrRxDone = 0x0001,
352 IntrTxDone = 0x0002,
353 IntrRxErr = 0x0004,
354 IntrTxError = 0x0008,
355 IntrRxEmpty = 0x0020,
356 IntrPCIErr = 0x0040,
357 IntrStatsMax = 0x0080,
358 IntrRxEarly = 0x0100,
359 IntrTxUnderrun = 0x0210,
360 IntrRxOverflow = 0x0400,
361 IntrRxDropped = 0x0800,
362 IntrRxNoBuf = 0x1000,
363 IntrTxAborted = 0x2000,
364 IntrLinkChange = 0x4000,
365 IntrRxWakeUp = 0x8000,
366 IntrTxDescRace = 0x080000, /* mapped from IntrStatus2 */
367 IntrNormalSummary = IntrRxDone | IntrTxDone,
368 IntrTxErrSummary = IntrTxDescRace | IntrTxAborted | IntrTxError |
369 IntrTxUnderrun,
370 };
371
372 /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
373 enum wol_bits {
374 WOLucast = 0x10,
375 WOLmagic = 0x20,
376 WOLbmcast = 0x30,
377 WOLlnkon = 0x40,
378 WOLlnkoff = 0x80,
379 };
380
381 /* The Rx and Tx buffer descriptors. */
382 struct rx_desc {
383 __le32 rx_status;
384 __le32 desc_length; /* Chain flag, Buffer/frame length */
385 __le32 addr;
386 __le32 next_desc;
387 };
388 struct tx_desc {
389 __le32 tx_status;
390 __le32 desc_length; /* Chain flag, Tx Config, Frame length */
391 __le32 addr;
392 __le32 next_desc;
393 };
394
395 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
396 #define TXDESC 0x00e08000
397
398 enum rx_status_bits {
399 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
400 };
401
402 /* Bits in *_desc.*_status */
403 enum desc_status_bits {
404 DescOwn=0x80000000
405 };
406
407 /* Bits in *_desc.*_length */
408 enum desc_length_bits {
409 DescTag=0x00010000
410 };
411
412 /* Bits in ChipCmd. */
413 enum chip_cmd_bits {
414 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
415 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
416 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
417 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
418 };
419
420 struct rhine_private {
421 /* Bit mask for configured VLAN ids */
422 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
423
424 /* Descriptor rings */
425 struct rx_desc *rx_ring;
426 struct tx_desc *tx_ring;
427 dma_addr_t rx_ring_dma;
428 dma_addr_t tx_ring_dma;
429
430 /* The addresses of receive-in-place skbuffs. */
431 struct sk_buff *rx_skbuff[RX_RING_SIZE];
432 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
433
434 /* The saved address of a sent-in-place packet/buffer, for later free(). */
435 struct sk_buff *tx_skbuff[TX_RING_SIZE];
436 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
437
438 /* Tx bounce buffers (Rhine-I only) */
439 unsigned char *tx_buf[TX_RING_SIZE];
440 unsigned char *tx_bufs;
441 dma_addr_t tx_bufs_dma;
442
443 struct pci_dev *pdev;
444 long pioaddr;
445 struct net_device *dev;
446 struct napi_struct napi;
447 spinlock_t lock;
448 struct mutex task_lock;
449 bool task_enable;
450 struct work_struct slow_event_task;
451 struct work_struct reset_task;
452
453 u32 msg_enable;
454
455 /* Frequently used values: keep some adjacent for cache effect. */
456 u32 quirks;
457 struct rx_desc *rx_head_desc;
458 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
459 unsigned int cur_tx, dirty_tx;
460 unsigned int rx_buf_sz; /* Based on MTU+slack. */
461 u8 wolopts;
462
463 u8 tx_thresh, rx_thresh;
464
465 struct mii_if_info mii_if;
466 void __iomem *base;
467 };
468
469 #define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
470 #define WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
471 #define DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
472
473 #define BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x))
474 #define WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x))
475 #define DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x))
476
477 #define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
478 #define WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
479 #define DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
480
481 #define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
482 #define WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
483 #define DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
484
485
486 static int mdio_read(struct net_device *dev, int phy_id, int location);
487 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
488 static int rhine_open(struct net_device *dev);
489 static void rhine_reset_task(struct work_struct *work);
490 static void rhine_slow_event_task(struct work_struct *work);
491 static void rhine_tx_timeout(struct net_device *dev);
492 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
493 struct net_device *dev);
494 static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
495 static void rhine_tx(struct net_device *dev);
496 static int rhine_rx(struct net_device *dev, int limit);
497 static void rhine_set_rx_mode(struct net_device *dev);
498 static struct net_device_stats *rhine_get_stats(struct net_device *dev);
499 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
500 static const struct ethtool_ops netdev_ethtool_ops;
501 static int rhine_close(struct net_device *dev);
502 static int rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);
503 static int rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);
504 static void rhine_restart_tx(struct net_device *dev);
505
506 static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool low)
507 {
508 void __iomem *ioaddr = rp->base;
509 int i;
510
511 for (i = 0; i < 1024; i++) {
512 bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask);
513
514 if (low ^ has_mask_bits)
515 break;
516 udelay(10);
517 }
518 if (i > 64) {
519 netif_dbg(rp, hw, rp->dev, "%s bit wait (%02x/%02x) cycle "
520 "count: %04d\n", low ? "low" : "high", reg, mask, i);
521 }
522 }
523
524 static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask)
525 {
526 rhine_wait_bit(rp, reg, mask, false);
527 }
528
529 static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask)
530 {
531 rhine_wait_bit(rp, reg, mask, true);
532 }
533
534 static u32 rhine_get_events(struct rhine_private *rp)
535 {
536 void __iomem *ioaddr = rp->base;
537 u32 intr_status;
538
539 intr_status = ioread16(ioaddr + IntrStatus);
540 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
541 if (rp->quirks & rqStatusWBRace)
542 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
543 return intr_status;
544 }
545
546 static void rhine_ack_events(struct rhine_private *rp, u32 mask)
547 {
548 void __iomem *ioaddr = rp->base;
549
550 if (rp->quirks & rqStatusWBRace)
551 iowrite8(mask >> 16, ioaddr + IntrStatus2);
552 iowrite16(mask, ioaddr + IntrStatus);
553 mmiowb();
554 }
555
556 /*
557 * Get power related registers into sane state.
558 * Notify user about past WOL event.
559 */
560 static void rhine_power_init(struct net_device *dev)
561 {
562 struct rhine_private *rp = netdev_priv(dev);
563 void __iomem *ioaddr = rp->base;
564 u16 wolstat;
565
566 if (rp->quirks & rqWOL) {
567 /* Make sure chip is in power state D0 */
568 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
569
570 /* Disable "force PME-enable" */
571 iowrite8(0x80, ioaddr + WOLcgClr);
572
573 /* Clear power-event config bits (WOL) */
574 iowrite8(0xFF, ioaddr + WOLcrClr);
575 /* More recent cards can manage two additional patterns */
576 if (rp->quirks & rq6patterns)
577 iowrite8(0x03, ioaddr + WOLcrClr1);
578
579 /* Save power-event status bits */
580 wolstat = ioread8(ioaddr + PwrcsrSet);
581 if (rp->quirks & rq6patterns)
582 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
583
584 /* Clear power-event status bits */
585 iowrite8(0xFF, ioaddr + PwrcsrClr);
586 if (rp->quirks & rq6patterns)
587 iowrite8(0x03, ioaddr + PwrcsrClr1);
588
589 if (wolstat) {
590 char *reason;
591 switch (wolstat) {
592 case WOLmagic:
593 reason = "Magic packet";
594 break;
595 case WOLlnkon:
596 reason = "Link went up";
597 break;
598 case WOLlnkoff:
599 reason = "Link went down";
600 break;
601 case WOLucast:
602 reason = "Unicast packet";
603 break;
604 case WOLbmcast:
605 reason = "Multicast/broadcast packet";
606 break;
607 default:
608 reason = "Unknown";
609 }
610 netdev_info(dev, "Woke system up. Reason: %s\n",
611 reason);
612 }
613 }
614 }
615
616 static void rhine_chip_reset(struct net_device *dev)
617 {
618 struct rhine_private *rp = netdev_priv(dev);
619 void __iomem *ioaddr = rp->base;
620 u8 cmd1;
621
622 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
623 IOSYNC;
624
625 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
626 netdev_info(dev, "Reset not complete yet. Trying harder.\n");
627
628 /* Force reset */
629 if (rp->quirks & rqForceReset)
630 iowrite8(0x40, ioaddr + MiscCmd);
631
632 /* Reset can take somewhat longer (rare) */
633 rhine_wait_bit_low(rp, ChipCmd1, Cmd1Reset);
634 }
635
636 cmd1 = ioread8(ioaddr + ChipCmd1);
637 netif_info(rp, hw, dev, "Reset %s\n", (cmd1 & Cmd1Reset) ?
638 "failed" : "succeeded");
639 }
640
641 #ifdef USE_MMIO
642 static void enable_mmio(long pioaddr, u32 quirks)
643 {
644 int n;
645 if (quirks & rqRhineI) {
646 /* More recent docs say that this bit is reserved ... */
647 n = inb(pioaddr + ConfigA) | 0x20;
648 outb(n, pioaddr + ConfigA);
649 } else {
650 n = inb(pioaddr + ConfigD) | 0x80;
651 outb(n, pioaddr + ConfigD);
652 }
653 }
654 #endif
655
656 /*
657 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
658 * (plus 0x6C for Rhine-I/II)
659 */
660 static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
661 {
662 struct rhine_private *rp = netdev_priv(dev);
663 void __iomem *ioaddr = rp->base;
664 int i;
665
666 outb(0x20, pioaddr + MACRegEEcsr);
667 for (i = 0; i < 1024; i++) {
668 if (!(inb(pioaddr + MACRegEEcsr) & 0x20))
669 break;
670 }
671 if (i > 512)
672 pr_info("%4d cycles used @ %s:%d\n", i, __func__, __LINE__);
673
674 #ifdef USE_MMIO
675 /*
676 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
677 * MMIO. If reloading EEPROM was done first this could be avoided, but
678 * it is not known if that still works with the "win98-reboot" problem.
679 */
680 enable_mmio(pioaddr, rp->quirks);
681 #endif
682
683 /* Turn off EEPROM-controlled wake-up (magic packet) */
684 if (rp->quirks & rqWOL)
685 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
686
687 }
688
689 #ifdef CONFIG_NET_POLL_CONTROLLER
690 static void rhine_poll(struct net_device *dev)
691 {
692 disable_irq(dev->irq);
693 rhine_interrupt(dev->irq, (void *)dev);
694 enable_irq(dev->irq);
695 }
696 #endif
697
698 static void rhine_kick_tx_threshold(struct rhine_private *rp)
699 {
700 if (rp->tx_thresh < 0xe0) {
701 void __iomem *ioaddr = rp->base;
702
703 rp->tx_thresh += 0x20;
704 BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig);
705 }
706 }
707
708 static void rhine_tx_err(struct rhine_private *rp, u32 status)
709 {
710 struct net_device *dev = rp->dev;
711
712 if (status & IntrTxAborted) {
713 netif_info(rp, tx_err, dev,
714 "Abort %08x, frame dropped\n", status);
715 }
716
717 if (status & IntrTxUnderrun) {
718 rhine_kick_tx_threshold(rp);
719 netif_info(rp, tx_err ,dev, "Transmitter underrun, "
720 "Tx threshold now %02x\n", rp->tx_thresh);
721 }
722
723 if (status & IntrTxDescRace)
724 netif_info(rp, tx_err, dev, "Tx descriptor write-back race\n");
725
726 if ((status & IntrTxError) &&
727 (status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace)) == 0) {
728 rhine_kick_tx_threshold(rp);
729 netif_info(rp, tx_err, dev, "Unspecified error. "
730 "Tx threshold now %02x\n", rp->tx_thresh);
731 }
732
733 rhine_restart_tx(dev);
734 }
735
736 static void rhine_update_rx_crc_and_missed_errord(struct rhine_private *rp)
737 {
738 void __iomem *ioaddr = rp->base;
739 struct net_device_stats *stats = &rp->dev->stats;
740
741 stats->rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
742 stats->rx_missed_errors += ioread16(ioaddr + RxMissed);
743
744 /*
745 * Clears the "tally counters" for CRC errors and missed frames(?).
746 * It has been reported that some chips need a write of 0 to clear
747 * these, for others the counters are set to 1 when written to and
748 * instead cleared when read. So we clear them both ways ...
749 */
750 iowrite32(0, ioaddr + RxMissed);
751 ioread16(ioaddr + RxCRCErrs);
752 ioread16(ioaddr + RxMissed);
753 }
754
755 #define RHINE_EVENT_NAPI_RX (IntrRxDone | \
756 IntrRxErr | \
757 IntrRxEmpty | \
758 IntrRxOverflow | \
759 IntrRxDropped | \
760 IntrRxNoBuf | \
761 IntrRxWakeUp)
762
763 #define RHINE_EVENT_NAPI_TX_ERR (IntrTxError | \
764 IntrTxAborted | \
765 IntrTxUnderrun | \
766 IntrTxDescRace)
767 #define RHINE_EVENT_NAPI_TX (IntrTxDone | RHINE_EVENT_NAPI_TX_ERR)
768
769 #define RHINE_EVENT_NAPI (RHINE_EVENT_NAPI_RX | \
770 RHINE_EVENT_NAPI_TX | \
771 IntrStatsMax)
772 #define RHINE_EVENT_SLOW (IntrPCIErr | IntrLinkChange)
773 #define RHINE_EVENT (RHINE_EVENT_NAPI | RHINE_EVENT_SLOW)
774
775 static int rhine_napipoll(struct napi_struct *napi, int budget)
776 {
777 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
778 struct net_device *dev = rp->dev;
779 void __iomem *ioaddr = rp->base;
780 u16 enable_mask = RHINE_EVENT & 0xffff;
781 int work_done = 0;
782 u32 status;
783
784 status = rhine_get_events(rp);
785 rhine_ack_events(rp, status & ~RHINE_EVENT_SLOW);
786
787 if (status & RHINE_EVENT_NAPI_RX)
788 work_done += rhine_rx(dev, budget);
789
790 if (status & RHINE_EVENT_NAPI_TX) {
791 if (status & RHINE_EVENT_NAPI_TX_ERR) {
792 /* Avoid scavenging before Tx engine turned off */
793 rhine_wait_bit_low(rp, ChipCmd, CmdTxOn);
794 if (ioread8(ioaddr + ChipCmd) & CmdTxOn)
795 netif_warn(rp, tx_err, dev, "Tx still on\n");
796 }
797
798 rhine_tx(dev);
799
800 if (status & RHINE_EVENT_NAPI_TX_ERR)
801 rhine_tx_err(rp, status);
802 }
803
804 if (status & IntrStatsMax) {
805 spin_lock(&rp->lock);
806 rhine_update_rx_crc_and_missed_errord(rp);
807 spin_unlock(&rp->lock);
808 }
809
810 if (status & RHINE_EVENT_SLOW) {
811 enable_mask &= ~RHINE_EVENT_SLOW;
812 schedule_work(&rp->slow_event_task);
813 }
814
815 if (work_done < budget) {
816 napi_complete(napi);
817 iowrite16(enable_mask, ioaddr + IntrEnable);
818 mmiowb();
819 }
820 return work_done;
821 }
822
823 static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
824 {
825 struct rhine_private *rp = netdev_priv(dev);
826
827 /* Reset the chip to erase previous misconfiguration. */
828 rhine_chip_reset(dev);
829
830 /* Rhine-I needs extra time to recuperate before EEPROM reload */
831 if (rp->quirks & rqRhineI)
832 msleep(5);
833
834 /* Reload EEPROM controlled bytes cleared by soft reset */
835 rhine_reload_eeprom(pioaddr, dev);
836 }
837
838 static const struct net_device_ops rhine_netdev_ops = {
839 .ndo_open = rhine_open,
840 .ndo_stop = rhine_close,
841 .ndo_start_xmit = rhine_start_tx,
842 .ndo_get_stats = rhine_get_stats,
843 .ndo_set_rx_mode = rhine_set_rx_mode,
844 .ndo_change_mtu = eth_change_mtu,
845 .ndo_validate_addr = eth_validate_addr,
846 .ndo_set_mac_address = eth_mac_addr,
847 .ndo_do_ioctl = netdev_ioctl,
848 .ndo_tx_timeout = rhine_tx_timeout,
849 .ndo_vlan_rx_add_vid = rhine_vlan_rx_add_vid,
850 .ndo_vlan_rx_kill_vid = rhine_vlan_rx_kill_vid,
851 #ifdef CONFIG_NET_POLL_CONTROLLER
852 .ndo_poll_controller = rhine_poll,
853 #endif
854 };
855
856 static int __devinit rhine_init_one(struct pci_dev *pdev,
857 const struct pci_device_id *ent)
858 {
859 struct net_device *dev;
860 struct rhine_private *rp;
861 int i, rc;
862 u32 quirks;
863 long pioaddr;
864 long memaddr;
865 void __iomem *ioaddr;
866 int io_size, phy_id;
867 const char *name;
868 #ifdef USE_MMIO
869 int bar = 1;
870 #else
871 int bar = 0;
872 #endif
873
874 /* when built into the kernel, we only print version if device is found */
875 #ifndef MODULE
876 pr_info_once("%s\n", version);
877 #endif
878
879 io_size = 256;
880 phy_id = 0;
881 quirks = 0;
882 name = "Rhine";
883 if (pdev->revision < VTunknown0) {
884 quirks = rqRhineI;
885 io_size = 128;
886 }
887 else if (pdev->revision >= VT6102) {
888 quirks = rqWOL | rqForceReset;
889 if (pdev->revision < VT6105) {
890 name = "Rhine II";
891 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
892 }
893 else {
894 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
895 if (pdev->revision >= VT6105_B0)
896 quirks |= rq6patterns;
897 if (pdev->revision < VT6105M)
898 name = "Rhine III";
899 else
900 name = "Rhine III (Management Adapter)";
901 }
902 }
903
904 rc = pci_enable_device(pdev);
905 if (rc)
906 goto err_out;
907
908 /* this should always be supported */
909 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
910 if (rc) {
911 dev_err(&pdev->dev,
912 "32-bit PCI DMA addresses not supported by the card!?\n");
913 goto err_out;
914 }
915
916 /* sanity check */
917 if ((pci_resource_len(pdev, 0) < io_size) ||
918 (pci_resource_len(pdev, 1) < io_size)) {
919 rc = -EIO;
920 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
921 goto err_out;
922 }
923
924 pioaddr = pci_resource_start(pdev, 0);
925 memaddr = pci_resource_start(pdev, 1);
926
927 pci_set_master(pdev);
928
929 dev = alloc_etherdev(sizeof(struct rhine_private));
930 if (!dev) {
931 rc = -ENOMEM;
932 dev_err(&pdev->dev, "alloc_etherdev failed\n");
933 goto err_out;
934 }
935 SET_NETDEV_DEV(dev, &pdev->dev);
936
937 rp = netdev_priv(dev);
938 rp->dev = dev;
939 rp->quirks = quirks;
940 rp->pioaddr = pioaddr;
941 rp->pdev = pdev;
942 rp->msg_enable = netif_msg_init(debug, RHINE_MSG_DEFAULT);
943
944 rc = pci_request_regions(pdev, DRV_NAME);
945 if (rc)
946 goto err_out_free_netdev;
947
948 ioaddr = pci_iomap(pdev, bar, io_size);
949 if (!ioaddr) {
950 rc = -EIO;
951 dev_err(&pdev->dev,
952 "ioremap failed for device %s, region 0x%X @ 0x%lX\n",
953 pci_name(pdev), io_size, memaddr);
954 goto err_out_free_res;
955 }
956
957 #ifdef USE_MMIO
958 enable_mmio(pioaddr, quirks);
959
960 /* Check that selected MMIO registers match the PIO ones */
961 i = 0;
962 while (mmio_verify_registers[i]) {
963 int reg = mmio_verify_registers[i++];
964 unsigned char a = inb(pioaddr+reg);
965 unsigned char b = readb(ioaddr+reg);
966 if (a != b) {
967 rc = -EIO;
968 dev_err(&pdev->dev,
969 "MMIO do not match PIO [%02x] (%02x != %02x)\n",
970 reg, a, b);
971 goto err_out_unmap;
972 }
973 }
974 #endif /* USE_MMIO */
975
976 dev->base_addr = (unsigned long)ioaddr;
977 rp->base = ioaddr;
978
979 /* Get chip registers into a sane state */
980 rhine_power_init(dev);
981 rhine_hw_init(dev, pioaddr);
982
983 for (i = 0; i < 6; i++)
984 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
985
986 if (!is_valid_ether_addr(dev->dev_addr)) {
987 /* Report it and use a random ethernet address instead */
988 netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
989 random_ether_addr(dev->dev_addr);
990 netdev_info(dev, "Using random MAC address: %pM\n",
991 dev->dev_addr);
992 }
993 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
994
995 /* For Rhine-I/II, phy_id is loaded from EEPROM */
996 if (!phy_id)
997 phy_id = ioread8(ioaddr + 0x6C);
998
999 dev->irq = pdev->irq;
1000
1001 spin_lock_init(&rp->lock);
1002 mutex_init(&rp->task_lock);
1003 INIT_WORK(&rp->reset_task, rhine_reset_task);
1004 INIT_WORK(&rp->slow_event_task, rhine_slow_event_task);
1005
1006 rp->mii_if.dev = dev;
1007 rp->mii_if.mdio_read = mdio_read;
1008 rp->mii_if.mdio_write = mdio_write;
1009 rp->mii_if.phy_id_mask = 0x1f;
1010 rp->mii_if.reg_num_mask = 0x1f;
1011
1012 /* The chip-specific entries in the device structure. */
1013 dev->netdev_ops = &rhine_netdev_ops;
1014 dev->ethtool_ops = &netdev_ethtool_ops,
1015 dev->watchdog_timeo = TX_TIMEOUT;
1016
1017 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
1018
1019 if (rp->quirks & rqRhineI)
1020 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
1021
1022 if (pdev->revision >= VT6105M)
1023 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
1024 NETIF_F_HW_VLAN_FILTER;
1025
1026 /* dev->name not defined before register_netdev()! */
1027 rc = register_netdev(dev);
1028 if (rc)
1029 goto err_out_unmap;
1030
1031 netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n",
1032 name,
1033 #ifdef USE_MMIO
1034 memaddr,
1035 #else
1036 (long)ioaddr,
1037 #endif
1038 dev->dev_addr, pdev->irq);
1039
1040 pci_set_drvdata(pdev, dev);
1041
1042 {
1043 u16 mii_cmd;
1044 int mii_status = mdio_read(dev, phy_id, 1);
1045 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
1046 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
1047 if (mii_status != 0xffff && mii_status != 0x0000) {
1048 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
1049 netdev_info(dev,
1050 "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",
1051 phy_id,
1052 mii_status, rp->mii_if.advertising,
1053 mdio_read(dev, phy_id, 5));
1054
1055 /* set IFF_RUNNING */
1056 if (mii_status & BMSR_LSTATUS)
1057 netif_carrier_on(dev);
1058 else
1059 netif_carrier_off(dev);
1060
1061 }
1062 }
1063 rp->mii_if.phy_id = phy_id;
1064 if (avoid_D3)
1065 netif_info(rp, probe, dev, "No D3 power state at shutdown\n");
1066
1067 return 0;
1068
1069 err_out_unmap:
1070 pci_iounmap(pdev, ioaddr);
1071 err_out_free_res:
1072 pci_release_regions(pdev);
1073 err_out_free_netdev:
1074 free_netdev(dev);
1075 err_out:
1076 return rc;
1077 }
1078
1079 static int alloc_ring(struct net_device* dev)
1080 {
1081 struct rhine_private *rp = netdev_priv(dev);
1082 void *ring;
1083 dma_addr_t ring_dma;
1084
1085 ring = pci_alloc_consistent(rp->pdev,
1086 RX_RING_SIZE * sizeof(struct rx_desc) +
1087 TX_RING_SIZE * sizeof(struct tx_desc),
1088 &ring_dma);
1089 if (!ring) {
1090 netdev_err(dev, "Could not allocate DMA memory\n");
1091 return -ENOMEM;
1092 }
1093 if (rp->quirks & rqRhineI) {
1094 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
1095 PKT_BUF_SZ * TX_RING_SIZE,
1096 &rp->tx_bufs_dma);
1097 if (rp->tx_bufs == NULL) {
1098 pci_free_consistent(rp->pdev,
1099 RX_RING_SIZE * sizeof(struct rx_desc) +
1100 TX_RING_SIZE * sizeof(struct tx_desc),
1101 ring, ring_dma);
1102 return -ENOMEM;
1103 }
1104 }
1105
1106 rp->rx_ring = ring;
1107 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
1108 rp->rx_ring_dma = ring_dma;
1109 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
1110
1111 return 0;
1112 }
1113
1114 static void free_ring(struct net_device* dev)
1115 {
1116 struct rhine_private *rp = netdev_priv(dev);
1117
1118 pci_free_consistent(rp->pdev,
1119 RX_RING_SIZE * sizeof(struct rx_desc) +
1120 TX_RING_SIZE * sizeof(struct tx_desc),
1121 rp->rx_ring, rp->rx_ring_dma);
1122 rp->tx_ring = NULL;
1123
1124 if (rp->tx_bufs)
1125 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
1126 rp->tx_bufs, rp->tx_bufs_dma);
1127
1128 rp->tx_bufs = NULL;
1129
1130 }
1131
1132 static void alloc_rbufs(struct net_device *dev)
1133 {
1134 struct rhine_private *rp = netdev_priv(dev);
1135 dma_addr_t next;
1136 int i;
1137
1138 rp->dirty_rx = rp->cur_rx = 0;
1139
1140 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1141 rp->rx_head_desc = &rp->rx_ring[0];
1142 next = rp->rx_ring_dma;
1143
1144 /* Init the ring entries */
1145 for (i = 0; i < RX_RING_SIZE; i++) {
1146 rp->rx_ring[i].rx_status = 0;
1147 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
1148 next += sizeof(struct rx_desc);
1149 rp->rx_ring[i].next_desc = cpu_to_le32(next);
1150 rp->rx_skbuff[i] = NULL;
1151 }
1152 /* Mark the last entry as wrapping the ring. */
1153 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
1154
1155 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1156 for (i = 0; i < RX_RING_SIZE; i++) {
1157 struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1158 rp->rx_skbuff[i] = skb;
1159 if (skb == NULL)
1160 break;
1161 skb->dev = dev; /* Mark as being used by this device. */
1162
1163 rp->rx_skbuff_dma[i] =
1164 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
1165 PCI_DMA_FROMDEVICE);
1166
1167 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
1168 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
1169 }
1170 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1171 }
1172
1173 static void free_rbufs(struct net_device* dev)
1174 {
1175 struct rhine_private *rp = netdev_priv(dev);
1176 int i;
1177
1178 /* Free all the skbuffs in the Rx queue. */
1179 for (i = 0; i < RX_RING_SIZE; i++) {
1180 rp->rx_ring[i].rx_status = 0;
1181 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1182 if (rp->rx_skbuff[i]) {
1183 pci_unmap_single(rp->pdev,
1184 rp->rx_skbuff_dma[i],
1185 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1186 dev_kfree_skb(rp->rx_skbuff[i]);
1187 }
1188 rp->rx_skbuff[i] = NULL;
1189 }
1190 }
1191
1192 static void alloc_tbufs(struct net_device* dev)
1193 {
1194 struct rhine_private *rp = netdev_priv(dev);
1195 dma_addr_t next;
1196 int i;
1197
1198 rp->dirty_tx = rp->cur_tx = 0;
1199 next = rp->tx_ring_dma;
1200 for (i = 0; i < TX_RING_SIZE; i++) {
1201 rp->tx_skbuff[i] = NULL;
1202 rp->tx_ring[i].tx_status = 0;
1203 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1204 next += sizeof(struct tx_desc);
1205 rp->tx_ring[i].next_desc = cpu_to_le32(next);
1206 if (rp->quirks & rqRhineI)
1207 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
1208 }
1209 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
1210
1211 }
1212
1213 static void free_tbufs(struct net_device* dev)
1214 {
1215 struct rhine_private *rp = netdev_priv(dev);
1216 int i;
1217
1218 for (i = 0; i < TX_RING_SIZE; i++) {
1219 rp->tx_ring[i].tx_status = 0;
1220 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1221 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1222 if (rp->tx_skbuff[i]) {
1223 if (rp->tx_skbuff_dma[i]) {
1224 pci_unmap_single(rp->pdev,
1225 rp->tx_skbuff_dma[i],
1226 rp->tx_skbuff[i]->len,
1227 PCI_DMA_TODEVICE);
1228 }
1229 dev_kfree_skb(rp->tx_skbuff[i]);
1230 }
1231 rp->tx_skbuff[i] = NULL;
1232 rp->tx_buf[i] = NULL;
1233 }
1234 }
1235
1236 static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1237 {
1238 struct rhine_private *rp = netdev_priv(dev);
1239 void __iomem *ioaddr = rp->base;
1240
1241 mii_check_media(&rp->mii_if, netif_msg_link(rp), init_media);
1242
1243 if (rp->mii_if.full_duplex)
1244 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1245 ioaddr + ChipCmd1);
1246 else
1247 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1248 ioaddr + ChipCmd1);
1249
1250 netif_info(rp, link, dev, "force_media %d, carrier %d\n",
1251 rp->mii_if.force_media, netif_carrier_ok(dev));
1252 }
1253
1254 /* Called after status of force_media possibly changed */
1255 static void rhine_set_carrier(struct mii_if_info *mii)
1256 {
1257 struct net_device *dev = mii->dev;
1258 struct rhine_private *rp = netdev_priv(dev);
1259
1260 if (mii->force_media) {
1261 /* autoneg is off: Link is always assumed to be up */
1262 if (!netif_carrier_ok(dev))
1263 netif_carrier_on(dev);
1264 } else /* Let MMI library update carrier status */
1265 rhine_check_media(dev, 0);
1266
1267 netif_info(rp, link, dev, "force_media %d, carrier %d\n",
1268 mii->force_media, netif_carrier_ok(dev));
1269 }
1270
1271 /**
1272 * rhine_set_cam - set CAM multicast filters
1273 * @ioaddr: register block of this Rhine
1274 * @idx: multicast CAM index [0..MCAM_SIZE-1]
1275 * @addr: multicast address (6 bytes)
1276 *
1277 * Load addresses into multicast filters.
1278 */
1279 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
1280 {
1281 int i;
1282
1283 iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1284 wmb();
1285
1286 /* Paranoid -- idx out of range should never happen */
1287 idx &= (MCAM_SIZE - 1);
1288
1289 iowrite8((u8) idx, ioaddr + CamAddr);
1290
1291 for (i = 0; i < 6; i++, addr++)
1292 iowrite8(*addr, ioaddr + MulticastFilter0 + i);
1293 udelay(10);
1294 wmb();
1295
1296 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1297 udelay(10);
1298
1299 iowrite8(0, ioaddr + CamCon);
1300 }
1301
1302 /**
1303 * rhine_set_vlan_cam - set CAM VLAN filters
1304 * @ioaddr: register block of this Rhine
1305 * @idx: VLAN CAM index [0..VCAM_SIZE-1]
1306 * @addr: VLAN ID (2 bytes)
1307 *
1308 * Load addresses into VLAN filters.
1309 */
1310 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
1311 {
1312 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1313 wmb();
1314
1315 /* Paranoid -- idx out of range should never happen */
1316 idx &= (VCAM_SIZE - 1);
1317
1318 iowrite8((u8) idx, ioaddr + CamAddr);
1319
1320 iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
1321 udelay(10);
1322 wmb();
1323
1324 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
1325 udelay(10);
1326
1327 iowrite8(0, ioaddr + CamCon);
1328 }
1329
1330 /**
1331 * rhine_set_cam_mask - set multicast CAM mask
1332 * @ioaddr: register block of this Rhine
1333 * @mask: multicast CAM mask
1334 *
1335 * Mask sets multicast filters active/inactive.
1336 */
1337 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
1338 {
1339 iowrite8(CAMC_CAMEN, ioaddr + CamCon);
1340 wmb();
1341
1342 /* write mask */
1343 iowrite32(mask, ioaddr + CamMask);
1344
1345 /* disable CAMEN */
1346 iowrite8(0, ioaddr + CamCon);
1347 }
1348
1349 /**
1350 * rhine_set_vlan_cam_mask - set VLAN CAM mask
1351 * @ioaddr: register block of this Rhine
1352 * @mask: VLAN CAM mask
1353 *
1354 * Mask sets VLAN filters active/inactive.
1355 */
1356 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
1357 {
1358 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
1359 wmb();
1360
1361 /* write mask */
1362 iowrite32(mask, ioaddr + CamMask);
1363
1364 /* disable CAMEN */
1365 iowrite8(0, ioaddr + CamCon);
1366 }
1367
1368 /**
1369 * rhine_init_cam_filter - initialize CAM filters
1370 * @dev: network device
1371 *
1372 * Initialize (disable) hardware VLAN and multicast support on this
1373 * Rhine.
1374 */
1375 static void rhine_init_cam_filter(struct net_device *dev)
1376 {
1377 struct rhine_private *rp = netdev_priv(dev);
1378 void __iomem *ioaddr = rp->base;
1379
1380 /* Disable all CAMs */
1381 rhine_set_vlan_cam_mask(ioaddr, 0);
1382 rhine_set_cam_mask(ioaddr, 0);
1383
1384 /* disable hardware VLAN support */
1385 BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
1386 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
1387 }
1388
1389 /**
1390 * rhine_update_vcam - update VLAN CAM filters
1391 * @rp: rhine_private data of this Rhine
1392 *
1393 * Update VLAN CAM filters to match configuration change.
1394 */
1395 static void rhine_update_vcam(struct net_device *dev)
1396 {
1397 struct rhine_private *rp = netdev_priv(dev);
1398 void __iomem *ioaddr = rp->base;
1399 u16 vid;
1400 u32 vCAMmask = 0; /* 32 vCAMs (6105M and better) */
1401 unsigned int i = 0;
1402
1403 for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
1404 rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
1405 vCAMmask |= 1 << i;
1406 if (++i >= VCAM_SIZE)
1407 break;
1408 }
1409 rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
1410 }
1411
1412 static int rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
1413 {
1414 struct rhine_private *rp = netdev_priv(dev);
1415
1416 spin_lock_bh(&rp->lock);
1417 set_bit(vid, rp->active_vlans);
1418 rhine_update_vcam(dev);
1419 spin_unlock_bh(&rp->lock);
1420 return 0;
1421 }
1422
1423 static int rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1424 {
1425 struct rhine_private *rp = netdev_priv(dev);
1426
1427 spin_lock_bh(&rp->lock);
1428 clear_bit(vid, rp->active_vlans);
1429 rhine_update_vcam(dev);
1430 spin_unlock_bh(&rp->lock);
1431 return 0;
1432 }
1433
1434 static void init_registers(struct net_device *dev)
1435 {
1436 struct rhine_private *rp = netdev_priv(dev);
1437 void __iomem *ioaddr = rp->base;
1438 int i;
1439
1440 for (i = 0; i < 6; i++)
1441 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1442
1443 /* Initialize other registers. */
1444 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1445 /* Configure initial FIFO thresholds. */
1446 iowrite8(0x20, ioaddr + TxConfig);
1447 rp->tx_thresh = 0x20;
1448 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1449
1450 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1451 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1452
1453 rhine_set_rx_mode(dev);
1454
1455 if (rp->pdev->revision >= VT6105M)
1456 rhine_init_cam_filter(dev);
1457
1458 napi_enable(&rp->napi);
1459
1460 iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable);
1461
1462 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1463 ioaddr + ChipCmd);
1464 rhine_check_media(dev, 1);
1465 }
1466
1467 /* Enable MII link status auto-polling (required for IntrLinkChange) */
1468 static void rhine_enable_linkmon(struct rhine_private *rp)
1469 {
1470 void __iomem *ioaddr = rp->base;
1471
1472 iowrite8(0, ioaddr + MIICmd);
1473 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1474 iowrite8(0x80, ioaddr + MIICmd);
1475
1476 rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
1477
1478 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1479 }
1480
1481 /* Disable MII link status auto-polling (required for MDIO access) */
1482 static void rhine_disable_linkmon(struct rhine_private *rp)
1483 {
1484 void __iomem *ioaddr = rp->base;
1485
1486 iowrite8(0, ioaddr + MIICmd);
1487
1488 if (rp->quirks & rqRhineI) {
1489 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1490
1491 /* Can be called from ISR. Evil. */
1492 mdelay(1);
1493
1494 /* 0x80 must be set immediately before turning it off */
1495 iowrite8(0x80, ioaddr + MIICmd);
1496
1497 rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
1498
1499 /* Heh. Now clear 0x80 again. */
1500 iowrite8(0, ioaddr + MIICmd);
1501 }
1502 else
1503 rhine_wait_bit_high(rp, MIIRegAddr, 0x80);
1504 }
1505
1506 /* Read and write over the MII Management Data I/O (MDIO) interface. */
1507
1508 static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1509 {
1510 struct rhine_private *rp = netdev_priv(dev);
1511 void __iomem *ioaddr = rp->base;
1512 int result;
1513
1514 rhine_disable_linkmon(rp);
1515
1516 /* rhine_disable_linkmon already cleared MIICmd */
1517 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1518 iowrite8(regnum, ioaddr + MIIRegAddr);
1519 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1520 rhine_wait_bit_low(rp, MIICmd, 0x40);
1521 result = ioread16(ioaddr + MIIData);
1522
1523 rhine_enable_linkmon(rp);
1524 return result;
1525 }
1526
1527 static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1528 {
1529 struct rhine_private *rp = netdev_priv(dev);
1530 void __iomem *ioaddr = rp->base;
1531
1532 rhine_disable_linkmon(rp);
1533
1534 /* rhine_disable_linkmon already cleared MIICmd */
1535 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1536 iowrite8(regnum, ioaddr + MIIRegAddr);
1537 iowrite16(value, ioaddr + MIIData);
1538 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1539 rhine_wait_bit_low(rp, MIICmd, 0x20);
1540
1541 rhine_enable_linkmon(rp);
1542 }
1543
1544 static void rhine_task_disable(struct rhine_private *rp)
1545 {
1546 mutex_lock(&rp->task_lock);
1547 rp->task_enable = false;
1548 mutex_unlock(&rp->task_lock);
1549
1550 cancel_work_sync(&rp->slow_event_task);
1551 cancel_work_sync(&rp->reset_task);
1552 }
1553
1554 static void rhine_task_enable(struct rhine_private *rp)
1555 {
1556 mutex_lock(&rp->task_lock);
1557 rp->task_enable = true;
1558 mutex_unlock(&rp->task_lock);
1559 }
1560
1561 static int rhine_open(struct net_device *dev)
1562 {
1563 struct rhine_private *rp = netdev_priv(dev);
1564 void __iomem *ioaddr = rp->base;
1565 int rc;
1566
1567 rc = request_irq(rp->pdev->irq, rhine_interrupt, IRQF_SHARED, dev->name,
1568 dev);
1569 if (rc)
1570 return rc;
1571
1572 netif_dbg(rp, ifup, dev, "%s() irq %d\n", __func__, rp->pdev->irq);
1573
1574 rc = alloc_ring(dev);
1575 if (rc) {
1576 free_irq(rp->pdev->irq, dev);
1577 return rc;
1578 }
1579 alloc_rbufs(dev);
1580 alloc_tbufs(dev);
1581 rhine_chip_reset(dev);
1582 rhine_task_enable(rp);
1583 init_registers(dev);
1584
1585 netif_dbg(rp, ifup, dev, "%s() Done - status %04x MII status: %04x\n",
1586 __func__, ioread16(ioaddr + ChipCmd),
1587 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1588
1589 netif_start_queue(dev);
1590
1591 return 0;
1592 }
1593
1594 static void rhine_reset_task(struct work_struct *work)
1595 {
1596 struct rhine_private *rp = container_of(work, struct rhine_private,
1597 reset_task);
1598 struct net_device *dev = rp->dev;
1599
1600 mutex_lock(&rp->task_lock);
1601
1602 if (!rp->task_enable)
1603 goto out_unlock;
1604
1605 napi_disable(&rp->napi);
1606 spin_lock_bh(&rp->lock);
1607
1608 /* clear all descriptors */
1609 free_tbufs(dev);
1610 free_rbufs(dev);
1611 alloc_tbufs(dev);
1612 alloc_rbufs(dev);
1613
1614 /* Reinitialize the hardware. */
1615 rhine_chip_reset(dev);
1616 init_registers(dev);
1617
1618 spin_unlock_bh(&rp->lock);
1619
1620 dev->trans_start = jiffies; /* prevent tx timeout */
1621 dev->stats.tx_errors++;
1622 netif_wake_queue(dev);
1623
1624 out_unlock:
1625 mutex_unlock(&rp->task_lock);
1626 }
1627
1628 static void rhine_tx_timeout(struct net_device *dev)
1629 {
1630 struct rhine_private *rp = netdev_priv(dev);
1631 void __iomem *ioaddr = rp->base;
1632
1633 netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",
1634 ioread16(ioaddr + IntrStatus),
1635 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1636
1637 schedule_work(&rp->reset_task);
1638 }
1639
1640 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
1641 struct net_device *dev)
1642 {
1643 struct rhine_private *rp = netdev_priv(dev);
1644 void __iomem *ioaddr = rp->base;
1645 unsigned entry;
1646
1647 /* Caution: the write order is important here, set the field
1648 with the "ownership" bits last. */
1649
1650 /* Calculate the next Tx descriptor entry. */
1651 entry = rp->cur_tx % TX_RING_SIZE;
1652
1653 if (skb_padto(skb, ETH_ZLEN))
1654 return NETDEV_TX_OK;
1655
1656 rp->tx_skbuff[entry] = skb;
1657
1658 if ((rp->quirks & rqRhineI) &&
1659 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
1660 /* Must use alignment buffer. */
1661 if (skb->len > PKT_BUF_SZ) {
1662 /* packet too long, drop it */
1663 dev_kfree_skb(skb);
1664 rp->tx_skbuff[entry] = NULL;
1665 dev->stats.tx_dropped++;
1666 return NETDEV_TX_OK;
1667 }
1668
1669 /* Padding is not copied and so must be redone. */
1670 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1671 if (skb->len < ETH_ZLEN)
1672 memset(rp->tx_buf[entry] + skb->len, 0,
1673 ETH_ZLEN - skb->len);
1674 rp->tx_skbuff_dma[entry] = 0;
1675 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1676 (rp->tx_buf[entry] -
1677 rp->tx_bufs));
1678 } else {
1679 rp->tx_skbuff_dma[entry] =
1680 pci_map_single(rp->pdev, skb->data, skb->len,
1681 PCI_DMA_TODEVICE);
1682 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1683 }
1684
1685 rp->tx_ring[entry].desc_length =
1686 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1687
1688 if (unlikely(vlan_tx_tag_present(skb))) {
1689 rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);
1690 /* request tagging */
1691 rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
1692 }
1693 else
1694 rp->tx_ring[entry].tx_status = 0;
1695
1696 /* lock eth irq */
1697 wmb();
1698 rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
1699 wmb();
1700
1701 rp->cur_tx++;
1702
1703 /* Non-x86 Todo: explicitly flush cache lines here. */
1704
1705 if (vlan_tx_tag_present(skb))
1706 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
1707 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
1708
1709 /* Wake the potentially-idle transmit channel */
1710 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1711 ioaddr + ChipCmd1);
1712 IOSYNC;
1713
1714 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1715 netif_stop_queue(dev);
1716
1717 netif_dbg(rp, tx_queued, dev, "Transmit frame #%d queued in slot %d\n",
1718 rp->cur_tx - 1, entry);
1719
1720 return NETDEV_TX_OK;
1721 }
1722
1723 static void rhine_irq_disable(struct rhine_private *rp)
1724 {
1725 iowrite16(0x0000, rp->base + IntrEnable);
1726 mmiowb();
1727 }
1728
1729 /* The interrupt handler does all of the Rx thread work and cleans up
1730 after the Tx thread. */
1731 static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
1732 {
1733 struct net_device *dev = dev_instance;
1734 struct rhine_private *rp = netdev_priv(dev);
1735 u32 status;
1736 int handled = 0;
1737
1738 status = rhine_get_events(rp);
1739
1740 netif_dbg(rp, intr, dev, "Interrupt, status %08x\n", status);
1741
1742 if (status & RHINE_EVENT) {
1743 handled = 1;
1744
1745 rhine_irq_disable(rp);
1746 napi_schedule(&rp->napi);
1747 }
1748
1749 if (status & ~(IntrLinkChange | IntrStatsMax | RHINE_EVENT_NAPI)) {
1750 netif_err(rp, intr, dev, "Something Wicked happened! %08x\n",
1751 status);
1752 }
1753
1754 return IRQ_RETVAL(handled);
1755 }
1756
1757 /* This routine is logically part of the interrupt handler, but isolated
1758 for clarity. */
1759 static void rhine_tx(struct net_device *dev)
1760 {
1761 struct rhine_private *rp = netdev_priv(dev);
1762 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1763
1764 /* find and cleanup dirty tx descriptors */
1765 while (rp->dirty_tx != rp->cur_tx) {
1766 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1767 netif_dbg(rp, tx_done, dev, "Tx scavenge %d status %08x\n",
1768 entry, txstatus);
1769 if (txstatus & DescOwn)
1770 break;
1771 if (txstatus & 0x8000) {
1772 netif_dbg(rp, tx_done, dev,
1773 "Transmit error, Tx status %08x\n", txstatus);
1774 dev->stats.tx_errors++;
1775 if (txstatus & 0x0400)
1776 dev->stats.tx_carrier_errors++;
1777 if (txstatus & 0x0200)
1778 dev->stats.tx_window_errors++;
1779 if (txstatus & 0x0100)
1780 dev->stats.tx_aborted_errors++;
1781 if (txstatus & 0x0080)
1782 dev->stats.tx_heartbeat_errors++;
1783 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1784 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1785 dev->stats.tx_fifo_errors++;
1786 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1787 break; /* Keep the skb - we try again */
1788 }
1789 /* Transmitter restarted in 'abnormal' handler. */
1790 } else {
1791 if (rp->quirks & rqRhineI)
1792 dev->stats.collisions += (txstatus >> 3) & 0x0F;
1793 else
1794 dev->stats.collisions += txstatus & 0x0F;
1795 netif_dbg(rp, tx_done, dev, "collisions: %1.1x:%1.1x\n",
1796 (txstatus >> 3) & 0xF, txstatus & 0xF);
1797 dev->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1798 dev->stats.tx_packets++;
1799 }
1800 /* Free the original skb. */
1801 if (rp->tx_skbuff_dma[entry]) {
1802 pci_unmap_single(rp->pdev,
1803 rp->tx_skbuff_dma[entry],
1804 rp->tx_skbuff[entry]->len,
1805 PCI_DMA_TODEVICE);
1806 }
1807 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1808 rp->tx_skbuff[entry] = NULL;
1809 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1810 }
1811 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1812 netif_wake_queue(dev);
1813 }
1814
1815 /**
1816 * rhine_get_vlan_tci - extract TCI from Rx data buffer
1817 * @skb: pointer to sk_buff
1818 * @data_size: used data area of the buffer including CRC
1819 *
1820 * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
1821 * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
1822 * aligned following the CRC.
1823 */
1824 static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
1825 {
1826 u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
1827 return be16_to_cpup((__be16 *)trailer);
1828 }
1829
1830 /* Process up to limit frames from receive ring */
1831 static int rhine_rx(struct net_device *dev, int limit)
1832 {
1833 struct rhine_private *rp = netdev_priv(dev);
1834 int count;
1835 int entry = rp->cur_rx % RX_RING_SIZE;
1836
1837 netif_dbg(rp, rx_status, dev, "%s(), entry %d status %08x\n", __func__,
1838 entry, le32_to_cpu(rp->rx_head_desc->rx_status));
1839
1840 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1841 for (count = 0; count < limit; ++count) {
1842 struct rx_desc *desc = rp->rx_head_desc;
1843 u32 desc_status = le32_to_cpu(desc->rx_status);
1844 u32 desc_length = le32_to_cpu(desc->desc_length);
1845 int data_size = desc_status >> 16;
1846
1847 if (desc_status & DescOwn)
1848 break;
1849
1850 netif_dbg(rp, rx_status, dev, "%s() status %08x\n", __func__,
1851 desc_status);
1852
1853 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1854 if ((desc_status & RxWholePkt) != RxWholePkt) {
1855 netdev_warn(dev,
1856 "Oversized Ethernet frame spanned multiple buffers, "
1857 "entry %#x length %d status %08x!\n",
1858 entry, data_size,
1859 desc_status);
1860 netdev_warn(dev,
1861 "Oversized Ethernet frame %p vs %p\n",
1862 rp->rx_head_desc,
1863 &rp->rx_ring[entry]);
1864 dev->stats.rx_length_errors++;
1865 } else if (desc_status & RxErr) {
1866 /* There was a error. */
1867 netif_dbg(rp, rx_err, dev,
1868 "%s() Rx error %08x\n", __func__,
1869 desc_status);
1870 dev->stats.rx_errors++;
1871 if (desc_status & 0x0030)
1872 dev->stats.rx_length_errors++;
1873 if (desc_status & 0x0048)
1874 dev->stats.rx_fifo_errors++;
1875 if (desc_status & 0x0004)
1876 dev->stats.rx_frame_errors++;
1877 if (desc_status & 0x0002) {
1878 /* this can also be updated outside the interrupt handler */
1879 spin_lock(&rp->lock);
1880 dev->stats.rx_crc_errors++;
1881 spin_unlock(&rp->lock);
1882 }
1883 }
1884 } else {
1885 struct sk_buff *skb = NULL;
1886 /* Length should omit the CRC */
1887 int pkt_len = data_size - 4;
1888 u16 vlan_tci = 0;
1889
1890 /* Check if the packet is long enough to accept without
1891 copying to a minimally-sized skbuff. */
1892 if (pkt_len < rx_copybreak)
1893 skb = netdev_alloc_skb_ip_align(dev, pkt_len);
1894 if (skb) {
1895 pci_dma_sync_single_for_cpu(rp->pdev,
1896 rp->rx_skbuff_dma[entry],
1897 rp->rx_buf_sz,
1898 PCI_DMA_FROMDEVICE);
1899
1900 skb_copy_to_linear_data(skb,
1901 rp->rx_skbuff[entry]->data,
1902 pkt_len);
1903 skb_put(skb, pkt_len);
1904 pci_dma_sync_single_for_device(rp->pdev,
1905 rp->rx_skbuff_dma[entry],
1906 rp->rx_buf_sz,
1907 PCI_DMA_FROMDEVICE);
1908 } else {
1909 skb = rp->rx_skbuff[entry];
1910 if (skb == NULL) {
1911 netdev_err(dev, "Inconsistent Rx descriptor chain\n");
1912 break;
1913 }
1914 rp->rx_skbuff[entry] = NULL;
1915 skb_put(skb, pkt_len);
1916 pci_unmap_single(rp->pdev,
1917 rp->rx_skbuff_dma[entry],
1918 rp->rx_buf_sz,
1919 PCI_DMA_FROMDEVICE);
1920 }
1921
1922 if (unlikely(desc_length & DescTag))
1923 vlan_tci = rhine_get_vlan_tci(skb, data_size);
1924
1925 skb->protocol = eth_type_trans(skb, dev);
1926
1927 if (unlikely(desc_length & DescTag))
1928 __vlan_hwaccel_put_tag(skb, vlan_tci);
1929 netif_receive_skb(skb);
1930 dev->stats.rx_bytes += pkt_len;
1931 dev->stats.rx_packets++;
1932 }
1933 entry = (++rp->cur_rx) % RX_RING_SIZE;
1934 rp->rx_head_desc = &rp->rx_ring[entry];
1935 }
1936
1937 /* Refill the Rx ring buffers. */
1938 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1939 struct sk_buff *skb;
1940 entry = rp->dirty_rx % RX_RING_SIZE;
1941 if (rp->rx_skbuff[entry] == NULL) {
1942 skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1943 rp->rx_skbuff[entry] = skb;
1944 if (skb == NULL)
1945 break; /* Better luck next round. */
1946 skb->dev = dev; /* Mark as being used by this device. */
1947 rp->rx_skbuff_dma[entry] =
1948 pci_map_single(rp->pdev, skb->data,
1949 rp->rx_buf_sz,
1950 PCI_DMA_FROMDEVICE);
1951 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1952 }
1953 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1954 }
1955
1956 return count;
1957 }
1958
1959 static void rhine_restart_tx(struct net_device *dev) {
1960 struct rhine_private *rp = netdev_priv(dev);
1961 void __iomem *ioaddr = rp->base;
1962 int entry = rp->dirty_tx % TX_RING_SIZE;
1963 u32 intr_status;
1964
1965 /*
1966 * If new errors occurred, we need to sort them out before doing Tx.
1967 * In that case the ISR will be back here RSN anyway.
1968 */
1969 intr_status = rhine_get_events(rp);
1970
1971 if ((intr_status & IntrTxErrSummary) == 0) {
1972
1973 /* We know better than the chip where it should continue. */
1974 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1975 ioaddr + TxRingPtr);
1976
1977 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1978 ioaddr + ChipCmd);
1979
1980 if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
1981 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
1982 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
1983
1984 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1985 ioaddr + ChipCmd1);
1986 IOSYNC;
1987 }
1988 else {
1989 /* This should never happen */
1990 netif_warn(rp, tx_err, dev, "another error occurred %08x\n",
1991 intr_status);
1992 }
1993
1994 }
1995
1996 static void rhine_slow_event_task(struct work_struct *work)
1997 {
1998 struct rhine_private *rp =
1999 container_of(work, struct rhine_private, slow_event_task);
2000 struct net_device *dev = rp->dev;
2001 u32 intr_status;
2002
2003 mutex_lock(&rp->task_lock);
2004
2005 if (!rp->task_enable)
2006 goto out_unlock;
2007
2008 intr_status = rhine_get_events(rp);
2009 rhine_ack_events(rp, intr_status & RHINE_EVENT_SLOW);
2010
2011 if (intr_status & IntrLinkChange)
2012 rhine_check_media(dev, 0);
2013
2014 if (intr_status & IntrPCIErr)
2015 netif_warn(rp, hw, dev, "PCI error\n");
2016
2017 napi_disable(&rp->napi);
2018 rhine_irq_disable(rp);
2019 /* Slow and safe. Consider __napi_schedule as a replacement ? */
2020 napi_enable(&rp->napi);
2021 napi_schedule(&rp->napi);
2022
2023 out_unlock:
2024 mutex_unlock(&rp->task_lock);
2025 }
2026
2027 static struct net_device_stats *rhine_get_stats(struct net_device *dev)
2028 {
2029 struct rhine_private *rp = netdev_priv(dev);
2030
2031 spin_lock_bh(&rp->lock);
2032 rhine_update_rx_crc_and_missed_errord(rp);
2033 spin_unlock_bh(&rp->lock);
2034
2035 return &dev->stats;
2036 }
2037
2038 static void rhine_set_rx_mode(struct net_device *dev)
2039 {
2040 struct rhine_private *rp = netdev_priv(dev);
2041 void __iomem *ioaddr = rp->base;
2042 u32 mc_filter[2]; /* Multicast hash filter */
2043 u8 rx_mode = 0x0C; /* Note: 0x02=accept runt, 0x01=accept errs */
2044 struct netdev_hw_addr *ha;
2045
2046 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2047 rx_mode = 0x1C;
2048 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
2049 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
2050 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2051 (dev->flags & IFF_ALLMULTI)) {
2052 /* Too many to match, or accept all multicasts. */
2053 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
2054 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
2055 } else if (rp->pdev->revision >= VT6105M) {
2056 int i = 0;
2057 u32 mCAMmask = 0; /* 32 mCAMs (6105M and better) */
2058 netdev_for_each_mc_addr(ha, dev) {
2059 if (i == MCAM_SIZE)
2060 break;
2061 rhine_set_cam(ioaddr, i, ha->addr);
2062 mCAMmask |= 1 << i;
2063 i++;
2064 }
2065 rhine_set_cam_mask(ioaddr, mCAMmask);
2066 } else {
2067 memset(mc_filter, 0, sizeof(mc_filter));
2068 netdev_for_each_mc_addr(ha, dev) {
2069 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2070
2071 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2072 }
2073 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
2074 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
2075 }
2076 /* enable/disable VLAN receive filtering */
2077 if (rp->pdev->revision >= VT6105M) {
2078 if (dev->flags & IFF_PROMISC)
2079 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2080 else
2081 BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
2082 }
2083 BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
2084 }
2085
2086 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2087 {
2088 struct rhine_private *rp = netdev_priv(dev);
2089
2090 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2091 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2092 strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
2093 }
2094
2095 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2096 {
2097 struct rhine_private *rp = netdev_priv(dev);
2098 int rc;
2099
2100 mutex_lock(&rp->task_lock);
2101 rc = mii_ethtool_gset(&rp->mii_if, cmd);
2102 mutex_unlock(&rp->task_lock);
2103
2104 return rc;
2105 }
2106
2107 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2108 {
2109 struct rhine_private *rp = netdev_priv(dev);
2110 int rc;
2111
2112 mutex_lock(&rp->task_lock);
2113 rc = mii_ethtool_sset(&rp->mii_if, cmd);
2114 rhine_set_carrier(&rp->mii_if);
2115 mutex_unlock(&rp->task_lock);
2116
2117 return rc;
2118 }
2119
2120 static int netdev_nway_reset(struct net_device *dev)
2121 {
2122 struct rhine_private *rp = netdev_priv(dev);
2123
2124 return mii_nway_restart(&rp->mii_if);
2125 }
2126
2127 static u32 netdev_get_link(struct net_device *dev)
2128 {
2129 struct rhine_private *rp = netdev_priv(dev);
2130
2131 return mii_link_ok(&rp->mii_if);
2132 }
2133
2134 static u32 netdev_get_msglevel(struct net_device *dev)
2135 {
2136 struct rhine_private *rp = netdev_priv(dev);
2137
2138 return rp->msg_enable;
2139 }
2140
2141 static void netdev_set_msglevel(struct net_device *dev, u32 value)
2142 {
2143 struct rhine_private *rp = netdev_priv(dev);
2144
2145 rp->msg_enable = value;
2146 }
2147
2148 static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2149 {
2150 struct rhine_private *rp = netdev_priv(dev);
2151
2152 if (!(rp->quirks & rqWOL))
2153 return;
2154
2155 spin_lock_irq(&rp->lock);
2156 wol->supported = WAKE_PHY | WAKE_MAGIC |
2157 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
2158 wol->wolopts = rp->wolopts;
2159 spin_unlock_irq(&rp->lock);
2160 }
2161
2162 static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2163 {
2164 struct rhine_private *rp = netdev_priv(dev);
2165 u32 support = WAKE_PHY | WAKE_MAGIC |
2166 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
2167
2168 if (!(rp->quirks & rqWOL))
2169 return -EINVAL;
2170
2171 if (wol->wolopts & ~support)
2172 return -EINVAL;
2173
2174 spin_lock_irq(&rp->lock);
2175 rp->wolopts = wol->wolopts;
2176 spin_unlock_irq(&rp->lock);
2177
2178 return 0;
2179 }
2180
2181 static const struct ethtool_ops netdev_ethtool_ops = {
2182 .get_drvinfo = netdev_get_drvinfo,
2183 .get_settings = netdev_get_settings,
2184 .set_settings = netdev_set_settings,
2185 .nway_reset = netdev_nway_reset,
2186 .get_link = netdev_get_link,
2187 .get_msglevel = netdev_get_msglevel,
2188 .set_msglevel = netdev_set_msglevel,
2189 .get_wol = rhine_get_wol,
2190 .set_wol = rhine_set_wol,
2191 };
2192
2193 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2194 {
2195 struct rhine_private *rp = netdev_priv(dev);
2196 int rc;
2197
2198 if (!netif_running(dev))
2199 return -EINVAL;
2200
2201 mutex_lock(&rp->task_lock);
2202 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
2203 rhine_set_carrier(&rp->mii_if);
2204 mutex_unlock(&rp->task_lock);
2205
2206 return rc;
2207 }
2208
2209 static int rhine_close(struct net_device *dev)
2210 {
2211 struct rhine_private *rp = netdev_priv(dev);
2212 void __iomem *ioaddr = rp->base;
2213
2214 rhine_task_disable(rp);
2215 napi_disable(&rp->napi);
2216 netif_stop_queue(dev);
2217
2218 netif_dbg(rp, ifdown, dev, "Shutting down ethercard, status was %04x\n",
2219 ioread16(ioaddr + ChipCmd));
2220
2221 /* Switch to loopback mode to avoid hardware races. */
2222 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
2223
2224 rhine_irq_disable(rp);
2225
2226 /* Stop the chip's Tx and Rx processes. */
2227 iowrite16(CmdStop, ioaddr + ChipCmd);
2228
2229 free_irq(rp->pdev->irq, dev);
2230 free_rbufs(dev);
2231 free_tbufs(dev);
2232 free_ring(dev);
2233
2234 return 0;
2235 }
2236
2237
2238 static void __devexit rhine_remove_one(struct pci_dev *pdev)
2239 {
2240 struct net_device *dev = pci_get_drvdata(pdev);
2241 struct rhine_private *rp = netdev_priv(dev);
2242
2243 unregister_netdev(dev);
2244
2245 pci_iounmap(pdev, rp->base);
2246 pci_release_regions(pdev);
2247
2248 free_netdev(dev);
2249 pci_disable_device(pdev);
2250 pci_set_drvdata(pdev, NULL);
2251 }
2252
2253 static void rhine_shutdown (struct pci_dev *pdev)
2254 {
2255 struct net_device *dev = pci_get_drvdata(pdev);
2256 struct rhine_private *rp = netdev_priv(dev);
2257 void __iomem *ioaddr = rp->base;
2258
2259 if (!(rp->quirks & rqWOL))
2260 return; /* Nothing to do for non-WOL adapters */
2261
2262 rhine_power_init(dev);
2263
2264 /* Make sure we use pattern 0, 1 and not 4, 5 */
2265 if (rp->quirks & rq6patterns)
2266 iowrite8(0x04, ioaddr + WOLcgClr);
2267
2268 spin_lock(&rp->lock);
2269
2270 if (rp->wolopts & WAKE_MAGIC) {
2271 iowrite8(WOLmagic, ioaddr + WOLcrSet);
2272 /*
2273 * Turn EEPROM-controlled wake-up back on -- some hardware may
2274 * not cooperate otherwise.
2275 */
2276 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
2277 }
2278
2279 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
2280 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
2281
2282 if (rp->wolopts & WAKE_PHY)
2283 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
2284
2285 if (rp->wolopts & WAKE_UCAST)
2286 iowrite8(WOLucast, ioaddr + WOLcrSet);
2287
2288 if (rp->wolopts) {
2289 /* Enable legacy WOL (for old motherboards) */
2290 iowrite8(0x01, ioaddr + PwcfgSet);
2291 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
2292 }
2293
2294 spin_unlock(&rp->lock);
2295
2296 if (system_state == SYSTEM_POWER_OFF && !avoid_D3) {
2297 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
2298
2299 pci_wake_from_d3(pdev, true);
2300 pci_set_power_state(pdev, PCI_D3hot);
2301 }
2302 }
2303
2304 #ifdef CONFIG_PM_SLEEP
2305 static int rhine_suspend(struct device *device)
2306 {
2307 struct pci_dev *pdev = to_pci_dev(device);
2308 struct net_device *dev = pci_get_drvdata(pdev);
2309 struct rhine_private *rp = netdev_priv(dev);
2310
2311 if (!netif_running(dev))
2312 return 0;
2313
2314 rhine_task_disable(rp);
2315 rhine_irq_disable(rp);
2316 napi_disable(&rp->napi);
2317
2318 netif_device_detach(dev);
2319
2320 rhine_shutdown(pdev);
2321
2322 return 0;
2323 }
2324
2325 static int rhine_resume(struct device *device)
2326 {
2327 struct pci_dev *pdev = to_pci_dev(device);
2328 struct net_device *dev = pci_get_drvdata(pdev);
2329 struct rhine_private *rp = netdev_priv(dev);
2330
2331 if (!netif_running(dev))
2332 return 0;
2333
2334 #ifdef USE_MMIO
2335 enable_mmio(rp->pioaddr, rp->quirks);
2336 #endif
2337 rhine_power_init(dev);
2338 free_tbufs(dev);
2339 free_rbufs(dev);
2340 alloc_tbufs(dev);
2341 alloc_rbufs(dev);
2342 rhine_task_enable(rp);
2343 spin_lock_bh(&rp->lock);
2344 init_registers(dev);
2345 spin_unlock_bh(&rp->lock);
2346
2347 netif_device_attach(dev);
2348
2349 return 0;
2350 }
2351
2352 static SIMPLE_DEV_PM_OPS(rhine_pm_ops, rhine_suspend, rhine_resume);
2353 #define RHINE_PM_OPS (&rhine_pm_ops)
2354
2355 #else
2356
2357 #define RHINE_PM_OPS NULL
2358
2359 #endif /* !CONFIG_PM_SLEEP */
2360
2361 static struct pci_driver rhine_driver = {
2362 .name = DRV_NAME,
2363 .id_table = rhine_pci_tbl,
2364 .probe = rhine_init_one,
2365 .remove = __devexit_p(rhine_remove_one),
2366 .shutdown = rhine_shutdown,
2367 .driver.pm = RHINE_PM_OPS,
2368 };
2369
2370 static struct dmi_system_id __initdata rhine_dmi_table[] = {
2371 {
2372 .ident = "EPIA-M",
2373 .matches = {
2374 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
2375 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2376 },
2377 },
2378 {
2379 .ident = "KV7",
2380 .matches = {
2381 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
2382 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
2383 },
2384 },
2385 { NULL }
2386 };
2387
2388 static int __init rhine_init(void)
2389 {
2390 /* when a module, this is printed whether or not devices are found in probe */
2391 #ifdef MODULE
2392 pr_info("%s\n", version);
2393 #endif
2394 if (dmi_check_system(rhine_dmi_table)) {
2395 /* these BIOSes fail at PXE boot if chip is in D3 */
2396 avoid_D3 = true;
2397 pr_warn("Broken BIOS detected, avoid_D3 enabled\n");
2398 }
2399 else if (avoid_D3)
2400 pr_info("avoid_D3 set\n");
2401
2402 return pci_register_driver(&rhine_driver);
2403 }
2404
2405
2406 static void __exit rhine_cleanup(void)
2407 {
2408 pci_unregister_driver(&rhine_driver);
2409 }
2410
2411
2412 module_init(rhine_init);
2413 module_exit(rhine_cleanup);