Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / net / wireless / ath / ath5k / attach.c
blobd7114c75fe9b0bb66515e6856128194ee8fd2b45
1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 /*************************************\
20 * Attach/Detach Functions and helpers *
21 \*************************************/
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include "ath5k.h"
26 #include "reg.h"
27 #include "debug.h"
29 /**
30 * ath5k_hw_post() - Power On Self Test helper function
31 * @ah: The &struct ath5k_hw
33 static int ath5k_hw_post(struct ath5k_hw *ah)
36 static const u32 static_pattern[4] = {
37 0x55555555, 0xaaaaaaaa,
38 0x66666666, 0x99999999
40 static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
41 int i, c;
42 u16 cur_reg;
43 u32 var_pattern;
44 u32 init_val;
45 u32 cur_val;
47 for (c = 0; c < 2; c++) {
49 cur_reg = regs[c];
51 /* Save previous value */
52 init_val = ath5k_hw_reg_read(ah, cur_reg);
54 for (i = 0; i < 256; i++) {
55 var_pattern = i << 16 | i;
56 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
57 cur_val = ath5k_hw_reg_read(ah, cur_reg);
59 if (cur_val != var_pattern) {
60 ATH5K_ERR(ah, "POST Failed !!!\n");
61 return -EAGAIN;
64 /* Found on ndiswrapper dumps */
65 var_pattern = 0x0039080f;
66 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
69 for (i = 0; i < 4; i++) {
70 var_pattern = static_pattern[i];
71 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
72 cur_val = ath5k_hw_reg_read(ah, cur_reg);
74 if (cur_val != var_pattern) {
75 ATH5K_ERR(ah, "POST Failed !!!\n");
76 return -EAGAIN;
79 /* Found on ndiswrapper dumps */
80 var_pattern = 0x003b080f;
81 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
84 /* Restore previous value */
85 ath5k_hw_reg_write(ah, init_val, cur_reg);
89 return 0;
93 /**
94 * ath5k_hw_init() - Check if hw is supported and init the needed structs
95 * @ah: The &struct ath5k_hw associated with the device
97 * Check if the device is supported, perform a POST and initialize the needed
98 * structs. Returns -ENOMEM if we don't have memory for the needed structs,
99 * -ENODEV if the device is not supported or prints an error msg if something
100 * else went wrong.
102 int ath5k_hw_init(struct ath5k_hw *ah)
104 static const u8 zero_mac[ETH_ALEN] = { };
105 struct ath_common *common = ath5k_hw_common(ah);
106 struct pci_dev *pdev = ah->pdev;
107 struct ath5k_eeprom_info *ee;
108 int ret;
109 u32 srev;
112 * HW information
114 ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
115 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
116 ah->ah_imr = 0;
117 ah->ah_retry_short = AR5K_INIT_RETRY_SHORT;
118 ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
119 ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
120 ah->ah_noise_floor = -95; /* until first NF calibration is run */
121 ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
122 ah->ah_current_channel = &ah->channels[0];
125 * Find the mac version
127 ath5k_hw_read_srev(ah);
128 srev = ah->ah_mac_srev;
129 if (srev < AR5K_SREV_AR5311)
130 ah->ah_version = AR5K_AR5210;
131 else if (srev < AR5K_SREV_AR5212)
132 ah->ah_version = AR5K_AR5211;
133 else
134 ah->ah_version = AR5K_AR5212;
136 /* Get the MAC version */
137 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
139 /* Fill the ath5k_hw struct with the needed functions */
140 ret = ath5k_hw_init_desc_functions(ah);
141 if (ret)
142 goto err;
144 /* Bring device out of sleep and reset its units */
145 ret = ath5k_hw_nic_wakeup(ah, NULL);
146 if (ret)
147 goto err;
149 /* Get PHY and RADIO revisions */
150 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
151 0xffffffff;
152 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
153 IEEE80211_BAND_5GHZ);
155 /* Try to identify radio chip based on its srev */
156 switch (ah->ah_radio_5ghz_revision & 0xf0) {
157 case AR5K_SREV_RAD_5111:
158 ah->ah_radio = AR5K_RF5111;
159 ah->ah_single_chip = false;
160 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
161 IEEE80211_BAND_2GHZ);
162 break;
163 case AR5K_SREV_RAD_5112:
164 case AR5K_SREV_RAD_2112:
165 ah->ah_radio = AR5K_RF5112;
166 ah->ah_single_chip = false;
167 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
168 IEEE80211_BAND_2GHZ);
169 break;
170 case AR5K_SREV_RAD_2413:
171 ah->ah_radio = AR5K_RF2413;
172 ah->ah_single_chip = true;
173 break;
174 case AR5K_SREV_RAD_5413:
175 ah->ah_radio = AR5K_RF5413;
176 ah->ah_single_chip = true;
177 break;
178 case AR5K_SREV_RAD_2316:
179 ah->ah_radio = AR5K_RF2316;
180 ah->ah_single_chip = true;
181 break;
182 case AR5K_SREV_RAD_2317:
183 ah->ah_radio = AR5K_RF2317;
184 ah->ah_single_chip = true;
185 break;
186 case AR5K_SREV_RAD_5424:
187 if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
188 ah->ah_mac_version == AR5K_SREV_AR2417) {
189 ah->ah_radio = AR5K_RF2425;
190 ah->ah_single_chip = true;
191 } else {
192 ah->ah_radio = AR5K_RF5413;
193 ah->ah_single_chip = true;
195 break;
196 default:
197 /* Identify radio based on mac/phy srev */
198 if (ah->ah_version == AR5K_AR5210) {
199 ah->ah_radio = AR5K_RF5110;
200 ah->ah_single_chip = false;
201 } else if (ah->ah_version == AR5K_AR5211) {
202 ah->ah_radio = AR5K_RF5111;
203 ah->ah_single_chip = false;
204 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
205 IEEE80211_BAND_2GHZ);
206 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
207 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
208 ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
209 ah->ah_radio = AR5K_RF2425;
210 ah->ah_single_chip = true;
211 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
212 } else if (srev == AR5K_SREV_AR5213A &&
213 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
214 ah->ah_radio = AR5K_RF5112;
215 ah->ah_single_chip = false;
216 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
217 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) ||
218 ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
219 ah->ah_radio = AR5K_RF2316;
220 ah->ah_single_chip = true;
221 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
222 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
223 ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
224 ah->ah_radio = AR5K_RF5413;
225 ah->ah_single_chip = true;
226 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
227 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
228 ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
229 ah->ah_radio = AR5K_RF2413;
230 ah->ah_single_chip = true;
231 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
232 } else {
233 ATH5K_ERR(ah, "Couldn't identify radio revision.\n");
234 ret = -ENODEV;
235 goto err;
240 /* Return on unsupported chips (unsupported eeprom etc) */
241 if ((srev >= AR5K_SREV_AR5416) && (srev < AR5K_SREV_AR2425)) {
242 ATH5K_ERR(ah, "Device not yet supported.\n");
243 ret = -ENODEV;
244 goto err;
248 * POST
250 ret = ath5k_hw_post(ah);
251 if (ret)
252 goto err;
254 /* Enable pci core retry fix on Hainan (5213A) and later chips */
255 if (srev >= AR5K_SREV_AR5213A)
256 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
259 * Get card capabilities, calibration values etc
260 * TODO: EEPROM work
262 ret = ath5k_eeprom_init(ah);
263 if (ret) {
264 ATH5K_ERR(ah, "unable to init EEPROM\n");
265 goto err;
268 ee = &ah->ah_capabilities.cap_eeprom;
271 * Write PCI-E power save settings
273 if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
274 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
275 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
277 /* Shut off RX when elecidle is asserted */
278 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
279 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
281 /* If serdes programming is enabled, increase PCI-E
282 * tx power for systems with long trace from host
283 * to minicard connector. */
284 if (ee->ee_serdes)
285 ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
286 else
287 ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
289 /* Shut off PLL and CLKREQ active in L1 */
290 ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
292 /* Preserve other settings */
293 ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
294 ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
295 ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
297 /* Reset SERDES to load new settings */
298 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
299 usleep_range(1000, 1500);
302 /* Get misc capabilities */
303 ret = ath5k_hw_set_capabilities(ah);
304 if (ret) {
305 ATH5K_ERR(ah, "unable to get device capabilities\n");
306 goto err;
309 /* Crypto settings */
310 common->keymax = (ah->ah_version == AR5K_AR5210 ?
311 AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
313 if (srev >= AR5K_SREV_AR5212_V4 &&
314 (ee->ee_version < AR5K_EEPROM_VERSION_5_0 ||
315 !AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
316 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
318 if (srev >= AR5K_SREV_AR2414) {
319 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
320 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
321 AR5K_MISC_MODE_COMBINED_MIC);
324 /* MAC address is cleared until add_interface */
325 ath5k_hw_set_lladdr(ah, zero_mac);
327 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
328 memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
329 ath5k_hw_set_bssid(ah);
330 ath5k_hw_set_opmode(ah, ah->opmode);
332 ath5k_hw_rfgain_opt_init(ah);
334 ath5k_hw_init_nfcal_hist(ah);
336 /* turn on HW LEDs */
337 ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
339 return 0;
340 err:
341 return ret;
345 * ath5k_hw_deinit() - Free the &struct ath5k_hw
346 * @ah: The &struct ath5k_hw
348 void ath5k_hw_deinit(struct ath5k_hw *ah)
350 __set_bit(ATH_STAT_INVALID, ah->status);
352 if (ah->ah_rf_banks != NULL)
353 kfree(ah->ah_rf_banks);
355 ath5k_eeprom_detach(ah);
357 /* assume interrupts are down */