| blob | f280e0161b1716989fa30af9cd25bc7358bd3128 |
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
30 #ifndef __il_4965_h__
31 #define __il_4965_h__
39 /* configuration for the _4965 devices */
46 /* tx queue */
50 /* RXON */
53 /* uCode */
56 /* lib */
64 /* rx */
75 /* tx */
96 /*
97 * Acquire il->lock before calling this function !
98 */
100 /**
101 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
102 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
103 * @scd_retry: (1) Indicates queue will be used in aggregation mode
104 *
105 * NOTE: Acquire il->lock before calling this function !
106 */
110 /* rx */
116 /* scan */
119 /* station mgmt */
123 /* hcmd */
126 #ifdef CONFIG_IWLEGACY_DEBUG
128 #else
131 {
133 }
134 #endif
136 /* station management */
163 /* rate */
166 {
168 }
170 /* eeprom */
176 /* mac80211 handlers (for 4965) */
194 u8 buf_size);
202 /* EEPROM */
203 #define IL4965_EEPROM_IMG_SIZE 1024
205 /*
206 * uCode queue management definitions ...
207 * The first queue used for block-ack aggregation is #7 (4965 only).
208 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
209 */
210 #define IL49_FIRST_AMPDU_QUEUE 7
212 /* Sizes and addresses for instruction and data memory (SRAM) in
213 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
214 #define IL49_RTC_INST_LOWER_BOUND (0x000000)
215 #define IL49_RTC_INST_UPPER_BOUND (0x018000)
217 #define IL49_RTC_DATA_LOWER_BOUND (0x800000)
218 #define IL49_RTC_DATA_UPPER_BOUND (0x80A000)
220 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
221 IL49_RTC_INST_LOWER_BOUND)
222 #define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \
223 IL49_RTC_DATA_LOWER_BOUND)
225 #define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE
226 #define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE
228 /* Size of uCode instruction memory in bootstrap state machine */
229 #define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE
233 {
236 }
238 /********************* START TEMPERATURE *************************************/
240 /**
241 * 4965 temperature calculation.
242 *
243 * The driver must calculate the device temperature before calculating
244 * a txpower setting (amplifier gain is temperature dependent). The
245 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
246 * values used for the life of the driver, and one of which (R4) is the
247 * real-time temperature indicator.
248 *
249 * uCode provides all 4 values to the driver via the "initialize alive"
250 * notification (see struct il4965_init_alive_resp). After the runtime uCode
251 * image loads, uCode updates the R4 value via stats notifications
252 * (see N_STATS), which occur after each received beacon
253 * when associated, or can be requested via C_STATS.
254 *
255 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
256 * must sign-extend to 32 bits before applying formula below.
257 *
258 * Formula:
259 *
260 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
261 *
262 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
263 * an additional correction, which should be centered around 0 degrees
264 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
265 * centering the 97/100 correction around 0 degrees K.
266 *
267 * Add 273 to Kelvin value to find degrees Celsius, for comparing current
268 * temperature with factory-measured temperatures when calculating txpower
269 * settings.
270 */
271 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
272 #define TEMPERATURE_CALIB_A_VAL 259
274 /* Limit range of calculated temperature to be between these Kelvin values */
275 #define IL_TX_POWER_TEMPERATURE_MIN (263)
276 #define IL_TX_POWER_TEMPERATURE_MAX (410)
278 #define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
279 ((t) < IL_TX_POWER_TEMPERATURE_MIN || \
280 (t) > IL_TX_POWER_TEMPERATURE_MAX)
282 /********************* END TEMPERATURE ***************************************/
284 /********************* START TXPOWER *****************************************/
286 /**
287 * 4965 txpower calculations rely on information from three sources:
288 *
289 * 1) EEPROM
290 * 2) "initialize" alive notification
291 * 3) stats notifications
292 *
293 * EEPROM data consists of:
294 *
295 * 1) Regulatory information (max txpower and channel usage flags) is provided
296 * separately for each channel that can possibly supported by 4965.
297 * 40 MHz wide (.11n HT40) channels are listed separately from 20 MHz
298 * (legacy) channels.
299 *
300 * See struct il4965_eeprom_channel for format, and struct il4965_eeprom
301 * for locations in EEPROM.
302 *
303 * 2) Factory txpower calibration information is provided separately for
304 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
305 * but 5 GHz has several sub-bands.
306 *
307 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
308 *
309 * See struct il4965_eeprom_calib_info (and the tree of structures
310 * contained within it) for format, and struct il4965_eeprom for
311 * locations in EEPROM.
312 *
313 * "Initialization alive" notification (see struct il4965_init_alive_resp)
314 * consists of:
315 *
316 * 1) Temperature calculation parameters.
317 *
318 * 2) Power supply voltage measurement.
319 *
320 * 3) Tx gain compensation to balance 2 transmitters for MIMO use.
321 *
322 * Statistics notifications deliver:
323 *
324 * 1) Current values for temperature param R4.
325 */
327 /**
328 * To calculate a txpower setting for a given desired target txpower, channel,
329 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
330 * support MIMO and transmit diversity), driver must do the following:
331 *
332 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
333 * Do not exceed regulatory limit; reduce target txpower if necessary.
334 *
335 * If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
336 * 2 transmitters will be used simultaneously; driver must reduce the
337 * regulatory limit by 3 dB (half-power) for each transmitter, so the
338 * combined total output of the 2 transmitters is within regulatory limits.
339 *
340 *
341 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
342 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
343 * reduce target txpower if necessary.
344 *
345 * Backoff values below are in 1/2 dB units (equivalent to steps in
346 * txpower gain tables):
347 *
348 * OFDM 6 - 36 MBit: 10 steps (5 dB)
349 * OFDM 48 MBit: 15 steps (7.5 dB)
350 * OFDM 54 MBit: 17 steps (8.5 dB)
351 * OFDM 60 MBit: 20 steps (10 dB)
352 * CCK all rates: 10 steps (5 dB)
353 *
354 * Backoff values apply to saturation txpower on a per-transmitter basis;
355 * when using MIMO (2 transmitters), each transmitter uses the same
356 * saturation level provided in EEPROM, and the same backoff values;
357 * no reduction (such as with regulatory txpower limits) is required.
358 *
359 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
360 * widths and 40 Mhz (.11n HT40) channel widths; there is no separate
361 * factory measurement for ht40 channels.
362 *
363 * The result of this step is the final target txpower. The rest of
364 * the steps figure out the proper settings for the device to achieve
365 * that target txpower.
366 *
367 *
368 * 3) Determine (EEPROM) calibration sub band for the target channel, by
369 * comparing against first and last channels in each sub band
370 * (see struct il4965_eeprom_calib_subband_info).
371 *
372 *
373 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
374 * referencing the 2 factory-measured (sample) channels within the sub band.
375 *
376 * Interpolation is based on difference between target channel's frequency
377 * and the sample channels' frequencies. Since channel numbers are based
378 * on frequency (5 MHz between each channel number), this is equivalent
379 * to interpolating based on channel number differences.
380 *
381 * Note that the sample channels may or may not be the channels at the
382 * edges of the sub band. The target channel may be "outside" of the
383 * span of the sampled channels.
384 *
385 * Driver may choose the pair (for 2 Tx chains) of measurements (see
386 * struct il4965_eeprom_calib_ch_info) for which the actual measured
387 * txpower comes closest to the desired txpower. Usually, though,
388 * the middle set of measurements is closest to the regulatory limits,
389 * and is therefore a good choice for all txpower calculations (this
390 * assumes that high accuracy is needed for maximizing legal txpower,
391 * while lower txpower configurations do not need as much accuracy).
392 *
393 * Driver should interpolate both members of the chosen measurement pair,
394 * i.e. for both Tx chains (radio transmitters), unless the driver knows
395 * that only one of the chains will be used (e.g. only one tx antenna
396 * connected, but this should be unusual). The rate scaling algorithm
397 * switches antennas to find best performance, so both Tx chains will
398 * be used (although only one at a time) even for non-MIMO transmissions.
399 *
400 * Driver should interpolate factory values for temperature, gain table
401 * idx, and actual power. The power amplifier detector values are
402 * not used by the driver.
403 *
404 * Sanity check: If the target channel happens to be one of the sample
405 * channels, the results should agree with the sample channel's
406 * measurements!
407 *
408 *
409 * 5) Find difference between desired txpower and (interpolated)
410 * factory-measured txpower. Using (interpolated) factory gain table idx
411 * (shown elsewhere) as a starting point, adjust this idx lower to
412 * increase txpower, or higher to decrease txpower, until the target
413 * txpower is reached. Each step in the gain table is 1/2 dB.
414 *
415 * For example, if factory measured txpower is 16 dBm, and target txpower
416 * is 13 dBm, add 6 steps to the factory gain idx to reduce txpower
417 * by 3 dB.
418 *
419 *
420 * 6) Find difference between current device temperature and (interpolated)
421 * factory-measured temperature for sub-band. Factory values are in
422 * degrees Celsius. To calculate current temperature, see comments for
423 * "4965 temperature calculation".
424 *
425 * If current temperature is higher than factory temperature, driver must
426 * increase gain (lower gain table idx), and vice verse.
427 *
428 * Temperature affects gain differently for different channels:
429 *
430 * 2.4 GHz all channels: 3.5 degrees per half-dB step
431 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
432 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
433 *
434 * NOTE: Temperature can increase rapidly when transmitting, especially
435 * with heavy traffic at high txpowers. Driver should update
436 * temperature calculations often under these conditions to
437 * maintain strong txpower in the face of rising temperature.
438 *
439 *
440 * 7) Find difference between current power supply voltage indicator
441 * (from "initialize alive") and factory-measured power supply voltage
442 * indicator (EEPROM).
443 *
444 * If the current voltage is higher (indicator is lower) than factory
445 * voltage, gain should be reduced (gain table idx increased) by:
446 *
447 * (eeprom - current) / 7
448 *
449 * If the current voltage is lower (indicator is higher) than factory
450 * voltage, gain should be increased (gain table idx decreased) by:
451 *
452 * 2 * (current - eeprom) / 7
453 *
454 * If number of idx steps in either direction turns out to be > 2,
455 * something is wrong ... just use 0.
456 *
457 * NOTE: Voltage compensation is independent of band/channel.
458 *
459 * NOTE: "Initialize" uCode measures current voltage, which is assumed
460 * to be constant after this initial measurement. Voltage
461 * compensation for txpower (number of steps in gain table)
462 * may be calculated once and used until the next uCode bootload.
463 *
464 *
465 * 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
466 * adjust txpower for each transmitter chain, so txpower is balanced
467 * between the two chains. There are 5 pairs of tx_atten[group][chain]
468 * values in "initialize alive", one pair for each of 5 channel ranges:
469 *
470 * Group 0: 5 GHz channel 34-43
471 * Group 1: 5 GHz channel 44-70
472 * Group 2: 5 GHz channel 71-124
473 * Group 3: 5 GHz channel 125-200
474 * Group 4: 2.4 GHz all channels
475 *
476 * Add the tx_atten[group][chain] value to the idx for the target chain.
477 * The values are signed, but are in pairs of 0 and a non-negative number,
478 * so as to reduce gain (if necessary) of the "hotter" channel. This
479 * avoids any need to double-check for regulatory compliance after
480 * this step.
481 *
482 *
483 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
484 * value to the idx:
485 *
486 * Hardware rev B: 9 steps (4.5 dB)
487 * Hardware rev C: 5 steps (2.5 dB)
488 *
489 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
490 * bits [3:2], 1 = B, 2 = C.
491 *
492 * NOTE: This compensation is in addition to any saturation backoff that
493 * might have been applied in an earlier step.
494 *
495 *
496 * 10) Select the gain table, based on band (2.4 vs 5 GHz).
497 *
498 * Limit the adjusted idx to stay within the table!
499 *
500 *
501 * 11) Read gain table entries for DSP and radio gain, place into appropriate
502 * location(s) in command (struct il4965_txpowertable_cmd).
503 */
505 /**
506 * When MIMO is used (2 transmitters operating simultaneously), driver should
507 * limit each transmitter to deliver a max of 3 dB below the regulatory limit
508 * for the device. That is, use half power for each transmitter, so total
509 * txpower is within regulatory limits.
510 *
511 * The value "6" represents number of steps in gain table to reduce power 3 dB.
512 * Each step is 1/2 dB.
513 */
514 #define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
516 /**
517 * CCK gain compensation.
518 *
519 * When calculating txpowers for CCK, after making sure that the target power
520 * is within regulatory and saturation limits, driver must additionally
521 * back off gain by adding these values to the gain table idx.
522 *
523 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
524 * bits [3:2], 1 = B, 2 = C.
525 */
526 #define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
527 #define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
529 /*
530 * 4965 power supply voltage compensation for txpower
531 */
532 #define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7)
534 /**
535 * Gain tables.
536 *
537 * The following tables contain pair of values for setting txpower, i.e.
538 * gain settings for the output of the device's digital signal processor (DSP),
539 * and for the analog gain structure of the transmitter.
540 *
541 * Each entry in the gain tables represents a step of 1/2 dB. Note that these
542 * are *relative* steps, not indications of absolute output power. Output
543 * power varies with temperature, voltage, and channel frequency, and also
544 * requires consideration of average power (to satisfy regulatory constraints),
545 * and peak power (to avoid distortion of the output signal).
546 *
547 * Each entry contains two values:
548 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
549 * linear value that multiplies the output of the digital signal processor,
550 * before being sent to the analog radio.
551 * 2) Radio gain. This sets the analog gain of the radio Tx path.
552 * It is a coarser setting, and behaves in a logarithmic (dB) fashion.
553 *
554 * EEPROM contains factory calibration data for txpower. This maps actual
555 * measured txpower levels to gain settings in the "well known" tables
556 * below ("well-known" means here that both factory calibration *and* the
557 * driver work with the same table).
558 *
559 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
560 * has an extension (into negative idxes), in case the driver needs to
561 * boost power setting for high device temperatures (higher than would be
562 * present during factory calibration). A 5 Ghz EEPROM idx of "40"
563 * corresponds to the 49th entry in the table used by the driver.
564 */
568 /**
569 * 2.4 GHz gain table
570 *
571 * Index Dsp gain Radio gain
572 * 0 110 0x3f (highest gain)
573 * 1 104 0x3f
574 * 2 98 0x3f
575 * 3 110 0x3e
576 * 4 104 0x3e
577 * 5 98 0x3e
578 * 6 110 0x3d
579 * 7 104 0x3d
580 * 8 98 0x3d
581 * 9 110 0x3c
582 * 10 104 0x3c
583 * 11 98 0x3c
584 * 12 110 0x3b
585 * 13 104 0x3b
586 * 14 98 0x3b
587 * 15 110 0x3a
588 * 16 104 0x3a
589 * 17 98 0x3a
590 * 18 110 0x39
591 * 19 104 0x39
592 * 20 98 0x39
593 * 21 110 0x38
594 * 22 104 0x38
595 * 23 98 0x38
596 * 24 110 0x37
597 * 25 104 0x37
598 * 26 98 0x37
599 * 27 110 0x36
600 * 28 104 0x36
601 * 29 98 0x36
602 * 30 110 0x35
603 * 31 104 0x35
604 * 32 98 0x35
605 * 33 110 0x34
606 * 34 104 0x34
607 * 35 98 0x34
608 * 36 110 0x33
609 * 37 104 0x33
610 * 38 98 0x33
611 * 39 110 0x32
612 * 40 104 0x32
613 * 41 98 0x32
614 * 42 110 0x31
615 * 43 104 0x31
616 * 44 98 0x31
617 * 45 110 0x30
618 * 46 104 0x30
619 * 47 98 0x30
620 * 48 110 0x6
621 * 49 104 0x6
622 * 50 98 0x6
623 * 51 110 0x5
624 * 52 104 0x5
625 * 53 98 0x5
626 * 54 110 0x4
627 * 55 104 0x4
628 * 56 98 0x4
629 * 57 110 0x3
630 * 58 104 0x3
631 * 59 98 0x3
632 * 60 110 0x2
633 * 61 104 0x2
634 * 62 98 0x2
635 * 63 110 0x1
636 * 64 104 0x1
637 * 65 98 0x1
638 * 66 110 0x0
639 * 67 104 0x0
640 * 68 98 0x0
641 * 69 97 0
642 * 70 96 0
643 * 71 95 0
644 * 72 94 0
645 * 73 93 0
646 * 74 92 0
647 * 75 91 0
648 * 76 90 0
649 * 77 89 0
650 * 78 88 0
651 * 79 87 0
652 * 80 86 0
653 * 81 85 0
654 * 82 84 0
655 * 83 83 0
656 * 84 82 0
657 * 85 81 0
658 * 86 80 0
659 * 87 79 0
660 * 88 78 0
661 * 89 77 0
662 * 90 76 0
663 * 91 75 0
664 * 92 74 0
665 * 93 73 0
666 * 94 72 0
667 * 95 71 0
668 * 96 70 0
669 * 97 69 0
670 * 98 68 0
671 */
673 /**
674 * 5 GHz gain table
675 *
676 * Index Dsp gain Radio gain
677 * -9 123 0x3F (highest gain)
678 * -8 117 0x3F
679 * -7 110 0x3F
680 * -6 104 0x3F
681 * -5 98 0x3F
682 * -4 110 0x3E
683 * -3 104 0x3E
684 * -2 98 0x3E
685 * -1 110 0x3D
686 * 0 104 0x3D
687 * 1 98 0x3D
688 * 2 110 0x3C
689 * 3 104 0x3C
690 * 4 98 0x3C
691 * 5 110 0x3B
692 * 6 104 0x3B
693 * 7 98 0x3B
694 * 8 110 0x3A
695 * 9 104 0x3A
696 * 10 98 0x3A
697 * 11 110 0x39
698 * 12 104 0x39
699 * 13 98 0x39
700 * 14 110 0x38
701 * 15 104 0x38
702 * 16 98 0x38
703 * 17 110 0x37
704 * 18 104 0x37
705 * 19 98 0x37
706 * 20 110 0x36
707 * 21 104 0x36
708 * 22 98 0x36
709 * 23 110 0x35
710 * 24 104 0x35
711 * 25 98 0x35
712 * 26 110 0x34
713 * 27 104 0x34
714 * 28 98 0x34
715 * 29 110 0x33
716 * 30 104 0x33
717 * 31 98 0x33
718 * 32 110 0x32
719 * 33 104 0x32
720 * 34 98 0x32
721 * 35 110 0x31
722 * 36 104 0x31
723 * 37 98 0x31
724 * 38 110 0x30
725 * 39 104 0x30
726 * 40 98 0x30
727 * 41 110 0x25
728 * 42 104 0x25
729 * 43 98 0x25
730 * 44 110 0x24
731 * 45 104 0x24
732 * 46 98 0x24
733 * 47 110 0x23
734 * 48 104 0x23
735 * 49 98 0x23
736 * 50 110 0x22
737 * 51 104 0x18
738 * 52 98 0x18
739 * 53 110 0x17
740 * 54 104 0x17
741 * 55 98 0x17
742 * 56 110 0x16
743 * 57 104 0x16
744 * 58 98 0x16
745 * 59 110 0x15
746 * 60 104 0x15
747 * 61 98 0x15
748 * 62 110 0x14
749 * 63 104 0x14
750 * 64 98 0x14
751 * 65 110 0x13
752 * 66 104 0x13
753 * 67 98 0x13
754 * 68 110 0x12
755 * 69 104 0x08
756 * 70 98 0x08
757 * 71 110 0x07
758 * 72 104 0x07
759 * 73 98 0x07
760 * 74 110 0x06
761 * 75 104 0x06
762 * 76 98 0x06
763 * 77 110 0x05
764 * 78 104 0x05
765 * 79 98 0x05
766 * 80 110 0x04
767 * 81 104 0x04
768 * 82 98 0x04
769 * 83 110 0x03
770 * 84 104 0x03
771 * 85 98 0x03
772 * 86 110 0x02
773 * 87 104 0x02
774 * 88 98 0x02
775 * 89 110 0x01
776 * 90 104 0x01
777 * 91 98 0x01
778 * 92 110 0x00
779 * 93 104 0x00
780 * 94 98 0x00
781 * 95 93 0x00
782 * 96 88 0x00
783 * 97 83 0x00
784 * 98 78 0x00
785 */
787 /**
788 * Sanity checks and default values for EEPROM regulatory levels.
789 * If EEPROM values fall outside MIN/MAX range, use default values.
790 *
791 * Regulatory limits refer to the maximum average txpower allowed by
792 * regulatory agencies in the geographies in which the device is meant
793 * to be operated. These limits are SKU-specific (i.e. geography-specific),
794 * and channel-specific; each channel has an individual regulatory limit
795 * listed in the EEPROM.
796 *
797 * Units are in half-dBm (i.e. "34" means 17 dBm).
798 */
799 #define IL_TX_POWER_DEFAULT_REGULATORY_24 (34)
800 #define IL_TX_POWER_DEFAULT_REGULATORY_52 (34)
801 #define IL_TX_POWER_REGULATORY_MIN (0)
802 #define IL_TX_POWER_REGULATORY_MAX (34)
804 /**
805 * Sanity checks and default values for EEPROM saturation levels.
806 * If EEPROM values fall outside MIN/MAX range, use default values.
807 *
808 * Saturation is the highest level that the output power amplifier can produce
809 * without significant clipping distortion. This is a "peak" power level.
810 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
811 * require differing amounts of backoff, relative to their average power output,
812 * in order to avoid clipping distortion.
813 *
814 * Driver must make sure that it is violating neither the saturation limit,
815 * nor the regulatory limit, when calculating Tx power settings for various
816 * rates.
817 *
818 * Units are in half-dBm (i.e. "38" means 19 dBm).
819 */
820 #define IL_TX_POWER_DEFAULT_SATURATION_24 (38)
821 #define IL_TX_POWER_DEFAULT_SATURATION_52 (38)
822 #define IL_TX_POWER_SATURATION_MIN (20)
823 #define IL_TX_POWER_SATURATION_MAX (50)
825 /**
826 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
827 * and thermal Txpower calibration.
828 *
829 * When calculating txpower, driver must compensate for current device
830 * temperature; higher temperature requires higher gain. Driver must calculate
831 * current temperature (see "4965 temperature calculation"), then compare vs.
832 * factory calibration temperature in EEPROM; if current temperature is higher
833 * than factory temperature, driver must *increase* gain by proportions shown
834 * in table below. If current temperature is lower than factory, driver must
835 * *decrease* gain.
836 *
837 * Different frequency ranges require different compensation, as shown below.
838 */
839 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
840 #define CALIB_IL_TX_ATTEN_GR1_FCH 34
841 #define CALIB_IL_TX_ATTEN_GR1_LCH 43
843 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
844 #define CALIB_IL_TX_ATTEN_GR2_FCH 44
845 #define CALIB_IL_TX_ATTEN_GR2_LCH 70
847 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
848 #define CALIB_IL_TX_ATTEN_GR3_FCH 71
849 #define CALIB_IL_TX_ATTEN_GR3_LCH 124
851 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
852 #define CALIB_IL_TX_ATTEN_GR4_FCH 125
853 #define CALIB_IL_TX_ATTEN_GR4_LCH 200
855 /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
856 #define CALIB_IL_TX_ATTEN_GR5_FCH 1
857 #define CALIB_IL_TX_ATTEN_GR5_LCH 20
865 CALIB_CH_GROUP_MAX
866 };
868 /********************* END TXPOWER *****************************************/
870 /**
871 * Tx/Rx Queues
872 *
873 * Most communication between driver and 4965 is via queues of data buffers.
874 * For example, all commands that the driver issues to device's embedded
875 * controller (uCode) are via the command queue (one of the Tx queues). All
876 * uCode command responses/replies/notifications, including Rx frames, are
877 * conveyed from uCode to driver via the Rx queue.
878 *
879 * Most support for these queues, including handshake support, resides in
880 * structures in host DRAM, shared between the driver and the device. When
881 * allocating this memory, the driver must make sure that data written by
882 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
883 * cache memory), so DRAM and cache are consistent, and the device can
884 * immediately see changes made by the driver.
885 *
886 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
887 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
888 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
889 */
890 #define IL49_NUM_FIFOS 7
891 #define IL49_CMD_FIFO_NUM 4
892 #define IL49_NUM_QUEUES 16
893 #define IL49_NUM_AMPDU_QUEUES 8
895 /**
896 * struct il4965_schedq_bc_tbl
897 *
898 * Byte Count table
899 *
900 * Each Tx queue uses a byte-count table containing 320 entries:
901 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
902 * duplicate the first 64 entries (to avoid wrap-around within a Tx win;
903 * max Tx win is 64 TFDs).
904 *
905 * When driver sets up a new TFD, it must also enter the total byte count
906 * of the frame to be transmitted into the corresponding entry in the byte
907 * count table for the chosen Tx queue. If the TFD idx is 0-63, the driver
908 * must duplicate the byte count entry in corresponding idx 256-319.
909 *
910 * padding puts each byte count table on a 1024-byte boundary;
911 * 4965 assumes tables are separated by 1024 bytes.
912 */
918 #define IL4965_RTC_INST_LOWER_BOUND (0x000000)
920 /* RSSI to dBm */
921 #define IL4965_RSSI_OFFSET 44
923 /* PCI registers */
924 #define PCI_CFG_RETRY_TIMEOUT 0x041
926 /* PCI register values */
927 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
928 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
930 #define IL4965_DEFAULT_TX_RETRY 15
932 /* EEPROM */
933 #define IL4965_FIRST_AMPDU_QUEUE 10
935 /* Calibration */
942 /* Debug */
943 #ifdef CONFIG_IWLEGACY_DEBUGFS
951 #endif
953 /****************************/
954 /* Flow Handler Definitions */
955 /****************************/
957 /**
958 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
959 * Addresses are offsets from device's PCI hardware base address.
960 */
961 #define FH49_MEM_LOWER_BOUND (0x1000)
962 #define FH49_MEM_UPPER_BOUND (0x2000)
964 /**
965 * Keep-Warm (KW) buffer base address.
966 *
967 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
968 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
969 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
970 * from going into a power-savings mode that would cause higher DRAM latency,
971 * and possible data over/under-runs, before all Tx/Rx is complete.
972 *
973 * Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4)
974 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
975 * automatically invokes keep-warm accesses when normal accesses might not
976 * be sufficient to maintain fast DRAM response.
977 *
978 * Bit fields:
979 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
980 */
981 #define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C)
983 /**
984 * TFD Circular Buffers Base (CBBC) addresses
985 *
986 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
987 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
988 * (see struct il_tfd_frame). These 16 pointer registers are offset by 0x04
989 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
990 * aligned (address bits 0-7 must be 0).
991 *
992 * Bit fields in each pointer register:
993 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
994 */
995 #define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
996 #define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10)
998 /* Find TFD CB base pointer for given queue (range 0-15). */
999 #define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
1001 /**
1002 * Rx SRAM Control and Status Registers (RSCSR)
1003 *
1004 * These registers provide handshake between driver and 4965 for the Rx queue
1005 * (this queue handles *all* command responses, notifications, Rx data, etc.
1006 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
1007 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1008 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1009 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1010 * mapping between RBDs and RBs.
1011 *
1012 * Driver must allocate host DRAM memory for the following, and set the
1013 * physical address of each into 4965 registers:
1014 *
1015 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1016 * entries (although any power of 2, up to 4096, is selectable by driver).
1017 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1018 * (typically 4K, although 8K or 16K are also selectable by driver).
1019 * Driver sets up RB size and number of RBDs in the CB via Rx config
1020 * register FH49_MEM_RCSR_CHNL0_CONFIG_REG.
1021 *
1022 * Bit fields within one RBD:
1023 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1024 *
1025 * Driver sets physical address [35:8] of base of RBD circular buffer
1026 * into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1027 *
1028 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
1029 * (RBs) have been filled, via a "write pointer", actually the idx of
1030 * the RB's corresponding RBD within the circular buffer. Driver sets
1031 * physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1032 *
1033 * Bit fields in lower dword of Rx status buffer (upper dword not used
1034 * by driver; see struct il4965_shared, val0):
1035 * 31-12: Not used by driver
1036 * 11- 0: Index of last filled Rx buffer descriptor
1037 * (4965 writes, driver reads this value)
1038 *
1039 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
1040 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1041 * and update the 4965's "write" idx register,
1042 * FH49_RSCSR_CHNL0_RBDCB_WPTR_REG.
1043 *
1044 * This "write" idx corresponds to the *next* RBD that the driver will make
1045 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1046 * the circular buffer. This value should initially be 0 (before preparing any
1047 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1048 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1049 * "read" idx has advanced past 1! See below).
1050 * NOTE: 4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8.
1051 *
1052 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
1053 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1054 * to tell the driver the idx of the latest filled RBD. The driver must
1055 * read this "read" idx from DRAM after receiving an Rx interrupt from 4965.
1056 *
1057 * The driver must also internally keep track of a third idx, which is the
1058 * next RBD to process. When receiving an Rx interrupt, driver should process
1059 * all filled but unprocessed RBs up to, but not including, the RB
1060 * corresponding to the "read" idx. For example, if "read" idx becomes "1",
1061 * driver may process the RB pointed to by RBD 0. Depending on volume of
1062 * traffic, there may be many RBs to process.
1063 *
1064 * If read idx == write idx, 4965 thinks there is no room to put new data.
1065 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1066 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1067 * and "read" idxes; that is, make sure that there are no more than 254
1068 * buffers waiting to be filled.
1069 */
1070 #define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0)
1071 #define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1072 #define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND)
1074 /**
1075 * Physical base address of 8-byte Rx Status buffer.
1076 * Bit fields:
1077 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1078 */
1079 #define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0)
1081 /**
1082 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1083 * Bit fields:
1084 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1085 */
1086 #define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004)
1088 /**
1089 * Rx write pointer (idx, really!).
1090 * Bit fields:
1091 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1092 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1093 */
1094 #define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008)
1095 #define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG)
1097 /**
1098 * Rx Config/Status Registers (RCSR)
1099 * Rx Config Reg for channel 0 (only channel used)
1100 *
1101 * Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1102 * normal operation (see bit fields).
1103 *
1104 * Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1105 * Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for
1106 * FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1107 *
1108 * Bit fields:
1109 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1110 * '10' operate normally
1111 * 29-24: reserved
1112 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1113 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1114 * 19-18: reserved
1115 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1116 * '10' 12K, '11' 16K.
1117 * 15-14: reserved
1118 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1119 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1120 * typical value 0x10 (about 1/2 msec)
1121 * 3- 0: reserved
1122 */
1123 #define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1124 #define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0)
1125 #define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND)
1127 #define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0)
1136 #define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1137 #define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1138 #define RX_RB_TIMEOUT (0x10)
1140 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1141 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1142 #define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1144 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1145 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1146 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1147 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1149 #define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1150 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1151 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1153 /**
1154 * Rx Shared Status Registers (RSSR)
1155 *
1156 * After stopping Rx DMA channel (writing 0 to
1157 * FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1158 * FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1159 *
1160 * Bit fields:
1161 * 24: 1 = Channel 0 is idle
1162 *
1163 * FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1164 * contain default values that should not be altered by the driver.
1165 */
1166 #define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40)
1167 #define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1169 #define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND)
1170 #define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004)
1171 #define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1172 (FH49_MEM_RSSR_LOWER_BOUND + 0x008)
1174 #define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1176 #define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1178 /* TFDB Area - TFDs buffer table */
1179 #define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1180 #define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900)
1181 #define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958)
1182 #define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1183 #define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1185 /**
1186 * Transmit DMA Channel Control/Status Registers (TCSR)
1187 *
1188 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1189 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1190 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1191 *
1192 * To use a Tx DMA channel, driver must initialize its
1193 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1194 *
1195 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1196 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1197 *
1198 * All other bits should be 0.
1199 *
1200 * Bit fields:
1201 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1202 * '10' operate normally
1203 * 29- 4: Reserved, set to "0"
1204 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1205 * 2- 0: Reserved, set to "0"
1206 */
1207 #define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1208 #define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60)
1210 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1211 #define FH49_TCSR_CHNL_NUM (7)
1212 #define FH50_TCSR_CHNL_NUM (8)
1214 /* TCSR: tx_config register values */
1215 #define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1216 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1217 #define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1218 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1219 #define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1220 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1222 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1223 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1225 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1226 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1228 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1229 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1230 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1232 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1233 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1234 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1236 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1237 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1238 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1240 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1241 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1242 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1244 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1245 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1247 /**
1248 * Tx Shared Status Registers (TSSR)
1249 *
1250 * After stopping Tx DMA channel (writing 0 to
1251 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1252 * FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle
1253 * (channel's buffers empty | no pending requests).
1254 *
1255 * Bit fields:
1256 * 31-24: 1 = Channel buffers empty (channel 7:0)
1257 * 23-16: 1 = No pending requests (channel 7:0)
1258 */
1259 #define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0)
1260 #define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0)
1262 #define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010)
1264 /**
1265 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1266 * 31: Indicates an address error when accessed to internal memory
1267 * uCode/driver must write "1" in order to clear this flag
1268 * 30: Indicates that Host did not send the expected number of dwords to FH
1269 * uCode/driver must write "1" in order to clear this flag
1270 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1271 * command was received from the scheduler while the TRB was already full
1272 * with previous command
1273 * uCode/driver must write "1" in order to clear this flag
1274 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1275 * bit is set, it indicates that the FH has received a full indication
1276 * from the RTC TxFIFO and the current value of the TxCredit counter was
1277 * not equal to zero. This mean that the credit mechanism was not
1278 * synchronized to the TxFIFO status
1279 * uCode/driver must write "1" in order to clear this flag
1280 */
1281 #define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018)
1283 #define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1285 /* Tx service channels */
1286 #define FH49_SRVC_CHNL (9)
1287 #define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8)
1288 #define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
1289 #define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1290 (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1292 #define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98)
1293 /* Instruct FH to increment the retry count of a packet when
1294 * it is brought from the memory to TX-FIFO
1295 */
1296 #define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1298 /* Keep Warm Size */