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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / rapidio / switches / idt_gen2.c
blob809b7a3336baa40e654f296feeaa8ebb5067411e
1 /*
2 * IDT CPS Gen.2 Serial RapidIO switch family support
3 *
4 * Copyright 2010 Integrated Device Technology, Inc.
5 * Alexandre Bounine <alexandre.bounine@idt.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13 #include <linux/stat.h>
14 #include <linux/rio.h>
15 #include <linux/rio_drv.h>
16 #include <linux/rio_ids.h>
17 #include <linux/delay.h>
18 #include "../rio.h"
19
20 #define LOCAL_RTE_CONF_DESTID_SEL 0x010070
21 #define LOCAL_RTE_CONF_DESTID_SEL_PSEL 0x0000001f
22
23 #define IDT_LT_ERR_REPORT_EN 0x03100c
24
25 #define IDT_PORT_ERR_REPORT_EN(n) (0x031044 + (n)*0x40)
26 #define IDT_PORT_ERR_REPORT_EN_BC 0x03ff04
27
28 #define IDT_PORT_ISERR_REPORT_EN(n) (0x03104C + (n)*0x40)
29 #define IDT_PORT_ISERR_REPORT_EN_BC 0x03ff0c
30 #define IDT_PORT_INIT_TX_ACQUIRED 0x00000020
31
32 #define IDT_LANE_ERR_REPORT_EN(n) (0x038010 + (n)*0x100)
33 #define IDT_LANE_ERR_REPORT_EN_BC 0x03ff10
34
35 #define IDT_DEV_CTRL_1 0xf2000c
36 #define IDT_DEV_CTRL_1_GENPW 0x02000000
37 #define IDT_DEV_CTRL_1_PRSTBEH 0x00000001
38
39 #define IDT_CFGBLK_ERR_CAPTURE_EN 0x020008
40 #define IDT_CFGBLK_ERR_REPORT 0xf20014
41 #define IDT_CFGBLK_ERR_REPORT_GENPW 0x00000002
42
43 #define IDT_AUX_PORT_ERR_CAP_EN 0x020000
44 #define IDT_AUX_ERR_REPORT_EN 0xf20018
45 #define IDT_AUX_PORT_ERR_LOG_I2C 0x00000002
46 #define IDT_AUX_PORT_ERR_LOG_JTAG 0x00000001
47
48 #define IDT_ISLTL_ADDRESS_CAP 0x021014
49
50 #define IDT_RIO_DOMAIN 0xf20020
51 #define IDT_RIO_DOMAIN_MASK 0x000000ff
52
53 #define IDT_PW_INFO_CSR 0xf20024
54
55 #define IDT_SOFT_RESET 0xf20040
56 #define IDT_SOFT_RESET_REQ 0x00030097
57
58 #define IDT_I2C_MCTRL 0xf20050
59 #define IDT_I2C_MCTRL_GENPW 0x04000000
60
61 #define IDT_JTAG_CTRL 0xf2005c
62 #define IDT_JTAG_CTRL_GENPW 0x00000002
63
64 #define IDT_LANE_CTRL(n) (0xff8000 + (n)*0x100)
65 #define IDT_LANE_CTRL_BC 0xffff00
66 #define IDT_LANE_CTRL_GENPW 0x00200000
67 #define IDT_LANE_DFE_1_BC 0xffff18
68 #define IDT_LANE_DFE_2_BC 0xffff1c
69
70 #define IDT_PORT_OPS(n) (0xf40004 + (n)*0x100)
71 #define IDT_PORT_OPS_GENPW 0x08000000
72 #define IDT_PORT_OPS_PL_ELOG 0x00000040
73 #define IDT_PORT_OPS_LL_ELOG 0x00000020
74 #define IDT_PORT_OPS_LT_ELOG 0x00000010
75 #define IDT_PORT_OPS_BC 0xf4ff04
76
77 #define IDT_PORT_ISERR_DET(n) (0xf40008 + (n)*0x100)
78
79 #define IDT_ERR_CAP 0xfd0000
80 #define IDT_ERR_CAP_LOG_OVERWR 0x00000004
81
82 #define IDT_ERR_RD 0xfd0004
83
84 #define IDT_DEFAULT_ROUTE 0xde
85 #define IDT_NO_ROUTE 0xdf
86
87 static int
88 idtg2_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
89 u16 table, u16 route_destid, u8 route_port)
90 {
91 /*
92 * Select routing table to update
93 */
94 if (table == RIO_GLOBAL_TABLE)
95 table = 0;
96 else
97 table++;
98
99 if (route_port == RIO_INVALID_ROUTE)
100 route_port = IDT_DEFAULT_ROUTE;
101
102 rio_mport_write_config_32(mport, destid, hopcount,
103 LOCAL_RTE_CONF_DESTID_SEL, table);
104
105 /*
106 * Program destination port for the specified destID
107 */
108 rio_mport_write_config_32(mport, destid, hopcount,
109 RIO_STD_RTE_CONF_DESTID_SEL_CSR,
110 (u32)route_destid);
111
112 rio_mport_write_config_32(mport, destid, hopcount,
113 RIO_STD_RTE_CONF_PORT_SEL_CSR,
114 (u32)route_port);
115 udelay(10);
116
117 return 0;
118 }
119
120 static int
121 idtg2_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
122 u16 table, u16 route_destid, u8 *route_port)
123 {
124 u32 result;
125
126 /*
127 * Select routing table to read
128 */
129 if (table == RIO_GLOBAL_TABLE)
130 table = 0;
131 else
132 table++;
133
134 rio_mport_write_config_32(mport, destid, hopcount,
135 LOCAL_RTE_CONF_DESTID_SEL, table);
136
137 rio_mport_write_config_32(mport, destid, hopcount,
138 RIO_STD_RTE_CONF_DESTID_SEL_CSR,
139 route_destid);
140
141 rio_mport_read_config_32(mport, destid, hopcount,
142 RIO_STD_RTE_CONF_PORT_SEL_CSR, &result);
143
144 if (IDT_DEFAULT_ROUTE == (u8)result || IDT_NO_ROUTE == (u8)result)
145 *route_port = RIO_INVALID_ROUTE;
146 else
147 *route_port = (u8)result;
148
149 return 0;
150 }
151
152 static int
153 idtg2_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
154 u16 table)
155 {
156 u32 i;
157
158 /*
159 * Select routing table to read
160 */
161 if (table == RIO_GLOBAL_TABLE)
162 table = 0;
163 else
164 table++;
165
166 rio_mport_write_config_32(mport, destid, hopcount,
167 LOCAL_RTE_CONF_DESTID_SEL, table);
168
169 for (i = RIO_STD_RTE_CONF_EXTCFGEN;
170 i <= (RIO_STD_RTE_CONF_EXTCFGEN | 0xff);) {
171 rio_mport_write_config_32(mport, destid, hopcount,
172 RIO_STD_RTE_CONF_DESTID_SEL_CSR, i);
173 rio_mport_write_config_32(mport, destid, hopcount,
174 RIO_STD_RTE_CONF_PORT_SEL_CSR,
175 (IDT_DEFAULT_ROUTE << 24) | (IDT_DEFAULT_ROUTE << 16) |
176 (IDT_DEFAULT_ROUTE << 8) | IDT_DEFAULT_ROUTE);
177 i += 4;
178 }
179
180 return 0;
181 }
182
183
184 static int
185 idtg2_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
186 u8 sw_domain)
187 {
188 /*
189 * Switch domain configuration operates only at global level
190 */
191 rio_mport_write_config_32(mport, destid, hopcount,
192 IDT_RIO_DOMAIN, (u32)sw_domain);
193 return 0;
194 }
195
196 static int
197 idtg2_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
198 u8 *sw_domain)
199 {
200 u32 regval;
201
202 /*
203 * Switch domain configuration operates only at global level
204 */
205 rio_mport_read_config_32(mport, destid, hopcount,
206 IDT_RIO_DOMAIN, &regval);
207
208 *sw_domain = (u8)(regval & 0xff);
209
210 return 0;
211 }
212
213 static int
214 idtg2_em_init(struct rio_dev *rdev)
215 {
216 u32 regval;
217 int i, tmp;
218
219 /*
220 * This routine performs device-specific initialization only.
221 * All standard EM configuration should be performed at upper level.
222 */
223
224 pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
225
226 /* Set Port-Write info CSR: PRIO=3 and CRF=1 */
227 rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000);
228
229 /*
230 * Configure LT LAYER error reporting.
231 */
232
233 /* Enable standard (RIO.p8) error reporting */
234 rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN,
235 REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR |
236 REM_LTL_ERR_UNSUPTR);
237
238 /* Use Port-Writes for LT layer error reporting.
239 * Enable per-port reset
240 */
241 rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval);
242 rio_write_config_32(rdev, IDT_DEV_CTRL_1,
243 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH);
244
245 /*
246 * Configure PORT error reporting.
247 */
248
249 /* Report all RIO.p8 errors supported by device */
250 rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037);
251
252 /* Configure reporting of implementation specific errors/events */
253 rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC,
254 IDT_PORT_INIT_TX_ACQUIRED);
255
256 /* Use Port-Writes for port error reporting and enable error logging */
257 tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo);
258 for (i = 0; i < tmp; i++) {
259 rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval);
260 rio_write_config_32(rdev,
261 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW |
262 IDT_PORT_OPS_PL_ELOG |
263 IDT_PORT_OPS_LL_ELOG |
264 IDT_PORT_OPS_LT_ELOG);
265 }
266 /* Overwrite error log if full */
267 rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR);
268
269 /*
270 * Configure LANE error reporting.
271 */
272
273 /* Disable line error reporting */
274 rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0);
275
276 /* Use Port-Writes for lane error reporting (when enabled)
277 * (do per-lane update because lanes may have different configuration)
278 */
279 tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16;
280 for (i = 0; i < tmp; i++) {
281 rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval);
282 rio_write_config_32(rdev, IDT_LANE_CTRL(i),
283 regval | IDT_LANE_CTRL_GENPW);
284 }
285
286 /*
287 * Configure AUX error reporting.
288 */
289
290 /* Disable JTAG and I2C Error capture */
291 rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0);
292
293 /* Disable JTAG and I2C Error reporting/logging */
294 rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0);
295
296 /* Disable Port-Write notification from JTAG */
297 rio_write_config_32(rdev, IDT_JTAG_CTRL, 0);
298
299 /* Disable Port-Write notification from I2C */
300 rio_read_config_32(rdev, IDT_I2C_MCTRL, &regval);
301 rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW);
302
303 /*
304 * Configure CFG_BLK error reporting.
305 */
306
307 /* Disable Configuration Block error capture */
308 rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0);
309
310 /* Disable Port-Writes for Configuration Block error reporting */
311 rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, &regval);
312 rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT,
313 regval & ~IDT_CFGBLK_ERR_REPORT_GENPW);
314
315 /* set TVAL = ~50us */
316 rio_write_config_32(rdev,
317 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);
318
319 return 0;
320 }
321
322 static int
323 idtg2_em_handler(struct rio_dev *rdev, u8 portnum)
324 {
325 u32 regval, em_perrdet, em_ltlerrdet;
326
327 rio_read_config_32(rdev,
328 rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet);
329 if (em_ltlerrdet) {
330 /* Service Logical/Transport Layer Error(s) */
331 if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) {
332 /* Implementation specific error reported */
333 rio_read_config_32(rdev,
334 IDT_ISLTL_ADDRESS_CAP, &regval);
335
336 pr_debug("RIO: %s Implementation Specific LTL errors" \
337 " 0x%x @(0x%x)\n",
338 rio_name(rdev), em_ltlerrdet, regval);
339
340 /* Clear implementation specific address capture CSR */
341 rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0);
342
343 }
344 }
345
346 rio_read_config_32(rdev,
347 rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet);
348 if (em_perrdet) {
349 /* Service Port-Level Error(s) */
350 if (em_perrdet & REM_PED_IMPL_SPEC) {
351 /* Implementation Specific port error reported */
352
353 /* Get IS errors reported */
354 rio_read_config_32(rdev,
355 IDT_PORT_ISERR_DET(portnum), &regval);
356
357 pr_debug("RIO: %s Implementation Specific Port" \
358 " errors 0x%x\n", rio_name(rdev), regval);
359
360 /* Clear all implementation specific events */
361 rio_write_config_32(rdev,
362 IDT_PORT_ISERR_DET(portnum), 0);
363 }
364 }
365
366 return 0;
367 }
368
369 static ssize_t
370 idtg2_show_errlog(struct device *dev, struct device_attribute *attr, char *buf)
371 {
372 struct rio_dev *rdev = to_rio_dev(dev);
373 ssize_t len = 0;
374 u32 regval;
375
376 while (!rio_read_config_32(rdev, IDT_ERR_RD, &regval)) {
377 if (!regval) /* 0 = end of log */
378 break;
379 len += snprintf(buf + len, PAGE_SIZE - len,
380 "%08x\n", regval);
381 if (len >= (PAGE_SIZE - 10))
382 break;
383 }
384
385 return len;
386 }
387
388 static DEVICE_ATTR(errlog, S_IRUGO, idtg2_show_errlog, NULL);
389
390 static int idtg2_sysfs(struct rio_dev *rdev, int create)
391 {
392 struct device *dev = &rdev->dev;
393 int err = 0;
394
395 if (create == RIO_SW_SYSFS_CREATE) {
396 /* Initialize sysfs entries */
397 err = device_create_file(dev, &dev_attr_errlog);
398 if (err)
399 dev_err(dev, "Unable create sysfs errlog file\n");
400 } else
401 device_remove_file(dev, &dev_attr_errlog);
402
403 return err;
404 }
405
406 static int idtg2_switch_init(struct rio_dev *rdev, int do_enum)
407 {
408 pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
409 rdev->rswitch->add_entry = idtg2_route_add_entry;
410 rdev->rswitch->get_entry = idtg2_route_get_entry;
411 rdev->rswitch->clr_table = idtg2_route_clr_table;
412 rdev->rswitch->set_domain = idtg2_set_domain;
413 rdev->rswitch->get_domain = idtg2_get_domain;
414 rdev->rswitch->em_init = idtg2_em_init;
415 rdev->rswitch->em_handle = idtg2_em_handler;
416 rdev->rswitch->sw_sysfs = idtg2_sysfs;
417
418 if (do_enum) {
419 /* Ensure that default routing is disabled on startup */
420 rio_write_config_32(rdev,
421 RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE);
422 }
423
424 return 0;
425 }
426
427 DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1848, idtg2_switch_init);
428 DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1616, idtg2_switch_init);
429 DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTVPS1616, idtg2_switch_init);
430 DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTSPS1616, idtg2_switch_init);
431 DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1432, idtg2_switch_init);