2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
8 #include <linux/delay.h>
10 #include <linux/ratelimit.h>
11 #include <linux/vmalloc.h>
12 #include <scsi/scsi_tcq.h>
14 #define MASK(n) ((1ULL<<(n))-1)
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
25 #define BLOCK_PROTECT_BITS 0x0F
27 /* CRB window related */
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
37 #define MAX_CRB_XFORM 60
38 static unsigned long crb_addr_xform
[MAX_CRB_XFORM
];
39 int qla82xx_crb_table_initialized
;
41 #define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
45 static void qla82xx_crb_addr_transform_setup(void)
47 qla82xx_crb_addr_transform(XDMA
);
48 qla82xx_crb_addr_transform(TIMR
);
49 qla82xx_crb_addr_transform(SRE
);
50 qla82xx_crb_addr_transform(SQN3
);
51 qla82xx_crb_addr_transform(SQN2
);
52 qla82xx_crb_addr_transform(SQN1
);
53 qla82xx_crb_addr_transform(SQN0
);
54 qla82xx_crb_addr_transform(SQS3
);
55 qla82xx_crb_addr_transform(SQS2
);
56 qla82xx_crb_addr_transform(SQS1
);
57 qla82xx_crb_addr_transform(SQS0
);
58 qla82xx_crb_addr_transform(RPMX7
);
59 qla82xx_crb_addr_transform(RPMX6
);
60 qla82xx_crb_addr_transform(RPMX5
);
61 qla82xx_crb_addr_transform(RPMX4
);
62 qla82xx_crb_addr_transform(RPMX3
);
63 qla82xx_crb_addr_transform(RPMX2
);
64 qla82xx_crb_addr_transform(RPMX1
);
65 qla82xx_crb_addr_transform(RPMX0
);
66 qla82xx_crb_addr_transform(ROMUSB
);
67 qla82xx_crb_addr_transform(SN
);
68 qla82xx_crb_addr_transform(QMN
);
69 qla82xx_crb_addr_transform(QMS
);
70 qla82xx_crb_addr_transform(PGNI
);
71 qla82xx_crb_addr_transform(PGND
);
72 qla82xx_crb_addr_transform(PGN3
);
73 qla82xx_crb_addr_transform(PGN2
);
74 qla82xx_crb_addr_transform(PGN1
);
75 qla82xx_crb_addr_transform(PGN0
);
76 qla82xx_crb_addr_transform(PGSI
);
77 qla82xx_crb_addr_transform(PGSD
);
78 qla82xx_crb_addr_transform(PGS3
);
79 qla82xx_crb_addr_transform(PGS2
);
80 qla82xx_crb_addr_transform(PGS1
);
81 qla82xx_crb_addr_transform(PGS0
);
82 qla82xx_crb_addr_transform(PS
);
83 qla82xx_crb_addr_transform(PH
);
84 qla82xx_crb_addr_transform(NIU
);
85 qla82xx_crb_addr_transform(I2Q
);
86 qla82xx_crb_addr_transform(EG
);
87 qla82xx_crb_addr_transform(MN
);
88 qla82xx_crb_addr_transform(MS
);
89 qla82xx_crb_addr_transform(CAS2
);
90 qla82xx_crb_addr_transform(CAS1
);
91 qla82xx_crb_addr_transform(CAS0
);
92 qla82xx_crb_addr_transform(CAM
);
93 qla82xx_crb_addr_transform(C2C1
);
94 qla82xx_crb_addr_transform(C2C0
);
95 qla82xx_crb_addr_transform(SMB
);
96 qla82xx_crb_addr_transform(OCM0
);
98 * Used only in P3 just define it for P2 also.
100 qla82xx_crb_addr_transform(I2C0
);
102 qla82xx_crb_table_initialized
= 1;
105 struct crb_128M_2M_block_map crb_128M_2M_map
[64] = {
107 {{{1, 0x0100000, 0x0102000, 0x120000},
108 {1, 0x0110000, 0x0120000, 0x130000},
109 {1, 0x0120000, 0x0122000, 0x124000},
110 {1, 0x0130000, 0x0132000, 0x126000},
111 {1, 0x0140000, 0x0142000, 0x128000},
112 {1, 0x0150000, 0x0152000, 0x12a000},
113 {1, 0x0160000, 0x0170000, 0x110000},
114 {1, 0x0170000, 0x0172000, 0x12e000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {1, 0x01e0000, 0x01e0800, 0x122000},
122 {0, 0x0000000, 0x0000000, 0x000000} } } ,
123 {{{1, 0x0200000, 0x0210000, 0x180000} } },
125 {{{1, 0x0400000, 0x0401000, 0x169000} } },
126 {{{1, 0x0500000, 0x0510000, 0x140000} } },
127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
129 {{{1, 0x0800000, 0x0802000, 0x170000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {1, 0x08f0000, 0x08f2000, 0x172000} } },
145 {{{1, 0x0900000, 0x0902000, 0x174000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {1, 0x09f0000, 0x09f2000, 0x176000} } },
161 {{{0, 0x0a00000, 0x0a02000, 0x178000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
177 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
198 {{{1, 0x1100000, 0x1101000, 0x160000} } },
199 {{{1, 0x1200000, 0x1201000, 0x161000} } },
200 {{{1, 0x1300000, 0x1301000, 0x162000} } },
201 {{{1, 0x1400000, 0x1401000, 0x163000} } },
202 {{{1, 0x1500000, 0x1501000, 0x165000} } },
203 {{{1, 0x1600000, 0x1601000, 0x166000} } },
210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
214 {{{1, 0x2100000, 0x2102000, 0x120000},
215 {1, 0x2110000, 0x2120000, 0x130000},
216 {1, 0x2120000, 0x2122000, 0x124000},
217 {1, 0x2130000, 0x2132000, 0x126000},
218 {1, 0x2140000, 0x2142000, 0x128000},
219 {1, 0x2150000, 0x2152000, 0x12a000},
220 {1, 0x2160000, 0x2170000, 0x110000},
221 {1, 0x2170000, 0x2172000, 0x12e000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000} } },
230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
237 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
263 * top 12 bits of crb internal address (hub, agent)
265 unsigned qla82xx_crb_hub_agt
[64] = {
267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS
,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN
,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS
,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE
,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU
,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN
,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0
,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1
,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2
,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3
,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q
,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR
,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB
,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4
,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA
,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0
,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1
,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2
,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3
,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND
,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI
,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0
,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1
,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2
,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3
,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI
,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN
,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG
,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS
,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM
,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR
,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1
,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2
,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3
,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4
,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5
,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6
,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7
,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA
,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q
,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB
,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0
,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8
,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9
,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0
,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB
,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0
,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1
,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC
,
333 char *q_dev_state
[] = {
344 char *qdev_state(uint32_t dev_state
)
346 return q_dev_state
[dev_state
];
350 * In: 'off' is offset from CRB space in 128M pci map
351 * Out: 'off' is 2M pci map addr
352 * side effect: lock crb window
355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data
*ha
, ulong
*off
)
358 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
360 ha
->crb_win
= CRB_HI(*off
);
362 (void *)(CRB_WINDOW_2M
+ ha
->nx_pcibase
));
364 /* Read back value to make sure write has gone through before trying
367 win_read
= RD_REG_DWORD((void *)(CRB_WINDOW_2M
+ ha
->nx_pcibase
));
368 if (win_read
!= ha
->crb_win
) {
369 ql_dbg(ql_dbg_p3p
, vha
, 0xb000,
370 "%s: Written crbwin (0x%x) "
371 "!= Read crbwin (0x%x), off=0x%lx.\n",
372 __func__
, ha
->crb_win
, win_read
, *off
);
374 *off
= (*off
& MASK(16)) + CRB_INDIRECT_2M
+ ha
->nx_pcibase
;
377 static inline unsigned long
378 qla82xx_pci_set_crbwindow(struct qla_hw_data
*ha
, u64 off
)
380 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
381 /* See if we are currently pointing to the region we want to use next */
382 if ((off
>= QLA82XX_CRB_PCIX_HOST
) && (off
< QLA82XX_CRB_DDR_NET
)) {
383 /* No need to change window. PCIX and PCIEregs are in both
384 * regs are in both windows.
389 if ((off
>= QLA82XX_CRB_PCIX_HOST
) && (off
< QLA82XX_CRB_PCIX_HOST2
)) {
390 /* We are in first CRB window */
391 if (ha
->curr_window
!= 0)
396 if ((off
> QLA82XX_CRB_PCIX_HOST2
) && (off
< QLA82XX_CRB_MAX
)) {
397 /* We are in second CRB window */
398 off
= off
- QLA82XX_CRB_PCIX_HOST2
+ QLA82XX_CRB_PCIX_HOST
;
400 if (ha
->curr_window
!= 1)
403 /* We are in the QM or direct access
404 * register region - do nothing
406 if ((off
>= QLA82XX_PCI_DIRECT_CRB
) &&
407 (off
< QLA82XX_PCI_CAMQM_MAX
))
410 /* strange address given */
411 ql_dbg(ql_dbg_p3p
, vha
, 0xb001,
412 "%s: Warning: unm_nic_pci_set_crbwindow "
413 "called with an unknown address(%llx).\n",
414 QLA2XXX_DRIVER_NAME
, off
);
419 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data
*ha
, ulong
*off
)
421 struct crb_128M_2M_sub_block_map
*m
;
423 if (*off
>= QLA82XX_CRB_MAX
)
426 if (*off
>= QLA82XX_PCI_CAMQM
&& (*off
< QLA82XX_PCI_CAMQM_2M_END
)) {
427 *off
= (*off
- QLA82XX_PCI_CAMQM
) +
428 QLA82XX_PCI_CAMQM_2M_BASE
+ ha
->nx_pcibase
;
432 if (*off
< QLA82XX_PCI_CRBSPACE
)
435 *off
-= QLA82XX_PCI_CRBSPACE
;
438 m
= &crb_128M_2M_map
[CRB_BLK(*off
)].sub_block
[CRB_SUBBLK(*off
)];
440 if (m
->valid
&& (m
->start_128M
<= *off
) && (m
->end_128M
> *off
)) {
441 *off
= *off
+ m
->start_2M
- m
->start_128M
+ ha
->nx_pcibase
;
444 /* Not in direct map, use crb window */
448 #define CRB_WIN_LOCK_TIMEOUT 100000000
449 static int qla82xx_crb_win_lock(struct qla_hw_data
*ha
)
451 int done
= 0, timeout
= 0;
454 /* acquire semaphore3 from PCI HW block */
455 done
= qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK
));
458 if (timeout
>= CRB_WIN_LOCK_TIMEOUT
)
462 qla82xx_wr_32(ha
, QLA82XX_CRB_WIN_LOCK_ID
, ha
->portnum
);
467 qla82xx_wr_32(struct qla_hw_data
*ha
, ulong off
, u32 data
)
469 unsigned long flags
= 0;
472 rv
= qla82xx_pci_get_crb_addr_2M(ha
, &off
);
477 write_lock_irqsave(&ha
->hw_lock
, flags
);
478 qla82xx_crb_win_lock(ha
);
479 qla82xx_pci_set_crbwindow_2M(ha
, &off
);
482 writel(data
, (void __iomem
*)off
);
485 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK
));
486 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
492 qla82xx_rd_32(struct qla_hw_data
*ha
, ulong off
)
494 unsigned long flags
= 0;
498 rv
= qla82xx_pci_get_crb_addr_2M(ha
, &off
);
503 write_lock_irqsave(&ha
->hw_lock
, flags
);
504 qla82xx_crb_win_lock(ha
);
505 qla82xx_pci_set_crbwindow_2M(ha
, &off
);
507 data
= RD_REG_DWORD((void __iomem
*)off
);
510 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK
));
511 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
516 #define IDC_LOCK_TIMEOUT 100000000
517 int qla82xx_idc_lock(struct qla_hw_data
*ha
)
520 int done
= 0, timeout
= 0;
523 /* acquire semaphore5 from PCI HW block */
524 done
= qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK
));
527 if (timeout
>= IDC_LOCK_TIMEOUT
)
536 for (i
= 0; i
< 20; i
++)
544 void qla82xx_idc_unlock(struct qla_hw_data
*ha
)
546 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK
));
549 /* PCI Windowing for DDR regions. */
550 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
551 (((addr) <= (high)) && ((addr) >= (low)))
553 * check memory access boundary.
554 * used by test agent. support ddr access only for now
557 qla82xx_pci_mem_bound_check(struct qla_hw_data
*ha
,
558 unsigned long long addr
, int size
)
560 if (!QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
561 QLA82XX_ADDR_DDR_NET_MAX
) ||
562 !QLA82XX_ADDR_IN_RANGE(addr
+ size
- 1, QLA82XX_ADDR_DDR_NET
,
563 QLA82XX_ADDR_DDR_NET_MAX
) ||
564 ((size
!= 1) && (size
!= 2) && (size
!= 4) && (size
!= 8)))
570 int qla82xx_pci_set_window_warning_count
;
573 qla82xx_pci_set_window(struct qla_hw_data
*ha
, unsigned long long addr
)
577 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
579 if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
580 QLA82XX_ADDR_DDR_NET_MAX
)) {
581 /* DDR network side */
582 window
= MN_WIN(addr
);
583 ha
->ddr_mn_window
= window
;
585 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
, window
);
586 win_read
= qla82xx_rd_32(ha
,
587 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
);
588 if ((win_read
<< 17) != window
) {
589 ql_dbg(ql_dbg_p3p
, vha
, 0xb003,
590 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
591 __func__
, window
, win_read
);
593 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_DDR_NET
;
594 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM0
,
595 QLA82XX_ADDR_OCM0_MAX
)) {
597 if ((addr
& 0x00ff800) == 0xff800) {
598 ql_log(ql_log_warn
, vha
, 0xb004,
599 "%s: QM access not handled.\n", __func__
);
602 window
= OCM_WIN(addr
);
603 ha
->ddr_mn_window
= window
;
605 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
, window
);
606 win_read
= qla82xx_rd_32(ha
,
607 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
);
608 temp1
= ((window
& 0x1FF) << 7) |
609 ((window
& 0x0FFFE0000) >> 17);
610 if (win_read
!= temp1
) {
611 ql_log(ql_log_warn
, vha
, 0xb005,
612 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
613 __func__
, temp1
, win_read
);
615 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_OCM0_2M
;
617 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_QDR_NET
,
618 QLA82XX_P3_ADDR_QDR_NET_MAX
)) {
619 /* QDR network side */
620 window
= MS_WIN(addr
);
621 ha
->qdr_sn_window
= window
;
623 ha
->ms_win_crb
| QLA82XX_PCI_CRBSPACE
, window
);
624 win_read
= qla82xx_rd_32(ha
,
625 ha
->ms_win_crb
| QLA82XX_PCI_CRBSPACE
);
626 if (win_read
!= window
) {
627 ql_log(ql_log_warn
, vha
, 0xb006,
628 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
629 __func__
, window
, win_read
);
631 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_QDR_NET
;
634 * peg gdb frequently accesses memory that doesn't exist,
635 * this limits the chit chat so debugging isn't slowed down.
637 if ((qla82xx_pci_set_window_warning_count
++ < 8) ||
638 (qla82xx_pci_set_window_warning_count
%64 == 0)) {
639 ql_log(ql_log_warn
, vha
, 0xb007,
640 "%s: Warning:%s Unknown address range!.\n",
641 __func__
, QLA2XXX_DRIVER_NAME
);
648 /* check if address is in the same windows as the previous access */
649 static int qla82xx_pci_is_same_window(struct qla_hw_data
*ha
,
650 unsigned long long addr
)
653 unsigned long long qdr_max
;
655 qdr_max
= QLA82XX_P3_ADDR_QDR_NET_MAX
;
657 /* DDR network side */
658 if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
659 QLA82XX_ADDR_DDR_NET_MAX
))
661 else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM0
,
662 QLA82XX_ADDR_OCM0_MAX
))
664 else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM1
,
665 QLA82XX_ADDR_OCM1_MAX
))
667 else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_QDR_NET
, qdr_max
)) {
668 /* QDR network side */
669 window
= ((addr
- QLA82XX_ADDR_QDR_NET
) >> 22) & 0x3f;
670 if (ha
->qdr_sn_window
== window
)
676 static int qla82xx_pci_mem_read_direct(struct qla_hw_data
*ha
,
677 u64 off
, void *data
, int size
)
683 uint8_t *mem_ptr
= NULL
;
684 unsigned long mem_base
;
685 unsigned long mem_page
;
686 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
688 write_lock_irqsave(&ha
->hw_lock
, flags
);
691 * If attempting to access unknown address or straddle hw windows,
694 start
= qla82xx_pci_set_window(ha
, off
);
695 if ((start
== -1UL) ||
696 (qla82xx_pci_is_same_window(ha
, off
+ size
- 1) == 0)) {
697 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
698 ql_log(ql_log_fatal
, vha
, 0xb008,
699 "%s out of bound pci memory "
700 "access, offset is 0x%llx.\n",
701 QLA2XXX_DRIVER_NAME
, off
);
705 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
706 mem_base
= pci_resource_start(ha
->pdev
, 0);
707 mem_page
= start
& PAGE_MASK
;
708 /* Map two pages whenever user tries to access addresses in two
711 if (mem_page
!= ((start
+ size
- 1) & PAGE_MASK
))
712 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
* 2);
714 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
);
715 if (mem_ptr
== 0UL) {
720 addr
+= start
& (PAGE_SIZE
- 1);
721 write_lock_irqsave(&ha
->hw_lock
, flags
);
725 *(u8
*)data
= readb(addr
);
728 *(u16
*)data
= readw(addr
);
731 *(u32
*)data
= readl(addr
);
734 *(u64
*)data
= readq(addr
);
740 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
748 qla82xx_pci_mem_write_direct(struct qla_hw_data
*ha
,
749 u64 off
, void *data
, int size
)
755 uint8_t *mem_ptr
= NULL
;
756 unsigned long mem_base
;
757 unsigned long mem_page
;
758 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
760 write_lock_irqsave(&ha
->hw_lock
, flags
);
763 * If attempting to access unknown address or straddle hw windows,
766 start
= qla82xx_pci_set_window(ha
, off
);
767 if ((start
== -1UL) ||
768 (qla82xx_pci_is_same_window(ha
, off
+ size
- 1) == 0)) {
769 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
770 ql_log(ql_log_fatal
, vha
, 0xb009,
771 "%s out of bount memory "
772 "access, offset is 0x%llx.\n",
773 QLA2XXX_DRIVER_NAME
, off
);
777 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
778 mem_base
= pci_resource_start(ha
->pdev
, 0);
779 mem_page
= start
& PAGE_MASK
;
780 /* Map two pages whenever user tries to access addresses in two
783 if (mem_page
!= ((start
+ size
- 1) & PAGE_MASK
))
784 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
*2);
786 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
);
791 addr
+= start
& (PAGE_SIZE
- 1);
792 write_lock_irqsave(&ha
->hw_lock
, flags
);
796 writeb(*(u8
*)data
, addr
);
799 writew(*(u16
*)data
, addr
);
802 writel(*(u32
*)data
, addr
);
805 writeq(*(u64
*)data
, addr
);
811 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
817 #define MTU_FUDGE_FACTOR 100
819 qla82xx_decode_crb_addr(unsigned long addr
)
822 unsigned long base_addr
, offset
, pci_base
;
824 if (!qla82xx_crb_table_initialized
)
825 qla82xx_crb_addr_transform_setup();
827 pci_base
= ADDR_ERROR
;
828 base_addr
= addr
& 0xfff00000;
829 offset
= addr
& 0x000fffff;
831 for (i
= 0; i
< MAX_CRB_XFORM
; i
++) {
832 if (crb_addr_xform
[i
] == base_addr
) {
837 if (pci_base
== ADDR_ERROR
)
839 return pci_base
+ offset
;
842 static long rom_max_timeout
= 100;
843 static long qla82xx_rom_lock_timeout
= 100;
846 qla82xx_rom_lock(struct qla_hw_data
*ha
)
848 int done
= 0, timeout
= 0;
851 /* acquire semaphore2 from PCI HW block */
852 done
= qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK
));
855 if (timeout
>= qla82xx_rom_lock_timeout
)
859 qla82xx_wr_32(ha
, QLA82XX_ROM_LOCK_ID
, ROM_LOCK_DRIVER
);
864 qla82xx_rom_unlock(struct qla_hw_data
*ha
)
866 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK
));
870 qla82xx_wait_rom_busy(struct qla_hw_data
*ha
)
874 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
877 done
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_STATUS
);
880 if (timeout
>= rom_max_timeout
) {
881 ql_dbg(ql_dbg_p3p
, vha
, 0xb00a,
882 "%s: Timeout reached waiting for rom busy.\n",
883 QLA2XXX_DRIVER_NAME
);
891 qla82xx_wait_rom_done(struct qla_hw_data
*ha
)
895 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
898 done
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_STATUS
);
901 if (timeout
>= rom_max_timeout
) {
902 ql_dbg(ql_dbg_p3p
, vha
, 0xb00b,
903 "%s: Timeout reached waiting for rom done.\n",
904 QLA2XXX_DRIVER_NAME
);
912 qla82xx_do_rom_fast_read(struct qla_hw_data
*ha
, int addr
, int *valp
)
914 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
916 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ADDRESS
, addr
);
917 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT
, 0);
918 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 3);
919 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, 0xb);
920 qla82xx_wait_rom_busy(ha
);
921 if (qla82xx_wait_rom_done(ha
)) {
922 ql_log(ql_log_fatal
, vha
, 0x00ba,
923 "Error waiting for rom done.\n");
926 /* Reset abyte_cnt and dummy_byte_cnt */
927 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT
, 0);
930 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 0);
931 *valp
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_ROM_RDATA
);
936 qla82xx_rom_fast_read(struct qla_hw_data
*ha
, int addr
, int *valp
)
939 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
941 while ((qla82xx_rom_lock(ha
) != 0) && (loops
< 50000)) {
946 if (loops
>= 50000) {
947 ql_log(ql_log_fatal
, vha
, 0x00b9,
948 "Failed to aquire SEM2 lock.\n");
951 ret
= qla82xx_do_rom_fast_read(ha
, addr
, valp
);
952 qla82xx_rom_unlock(ha
);
957 qla82xx_read_status_reg(struct qla_hw_data
*ha
, uint32_t *val
)
959 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
960 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_RDSR
);
961 qla82xx_wait_rom_busy(ha
);
962 if (qla82xx_wait_rom_done(ha
)) {
963 ql_log(ql_log_warn
, vha
, 0xb00c,
964 "Error waiting for rom done.\n");
967 *val
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_ROM_RDATA
);
972 qla82xx_flash_wait_write_finish(struct qla_hw_data
*ha
)
978 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
980 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 0);
981 while ((done
!= 0) && (ret
== 0)) {
982 ret
= qla82xx_read_status_reg(ha
, &val
);
987 if (timeout
>= 50000) {
988 ql_log(ql_log_warn
, vha
, 0xb00d,
989 "Timeout reached waiting for write finish.\n");
997 qla82xx_flash_set_write_enable(struct qla_hw_data
*ha
)
1000 qla82xx_wait_rom_busy(ha
);
1001 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 0);
1002 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_WREN
);
1003 qla82xx_wait_rom_busy(ha
);
1004 if (qla82xx_wait_rom_done(ha
))
1006 if (qla82xx_read_status_reg(ha
, &val
) != 0)
1014 qla82xx_write_status_reg(struct qla_hw_data
*ha
, uint32_t val
)
1016 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1017 if (qla82xx_flash_set_write_enable(ha
))
1019 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_WDATA
, val
);
1020 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, 0x1);
1021 if (qla82xx_wait_rom_done(ha
)) {
1022 ql_log(ql_log_warn
, vha
, 0xb00e,
1023 "Error waiting for rom done.\n");
1026 return qla82xx_flash_wait_write_finish(ha
);
1030 qla82xx_write_disable_flash(struct qla_hw_data
*ha
)
1032 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1033 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_WRDI
);
1034 if (qla82xx_wait_rom_done(ha
)) {
1035 ql_log(ql_log_warn
, vha
, 0xb00f,
1036 "Error waiting for rom done.\n");
1043 ql82xx_rom_lock_d(struct qla_hw_data
*ha
)
1046 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1048 while ((qla82xx_rom_lock(ha
) != 0) && (loops
< 50000)) {
1053 if (loops
>= 50000) {
1054 ql_log(ql_log_warn
, vha
, 0xb010,
1055 "ROM lock failed.\n");
1062 qla82xx_write_flash_dword(struct qla_hw_data
*ha
, uint32_t flashaddr
,
1066 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1068 ret
= ql82xx_rom_lock_d(ha
);
1070 ql_log(ql_log_warn
, vha
, 0xb011,
1071 "ROM lock failed.\n");
1075 if (qla82xx_flash_set_write_enable(ha
))
1078 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_WDATA
, data
);
1079 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ADDRESS
, flashaddr
);
1080 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 3);
1081 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_PP
);
1082 qla82xx_wait_rom_busy(ha
);
1083 if (qla82xx_wait_rom_done(ha
)) {
1084 ql_log(ql_log_warn
, vha
, 0xb012,
1085 "Error waiting for rom done.\n");
1090 ret
= qla82xx_flash_wait_write_finish(ha
);
1093 qla82xx_rom_unlock(ha
);
1097 /* This routine does CRB initialize sequence
1098 * to put the ISP into operational state
1101 qla82xx_pinit_from_rom(scsi_qla_host_t
*vha
)
1105 struct crb_addr_pair
*buf
;
1108 struct qla_hw_data
*ha
= vha
->hw
;
1110 struct crb_addr_pair
{
1115 /* Halt all the indiviual PEGs and other blocks of the ISP */
1116 qla82xx_rom_lock(ha
);
1118 /* disable all I2Q */
1119 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x10, 0x0);
1120 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x14, 0x0);
1121 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x18, 0x0);
1122 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x1c, 0x0);
1123 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x20, 0x0);
1124 qla82xx_wr_32(ha
, QLA82XX_CRB_I2Q
+ 0x24, 0x0);
1126 /* disable all niu interrupts */
1127 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0x40, 0xff);
1128 /* disable xge rx/tx */
1129 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0x70000, 0x00);
1130 /* disable xg1 rx/tx */
1131 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0x80000, 0x00);
1132 /* disable sideband mac */
1133 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0x90000, 0x00);
1134 /* disable ap0 mac */
1135 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0xa0000, 0x00);
1136 /* disable ap1 mac */
1137 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0xb0000, 0x00);
1140 val
= qla82xx_rd_32(ha
, QLA82XX_CRB_SRE
+ 0x1000);
1141 qla82xx_wr_32(ha
, QLA82XX_CRB_SRE
+ 0x1000, val
& (~(0x1)));
1144 qla82xx_wr_32(ha
, QLA82XX_CRB_EPG
+ 0x1300, 0x1);
1147 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x0, 0x0);
1148 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x8, 0x0);
1149 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x10, 0x0);
1150 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x18, 0x0);
1151 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x100, 0x0);
1152 qla82xx_wr_32(ha
, QLA82XX_CRB_TIMER
+ 0x200, 0x0);
1155 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+ 0x3c, 1);
1156 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_1
+ 0x3c, 1);
1157 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_2
+ 0x3c, 1);
1158 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_3
+ 0x3c, 1);
1159 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_4
+ 0x3c, 1);
1163 if (test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
))
1164 /* don't reset CAM block on reset */
1165 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0xfeffffff);
1167 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0xffffffff);
1168 qla82xx_rom_unlock(ha
);
1170 /* Read the signature value from the flash.
1171 * Offset 0: Contain signature (0xcafecafe)
1172 * Offset 4: Offset and number of addr/value pairs
1173 * that present in CRB initialize sequence
1175 if (qla82xx_rom_fast_read(ha
, 0, &n
) != 0 || n
!= 0xcafecafeUL
||
1176 qla82xx_rom_fast_read(ha
, 4, &n
) != 0) {
1177 ql_log(ql_log_fatal
, vha
, 0x006e,
1178 "Error Reading crb_init area: n: %08x.\n", n
);
1182 /* Offset in flash = lower 16 bits
1183 * Number of enteries = upper 16 bits
1185 offset
= n
& 0xffffU
;
1186 n
= (n
>> 16) & 0xffffU
;
1188 /* number of addr/value pair should not exceed 1024 enteries */
1190 ql_log(ql_log_fatal
, vha
, 0x0071,
1191 "Card flash not initialized:n=0x%x.\n", n
);
1195 ql_log(ql_log_info
, vha
, 0x0072,
1196 "%d CRB init values found in ROM.\n", n
);
1198 buf
= kmalloc(n
* sizeof(struct crb_addr_pair
), GFP_KERNEL
);
1200 ql_log(ql_log_fatal
, vha
, 0x010c,
1201 "Unable to allocate memory.\n");
1205 for (i
= 0; i
< n
; i
++) {
1206 if (qla82xx_rom_fast_read(ha
, 8*i
+ 4*offset
, &val
) != 0 ||
1207 qla82xx_rom_fast_read(ha
, 8*i
+ 4*offset
+ 4, &addr
) != 0) {
1216 for (i
= 0; i
< n
; i
++) {
1217 /* Translate internal CRB initialization
1218 * address to PCI bus address
1220 off
= qla82xx_decode_crb_addr((unsigned long)buf
[i
].addr
) +
1221 QLA82XX_PCI_CRBSPACE
;
1222 /* Not all CRB addr/value pair to be written,
1223 * some of them are skipped
1226 /* skipping cold reboot MAGIC */
1227 if (off
== QLA82XX_CAM_RAM(0x1fc))
1230 /* do not reset PCI */
1231 if (off
== (ROMUSB_GLB
+ 0xbc))
1234 /* skip core clock, so that firmware can increase the clock */
1235 if (off
== (ROMUSB_GLB
+ 0xc8))
1238 /* skip the function enable register */
1239 if (off
== QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION
))
1242 if (off
== QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2
))
1245 if ((off
& 0x0ff00000) == QLA82XX_CRB_SMB
)
1248 if ((off
& 0x0ff00000) == QLA82XX_CRB_DDR_NET
)
1251 if (off
== ADDR_ERROR
) {
1252 ql_log(ql_log_fatal
, vha
, 0x0116,
1253 "Unknow addr: 0x%08lx.\n", buf
[i
].addr
);
1257 qla82xx_wr_32(ha
, off
, buf
[i
].data
);
1259 /* ISP requires much bigger delay to settle down,
1260 * else crb_window returns 0xffffffff
1262 if (off
== QLA82XX_ROMUSB_GLB_SW_RESET
)
1265 /* ISP requires millisec delay between
1266 * successive CRB register updation
1273 /* Resetting the data and instruction cache */
1274 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_D
+0xec, 0x1e);
1275 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_D
+0x4c, 8);
1276 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_I
+0x4c, 8);
1278 /* Clear all protocol processing engines */
1279 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+0x8, 0);
1280 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+0xc, 0);
1281 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_1
+0x8, 0);
1282 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_1
+0xc, 0);
1283 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_2
+0x8, 0);
1284 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_2
+0xc, 0);
1285 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_3
+0x8, 0);
1286 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_3
+0xc, 0);
1291 qla82xx_pci_mem_write_2M(struct qla_hw_data
*ha
,
1292 u64 off
, void *data
, int size
)
1294 int i
, j
, ret
= 0, loop
, sz
[2], off0
;
1295 int scale
, shift_amount
, startword
;
1297 uint64_t off8
, mem_crb
, tmpw
, word
[2] = {0, 0};
1300 * If not MN, go check for MS or invalid.
1302 if (off
>= QLA82XX_ADDR_QDR_NET
&& off
<= QLA82XX_P3_ADDR_QDR_NET_MAX
)
1303 mem_crb
= QLA82XX_CRB_QDR_NET
;
1305 mem_crb
= QLA82XX_CRB_DDR_NET
;
1306 if (qla82xx_pci_mem_bound_check(ha
, off
, size
) == 0)
1307 return qla82xx_pci_mem_write_direct(ha
,
1312 sz
[0] = (size
< (8 - off0
)) ? size
: (8 - off0
);
1313 sz
[1] = size
- sz
[0];
1315 off8
= off
& 0xfffffff0;
1316 loop
= (((off
& 0xf) + size
- 1) >> 4) + 1;
1319 startword
= (off
& 0xf)/8;
1321 for (i
= 0; i
< loop
; i
++) {
1322 if (qla82xx_pci_mem_read_2M(ha
, off8
+
1323 (i
<< shift_amount
), &word
[i
* scale
], 8))
1329 tmpw
= *((uint8_t *)data
);
1332 tmpw
= *((uint16_t *)data
);
1335 tmpw
= *((uint32_t *)data
);
1339 tmpw
= *((uint64_t *)data
);
1344 word
[startword
] = tmpw
;
1347 ~((~(~0ULL << (sz
[0] * 8))) << (off0
* 8));
1348 word
[startword
] |= tmpw
<< (off0
* 8);
1351 word
[startword
+1] &= ~(~0ULL << (sz
[1] * 8));
1352 word
[startword
+1] |= tmpw
>> (sz
[0] * 8);
1355 for (i
= 0; i
< loop
; i
++) {
1356 temp
= off8
+ (i
<< shift_amount
);
1357 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_ADDR_LO
, temp
);
1359 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_ADDR_HI
, temp
);
1360 temp
= word
[i
* scale
] & 0xffffffff;
1361 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_WRDATA_LO
, temp
);
1362 temp
= (word
[i
* scale
] >> 32) & 0xffffffff;
1363 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_WRDATA_HI
, temp
);
1364 temp
= word
[i
*scale
+ 1] & 0xffffffff;
1365 qla82xx_wr_32(ha
, mem_crb
+
1366 MIU_TEST_AGT_WRDATA_UPPER_LO
, temp
);
1367 temp
= (word
[i
*scale
+ 1] >> 32) & 0xffffffff;
1368 qla82xx_wr_32(ha
, mem_crb
+
1369 MIU_TEST_AGT_WRDATA_UPPER_HI
, temp
);
1371 temp
= MIU_TA_CTL_ENABLE
| MIU_TA_CTL_WRITE
;
1372 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1373 temp
= MIU_TA_CTL_START
| MIU_TA_CTL_ENABLE
| MIU_TA_CTL_WRITE
;
1374 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1376 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1377 temp
= qla82xx_rd_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
);
1378 if ((temp
& MIU_TA_CTL_BUSY
) == 0)
1382 if (j
>= MAX_CTL_CHECK
) {
1383 if (printk_ratelimit())
1384 dev_err(&ha
->pdev
->dev
,
1385 "failed to write through agent.\n");
1395 qla82xx_fw_load_from_flash(struct qla_hw_data
*ha
)
1399 long flashaddr
= ha
->flt_region_bootload
<< 2;
1400 long memaddr
= BOOTLD_START
;
1403 size
= (IMAGE_START
- BOOTLD_START
) / 8;
1405 for (i
= 0; i
< size
; i
++) {
1406 if ((qla82xx_rom_fast_read(ha
, flashaddr
, (int *)&low
)) ||
1407 (qla82xx_rom_fast_read(ha
, flashaddr
+ 4, (int *)&high
))) {
1410 data
= ((u64
)high
<< 32) | low
;
1411 qla82xx_pci_mem_write_2M(ha
, memaddr
, &data
, 8);
1415 if (i
% 0x1000 == 0)
1419 read_lock(&ha
->hw_lock
);
1420 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+ 0x18, 0x1020);
1421 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0x80001e);
1422 read_unlock(&ha
->hw_lock
);
1427 qla82xx_pci_mem_read_2M(struct qla_hw_data
*ha
,
1428 u64 off
, void *data
, int size
)
1430 int i
, j
= 0, k
, start
, end
, loop
, sz
[2], off0
[2];
1433 uint64_t off8
, val
, mem_crb
, word
[2] = {0, 0};
1436 * If not MN, go check for MS or invalid.
1439 if (off
>= QLA82XX_ADDR_QDR_NET
&& off
<= QLA82XX_P3_ADDR_QDR_NET_MAX
)
1440 mem_crb
= QLA82XX_CRB_QDR_NET
;
1442 mem_crb
= QLA82XX_CRB_DDR_NET
;
1443 if (qla82xx_pci_mem_bound_check(ha
, off
, size
) == 0)
1444 return qla82xx_pci_mem_read_direct(ha
,
1448 off8
= off
& 0xfffffff0;
1449 off0
[0] = off
& 0xf;
1450 sz
[0] = (size
< (16 - off0
[0])) ? size
: (16 - off0
[0]);
1452 loop
= ((off0
[0] + size
- 1) >> shift_amount
) + 1;
1454 sz
[1] = size
- sz
[0];
1456 for (i
= 0; i
< loop
; i
++) {
1457 temp
= off8
+ (i
<< shift_amount
);
1458 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_ADDR_LO
, temp
);
1460 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_ADDR_HI
, temp
);
1461 temp
= MIU_TA_CTL_ENABLE
;
1462 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1463 temp
= MIU_TA_CTL_START
| MIU_TA_CTL_ENABLE
;
1464 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1466 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1467 temp
= qla82xx_rd_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
);
1468 if ((temp
& MIU_TA_CTL_BUSY
) == 0)
1472 if (j
>= MAX_CTL_CHECK
) {
1473 if (printk_ratelimit())
1474 dev_err(&ha
->pdev
->dev
,
1475 "failed to read through agent.\n");
1479 start
= off0
[i
] >> 2;
1480 end
= (off0
[i
] + sz
[i
] - 1) >> 2;
1481 for (k
= start
; k
<= end
; k
++) {
1482 temp
= qla82xx_rd_32(ha
,
1483 mem_crb
+ MIU_TEST_AGT_RDDATA(k
));
1484 word
[i
] |= ((uint64_t)temp
<< (32 * (k
& 1)));
1488 if (j
>= MAX_CTL_CHECK
)
1491 if ((off0
[0] & 7) == 0) {
1494 val
= ((word
[0] >> (off0
[0] * 8)) & (~(~0ULL << (sz
[0] * 8)))) |
1495 ((word
[1] & (~(~0ULL << (sz
[1] * 8)))) << (sz
[0] * 8));
1500 *(uint8_t *)data
= val
;
1503 *(uint16_t *)data
= val
;
1506 *(uint32_t *)data
= val
;
1509 *(uint64_t *)data
= val
;
1516 static struct qla82xx_uri_table_desc
*
1517 qla82xx_get_table_desc(const u8
*unirom
, int section
)
1520 struct qla82xx_uri_table_desc
*directory
=
1521 (struct qla82xx_uri_table_desc
*)&unirom
[0];
1524 __le32 entries
= cpu_to_le32(directory
->num_entries
);
1526 for (i
= 0; i
< entries
; i
++) {
1527 offset
= cpu_to_le32(directory
->findex
) +
1528 (i
* cpu_to_le32(directory
->entry_size
));
1529 tab_type
= cpu_to_le32(*((u32
*)&unirom
[offset
] + 8));
1531 if (tab_type
== section
)
1532 return (struct qla82xx_uri_table_desc
*)&unirom
[offset
];
1538 static struct qla82xx_uri_data_desc
*
1539 qla82xx_get_data_desc(struct qla_hw_data
*ha
,
1540 u32 section
, u32 idx_offset
)
1542 const u8
*unirom
= ha
->hablob
->fw
->data
;
1543 int idx
= cpu_to_le32(*((int *)&unirom
[ha
->file_prd_off
] + idx_offset
));
1544 struct qla82xx_uri_table_desc
*tab_desc
= NULL
;
1547 tab_desc
= qla82xx_get_table_desc(unirom
, section
);
1551 offset
= cpu_to_le32(tab_desc
->findex
) +
1552 (cpu_to_le32(tab_desc
->entry_size
) * idx
);
1554 return (struct qla82xx_uri_data_desc
*)&unirom
[offset
];
1558 qla82xx_get_bootld_offset(struct qla_hw_data
*ha
)
1560 u32 offset
= BOOTLD_START
;
1561 struct qla82xx_uri_data_desc
*uri_desc
= NULL
;
1563 if (ha
->fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1564 uri_desc
= qla82xx_get_data_desc(ha
,
1565 QLA82XX_URI_DIR_SECT_BOOTLD
, QLA82XX_URI_BOOTLD_IDX_OFF
);
1567 offset
= cpu_to_le32(uri_desc
->findex
);
1570 return (u8
*)&ha
->hablob
->fw
->data
[offset
];
1574 qla82xx_get_fw_size(struct qla_hw_data
*ha
)
1576 struct qla82xx_uri_data_desc
*uri_desc
= NULL
;
1578 if (ha
->fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1579 uri_desc
= qla82xx_get_data_desc(ha
, QLA82XX_URI_DIR_SECT_FW
,
1580 QLA82XX_URI_FIRMWARE_IDX_OFF
);
1582 return cpu_to_le32(uri_desc
->size
);
1585 return cpu_to_le32(*(u32
*)&ha
->hablob
->fw
->data
[FW_SIZE_OFFSET
]);
1589 qla82xx_get_fw_offs(struct qla_hw_data
*ha
)
1591 u32 offset
= IMAGE_START
;
1592 struct qla82xx_uri_data_desc
*uri_desc
= NULL
;
1594 if (ha
->fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1595 uri_desc
= qla82xx_get_data_desc(ha
, QLA82XX_URI_DIR_SECT_FW
,
1596 QLA82XX_URI_FIRMWARE_IDX_OFF
);
1598 offset
= cpu_to_le32(uri_desc
->findex
);
1601 return (u8
*)&ha
->hablob
->fw
->data
[offset
];
1604 /* PCI related functions */
1606 qla82xx_pci_info_str(struct scsi_qla_host
*vha
, char *str
)
1609 struct qla_hw_data
*ha
= vha
->hw
;
1613 pcie_reg
= pci_find_capability(ha
->pdev
, PCI_CAP_ID_EXP
);
1614 pci_read_config_word(ha
->pdev
, pcie_reg
+ PCI_EXP_LNKSTA
, &lnk
);
1615 ha
->link_width
= (lnk
>> 4) & 0x3f;
1617 strcpy(str
, "PCIe (");
1618 strcat(str
, "2.5Gb/s ");
1619 snprintf(lwstr
, sizeof(lwstr
), "x%d)", ha
->link_width
);
1624 int qla82xx_pci_region_offset(struct pci_dev
*pdev
, int region
)
1626 unsigned long val
= 0;
1634 pci_read_config_dword(pdev
, QLA82XX_PCI_REG_MSIX_TBL
, &control
);
1635 val
= control
+ QLA82XX_MSIX_TBL_SPACE
;
1643 qla82xx_iospace_config(struct qla_hw_data
*ha
)
1647 if (pci_request_regions(ha
->pdev
, QLA2XXX_DRIVER_NAME
)) {
1648 ql_log_pci(ql_log_fatal
, ha
->pdev
, 0x000c,
1649 "Failed to reserver selected regions.\n");
1650 goto iospace_error_exit
;
1653 /* Use MMIO operations for all accesses. */
1654 if (!(pci_resource_flags(ha
->pdev
, 0) & IORESOURCE_MEM
)) {
1655 ql_log_pci(ql_log_fatal
, ha
->pdev
, 0x000d,
1656 "Region #0 not an MMIO resource, aborting.\n");
1657 goto iospace_error_exit
;
1660 len
= pci_resource_len(ha
->pdev
, 0);
1662 (unsigned long)ioremap(pci_resource_start(ha
->pdev
, 0), len
);
1663 if (!ha
->nx_pcibase
) {
1664 ql_log_pci(ql_log_fatal
, ha
->pdev
, 0x000e,
1665 "Cannot remap pcibase MMIO, aborting.\n");
1666 pci_release_regions(ha
->pdev
);
1667 goto iospace_error_exit
;
1670 /* Mapping of IO base pointer */
1671 ha
->iobase
= (device_reg_t __iomem
*)((uint8_t *)ha
->nx_pcibase
+
1672 0xbc000 + (ha
->pdev
->devfn
<< 11));
1676 (unsigned long)ioremap((pci_resource_start(ha
->pdev
, 4) +
1677 (ha
->pdev
->devfn
<< 12)), 4);
1678 if (!ha
->nxdb_wr_ptr
) {
1679 ql_log_pci(ql_log_fatal
, ha
->pdev
, 0x000f,
1680 "Cannot remap MMIO, aborting.\n");
1681 pci_release_regions(ha
->pdev
);
1682 goto iospace_error_exit
;
1685 /* Mapping of IO base pointer,
1686 * door bell read and write pointer
1688 ha
->nxdb_rd_ptr
= (uint8_t *) ha
->nx_pcibase
+ (512 * 1024) +
1689 (ha
->pdev
->devfn
* 8);
1691 ha
->nxdb_wr_ptr
= (ha
->pdev
->devfn
== 6 ?
1692 QLA82XX_CAMRAM_DB1
:
1693 QLA82XX_CAMRAM_DB2
);
1696 ha
->max_req_queues
= ha
->max_rsp_queues
= 1;
1697 ha
->msix_count
= ha
->max_rsp_queues
+ 1;
1698 ql_dbg_pci(ql_dbg_multiq
, ha
->pdev
, 0xc006,
1699 "nx_pci_base=%p iobase=%p "
1700 "max_req_queues=%d msix_count=%d.\n",
1701 (void *)ha
->nx_pcibase
, ha
->iobase
,
1702 ha
->max_req_queues
, ha
->msix_count
);
1703 ql_dbg_pci(ql_dbg_init
, ha
->pdev
, 0x0010,
1704 "nx_pci_base=%p iobase=%p "
1705 "max_req_queues=%d msix_count=%d.\n",
1706 (void *)ha
->nx_pcibase
, ha
->iobase
,
1707 ha
->max_req_queues
, ha
->msix_count
);
1714 /* GS related functions */
1716 /* Initialization related functions */
1719 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1722 * Returns 0 on success.
1725 qla82xx_pci_config(scsi_qla_host_t
*vha
)
1727 struct qla_hw_data
*ha
= vha
->hw
;
1730 pci_set_master(ha
->pdev
);
1731 ret
= pci_set_mwi(ha
->pdev
);
1732 ha
->chip_revision
= ha
->pdev
->revision
;
1733 ql_dbg(ql_dbg_init
, vha
, 0x0043,
1734 "Chip revision:%d.\n",
1740 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1743 * Returns 0 on success.
1746 qla82xx_reset_chip(scsi_qla_host_t
*vha
)
1748 struct qla_hw_data
*ha
= vha
->hw
;
1749 ha
->isp_ops
->disable_intrs(ha
);
1752 void qla82xx_config_rings(struct scsi_qla_host
*vha
)
1754 struct qla_hw_data
*ha
= vha
->hw
;
1755 struct device_reg_82xx __iomem
*reg
= &ha
->iobase
->isp82
;
1756 struct init_cb_81xx
*icb
;
1757 struct req_que
*req
= ha
->req_q_map
[0];
1758 struct rsp_que
*rsp
= ha
->rsp_q_map
[0];
1760 /* Setup ring parameters in initialization control block. */
1761 icb
= (struct init_cb_81xx
*)ha
->init_cb
;
1762 icb
->request_q_outpointer
= __constant_cpu_to_le16(0);
1763 icb
->response_q_inpointer
= __constant_cpu_to_le16(0);
1764 icb
->request_q_length
= cpu_to_le16(req
->length
);
1765 icb
->response_q_length
= cpu_to_le16(rsp
->length
);
1766 icb
->request_q_address
[0] = cpu_to_le32(LSD(req
->dma
));
1767 icb
->request_q_address
[1] = cpu_to_le32(MSD(req
->dma
));
1768 icb
->response_q_address
[0] = cpu_to_le32(LSD(rsp
->dma
));
1769 icb
->response_q_address
[1] = cpu_to_le32(MSD(rsp
->dma
));
1771 WRT_REG_DWORD((unsigned long __iomem
*)®
->req_q_out
[0], 0);
1772 WRT_REG_DWORD((unsigned long __iomem
*)®
->rsp_q_in
[0], 0);
1773 WRT_REG_DWORD((unsigned long __iomem
*)®
->rsp_q_out
[0], 0);
1776 void qla82xx_reset_adapter(struct scsi_qla_host
*vha
)
1778 struct qla_hw_data
*ha
= vha
->hw
;
1779 vha
->flags
.online
= 0;
1780 qla2x00_try_to_stop_firmware(vha
);
1781 ha
->isp_ops
->disable_intrs(ha
);
1785 qla82xx_fw_load_from_blob(struct qla_hw_data
*ha
)
1788 u32 i
, flashaddr
, size
;
1791 size
= (IMAGE_START
- BOOTLD_START
) / 8;
1793 ptr64
= (u64
*)qla82xx_get_bootld_offset(ha
);
1794 flashaddr
= BOOTLD_START
;
1796 for (i
= 0; i
< size
; i
++) {
1797 data
= cpu_to_le64(ptr64
[i
]);
1798 if (qla82xx_pci_mem_write_2M(ha
, flashaddr
, &data
, 8))
1803 flashaddr
= FLASH_ADDR_START
;
1804 size
= (__force u32
)qla82xx_get_fw_size(ha
) / 8;
1805 ptr64
= (u64
*)qla82xx_get_fw_offs(ha
);
1807 for (i
= 0; i
< size
; i
++) {
1808 data
= cpu_to_le64(ptr64
[i
]);
1810 if (qla82xx_pci_mem_write_2M(ha
, flashaddr
, &data
, 8))
1816 /* Write a magic value to CAMRAM register
1817 * at a specified offset to indicate
1818 * that all data is written and
1819 * ready for firmware to initialize.
1821 qla82xx_wr_32(ha
, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC
);
1823 read_lock(&ha
->hw_lock
);
1824 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+ 0x18, 0x1020);
1825 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0x80001e);
1826 read_unlock(&ha
->hw_lock
);
1831 qla82xx_set_product_offset(struct qla_hw_data
*ha
)
1833 struct qla82xx_uri_table_desc
*ptab_desc
= NULL
;
1834 const uint8_t *unirom
= ha
->hablob
->fw
->data
;
1837 __le32 flags
, file_chiprev
, offset
;
1838 uint8_t chiprev
= ha
->chip_revision
;
1839 /* Hardcoding mn_present flag for P3P */
1843 ptab_desc
= qla82xx_get_table_desc(unirom
,
1844 QLA82XX_URI_DIR_SECT_PRODUCT_TBL
);
1848 entries
= cpu_to_le32(ptab_desc
->num_entries
);
1850 for (i
= 0; i
< entries
; i
++) {
1851 offset
= cpu_to_le32(ptab_desc
->findex
) +
1852 (i
* cpu_to_le32(ptab_desc
->entry_size
));
1853 flags
= cpu_to_le32(*((int *)&unirom
[offset
] +
1854 QLA82XX_URI_FLAGS_OFF
));
1855 file_chiprev
= cpu_to_le32(*((int *)&unirom
[offset
] +
1856 QLA82XX_URI_CHIP_REV_OFF
));
1858 flagbit
= mn_present
? 1 : 2;
1860 if ((chiprev
== file_chiprev
) && ((1ULL << flagbit
) & flags
)) {
1861 ha
->file_prd_off
= offset
;
1869 qla82xx_validate_firmware_blob(scsi_qla_host_t
*vha
, uint8_t fw_type
)
1873 struct qla_hw_data
*ha
= vha
->hw
;
1874 const struct firmware
*fw
= ha
->hablob
->fw
;
1876 ha
->fw_type
= fw_type
;
1878 if (fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1879 if (qla82xx_set_product_offset(ha
))
1882 min_size
= QLA82XX_URI_FW_MIN_SIZE
;
1884 val
= cpu_to_le32(*(u32
*)&fw
->data
[QLA82XX_FW_MAGIC_OFFSET
]);
1885 if ((__force u32
)val
!= QLA82XX_BDINFO_MAGIC
)
1888 min_size
= QLA82XX_FW_MIN_SIZE
;
1891 if (fw
->size
< min_size
)
1897 qla82xx_check_cmdpeg_state(struct qla_hw_data
*ha
)
1901 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1904 read_lock(&ha
->hw_lock
);
1905 val
= qla82xx_rd_32(ha
, CRB_CMDPEG_STATE
);
1906 read_unlock(&ha
->hw_lock
);
1909 case PHAN_INITIALIZE_COMPLETE
:
1910 case PHAN_INITIALIZE_ACK
:
1912 case PHAN_INITIALIZE_FAILED
:
1917 ql_log(ql_log_info
, vha
, 0x00a8,
1918 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1923 } while (--retries
);
1925 ql_log(ql_log_fatal
, vha
, 0x00a9,
1926 "Cmd Peg initialization failed: 0x%x.\n", val
);
1928 val
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE
);
1929 read_lock(&ha
->hw_lock
);
1930 qla82xx_wr_32(ha
, CRB_CMDPEG_STATE
, PHAN_INITIALIZE_FAILED
);
1931 read_unlock(&ha
->hw_lock
);
1932 return QLA_FUNCTION_FAILED
;
1936 qla82xx_check_rcvpeg_state(struct qla_hw_data
*ha
)
1940 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
1943 read_lock(&ha
->hw_lock
);
1944 val
= qla82xx_rd_32(ha
, CRB_RCVPEG_STATE
);
1945 read_unlock(&ha
->hw_lock
);
1948 case PHAN_INITIALIZE_COMPLETE
:
1949 case PHAN_INITIALIZE_ACK
:
1951 case PHAN_INITIALIZE_FAILED
:
1956 ql_log(ql_log_info
, vha
, 0x00ab,
1957 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1962 } while (--retries
);
1964 ql_log(ql_log_fatal
, vha
, 0x00ac,
1965 "Rcv Peg initializatin failed: 0x%x.\n", val
);
1966 read_lock(&ha
->hw_lock
);
1967 qla82xx_wr_32(ha
, CRB_RCVPEG_STATE
, PHAN_INITIALIZE_FAILED
);
1968 read_unlock(&ha
->hw_lock
);
1969 return QLA_FUNCTION_FAILED
;
1972 /* ISR related functions */
1973 uint32_t qla82xx_isr_int_target_mask_enable
[8] = {
1974 ISR_INT_TARGET_MASK
, ISR_INT_TARGET_MASK_F1
,
1975 ISR_INT_TARGET_MASK_F2
, ISR_INT_TARGET_MASK_F3
,
1976 ISR_INT_TARGET_MASK_F4
, ISR_INT_TARGET_MASK_F5
,
1977 ISR_INT_TARGET_MASK_F7
, ISR_INT_TARGET_MASK_F7
1980 uint32_t qla82xx_isr_int_target_status
[8] = {
1981 ISR_INT_TARGET_STATUS
, ISR_INT_TARGET_STATUS_F1
,
1982 ISR_INT_TARGET_STATUS_F2
, ISR_INT_TARGET_STATUS_F3
,
1983 ISR_INT_TARGET_STATUS_F4
, ISR_INT_TARGET_STATUS_F5
,
1984 ISR_INT_TARGET_STATUS_F7
, ISR_INT_TARGET_STATUS_F7
1987 static struct qla82xx_legacy_intr_set legacy_intr
[] = \
1988 QLA82XX_LEGACY_INTR_CONFIG
;
1991 * qla82xx_mbx_completion() - Process mailbox command completions.
1992 * @ha: SCSI driver HA context
1993 * @mb0: Mailbox0 register
1996 qla82xx_mbx_completion(scsi_qla_host_t
*vha
, uint16_t mb0
)
1999 uint16_t __iomem
*wptr
;
2000 struct qla_hw_data
*ha
= vha
->hw
;
2001 struct device_reg_82xx __iomem
*reg
= &ha
->iobase
->isp82
;
2002 wptr
= (uint16_t __iomem
*)®
->mailbox_out
[1];
2004 /* Load return mailbox registers. */
2005 ha
->flags
.mbox_int
= 1;
2006 ha
->mailbox_out
[0] = mb0
;
2008 for (cnt
= 1; cnt
< ha
->mbx_count
; cnt
++) {
2009 ha
->mailbox_out
[cnt
] = RD_REG_WORD(wptr
);
2014 ql_dbg(ql_dbg_async
, vha
, 0x5053,
2015 "MBX pointer ERROR.\n");
2019 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2021 * @dev_id: SCSI driver HA context
2024 * Called by system whenever the host adapter generates an interrupt.
2026 * Returns handled flag.
2029 qla82xx_intr_handler(int irq
, void *dev_id
)
2031 scsi_qla_host_t
*vha
;
2032 struct qla_hw_data
*ha
;
2033 struct rsp_que
*rsp
;
2034 struct device_reg_82xx __iomem
*reg
;
2035 int status
= 0, status1
= 0;
2036 unsigned long flags
;
2041 rsp
= (struct rsp_que
*) dev_id
;
2044 "%s(): NULL response queue pointer.\n", __func__
);
2049 if (!ha
->flags
.msi_enabled
) {
2050 status
= qla82xx_rd_32(ha
, ISR_INT_VECTOR
);
2051 if (!(status
& ha
->nx_legacy_intr
.int_vec_bit
))
2054 status1
= qla82xx_rd_32(ha
, ISR_INT_STATE_REG
);
2055 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1
))
2059 /* clear the interrupt */
2060 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_status_reg
, 0xffffffff);
2062 /* read twice to ensure write is flushed */
2063 qla82xx_rd_32(ha
, ISR_INT_VECTOR
);
2064 qla82xx_rd_32(ha
, ISR_INT_VECTOR
);
2066 reg
= &ha
->iobase
->isp82
;
2068 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2069 vha
= pci_get_drvdata(ha
->pdev
);
2070 for (iter
= 1; iter
--; ) {
2072 if (RD_REG_DWORD(®
->host_int
)) {
2073 stat
= RD_REG_DWORD(®
->host_status
);
2075 switch (stat
& 0xff) {
2080 qla82xx_mbx_completion(vha
, MSW(stat
));
2081 status
|= MBX_INTERRUPT
;
2085 mb
[1] = RD_REG_WORD(®
->mailbox_out
[1]);
2086 mb
[2] = RD_REG_WORD(®
->mailbox_out
[2]);
2087 mb
[3] = RD_REG_WORD(®
->mailbox_out
[3]);
2088 qla2x00_async_event(vha
, rsp
, mb
);
2091 qla24xx_process_response_queue(vha
, rsp
);
2094 ql_dbg(ql_dbg_async
, vha
, 0x5054,
2095 "Unrecognized interrupt type (%d).\n",
2100 WRT_REG_DWORD(®
->host_int
, 0);
2102 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2103 if (!ha
->flags
.msi_enabled
)
2104 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0xfbff);
2106 #ifdef QL_DEBUG_LEVEL_17
2107 if (!irq
&& ha
->flags
.eeh_busy
)
2108 ql_log(ql_log_warn
, vha
, 0x503d,
2109 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2110 status
, ha
->mbx_cmd_flags
, ha
->flags
.mbox_int
, stat
);
2113 if (test_bit(MBX_INTR_WAIT
, &ha
->mbx_cmd_flags
) &&
2114 (status
& MBX_INTERRUPT
) && ha
->flags
.mbox_int
) {
2115 set_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
2116 complete(&ha
->mbx_intr_comp
);
2122 qla82xx_msix_default(int irq
, void *dev_id
)
2124 scsi_qla_host_t
*vha
;
2125 struct qla_hw_data
*ha
;
2126 struct rsp_que
*rsp
;
2127 struct device_reg_82xx __iomem
*reg
;
2129 unsigned long flags
;
2133 rsp
= (struct rsp_que
*) dev_id
;
2136 "%s(): NULL response queue pointer.\n", __func__
);
2141 reg
= &ha
->iobase
->isp82
;
2143 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2144 vha
= pci_get_drvdata(ha
->pdev
);
2146 if (RD_REG_DWORD(®
->host_int
)) {
2147 stat
= RD_REG_DWORD(®
->host_status
);
2149 switch (stat
& 0xff) {
2154 qla82xx_mbx_completion(vha
, MSW(stat
));
2155 status
|= MBX_INTERRUPT
;
2159 mb
[1] = RD_REG_WORD(®
->mailbox_out
[1]);
2160 mb
[2] = RD_REG_WORD(®
->mailbox_out
[2]);
2161 mb
[3] = RD_REG_WORD(®
->mailbox_out
[3]);
2162 qla2x00_async_event(vha
, rsp
, mb
);
2165 qla24xx_process_response_queue(vha
, rsp
);
2168 ql_dbg(ql_dbg_async
, vha
, 0x5041,
2169 "Unrecognized interrupt type (%d).\n",
2174 WRT_REG_DWORD(®
->host_int
, 0);
2177 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2179 #ifdef QL_DEBUG_LEVEL_17
2180 if (!irq
&& ha
->flags
.eeh_busy
)
2181 ql_log(ql_log_warn
, vha
, 0x5044,
2182 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2183 status
, ha
->mbx_cmd_flags
, ha
->flags
.mbox_int
, stat
);
2186 if (test_bit(MBX_INTR_WAIT
, &ha
->mbx_cmd_flags
) &&
2187 (status
& MBX_INTERRUPT
) && ha
->flags
.mbox_int
) {
2188 set_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
2189 complete(&ha
->mbx_intr_comp
);
2195 qla82xx_msix_rsp_q(int irq
, void *dev_id
)
2197 scsi_qla_host_t
*vha
;
2198 struct qla_hw_data
*ha
;
2199 struct rsp_que
*rsp
;
2200 struct device_reg_82xx __iomem
*reg
;
2201 unsigned long flags
;
2203 rsp
= (struct rsp_que
*) dev_id
;
2206 "%s(): NULL response queue pointer.\n", __func__
);
2211 reg
= &ha
->iobase
->isp82
;
2212 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2213 vha
= pci_get_drvdata(ha
->pdev
);
2214 qla24xx_process_response_queue(vha
, rsp
);
2215 WRT_REG_DWORD(®
->host_int
, 0);
2216 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2221 qla82xx_poll(int irq
, void *dev_id
)
2223 scsi_qla_host_t
*vha
;
2224 struct qla_hw_data
*ha
;
2225 struct rsp_que
*rsp
;
2226 struct device_reg_82xx __iomem
*reg
;
2230 unsigned long flags
;
2232 rsp
= (struct rsp_que
*) dev_id
;
2235 "%s(): NULL response queue pointer.\n", __func__
);
2240 reg
= &ha
->iobase
->isp82
;
2241 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2242 vha
= pci_get_drvdata(ha
->pdev
);
2244 if (RD_REG_DWORD(®
->host_int
)) {
2245 stat
= RD_REG_DWORD(®
->host_status
);
2246 switch (stat
& 0xff) {
2251 qla82xx_mbx_completion(vha
, MSW(stat
));
2252 status
|= MBX_INTERRUPT
;
2256 mb
[1] = RD_REG_WORD(®
->mailbox_out
[1]);
2257 mb
[2] = RD_REG_WORD(®
->mailbox_out
[2]);
2258 mb
[3] = RD_REG_WORD(®
->mailbox_out
[3]);
2259 qla2x00_async_event(vha
, rsp
, mb
);
2262 qla24xx_process_response_queue(vha
, rsp
);
2265 ql_dbg(ql_dbg_p3p
, vha
, 0xb013,
2266 "Unrecognized interrupt type (%d).\n",
2271 WRT_REG_DWORD(®
->host_int
, 0);
2272 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2276 qla82xx_enable_intrs(struct qla_hw_data
*ha
)
2278 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2279 qla82xx_mbx_intr_enable(vha
);
2280 spin_lock_irq(&ha
->hardware_lock
);
2281 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0xfbff);
2282 spin_unlock_irq(&ha
->hardware_lock
);
2283 ha
->interrupts_on
= 1;
2287 qla82xx_disable_intrs(struct qla_hw_data
*ha
)
2289 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2290 qla82xx_mbx_intr_disable(vha
);
2291 spin_lock_irq(&ha
->hardware_lock
);
2292 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0x0400);
2293 spin_unlock_irq(&ha
->hardware_lock
);
2294 ha
->interrupts_on
= 0;
2297 void qla82xx_init_flags(struct qla_hw_data
*ha
)
2299 struct qla82xx_legacy_intr_set
*nx_legacy_intr
;
2301 /* ISP 8021 initializations */
2302 rwlock_init(&ha
->hw_lock
);
2303 ha
->qdr_sn_window
= -1;
2304 ha
->ddr_mn_window
= -1;
2305 ha
->curr_window
= 255;
2306 ha
->portnum
= PCI_FUNC(ha
->pdev
->devfn
);
2307 nx_legacy_intr
= &legacy_intr
[ha
->portnum
];
2308 ha
->nx_legacy_intr
.int_vec_bit
= nx_legacy_intr
->int_vec_bit
;
2309 ha
->nx_legacy_intr
.tgt_status_reg
= nx_legacy_intr
->tgt_status_reg
;
2310 ha
->nx_legacy_intr
.tgt_mask_reg
= nx_legacy_intr
->tgt_mask_reg
;
2311 ha
->nx_legacy_intr
.pci_int_reg
= nx_legacy_intr
->pci_int_reg
;
2315 qla82xx_set_drv_active(scsi_qla_host_t
*vha
)
2317 uint32_t drv_active
;
2318 struct qla_hw_data
*ha
= vha
->hw
;
2320 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2322 /* If reset value is all FF's, initialize DRV_ACTIVE */
2323 if (drv_active
== 0xffffffff) {
2324 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
,
2325 QLA82XX_DRV_NOT_ACTIVE
);
2326 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2328 drv_active
|= (QLA82XX_DRV_ACTIVE
<< (ha
->portnum
* 4));
2329 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
, drv_active
);
2333 qla82xx_clear_drv_active(struct qla_hw_data
*ha
)
2335 uint32_t drv_active
;
2337 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2338 drv_active
&= ~(QLA82XX_DRV_ACTIVE
<< (ha
->portnum
* 4));
2339 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
, drv_active
);
2343 qla82xx_need_reset(struct qla_hw_data
*ha
)
2348 if (ha
->flags
.isp82xx_reset_owner
)
2351 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2352 rval
= drv_state
& (QLA82XX_DRVST_RST_RDY
<< (ha
->portnum
* 4));
2358 qla82xx_set_rst_ready(struct qla_hw_data
*ha
)
2361 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2363 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2365 /* If reset value is all FF's, initialize DRV_STATE */
2366 if (drv_state
== 0xffffffff) {
2367 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, QLA82XX_DRVST_NOT_RDY
);
2368 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2370 drv_state
|= (QLA82XX_DRVST_RST_RDY
<< (ha
->portnum
* 4));
2371 ql_dbg(ql_dbg_init
, vha
, 0x00bb,
2372 "drv_state = 0x%08x.\n", drv_state
);
2373 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, drv_state
);
2377 qla82xx_clear_rst_ready(struct qla_hw_data
*ha
)
2381 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2382 drv_state
&= ~(QLA82XX_DRVST_RST_RDY
<< (ha
->portnum
* 4));
2383 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, drv_state
);
2387 qla82xx_set_qsnt_ready(struct qla_hw_data
*ha
)
2389 uint32_t qsnt_state
;
2391 qsnt_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2392 qsnt_state
|= (QLA82XX_DRVST_QSNT_RDY
<< (ha
->portnum
* 4));
2393 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, qsnt_state
);
2397 qla82xx_clear_qsnt_ready(scsi_qla_host_t
*vha
)
2399 struct qla_hw_data
*ha
= vha
->hw
;
2400 uint32_t qsnt_state
;
2402 qsnt_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2403 qsnt_state
&= ~(QLA82XX_DRVST_QSNT_RDY
<< (ha
->portnum
* 4));
2404 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, qsnt_state
);
2408 qla82xx_load_fw(scsi_qla_host_t
*vha
)
2411 struct fw_blob
*blob
;
2412 struct qla_hw_data
*ha
= vha
->hw
;
2414 if (qla82xx_pinit_from_rom(vha
) != QLA_SUCCESS
) {
2415 ql_log(ql_log_fatal
, vha
, 0x009f,
2416 "Error during CRB initialization.\n");
2417 return QLA_FUNCTION_FAILED
;
2421 /* Bring QM and CAMRAM out of reset */
2422 rst
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
);
2423 rst
&= ~((1 << 28) | (1 << 24));
2424 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, rst
);
2428 * 1) Operational firmware residing in flash.
2429 * 2) Firmware via request-firmware interface (.bin file).
2431 if (ql2xfwloadbin
== 2)
2434 ql_log(ql_log_info
, vha
, 0x00a0,
2435 "Attempting to load firmware from flash.\n");
2437 if (qla82xx_fw_load_from_flash(ha
) == QLA_SUCCESS
) {
2438 ql_log(ql_log_info
, vha
, 0x00a1,
2439 "Firmware loaded successully from flash.\n");
2442 ql_log(ql_log_warn
, vha
, 0x0108,
2443 "Firmware load from flash failed.\n");
2447 ql_log(ql_log_info
, vha
, 0x00a2,
2448 "Attempting to load firmware from blob.\n");
2450 /* Load firmware blob. */
2451 blob
= ha
->hablob
= qla2x00_request_firmware(vha
);
2453 ql_log(ql_log_fatal
, vha
, 0x00a3,
2454 "Firmware image not preset.\n");
2455 goto fw_load_failed
;
2458 /* Validating firmware blob */
2459 if (qla82xx_validate_firmware_blob(vha
,
2460 QLA82XX_FLASH_ROMIMAGE
)) {
2461 /* Fallback to URI format */
2462 if (qla82xx_validate_firmware_blob(vha
,
2463 QLA82XX_UNIFIED_ROMIMAGE
)) {
2464 ql_log(ql_log_fatal
, vha
, 0x00a4,
2465 "No valid firmware image found.\n");
2466 return QLA_FUNCTION_FAILED
;
2470 if (qla82xx_fw_load_from_blob(ha
) == QLA_SUCCESS
) {
2471 ql_log(ql_log_info
, vha
, 0x00a5,
2472 "Firmware loaded successfully from binary blob.\n");
2475 ql_log(ql_log_fatal
, vha
, 0x00a6,
2476 "Firmware load failed for binary blob.\n");
2479 goto fw_load_failed
;
2484 return QLA_FUNCTION_FAILED
;
2488 qla82xx_start_firmware(scsi_qla_host_t
*vha
)
2492 struct qla_hw_data
*ha
= vha
->hw
;
2494 /* scrub dma mask expansion register */
2495 qla82xx_wr_32(ha
, CRB_DMA_SHIFT
, QLA82XX_DMA_SHIFT_VALUE
);
2497 /* Put both the PEG CMD and RCV PEG to default state
2498 * of 0 before resetting the hardware
2500 qla82xx_wr_32(ha
, CRB_CMDPEG_STATE
, 0);
2501 qla82xx_wr_32(ha
, CRB_RCVPEG_STATE
, 0);
2503 /* Overwrite stale initialization register values */
2504 qla82xx_wr_32(ha
, QLA82XX_PEG_HALT_STATUS1
, 0);
2505 qla82xx_wr_32(ha
, QLA82XX_PEG_HALT_STATUS2
, 0);
2507 if (qla82xx_load_fw(vha
) != QLA_SUCCESS
) {
2508 ql_log(ql_log_fatal
, vha
, 0x00a7,
2509 "Error trying to start fw.\n");
2510 return QLA_FUNCTION_FAILED
;
2513 /* Handshake with the card before we register the devices. */
2514 if (qla82xx_check_cmdpeg_state(ha
) != QLA_SUCCESS
) {
2515 ql_log(ql_log_fatal
, vha
, 0x00aa,
2516 "Error during card handshake.\n");
2517 return QLA_FUNCTION_FAILED
;
2520 /* Negotiated Link width */
2521 pcie_cap
= pci_find_capability(ha
->pdev
, PCI_CAP_ID_EXP
);
2522 pci_read_config_word(ha
->pdev
, pcie_cap
+ PCI_EXP_LNKSTA
, &lnk
);
2523 ha
->link_width
= (lnk
>> 4) & 0x3f;
2525 /* Synchronize with Receive peg */
2526 return qla82xx_check_rcvpeg_state(ha
);
2530 qla82xx_read_flash_data(scsi_qla_host_t
*vha
, uint32_t *dwptr
, uint32_t faddr
,
2535 struct qla_hw_data
*ha
= vha
->hw
;
2537 /* Dword reads to flash. */
2538 for (i
= 0; i
< length
/4; i
++, faddr
+= 4) {
2539 if (qla82xx_rom_fast_read(ha
, faddr
, &val
)) {
2540 ql_log(ql_log_warn
, vha
, 0x0106,
2541 "Do ROM fast read failed.\n");
2544 dwptr
[i
] = __constant_cpu_to_le32(val
);
2551 qla82xx_unprotect_flash(struct qla_hw_data
*ha
)
2555 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2557 ret
= ql82xx_rom_lock_d(ha
);
2559 ql_log(ql_log_warn
, vha
, 0xb014,
2560 "ROM Lock failed.\n");
2564 ret
= qla82xx_read_status_reg(ha
, &val
);
2566 goto done_unprotect
;
2568 val
&= ~(BLOCK_PROTECT_BITS
<< 2);
2569 ret
= qla82xx_write_status_reg(ha
, val
);
2571 val
|= (BLOCK_PROTECT_BITS
<< 2);
2572 qla82xx_write_status_reg(ha
, val
);
2575 if (qla82xx_write_disable_flash(ha
) != 0)
2576 ql_log(ql_log_warn
, vha
, 0xb015,
2577 "Write disable failed.\n");
2580 qla82xx_rom_unlock(ha
);
2585 qla82xx_protect_flash(struct qla_hw_data
*ha
)
2589 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2591 ret
= ql82xx_rom_lock_d(ha
);
2593 ql_log(ql_log_warn
, vha
, 0xb016,
2594 "ROM Lock failed.\n");
2598 ret
= qla82xx_read_status_reg(ha
, &val
);
2602 val
|= (BLOCK_PROTECT_BITS
<< 2);
2603 /* LOCK all sectors */
2604 ret
= qla82xx_write_status_reg(ha
, val
);
2606 ql_log(ql_log_warn
, vha
, 0xb017,
2607 "Write status register failed.\n");
2609 if (qla82xx_write_disable_flash(ha
) != 0)
2610 ql_log(ql_log_warn
, vha
, 0xb018,
2611 "Write disable failed.\n");
2613 qla82xx_rom_unlock(ha
);
2618 qla82xx_erase_sector(struct qla_hw_data
*ha
, int addr
)
2621 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2623 ret
= ql82xx_rom_lock_d(ha
);
2625 ql_log(ql_log_warn
, vha
, 0xb019,
2626 "ROM Lock failed.\n");
2630 qla82xx_flash_set_write_enable(ha
);
2631 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ADDRESS
, addr
);
2632 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 3);
2633 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_SE
);
2635 if (qla82xx_wait_rom_done(ha
)) {
2636 ql_log(ql_log_warn
, vha
, 0xb01a,
2637 "Error waiting for rom done.\n");
2641 ret
= qla82xx_flash_wait_write_finish(ha
);
2643 qla82xx_rom_unlock(ha
);
2648 * Address and length are byte address
2651 qla82xx_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2652 uint32_t offset
, uint32_t length
)
2654 scsi_block_requests(vha
->host
);
2655 qla82xx_read_flash_data(vha
, (uint32_t *)buf
, offset
, length
);
2656 scsi_unblock_requests(vha
->host
);
2661 qla82xx_write_flash_data(struct scsi_qla_host
*vha
, uint32_t *dwptr
,
2662 uint32_t faddr
, uint32_t dwords
)
2666 uint32_t sec_mask
, rest_addr
;
2667 dma_addr_t optrom_dma
;
2668 void *optrom
= NULL
;
2670 struct qla_hw_data
*ha
= vha
->hw
;
2674 /* Prepare burst-capable write on supported ISPs. */
2675 if (page_mode
&& !(faddr
& 0xfff) &&
2676 dwords
> OPTROM_BURST_DWORDS
) {
2677 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
2678 &optrom_dma
, GFP_KERNEL
);
2680 ql_log(ql_log_warn
, vha
, 0xb01b,
2681 "Unable to allocate memory "
2682 "for optron burst write (%x KB).\n",
2683 OPTROM_BURST_SIZE
/ 1024);
2687 rest_addr
= ha
->fdt_block_size
- 1;
2688 sec_mask
= ~rest_addr
;
2690 ret
= qla82xx_unprotect_flash(ha
);
2692 ql_log(ql_log_warn
, vha
, 0xb01c,
2693 "Unable to unprotect flash for update.\n");
2697 for (liter
= 0; liter
< dwords
; liter
++, faddr
+= 4, dwptr
++) {
2698 /* Are we at the beginning of a sector? */
2699 if ((faddr
& rest_addr
) == 0) {
2701 ret
= qla82xx_erase_sector(ha
, faddr
);
2703 ql_log(ql_log_warn
, vha
, 0xb01d,
2704 "Unable to erase sector: address=%x.\n",
2710 /* Go with burst-write. */
2711 if (optrom
&& (liter
+ OPTROM_BURST_DWORDS
) <= dwords
) {
2712 /* Copy data to DMA'ble buffer. */
2713 memcpy(optrom
, dwptr
, OPTROM_BURST_SIZE
);
2715 ret
= qla2x00_load_ram(vha
, optrom_dma
,
2716 (ha
->flash_data_off
| faddr
),
2717 OPTROM_BURST_DWORDS
);
2718 if (ret
!= QLA_SUCCESS
) {
2719 ql_log(ql_log_warn
, vha
, 0xb01e,
2720 "Unable to burst-write optrom segment "
2721 "(%x/%x/%llx).\n", ret
,
2722 (ha
->flash_data_off
| faddr
),
2723 (unsigned long long)optrom_dma
);
2724 ql_log(ql_log_warn
, vha
, 0xb01f,
2725 "Reverting to slow-write.\n");
2727 dma_free_coherent(&ha
->pdev
->dev
,
2728 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
2731 liter
+= OPTROM_BURST_DWORDS
- 1;
2732 faddr
+= OPTROM_BURST_DWORDS
- 1;
2733 dwptr
+= OPTROM_BURST_DWORDS
- 1;
2738 ret
= qla82xx_write_flash_dword(ha
, faddr
,
2739 cpu_to_le32(*dwptr
));
2741 ql_dbg(ql_dbg_p3p
, vha
, 0xb020,
2742 "Unable to program flash address=%x data=%x.\n",
2748 ret
= qla82xx_protect_flash(ha
);
2750 ql_log(ql_log_warn
, vha
, 0xb021,
2751 "Unable to protect flash after update.\n");
2754 dma_free_coherent(&ha
->pdev
->dev
,
2755 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
2760 qla82xx_write_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2761 uint32_t offset
, uint32_t length
)
2766 scsi_block_requests(vha
->host
);
2767 rval
= qla82xx_write_flash_data(vha
, (uint32_t *)buf
, offset
,
2769 scsi_unblock_requests(vha
->host
);
2771 /* Convert return ISP82xx to generic */
2773 rval
= QLA_FUNCTION_FAILED
;
2780 qla82xx_start_iocbs(scsi_qla_host_t
*vha
)
2782 struct qla_hw_data
*ha
= vha
->hw
;
2783 struct req_que
*req
= ha
->req_q_map
[0];
2784 struct device_reg_82xx __iomem
*reg
;
2787 /* Adjust ring index. */
2789 if (req
->ring_index
== req
->length
) {
2790 req
->ring_index
= 0;
2791 req
->ring_ptr
= req
->ring
;
2795 reg
= &ha
->iobase
->isp82
;
2796 dbval
= 0x04 | (ha
->portnum
<< 5);
2798 dbval
= dbval
| (req
->id
<< 8) | (req
->ring_index
<< 16);
2800 qla82xx_wr_32(ha
, ha
->nxdb_wr_ptr
, dbval
);
2802 WRT_REG_DWORD((unsigned long __iomem
*)ha
->nxdb_wr_ptr
, dbval
);
2804 while (RD_REG_DWORD(ha
->nxdb_rd_ptr
) != dbval
) {
2805 WRT_REG_DWORD((unsigned long __iomem
*)ha
->nxdb_wr_ptr
,
2812 void qla82xx_rom_lock_recovery(struct qla_hw_data
*ha
)
2814 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2816 if (qla82xx_rom_lock(ha
))
2817 /* Someone else is holding the lock. */
2818 ql_log(ql_log_info
, vha
, 0xb022,
2819 "Resetting rom_lock.\n");
2822 * Either we got the lock, or someone
2823 * else died while holding it.
2824 * In either case, unlock.
2826 qla82xx_rom_unlock(ha
);
2830 * qla82xx_device_bootstrap
2831 * Initialize device, set DEV_READY, start fw
2834 * IDC lock must be held upon entry
2841 qla82xx_device_bootstrap(scsi_qla_host_t
*vha
)
2843 int rval
= QLA_SUCCESS
;
2845 uint32_t old_count
, count
;
2846 struct qla_hw_data
*ha
= vha
->hw
;
2847 int need_reset
= 0, peg_stuck
= 1;
2849 need_reset
= qla82xx_need_reset(ha
);
2851 old_count
= qla82xx_rd_32(ha
, QLA82XX_PEG_ALIVE_COUNTER
);
2853 for (i
= 0; i
< 10; i
++) {
2854 timeout
= msleep_interruptible(200);
2856 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
2857 QLA82XX_DEV_FAILED
);
2858 return QLA_FUNCTION_FAILED
;
2861 count
= qla82xx_rd_32(ha
, QLA82XX_PEG_ALIVE_COUNTER
);
2862 if (count
!= old_count
)
2867 /* We are trying to perform a recovery here. */
2869 qla82xx_rom_lock_recovery(ha
);
2870 goto dev_initialize
;
2872 /* Start of day for this ha context. */
2874 /* Either we are the first or recovery in progress. */
2875 qla82xx_rom_lock_recovery(ha
);
2876 goto dev_initialize
;
2878 /* Firmware already running. */
2885 /* set to DEV_INITIALIZING */
2886 ql_log(ql_log_info
, vha
, 0x009e,
2887 "HW State: INITIALIZING.\n");
2888 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_INITIALIZING
);
2890 /* Driver that sets device state to initializating sets IDC version */
2891 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_IDC_VERSION
, QLA82XX_IDC_VERSION
);
2893 qla82xx_idc_unlock(ha
);
2894 rval
= qla82xx_start_firmware(vha
);
2895 qla82xx_idc_lock(ha
);
2897 if (rval
!= QLA_SUCCESS
) {
2898 ql_log(ql_log_fatal
, vha
, 0x00ad,
2899 "HW State: FAILED.\n");
2900 qla82xx_clear_drv_active(ha
);
2901 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_FAILED
);
2906 ql_log(ql_log_info
, vha
, 0x00ae,
2907 "HW State: READY.\n");
2908 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_READY
);
2914 * qla82xx_need_qsnt_handler
2915 * Code to start quiescence sequence
2918 * IDC lock must be held upon entry
2924 qla82xx_need_qsnt_handler(scsi_qla_host_t
*vha
)
2926 struct qla_hw_data
*ha
= vha
->hw
;
2927 uint32_t dev_state
, drv_state
, drv_active
;
2928 unsigned long reset_timeout
;
2930 if (vha
->flags
.online
) {
2931 /*Block any further I/O and wait for pending cmnds to complete*/
2932 qla82xx_quiescent_state_cleanup(vha
);
2935 /* Set the quiescence ready bit */
2936 qla82xx_set_qsnt_ready(ha
);
2938 /*wait for 30 secs for other functions to ack */
2939 reset_timeout
= jiffies
+ (30 * HZ
);
2941 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2942 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2943 /* Its 2 that is written when qsnt is acked, moving one bit */
2944 drv_active
= drv_active
<< 0x01;
2946 while (drv_state
!= drv_active
) {
2948 if (time_after_eq(jiffies
, reset_timeout
)) {
2949 /* quiescence timeout, other functions didn't ack
2950 * changing the state to DEV_READY
2952 ql_log(ql_log_info
, vha
, 0xb023,
2953 "%s : QUIESCENT TIMEOUT.\n", QLA2XXX_DRIVER_NAME
);
2954 ql_log(ql_log_info
, vha
, 0xb024,
2955 "DRV_ACTIVE:%d DRV_STATE:%d.\n",
2956 drv_active
, drv_state
);
2957 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
2959 ql_log(ql_log_info
, vha
, 0xb025,
2960 "HW State: DEV_READY.\n");
2961 qla82xx_idc_unlock(ha
);
2962 qla2x00_perform_loop_resync(vha
);
2963 qla82xx_idc_lock(ha
);
2965 qla82xx_clear_qsnt_ready(vha
);
2969 qla82xx_idc_unlock(ha
);
2971 qla82xx_idc_lock(ha
);
2973 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2974 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2975 drv_active
= drv_active
<< 0x01;
2977 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
2978 /* everyone acked so set the state to DEV_QUIESCENCE */
2979 if (dev_state
== QLA82XX_DEV_NEED_QUIESCENT
) {
2980 ql_log(ql_log_info
, vha
, 0xb026,
2981 "HW State: DEV_QUIESCENT.\n");
2982 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_QUIESCENT
);
2987 * qla82xx_wait_for_state_change
2988 * Wait for device state to change from given current state
2991 * IDC lock must not be held upon entry
2994 * Changed device state.
2997 qla82xx_wait_for_state_change(scsi_qla_host_t
*vha
, uint32_t curr_state
)
2999 struct qla_hw_data
*ha
= vha
->hw
;
3004 qla82xx_idc_lock(ha
);
3005 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3006 qla82xx_idc_unlock(ha
);
3007 } while (dev_state
== curr_state
);
3013 qla82xx_dev_failed_handler(scsi_qla_host_t
*vha
)
3015 struct qla_hw_data
*ha
= vha
->hw
;
3017 /* Disable the board */
3018 ql_log(ql_log_fatal
, vha
, 0x00b8,
3019 "Disabling the board.\n");
3021 qla82xx_idc_lock(ha
);
3022 qla82xx_clear_drv_active(ha
);
3023 qla82xx_idc_unlock(ha
);
3025 /* Set DEV_FAILED flag to disable timer */
3026 vha
->device_flags
|= DFLG_DEV_FAILED
;
3027 qla2x00_abort_all_cmds(vha
, DID_NO_CONNECT
<< 16);
3028 qla2x00_mark_all_devices_lost(vha
, 0);
3029 vha
->flags
.online
= 0;
3030 vha
->flags
.init_done
= 0;
3034 * qla82xx_need_reset_handler
3035 * Code to start reset sequence
3038 * IDC lock must be held upon entry
3045 qla82xx_need_reset_handler(scsi_qla_host_t
*vha
)
3047 uint32_t dev_state
, drv_state
, drv_active
;
3048 uint32_t active_mask
= 0;
3049 unsigned long reset_timeout
;
3050 struct qla_hw_data
*ha
= vha
->hw
;
3051 struct req_que
*req
= ha
->req_q_map
[0];
3053 if (vha
->flags
.online
) {
3054 qla82xx_idc_unlock(ha
);
3055 qla2x00_abort_isp_cleanup(vha
);
3056 ha
->isp_ops
->get_flash_version(vha
, req
->ring
);
3057 ha
->isp_ops
->nvram_config(vha
);
3058 qla82xx_idc_lock(ha
);
3061 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
3062 if (!ha
->flags
.isp82xx_reset_owner
) {
3063 ql_dbg(ql_dbg_p3p
, vha
, 0xb028,
3064 "reset_acknowledged by 0x%x\n", ha
->portnum
);
3065 qla82xx_set_rst_ready(ha
);
3067 active_mask
= ~(QLA82XX_DRV_ACTIVE
<< (ha
->portnum
* 4));
3068 drv_active
&= active_mask
;
3069 ql_dbg(ql_dbg_p3p
, vha
, 0xb029,
3070 "active_mask: 0x%08x\n", active_mask
);
3073 /* wait for 10 seconds for reset ack from all functions */
3074 reset_timeout
= jiffies
+ (ha
->nx_reset_timeout
* HZ
);
3076 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
3077 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
3078 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3080 ql_dbg(ql_dbg_p3p
, vha
, 0xb02a,
3081 "drv_state: 0x%08x, drv_active: 0x%08x, "
3082 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3083 drv_state
, drv_active
, dev_state
, active_mask
);
3085 while (drv_state
!= drv_active
&&
3086 dev_state
!= QLA82XX_DEV_INITIALIZING
) {
3087 if (time_after_eq(jiffies
, reset_timeout
)) {
3088 ql_log(ql_log_warn
, vha
, 0x00b5,
3089 "Reset timeout.\n");
3092 qla82xx_idc_unlock(ha
);
3094 qla82xx_idc_lock(ha
);
3095 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
3096 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
3097 if (ha
->flags
.isp82xx_reset_owner
)
3098 drv_active
&= active_mask
;
3099 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3102 ql_dbg(ql_dbg_p3p
, vha
, 0xb02b,
3103 "drv_state: 0x%08x, drv_active: 0x%08x, "
3104 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3105 drv_state
, drv_active
, dev_state
, active_mask
);
3107 ql_log(ql_log_info
, vha
, 0x00b6,
3108 "Device state is 0x%x = %s.\n",
3110 dev_state
< MAX_STATES
? qdev_state(dev_state
) : "Unknown");
3112 /* Force to DEV_COLD unless someone else is starting a reset */
3113 if (dev_state
!= QLA82XX_DEV_INITIALIZING
&&
3114 dev_state
!= QLA82XX_DEV_COLD
) {
3115 ql_log(ql_log_info
, vha
, 0x00b7,
3116 "HW State: COLD/RE-INIT.\n");
3117 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_COLD
);
3119 if (qla82xx_md_collect(vha
))
3120 ql_log(ql_log_warn
, vha
, 0xb02c,
3121 "Not able to collect minidump.\n");
3123 ql_log(ql_log_warn
, vha
, 0xb04f,
3124 "Minidump disabled.\n");
3129 qla82xx_check_md_needed(scsi_qla_host_t
*vha
)
3131 struct qla_hw_data
*ha
= vha
->hw
;
3132 uint16_t fw_major_version
, fw_minor_version
, fw_subminor_version
;
3133 int rval
= QLA_SUCCESS
;
3135 fw_major_version
= ha
->fw_major_version
;
3136 fw_minor_version
= ha
->fw_minor_version
;
3137 fw_subminor_version
= ha
->fw_subminor_version
;
3139 rval
= qla2x00_get_fw_version(vha
, &ha
->fw_major_version
,
3140 &ha
->fw_minor_version
, &ha
->fw_subminor_version
,
3141 &ha
->fw_attributes
, &ha
->fw_memory_size
,
3142 ha
->mpi_version
, &ha
->mpi_capabilities
,
3145 if (rval
!= QLA_SUCCESS
)
3149 if (!ha
->fw_dumped
) {
3150 if (fw_major_version
!= ha
->fw_major_version
||
3151 fw_minor_version
!= ha
->fw_minor_version
||
3152 fw_subminor_version
!= ha
->fw_subminor_version
) {
3154 ql_log(ql_log_info
, vha
, 0xb02d,
3155 "Firmware version differs "
3156 "Previous version: %d:%d:%d - "
3157 "New version: %d:%d:%d\n",
3158 ha
->fw_major_version
,
3159 ha
->fw_minor_version
,
3160 ha
->fw_subminor_version
,
3161 fw_major_version
, fw_minor_version
,
3162 fw_subminor_version
);
3163 /* Release MiniDump resources */
3164 qla82xx_md_free(vha
);
3165 /* ALlocate MiniDump resources */
3166 qla82xx_md_prep(vha
);
3169 ql_log(ql_log_info
, vha
, 0xb02e,
3170 "Firmware dump available to retrieve\n");
3177 qla82xx_check_fw_alive(scsi_qla_host_t
*vha
)
3179 uint32_t fw_heartbeat_counter
;
3182 fw_heartbeat_counter
= qla82xx_rd_32(vha
->hw
,
3183 QLA82XX_PEG_ALIVE_COUNTER
);
3184 /* all 0xff, assume AER/EEH in progress, ignore */
3185 if (fw_heartbeat_counter
== 0xffffffff) {
3186 ql_dbg(ql_dbg_timer
, vha
, 0x6003,
3187 "FW heartbeat counter is 0xffffffff, "
3188 "returning status=%d.\n", status
);
3191 if (vha
->fw_heartbeat_counter
== fw_heartbeat_counter
) {
3192 vha
->seconds_since_last_heartbeat
++;
3193 /* FW not alive after 2 seconds */
3194 if (vha
->seconds_since_last_heartbeat
== 2) {
3195 vha
->seconds_since_last_heartbeat
= 0;
3199 vha
->seconds_since_last_heartbeat
= 0;
3200 vha
->fw_heartbeat_counter
= fw_heartbeat_counter
;
3202 ql_dbg(ql_dbg_timer
, vha
, 0x6004,
3203 "Returning status=%d.\n", status
);
3208 * qla82xx_device_state_handler
3209 * Main state handler
3212 * IDC lock must be held upon entry
3219 qla82xx_device_state_handler(scsi_qla_host_t
*vha
)
3222 uint32_t old_dev_state
;
3223 int rval
= QLA_SUCCESS
;
3224 unsigned long dev_init_timeout
;
3225 struct qla_hw_data
*ha
= vha
->hw
;
3228 qla82xx_idc_lock(ha
);
3229 if (!vha
->flags
.init_done
)
3230 qla82xx_set_drv_active(vha
);
3232 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3233 old_dev_state
= dev_state
;
3234 ql_log(ql_log_info
, vha
, 0x009b,
3235 "Device state is 0x%x = %s.\n",
3237 dev_state
< MAX_STATES
? qdev_state(dev_state
) : "Unknown");
3239 /* wait for 30 seconds for device to go ready */
3240 dev_init_timeout
= jiffies
+ (ha
->nx_dev_init_timeout
* HZ
);
3244 if (time_after_eq(jiffies
, dev_init_timeout
)) {
3245 ql_log(ql_log_fatal
, vha
, 0x009c,
3246 "Device init failed.\n");
3247 rval
= QLA_FUNCTION_FAILED
;
3250 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3251 if (old_dev_state
!= dev_state
) {
3253 old_dev_state
= dev_state
;
3255 if (loopcount
< 5) {
3256 ql_log(ql_log_info
, vha
, 0x009d,
3257 "Device state is 0x%x = %s.\n",
3259 dev_state
< MAX_STATES
? qdev_state(dev_state
) :
3263 switch (dev_state
) {
3264 case QLA82XX_DEV_READY
:
3265 ha
->flags
.isp82xx_reset_owner
= 0;
3267 case QLA82XX_DEV_COLD
:
3268 rval
= qla82xx_device_bootstrap(vha
);
3270 case QLA82XX_DEV_INITIALIZING
:
3271 qla82xx_idc_unlock(ha
);
3273 qla82xx_idc_lock(ha
);
3275 case QLA82XX_DEV_NEED_RESET
:
3276 if (!ql2xdontresethba
)
3277 qla82xx_need_reset_handler(vha
);
3279 qla82xx_idc_unlock(ha
);
3281 qla82xx_idc_lock(ha
);
3283 dev_init_timeout
= jiffies
+
3284 (ha
->nx_dev_init_timeout
* HZ
);
3286 case QLA82XX_DEV_NEED_QUIESCENT
:
3287 qla82xx_need_qsnt_handler(vha
);
3288 /* Reset timeout value after quiescence handler */
3289 dev_init_timeout
= jiffies
+ (ha
->nx_dev_init_timeout\
3292 case QLA82XX_DEV_QUIESCENT
:
3293 /* Owner will exit and other will wait for the state
3296 if (ha
->flags
.quiesce_owner
)
3299 qla82xx_idc_unlock(ha
);
3301 qla82xx_idc_lock(ha
);
3303 /* Reset timeout value after quiescence handler */
3304 dev_init_timeout
= jiffies
+ (ha
->nx_dev_init_timeout\
3307 case QLA82XX_DEV_FAILED
:
3308 qla82xx_dev_failed_handler(vha
);
3309 rval
= QLA_FUNCTION_FAILED
;
3312 qla82xx_idc_unlock(ha
);
3314 qla82xx_idc_lock(ha
);
3319 qla82xx_idc_unlock(ha
);
3323 void qla82xx_clear_pending_mbx(scsi_qla_host_t
*vha
)
3325 struct qla_hw_data
*ha
= vha
->hw
;
3327 if (ha
->flags
.mbox_busy
) {
3328 ha
->flags
.mbox_int
= 1;
3329 ha
->flags
.mbox_busy
= 0;
3330 ql_log(ql_log_warn
, vha
, 0x6010,
3331 "Doing premature completion of mbx command.\n");
3332 if (test_bit(MBX_INTR_WAIT
, &ha
->mbx_cmd_flags
))
3333 complete(&ha
->mbx_intr_comp
);
3337 void qla82xx_watchdog(scsi_qla_host_t
*vha
)
3339 uint32_t dev_state
, halt_status
;
3340 struct qla_hw_data
*ha
= vha
->hw
;
3342 /* don't poll if reset is going on */
3343 if (!ha
->flags
.isp82xx_reset_hdlr_active
) {
3344 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3345 if (dev_state
== QLA82XX_DEV_NEED_RESET
&&
3346 !test_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
)) {
3347 ql_log(ql_log_warn
, vha
, 0x6001,
3348 "Adapter reset needed.\n");
3349 set_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
);
3350 qla2xxx_wake_dpc(vha
);
3351 } else if (dev_state
== QLA82XX_DEV_NEED_QUIESCENT
&&
3352 !test_bit(ISP_QUIESCE_NEEDED
, &vha
->dpc_flags
)) {
3353 ql_log(ql_log_warn
, vha
, 0x6002,
3354 "Quiescent needed.\n");
3355 set_bit(ISP_QUIESCE_NEEDED
, &vha
->dpc_flags
);
3356 qla2xxx_wake_dpc(vha
);
3358 if (qla82xx_check_fw_alive(vha
)) {
3359 ql_dbg(ql_dbg_timer
, vha
, 0x6011,
3360 "disabling pause transmit on port 0 & 1.\n");
3361 qla82xx_wr_32(ha
, QLA82XX_CRB_NIU
+ 0x98,
3362 CRB_NIU_XG_PAUSE_CTL_P0
|CRB_NIU_XG_PAUSE_CTL_P1
);
3363 halt_status
= qla82xx_rd_32(ha
,
3364 QLA82XX_PEG_HALT_STATUS1
);
3365 ql_log(ql_log_info
, vha
, 0x6005,
3366 "dumping hw/fw registers:.\n "
3367 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3368 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3369 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3370 " PEG_NET_4_PC: 0x%x.\n", halt_status
,
3371 qla82xx_rd_32(ha
, QLA82XX_PEG_HALT_STATUS2
),
3373 QLA82XX_CRB_PEG_NET_0
+ 0x3c),
3375 QLA82XX_CRB_PEG_NET_1
+ 0x3c),
3377 QLA82XX_CRB_PEG_NET_2
+ 0x3c),
3379 QLA82XX_CRB_PEG_NET_3
+ 0x3c),
3381 QLA82XX_CRB_PEG_NET_4
+ 0x3c));
3382 if (((halt_status
& 0x1fffff00) >> 8) == 0x67)
3383 ql_log(ql_log_warn
, vha
, 0xb052,
3384 "Firmware aborted with "
3385 "error code 0x00006700. Device is "
3387 if (halt_status
& HALT_STATUS_UNRECOVERABLE
) {
3388 set_bit(ISP_UNRECOVERABLE
,
3391 ql_log(ql_log_info
, vha
, 0x6006,
3392 "Detect abort needed.\n");
3393 set_bit(ISP_ABORT_NEEDED
,
3396 qla2xxx_wake_dpc(vha
);
3397 ha
->flags
.isp82xx_fw_hung
= 1;
3398 ql_log(ql_log_warn
, vha
, 0x6007, "Firmware hung.\n");
3399 qla82xx_clear_pending_mbx(vha
);
3405 int qla82xx_load_risc(scsi_qla_host_t
*vha
, uint32_t *srisc_addr
)
3408 rval
= qla82xx_device_state_handler(vha
);
3413 qla82xx_set_reset_owner(scsi_qla_host_t
*vha
)
3415 struct qla_hw_data
*ha
= vha
->hw
;
3418 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3419 if (dev_state
== QLA82XX_DEV_READY
) {
3420 ql_log(ql_log_info
, vha
, 0xb02f,
3421 "HW State: NEED RESET\n");
3422 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
3423 QLA82XX_DEV_NEED_RESET
);
3424 ha
->flags
.isp82xx_reset_owner
= 1;
3425 ql_dbg(ql_dbg_p3p
, vha
, 0xb030,
3426 "reset_owner is 0x%x\n", ha
->portnum
);
3428 ql_log(ql_log_info
, vha
, 0xb031,
3429 "Device state is 0x%x = %s.\n",
3431 dev_state
< MAX_STATES
? qdev_state(dev_state
) : "Unknown");
3436 * Resets ISP and aborts all outstanding commands.
3439 * ha = adapter block pointer.
3445 qla82xx_abort_isp(scsi_qla_host_t
*vha
)
3448 struct qla_hw_data
*ha
= vha
->hw
;
3450 if (vha
->device_flags
& DFLG_DEV_FAILED
) {
3451 ql_log(ql_log_warn
, vha
, 0x8024,
3452 "Device in failed state, exiting.\n");
3455 ha
->flags
.isp82xx_reset_hdlr_active
= 1;
3457 qla82xx_idc_lock(ha
);
3458 qla82xx_set_reset_owner(vha
);
3459 qla82xx_idc_unlock(ha
);
3461 rval
= qla82xx_device_state_handler(vha
);
3463 qla82xx_idc_lock(ha
);
3464 qla82xx_clear_rst_ready(ha
);
3465 qla82xx_idc_unlock(ha
);
3467 if (rval
== QLA_SUCCESS
) {
3468 ha
->flags
.isp82xx_fw_hung
= 0;
3469 ha
->flags
.isp82xx_reset_hdlr_active
= 0;
3470 qla82xx_restart_isp(vha
);
3474 vha
->flags
.online
= 1;
3475 if (test_bit(ISP_ABORT_RETRY
, &vha
->dpc_flags
)) {
3476 if (ha
->isp_abort_cnt
== 0) {
3477 ql_log(ql_log_warn
, vha
, 0x8027,
3478 "ISP error recover failed - board "
3481 * The next call disables the board
3484 ha
->isp_ops
->reset_adapter(vha
);
3485 vha
->flags
.online
= 0;
3486 clear_bit(ISP_ABORT_RETRY
,
3489 } else { /* schedule another ISP abort */
3490 ha
->isp_abort_cnt
--;
3491 ql_log(ql_log_warn
, vha
, 0x8036,
3492 "ISP abort - retry remaining %d.\n",
3494 rval
= QLA_FUNCTION_FAILED
;
3497 ha
->isp_abort_cnt
= MAX_RETRIES_OF_ISP_ABORT
;
3498 ql_dbg(ql_dbg_taskm
, vha
, 0x8029,
3499 "ISP error recovery - retrying (%d) more times.\n",
3501 set_bit(ISP_ABORT_RETRY
, &vha
->dpc_flags
);
3502 rval
= QLA_FUNCTION_FAILED
;
3509 * qla82xx_fcoe_ctx_reset
3510 * Perform a quick reset and aborts all outstanding commands.
3511 * This will only perform an FCoE context reset and avoids a full blown
3515 * ha = adapter block pointer.
3516 * is_reset_path = flag for identifying the reset path.
3521 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t
*vha
)
3523 int rval
= QLA_FUNCTION_FAILED
;
3525 if (vha
->flags
.online
) {
3526 /* Abort all outstanding commands, so as to be requeued later */
3527 qla2x00_abort_isp_cleanup(vha
);
3530 /* Stop currently executing firmware.
3531 * This will destroy existing FCoE context at the F/W end.
3533 qla2x00_try_to_stop_firmware(vha
);
3535 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3536 rval
= qla82xx_restart_isp(vha
);
3542 * qla2x00_wait_for_fcoe_ctx_reset
3543 * Wait till the FCoE context is reset.
3546 * Does context switching here.
3547 * Release SPIN_LOCK (if any) before calling this routine.
3550 * Success (fcoe_ctx reset is done) : 0
3551 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3553 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t
*vha
)
3555 int status
= QLA_FUNCTION_FAILED
;
3556 unsigned long wait_reset
;
3558 wait_reset
= jiffies
+ (MAX_LOOP_TIMEOUT
* HZ
);
3559 while ((test_bit(FCOE_CTX_RESET_NEEDED
, &vha
->dpc_flags
) ||
3560 test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
))
3561 && time_before(jiffies
, wait_reset
)) {
3563 set_current_state(TASK_UNINTERRUPTIBLE
);
3564 schedule_timeout(HZ
);
3566 if (!test_bit(FCOE_CTX_RESET_NEEDED
, &vha
->dpc_flags
) &&
3567 !test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
)) {
3568 status
= QLA_SUCCESS
;
3572 ql_dbg(ql_dbg_p3p
, vha
, 0xb027,
3573 "%s: status=%d.\n", __func__
, status
);
3579 qla82xx_chip_reset_cleanup(scsi_qla_host_t
*vha
)
3582 unsigned long flags
;
3583 struct qla_hw_data
*ha
= vha
->hw
;
3585 /* Check if 82XX firmware is alive or not
3586 * We may have arrived here from NEED_RESET
3589 if (!ha
->flags
.isp82xx_fw_hung
) {
3590 for (i
= 0; i
< 2; i
++) {
3592 if (qla82xx_check_fw_alive(vha
)) {
3593 ha
->flags
.isp82xx_fw_hung
= 1;
3594 qla82xx_clear_pending_mbx(vha
);
3599 ql_dbg(ql_dbg_init
, vha
, 0x00b0,
3600 "Entered %s fw_hung=%d.\n",
3601 __func__
, ha
->flags
.isp82xx_fw_hung
);
3603 /* Abort all commands gracefully if fw NOT hung */
3604 if (!ha
->flags
.isp82xx_fw_hung
) {
3607 struct req_que
*req
;
3609 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
3610 for (que
= 0; que
< ha
->max_req_queues
; que
++) {
3611 req
= ha
->req_q_map
[que
];
3614 for (cnt
= 1; cnt
< MAX_OUTSTANDING_COMMANDS
; cnt
++) {
3615 sp
= req
->outstanding_cmds
[cnt
];
3618 (sp
->flags
& SRB_FCP_CMND_DMA_VALID
)) {
3619 spin_unlock_irqrestore(
3620 &ha
->hardware_lock
, flags
);
3621 if (ha
->isp_ops
->abort_command(sp
)) {
3622 ql_log(ql_log_info
, vha
,
3624 "mbx abort failed.\n");
3626 ql_log(ql_log_info
, vha
,
3628 "mbx abort success.\n");
3630 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
3635 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
3637 /* Wait for pending cmds (physical and virtual) to complete */
3638 if (!qla2x00_eh_wait_for_pending_commands(vha
, 0, 0,
3639 WAIT_HOST
) == QLA_SUCCESS
) {
3640 ql_dbg(ql_dbg_init
, vha
, 0x00b3,
3642 "pending commands.\n");
3647 /* Minidump related functions */
3649 qla82xx_md_rw_32(struct qla_hw_data
*ha
, uint32_t off
, u32 data
, uint8_t flag
)
3651 uint32_t off_value
, rval
= 0;
3653 WRT_REG_DWORD((void *)(CRB_WINDOW_2M
+ ha
->nx_pcibase
),
3654 (off
& 0xFFFF0000));
3656 /* Read back value to make sure write has gone through */
3657 RD_REG_DWORD((void *)(CRB_WINDOW_2M
+ ha
->nx_pcibase
));
3658 off_value
= (off
& 0x0000FFFF);
3661 WRT_REG_DWORD((void *)
3662 (off_value
+ CRB_INDIRECT_2M
+ ha
->nx_pcibase
),
3665 rval
= RD_REG_DWORD((void *)
3666 (off_value
+ CRB_INDIRECT_2M
+ ha
->nx_pcibase
));
3672 qla82xx_minidump_process_control(scsi_qla_host_t
*vha
,
3673 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3675 struct qla_hw_data
*ha
= vha
->hw
;
3676 struct qla82xx_md_entry_crb
*crb_entry
;
3677 uint32_t read_value
, opcode
, poll_time
;
3678 uint32_t addr
, index
, crb_addr
;
3679 unsigned long wtime
;
3680 struct qla82xx_md_template_hdr
*tmplt_hdr
;
3681 uint32_t rval
= QLA_SUCCESS
;
3684 tmplt_hdr
= (struct qla82xx_md_template_hdr
*)ha
->md_tmplt_hdr
;
3685 crb_entry
= (struct qla82xx_md_entry_crb
*)entry_hdr
;
3686 crb_addr
= crb_entry
->addr
;
3688 for (i
= 0; i
< crb_entry
->op_count
; i
++) {
3689 opcode
= crb_entry
->crb_ctrl
.opcode
;
3690 if (opcode
& QLA82XX_DBG_OPCODE_WR
) {
3691 qla82xx_md_rw_32(ha
, crb_addr
,
3692 crb_entry
->value_1
, 1);
3693 opcode
&= ~QLA82XX_DBG_OPCODE_WR
;
3696 if (opcode
& QLA82XX_DBG_OPCODE_RW
) {
3697 read_value
= qla82xx_md_rw_32(ha
, crb_addr
, 0, 0);
3698 qla82xx_md_rw_32(ha
, crb_addr
, read_value
, 1);
3699 opcode
&= ~QLA82XX_DBG_OPCODE_RW
;
3702 if (opcode
& QLA82XX_DBG_OPCODE_AND
) {
3703 read_value
= qla82xx_md_rw_32(ha
, crb_addr
, 0, 0);
3704 read_value
&= crb_entry
->value_2
;
3705 opcode
&= ~QLA82XX_DBG_OPCODE_AND
;
3706 if (opcode
& QLA82XX_DBG_OPCODE_OR
) {
3707 read_value
|= crb_entry
->value_3
;
3708 opcode
&= ~QLA82XX_DBG_OPCODE_OR
;
3710 qla82xx_md_rw_32(ha
, crb_addr
, read_value
, 1);
3713 if (opcode
& QLA82XX_DBG_OPCODE_OR
) {
3714 read_value
= qla82xx_md_rw_32(ha
, crb_addr
, 0, 0);
3715 read_value
|= crb_entry
->value_3
;
3716 qla82xx_md_rw_32(ha
, crb_addr
, read_value
, 1);
3717 opcode
&= ~QLA82XX_DBG_OPCODE_OR
;
3720 if (opcode
& QLA82XX_DBG_OPCODE_POLL
) {
3721 poll_time
= crb_entry
->crb_strd
.poll_timeout
;
3722 wtime
= jiffies
+ poll_time
;
3723 read_value
= qla82xx_md_rw_32(ha
, crb_addr
, 0, 0);
3726 if ((read_value
& crb_entry
->value_2
)
3727 == crb_entry
->value_1
)
3729 else if (time_after_eq(jiffies
, wtime
)) {
3730 /* capturing dump failed */
3731 rval
= QLA_FUNCTION_FAILED
;
3734 read_value
= qla82xx_md_rw_32(ha
,
3737 opcode
&= ~QLA82XX_DBG_OPCODE_POLL
;
3740 if (opcode
& QLA82XX_DBG_OPCODE_RDSTATE
) {
3741 if (crb_entry
->crb_strd
.state_index_a
) {
3742 index
= crb_entry
->crb_strd
.state_index_a
;
3743 addr
= tmplt_hdr
->saved_state_array
[index
];
3747 read_value
= qla82xx_md_rw_32(ha
, addr
, 0, 0);
3748 index
= crb_entry
->crb_ctrl
.state_index_v
;
3749 tmplt_hdr
->saved_state_array
[index
] = read_value
;
3750 opcode
&= ~QLA82XX_DBG_OPCODE_RDSTATE
;
3753 if (opcode
& QLA82XX_DBG_OPCODE_WRSTATE
) {
3754 if (crb_entry
->crb_strd
.state_index_a
) {
3755 index
= crb_entry
->crb_strd
.state_index_a
;
3756 addr
= tmplt_hdr
->saved_state_array
[index
];
3760 if (crb_entry
->crb_ctrl
.state_index_v
) {
3761 index
= crb_entry
->crb_ctrl
.state_index_v
;
3763 tmplt_hdr
->saved_state_array
[index
];
3765 read_value
= crb_entry
->value_1
;
3767 qla82xx_md_rw_32(ha
, addr
, read_value
, 1);
3768 opcode
&= ~QLA82XX_DBG_OPCODE_WRSTATE
;
3771 if (opcode
& QLA82XX_DBG_OPCODE_MDSTATE
) {
3772 index
= crb_entry
->crb_ctrl
.state_index_v
;
3773 read_value
= tmplt_hdr
->saved_state_array
[index
];
3774 read_value
<<= crb_entry
->crb_ctrl
.shl
;
3775 read_value
>>= crb_entry
->crb_ctrl
.shr
;
3776 if (crb_entry
->value_2
)
3777 read_value
&= crb_entry
->value_2
;
3778 read_value
|= crb_entry
->value_3
;
3779 read_value
+= crb_entry
->value_1
;
3780 tmplt_hdr
->saved_state_array
[index
] = read_value
;
3781 opcode
&= ~QLA82XX_DBG_OPCODE_MDSTATE
;
3783 crb_addr
+= crb_entry
->crb_strd
.addr_stride
;
3789 qla82xx_minidump_process_rdocm(scsi_qla_host_t
*vha
,
3790 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3792 struct qla_hw_data
*ha
= vha
->hw
;
3793 uint32_t r_addr
, r_stride
, loop_cnt
, i
, r_value
;
3794 struct qla82xx_md_entry_rdocm
*ocm_hdr
;
3795 uint32_t *data_ptr
= *d_ptr
;
3797 ocm_hdr
= (struct qla82xx_md_entry_rdocm
*)entry_hdr
;
3798 r_addr
= ocm_hdr
->read_addr
;
3799 r_stride
= ocm_hdr
->read_addr_stride
;
3800 loop_cnt
= ocm_hdr
->op_count
;
3802 for (i
= 0; i
< loop_cnt
; i
++) {
3803 r_value
= RD_REG_DWORD((void *)(r_addr
+ ha
->nx_pcibase
));
3804 *data_ptr
++ = cpu_to_le32(r_value
);
3811 qla82xx_minidump_process_rdmux(scsi_qla_host_t
*vha
,
3812 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3814 struct qla_hw_data
*ha
= vha
->hw
;
3815 uint32_t r_addr
, s_stride
, s_addr
, s_value
, loop_cnt
, i
, r_value
;
3816 struct qla82xx_md_entry_mux
*mux_hdr
;
3817 uint32_t *data_ptr
= *d_ptr
;
3819 mux_hdr
= (struct qla82xx_md_entry_mux
*)entry_hdr
;
3820 r_addr
= mux_hdr
->read_addr
;
3821 s_addr
= mux_hdr
->select_addr
;
3822 s_stride
= mux_hdr
->select_value_stride
;
3823 s_value
= mux_hdr
->select_value
;
3824 loop_cnt
= mux_hdr
->op_count
;
3826 for (i
= 0; i
< loop_cnt
; i
++) {
3827 qla82xx_md_rw_32(ha
, s_addr
, s_value
, 1);
3828 r_value
= qla82xx_md_rw_32(ha
, r_addr
, 0, 0);
3829 *data_ptr
++ = cpu_to_le32(s_value
);
3830 *data_ptr
++ = cpu_to_le32(r_value
);
3831 s_value
+= s_stride
;
3837 qla82xx_minidump_process_rdcrb(scsi_qla_host_t
*vha
,
3838 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3840 struct qla_hw_data
*ha
= vha
->hw
;
3841 uint32_t r_addr
, r_stride
, loop_cnt
, i
, r_value
;
3842 struct qla82xx_md_entry_crb
*crb_hdr
;
3843 uint32_t *data_ptr
= *d_ptr
;
3845 crb_hdr
= (struct qla82xx_md_entry_crb
*)entry_hdr
;
3846 r_addr
= crb_hdr
->addr
;
3847 r_stride
= crb_hdr
->crb_strd
.addr_stride
;
3848 loop_cnt
= crb_hdr
->op_count
;
3850 for (i
= 0; i
< loop_cnt
; i
++) {
3851 r_value
= qla82xx_md_rw_32(ha
, r_addr
, 0, 0);
3852 *data_ptr
++ = cpu_to_le32(r_addr
);
3853 *data_ptr
++ = cpu_to_le32(r_value
);
3860 qla82xx_minidump_process_l2tag(scsi_qla_host_t
*vha
,
3861 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3863 struct qla_hw_data
*ha
= vha
->hw
;
3864 uint32_t addr
, r_addr
, c_addr
, t_r_addr
;
3865 uint32_t i
, k
, loop_count
, t_value
, r_cnt
, r_value
;
3866 unsigned long p_wait
, w_time
, p_mask
;
3867 uint32_t c_value_w
, c_value_r
;
3868 struct qla82xx_md_entry_cache
*cache_hdr
;
3869 int rval
= QLA_FUNCTION_FAILED
;
3870 uint32_t *data_ptr
= *d_ptr
;
3872 cache_hdr
= (struct qla82xx_md_entry_cache
*)entry_hdr
;
3873 loop_count
= cache_hdr
->op_count
;
3874 r_addr
= cache_hdr
->read_addr
;
3875 c_addr
= cache_hdr
->control_addr
;
3876 c_value_w
= cache_hdr
->cache_ctrl
.write_value
;
3878 t_r_addr
= cache_hdr
->tag_reg_addr
;
3879 t_value
= cache_hdr
->addr_ctrl
.init_tag_value
;
3880 r_cnt
= cache_hdr
->read_ctrl
.read_addr_cnt
;
3881 p_wait
= cache_hdr
->cache_ctrl
.poll_wait
;
3882 p_mask
= cache_hdr
->cache_ctrl
.poll_mask
;
3884 for (i
= 0; i
< loop_count
; i
++) {
3885 qla82xx_md_rw_32(ha
, t_r_addr
, t_value
, 1);
3887 qla82xx_md_rw_32(ha
, c_addr
, c_value_w
, 1);
3890 w_time
= jiffies
+ p_wait
;
3892 c_value_r
= qla82xx_md_rw_32(ha
, c_addr
, 0, 0);
3893 if ((c_value_r
& p_mask
) == 0)
3895 else if (time_after_eq(jiffies
, w_time
)) {
3896 /* capturing dump failed */
3897 ql_dbg(ql_dbg_p3p
, vha
, 0xb032,
3898 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3900 c_value_r
, p_mask
, w_time
);
3907 for (k
= 0; k
< r_cnt
; k
++) {
3908 r_value
= qla82xx_md_rw_32(ha
, addr
, 0, 0);
3909 *data_ptr
++ = cpu_to_le32(r_value
);
3910 addr
+= cache_hdr
->read_ctrl
.read_addr_stride
;
3912 t_value
+= cache_hdr
->addr_ctrl
.tag_value_stride
;
3919 qla82xx_minidump_process_l1cache(scsi_qla_host_t
*vha
,
3920 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3922 struct qla_hw_data
*ha
= vha
->hw
;
3923 uint32_t addr
, r_addr
, c_addr
, t_r_addr
;
3924 uint32_t i
, k
, loop_count
, t_value
, r_cnt
, r_value
;
3926 struct qla82xx_md_entry_cache
*cache_hdr
;
3927 uint32_t *data_ptr
= *d_ptr
;
3929 cache_hdr
= (struct qla82xx_md_entry_cache
*)entry_hdr
;
3930 loop_count
= cache_hdr
->op_count
;
3931 r_addr
= cache_hdr
->read_addr
;
3932 c_addr
= cache_hdr
->control_addr
;
3933 c_value_w
= cache_hdr
->cache_ctrl
.write_value
;
3935 t_r_addr
= cache_hdr
->tag_reg_addr
;
3936 t_value
= cache_hdr
->addr_ctrl
.init_tag_value
;
3937 r_cnt
= cache_hdr
->read_ctrl
.read_addr_cnt
;
3939 for (i
= 0; i
< loop_count
; i
++) {
3940 qla82xx_md_rw_32(ha
, t_r_addr
, t_value
, 1);
3941 qla82xx_md_rw_32(ha
, c_addr
, c_value_w
, 1);
3943 for (k
= 0; k
< r_cnt
; k
++) {
3944 r_value
= qla82xx_md_rw_32(ha
, addr
, 0, 0);
3945 *data_ptr
++ = cpu_to_le32(r_value
);
3946 addr
+= cache_hdr
->read_ctrl
.read_addr_stride
;
3948 t_value
+= cache_hdr
->addr_ctrl
.tag_value_stride
;
3954 qla82xx_minidump_process_queue(scsi_qla_host_t
*vha
,
3955 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3957 struct qla_hw_data
*ha
= vha
->hw
;
3958 uint32_t s_addr
, r_addr
;
3959 uint32_t r_stride
, r_value
, r_cnt
, qid
= 0;
3960 uint32_t i
, k
, loop_cnt
;
3961 struct qla82xx_md_entry_queue
*q_hdr
;
3962 uint32_t *data_ptr
= *d_ptr
;
3964 q_hdr
= (struct qla82xx_md_entry_queue
*)entry_hdr
;
3965 s_addr
= q_hdr
->select_addr
;
3966 r_cnt
= q_hdr
->rd_strd
.read_addr_cnt
;
3967 r_stride
= q_hdr
->rd_strd
.read_addr_stride
;
3968 loop_cnt
= q_hdr
->op_count
;
3970 for (i
= 0; i
< loop_cnt
; i
++) {
3971 qla82xx_md_rw_32(ha
, s_addr
, qid
, 1);
3972 r_addr
= q_hdr
->read_addr
;
3973 for (k
= 0; k
< r_cnt
; k
++) {
3974 r_value
= qla82xx_md_rw_32(ha
, r_addr
, 0, 0);
3975 *data_ptr
++ = cpu_to_le32(r_value
);
3978 qid
+= q_hdr
->q_strd
.queue_id_stride
;
3984 qla82xx_minidump_process_rdrom(scsi_qla_host_t
*vha
,
3985 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
3987 struct qla_hw_data
*ha
= vha
->hw
;
3988 uint32_t r_addr
, r_value
;
3989 uint32_t i
, loop_cnt
;
3990 struct qla82xx_md_entry_rdrom
*rom_hdr
;
3991 uint32_t *data_ptr
= *d_ptr
;
3993 rom_hdr
= (struct qla82xx_md_entry_rdrom
*)entry_hdr
;
3994 r_addr
= rom_hdr
->read_addr
;
3995 loop_cnt
= rom_hdr
->read_data_size
/sizeof(uint32_t);
3997 for (i
= 0; i
< loop_cnt
; i
++) {
3998 qla82xx_md_rw_32(ha
, MD_DIRECT_ROM_WINDOW
,
3999 (r_addr
& 0xFFFF0000), 1);
4000 r_value
= qla82xx_md_rw_32(ha
,
4001 MD_DIRECT_ROM_READ_BASE
+
4002 (r_addr
& 0x0000FFFF), 0, 0);
4003 *data_ptr
++ = cpu_to_le32(r_value
);
4004 r_addr
+= sizeof(uint32_t);
4010 qla82xx_minidump_process_rdmem(scsi_qla_host_t
*vha
,
4011 qla82xx_md_entry_hdr_t
*entry_hdr
, uint32_t **d_ptr
)
4013 struct qla_hw_data
*ha
= vha
->hw
;
4014 uint32_t r_addr
, r_value
, r_data
;
4015 uint32_t i
, j
, loop_cnt
;
4016 struct qla82xx_md_entry_rdmem
*m_hdr
;
4017 unsigned long flags
;
4018 int rval
= QLA_FUNCTION_FAILED
;
4019 uint32_t *data_ptr
= *d_ptr
;
4021 m_hdr
= (struct qla82xx_md_entry_rdmem
*)entry_hdr
;
4022 r_addr
= m_hdr
->read_addr
;
4023 loop_cnt
= m_hdr
->read_data_size
/16;
4026 ql_log(ql_log_warn
, vha
, 0xb033,
4027 "Read addr 0x%x not 16 bytes alligned\n", r_addr
);
4031 if (m_hdr
->read_data_size
% 16) {
4032 ql_log(ql_log_warn
, vha
, 0xb034,
4033 "Read data[0x%x] not multiple of 16 bytes\n",
4034 m_hdr
->read_data_size
);
4038 ql_dbg(ql_dbg_p3p
, vha
, 0xb035,
4039 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4040 __func__
, r_addr
, m_hdr
->read_data_size
, loop_cnt
);
4042 write_lock_irqsave(&ha
->hw_lock
, flags
);
4043 for (i
= 0; i
< loop_cnt
; i
++) {
4044 qla82xx_md_rw_32(ha
, MD_MIU_TEST_AGT_ADDR_LO
, r_addr
, 1);
4046 qla82xx_md_rw_32(ha
, MD_MIU_TEST_AGT_ADDR_HI
, r_value
, 1);
4047 r_value
= MIU_TA_CTL_ENABLE
;
4048 qla82xx_md_rw_32(ha
, MD_MIU_TEST_AGT_CTRL
, r_value
, 1);
4049 r_value
= MIU_TA_CTL_START
| MIU_TA_CTL_ENABLE
;
4050 qla82xx_md_rw_32(ha
, MD_MIU_TEST_AGT_CTRL
, r_value
, 1);
4052 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
4053 r_value
= qla82xx_md_rw_32(ha
,
4054 MD_MIU_TEST_AGT_CTRL
, 0, 0);
4055 if ((r_value
& MIU_TA_CTL_BUSY
) == 0)
4059 if (j
>= MAX_CTL_CHECK
) {
4060 printk_ratelimited(KERN_ERR
4061 "failed to read through agent\n");
4062 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
4066 for (j
= 0; j
< 4; j
++) {
4067 r_data
= qla82xx_md_rw_32(ha
,
4068 MD_MIU_TEST_AGT_RDDATA
[j
], 0, 0);
4069 *data_ptr
++ = cpu_to_le32(r_data
);
4073 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
4079 qla82xx_validate_template_chksum(scsi_qla_host_t
*vha
)
4081 struct qla_hw_data
*ha
= vha
->hw
;
4082 uint64_t chksum
= 0;
4083 uint32_t *d_ptr
= (uint32_t *)ha
->md_tmplt_hdr
;
4084 int count
= ha
->md_template_size
/sizeof(uint32_t);
4088 while (chksum
>> 32)
4089 chksum
= (chksum
& 0xFFFFFFFF) + (chksum
>> 32);
4094 qla82xx_mark_entry_skipped(scsi_qla_host_t
*vha
,
4095 qla82xx_md_entry_hdr_t
*entry_hdr
, int index
)
4097 entry_hdr
->d_ctrl
.driver_flags
|= QLA82XX_DBG_SKIPPED_FLAG
;
4098 ql_dbg(ql_dbg_p3p
, vha
, 0xb036,
4099 "Skipping entry[%d]: "
4100 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4101 index
, entry_hdr
->entry_type
,
4102 entry_hdr
->d_ctrl
.entry_capture_mask
);
4106 qla82xx_md_collect(scsi_qla_host_t
*vha
)
4108 struct qla_hw_data
*ha
= vha
->hw
;
4109 int no_entry_hdr
= 0;
4110 qla82xx_md_entry_hdr_t
*entry_hdr
;
4111 struct qla82xx_md_template_hdr
*tmplt_hdr
;
4113 uint32_t total_data_size
= 0, f_capture_mask
, data_collected
= 0;
4114 int i
= 0, rval
= QLA_FUNCTION_FAILED
;
4116 tmplt_hdr
= (struct qla82xx_md_template_hdr
*)ha
->md_tmplt_hdr
;
4117 data_ptr
= (uint32_t *)ha
->md_dump
;
4119 if (ha
->fw_dumped
) {
4120 ql_log(ql_log_info
, vha
, 0xb037,
4121 "Firmware dump available to retrive\n");
4127 if (!ha
->md_tmplt_hdr
|| !ha
->md_dump
) {
4128 ql_log(ql_log_warn
, vha
, 0xb038,
4129 "Memory not allocated for minidump capture\n");
4133 if (qla82xx_validate_template_chksum(vha
)) {
4134 ql_log(ql_log_info
, vha
, 0xb039,
4135 "Template checksum validation error\n");
4139 no_entry_hdr
= tmplt_hdr
->num_of_entries
;
4140 ql_dbg(ql_dbg_p3p
, vha
, 0xb03a,
4141 "No of entry headers in Template: 0x%x\n", no_entry_hdr
);
4143 ql_dbg(ql_dbg_p3p
, vha
, 0xb03b,
4144 "Capture Mask obtained: 0x%x\n", tmplt_hdr
->capture_debug_level
);
4146 f_capture_mask
= tmplt_hdr
->capture_debug_level
& 0xFF;
4148 /* Validate whether required debug level is set */
4149 if ((f_capture_mask
& 0x3) != 0x3) {
4150 ql_log(ql_log_warn
, vha
, 0xb03c,
4151 "Minimum required capture mask[0x%x] level not set\n",
4155 tmplt_hdr
->driver_capture_mask
= ql2xmdcapmask
;
4157 tmplt_hdr
->driver_info
[0] = vha
->host_no
;
4158 tmplt_hdr
->driver_info
[1] = (QLA_DRIVER_MAJOR_VER
<< 24) |
4159 (QLA_DRIVER_MINOR_VER
<< 16) | (QLA_DRIVER_PATCH_VER
<< 8) |
4160 QLA_DRIVER_BETA_VER
;
4162 total_data_size
= ha
->md_dump_size
;
4164 ql_dbg(ql_log_info
, vha
, 0xb03d,
4165 "Total minidump data_size 0x%x to be captured\n", total_data_size
);
4167 /* Check whether template obtained is valid */
4168 if (tmplt_hdr
->entry_type
!= QLA82XX_TLHDR
) {
4169 ql_log(ql_log_warn
, vha
, 0xb04e,
4170 "Bad template header entry type: 0x%x obtained\n",
4171 tmplt_hdr
->entry_type
);
4175 entry_hdr
= (qla82xx_md_entry_hdr_t
*) \
4176 (((uint8_t *)ha
->md_tmplt_hdr
) + tmplt_hdr
->first_entry_offset
);
4178 /* Walk through the entry headers */
4179 for (i
= 0; i
< no_entry_hdr
; i
++) {
4181 if (data_collected
> total_data_size
) {
4182 ql_log(ql_log_warn
, vha
, 0xb03e,
4183 "More MiniDump data collected: [0x%x]\n",
4188 if (!(entry_hdr
->d_ctrl
.entry_capture_mask
&
4190 entry_hdr
->d_ctrl
.driver_flags
|=
4191 QLA82XX_DBG_SKIPPED_FLAG
;
4192 ql_dbg(ql_dbg_p3p
, vha
, 0xb03f,
4193 "Skipping entry[%d]: "
4194 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4195 i
, entry_hdr
->entry_type
,
4196 entry_hdr
->d_ctrl
.entry_capture_mask
);
4197 goto skip_nxt_entry
;
4200 ql_dbg(ql_dbg_p3p
, vha
, 0xb040,
4201 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4202 "entry_type: 0x%x, captrue_mask: 0x%x\n",
4203 __func__
, i
, data_ptr
, entry_hdr
,
4204 entry_hdr
->entry_type
,
4205 entry_hdr
->d_ctrl
.entry_capture_mask
);
4207 ql_dbg(ql_dbg_p3p
, vha
, 0xb041,
4208 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4209 data_collected
, (ha
->md_dump_size
- data_collected
));
4211 /* Decode the entry type and take
4212 * required action to capture debug data */
4213 switch (entry_hdr
->entry_type
) {
4215 qla82xx_mark_entry_skipped(vha
, entry_hdr
, i
);
4218 rval
= qla82xx_minidump_process_control(vha
,
4219 entry_hdr
, &data_ptr
);
4220 if (rval
!= QLA_SUCCESS
) {
4221 qla82xx_mark_entry_skipped(vha
, entry_hdr
, i
);
4226 qla82xx_minidump_process_rdcrb(vha
,
4227 entry_hdr
, &data_ptr
);
4230 rval
= qla82xx_minidump_process_rdmem(vha
,
4231 entry_hdr
, &data_ptr
);
4232 if (rval
!= QLA_SUCCESS
) {
4233 qla82xx_mark_entry_skipped(vha
, entry_hdr
, i
);
4239 qla82xx_minidump_process_rdrom(vha
,
4240 entry_hdr
, &data_ptr
);
4246 rval
= qla82xx_minidump_process_l2tag(vha
,
4247 entry_hdr
, &data_ptr
);
4248 if (rval
!= QLA_SUCCESS
) {
4249 qla82xx_mark_entry_skipped(vha
, entry_hdr
, i
);
4255 qla82xx_minidump_process_l1cache(vha
,
4256 entry_hdr
, &data_ptr
);
4259 qla82xx_minidump_process_rdocm(vha
,
4260 entry_hdr
, &data_ptr
);
4263 qla82xx_minidump_process_rdmux(vha
,
4264 entry_hdr
, &data_ptr
);
4267 qla82xx_minidump_process_queue(vha
,
4268 entry_hdr
, &data_ptr
);
4272 qla82xx_mark_entry_skipped(vha
, entry_hdr
, i
);
4276 ql_dbg(ql_dbg_p3p
, vha
, 0xb042,
4277 "[%s]: data ptr[%d]: %p\n", __func__
, i
, data_ptr
);
4279 data_collected
= (uint8_t *)data_ptr
-
4280 (uint8_t *)ha
->md_dump
;
4282 entry_hdr
= (qla82xx_md_entry_hdr_t
*) \
4283 (((uint8_t *)entry_hdr
) + entry_hdr
->entry_size
);
4286 if (data_collected
!= total_data_size
) {
4287 ql_dbg(ql_log_warn
, vha
, 0xb043,
4288 "MiniDump data mismatch: Data collected: [0x%x],"
4289 "total_data_size:[0x%x]\n",
4290 data_collected
, total_data_size
);
4294 ql_log(ql_log_info
, vha
, 0xb044,
4295 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4296 vha
->host_no
, ha
->md_tmplt_hdr
, vha
->host_no
, ha
->md_dump
);
4298 qla2x00_post_uevent_work(vha
, QLA_UEVENT_CODE_FW_DUMP
);
4305 qla82xx_md_alloc(scsi_qla_host_t
*vha
)
4307 struct qla_hw_data
*ha
= vha
->hw
;
4309 struct qla82xx_md_template_hdr
*tmplt_hdr
;
4311 tmplt_hdr
= (struct qla82xx_md_template_hdr
*)ha
->md_tmplt_hdr
;
4313 if (ql2xmdcapmask
< 0x3 || ql2xmdcapmask
> 0x7F) {
4314 ql2xmdcapmask
= tmplt_hdr
->capture_debug_level
& 0xFF;
4315 ql_log(ql_log_info
, vha
, 0xb045,
4316 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4320 for (i
= 0x2, k
= 1; (i
& QLA82XX_DEFAULT_CAP_MASK
); i
<<= 1, k
++) {
4321 if (i
& ql2xmdcapmask
)
4322 ha
->md_dump_size
+= tmplt_hdr
->capture_size_array
[k
];
4326 ql_log(ql_log_warn
, vha
, 0xb046,
4327 "Firmware dump previously allocated.\n");
4331 ha
->md_dump
= vmalloc(ha
->md_dump_size
);
4332 if (ha
->md_dump
== NULL
) {
4333 ql_log(ql_log_warn
, vha
, 0xb047,
4334 "Unable to allocate memory for Minidump size "
4335 "(0x%x).\n", ha
->md_dump_size
);
4342 qla82xx_md_free(scsi_qla_host_t
*vha
)
4344 struct qla_hw_data
*ha
= vha
->hw
;
4346 /* Release the template header allocated */
4347 if (ha
->md_tmplt_hdr
) {
4348 ql_log(ql_log_info
, vha
, 0xb048,
4349 "Free MiniDump template: %p, size (%d KB)\n",
4350 ha
->md_tmplt_hdr
, ha
->md_template_size
/ 1024);
4351 dma_free_coherent(&ha
->pdev
->dev
, ha
->md_template_size
,
4352 ha
->md_tmplt_hdr
, ha
->md_tmplt_hdr_dma
);
4353 ha
->md_tmplt_hdr
= 0;
4356 /* Release the template data buffer allocated */
4358 ql_log(ql_log_info
, vha
, 0xb049,
4359 "Free MiniDump memory: %p, size (%d KB)\n",
4360 ha
->md_dump
, ha
->md_dump_size
/ 1024);
4362 ha
->md_dump_size
= 0;
4368 qla82xx_md_prep(scsi_qla_host_t
*vha
)
4370 struct qla_hw_data
*ha
= vha
->hw
;
4373 /* Get Minidump template size */
4374 rval
= qla82xx_md_get_template_size(vha
);
4375 if (rval
== QLA_SUCCESS
) {
4376 ql_log(ql_log_info
, vha
, 0xb04a,
4377 "MiniDump Template size obtained (%d KB)\n",
4378 ha
->md_template_size
/ 1024);
4380 /* Get Minidump template */
4381 rval
= qla82xx_md_get_template(vha
);
4382 if (rval
== QLA_SUCCESS
) {
4383 ql_dbg(ql_dbg_p3p
, vha
, 0xb04b,
4384 "MiniDump Template obtained\n");
4386 /* Allocate memory for minidump */
4387 rval
= qla82xx_md_alloc(vha
);
4388 if (rval
== QLA_SUCCESS
)
4389 ql_log(ql_log_info
, vha
, 0xb04c,
4390 "MiniDump memory allocated (%d KB)\n",
4391 ha
->md_dump_size
/ 1024);
4393 ql_log(ql_log_info
, vha
, 0xb04d,
4394 "Free MiniDump template: %p, size: (%d KB)\n",
4396 ha
->md_template_size
/ 1024);
4397 dma_free_coherent(&ha
->pdev
->dev
,
4398 ha
->md_template_size
,
4399 ha
->md_tmplt_hdr
, ha
->md_tmplt_hdr_dma
);
4400 ha
->md_tmplt_hdr
= 0;
4408 qla82xx_beacon_on(struct scsi_qla_host
*vha
)
4412 struct qla_hw_data
*ha
= vha
->hw
;
4413 qla82xx_idc_lock(ha
);
4414 rval
= qla82xx_mbx_beacon_ctl(vha
, 1);
4417 ql_log(ql_log_warn
, vha
, 0xb050,
4418 "mbx set led config failed in %s\n", __func__
);
4421 ha
->beacon_blink_led
= 1;
4423 qla82xx_idc_unlock(ha
);
4428 qla82xx_beacon_off(struct scsi_qla_host
*vha
)
4432 struct qla_hw_data
*ha
= vha
->hw
;
4433 qla82xx_idc_lock(ha
);
4434 rval
= qla82xx_mbx_beacon_ctl(vha
, 0);
4437 ql_log(ql_log_warn
, vha
, 0xb051,
4438 "mbx set led config failed in %s\n", __func__
);
4441 ha
->beacon_blink_led
= 0;
4443 qla82xx_idc_unlock(ha
);