2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/vmalloc.h>
12 #include <asm/uaccess.h>
15 * NVRAM support routines
19 * qla2x00_lock_nvram_access() -
23 qla2x00_lock_nvram_access(struct qla_hw_data
*ha
)
26 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
28 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
29 data
= RD_REG_WORD(®
->nvram
);
30 while (data
& NVR_BUSY
) {
32 data
= RD_REG_WORD(®
->nvram
);
36 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
37 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
39 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
40 while ((data
& BIT_0
) == 0) {
43 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
44 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
46 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
52 * qla2x00_unlock_nvram_access() -
56 qla2x00_unlock_nvram_access(struct qla_hw_data
*ha
)
58 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
60 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
61 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0);
62 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
69 * @data: Serial interface selector
72 qla2x00_nv_write(struct qla_hw_data
*ha
, uint16_t data
)
74 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
76 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
77 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
79 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_CLOCK
|
81 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
83 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
84 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
92 * @nv_cmd: NVRAM command
94 * Bit definitions for NVRAM command:
99 * Bit 15-0 = write data
101 * Returns the word read from nvram @addr.
104 qla2x00_nvram_request(struct qla_hw_data
*ha
, uint32_t nv_cmd
)
107 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
111 /* Send command to NVRAM. */
113 for (cnt
= 0; cnt
< 11; cnt
++) {
115 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
117 qla2x00_nv_write(ha
, 0);
121 /* Read data from NVRAM. */
122 for (cnt
= 0; cnt
< 16; cnt
++) {
123 WRT_REG_WORD(®
->nvram
, NVR_SELECT
| NVR_CLOCK
);
124 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
127 reg_data
= RD_REG_WORD(®
->nvram
);
128 if (reg_data
& NVR_DATA_IN
)
130 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
131 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
136 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
137 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
146 * request routine to get the word from NVRAM.
148 * @addr: Address in NVRAM to read
150 * Returns the word read from nvram @addr.
153 qla2x00_get_nvram_word(struct qla_hw_data
*ha
, uint32_t addr
)
159 nv_cmd
|= NV_READ_OP
;
160 data
= qla2x00_nvram_request(ha
, nv_cmd
);
166 * qla2x00_nv_deselect() - Deselect NVRAM operations.
170 qla2x00_nv_deselect(struct qla_hw_data
*ha
)
172 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
174 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
175 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
180 * qla2x00_write_nvram_word() - Write NVRAM data.
182 * @addr: Address in NVRAM to write
183 * @data: word to program
186 qla2x00_write_nvram_word(struct qla_hw_data
*ha
, uint32_t addr
, uint16_t data
)
190 uint32_t nv_cmd
, wait_cnt
;
191 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
192 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
194 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
195 qla2x00_nv_write(ha
, 0);
196 qla2x00_nv_write(ha
, 0);
198 for (word
= 0; word
< 8; word
++)
199 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
201 qla2x00_nv_deselect(ha
);
204 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
207 for (count
= 0; count
< 27; count
++) {
209 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
211 qla2x00_nv_write(ha
, 0);
216 qla2x00_nv_deselect(ha
);
218 /* Wait for NVRAM to become ready */
219 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
220 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
221 wait_cnt
= NVR_WAIT_CNT
;
224 ql_dbg(ql_dbg_user
, vha
, 0x708d,
225 "NVRAM didn't go ready...\n");
229 word
= RD_REG_WORD(®
->nvram
);
230 } while ((word
& NVR_DATA_IN
) == 0);
232 qla2x00_nv_deselect(ha
);
235 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
236 for (count
= 0; count
< 10; count
++)
237 qla2x00_nv_write(ha
, 0);
239 qla2x00_nv_deselect(ha
);
243 qla2x00_write_nvram_word_tmo(struct qla_hw_data
*ha
, uint32_t addr
,
244 uint16_t data
, uint32_t tmo
)
249 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
253 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
254 qla2x00_nv_write(ha
, 0);
255 qla2x00_nv_write(ha
, 0);
257 for (word
= 0; word
< 8; word
++)
258 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
260 qla2x00_nv_deselect(ha
);
263 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
266 for (count
= 0; count
< 27; count
++) {
268 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
270 qla2x00_nv_write(ha
, 0);
275 qla2x00_nv_deselect(ha
);
277 /* Wait for NVRAM to become ready */
278 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
279 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
282 word
= RD_REG_WORD(®
->nvram
);
284 ret
= QLA_FUNCTION_FAILED
;
287 } while ((word
& NVR_DATA_IN
) == 0);
289 qla2x00_nv_deselect(ha
);
292 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
293 for (count
= 0; count
< 10; count
++)
294 qla2x00_nv_write(ha
, 0);
296 qla2x00_nv_deselect(ha
);
302 * qla2x00_clear_nvram_protection() -
306 qla2x00_clear_nvram_protection(struct qla_hw_data
*ha
)
309 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
310 uint32_t word
, wait_cnt
;
311 uint16_t wprot
, wprot_old
;
312 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
314 /* Clear NVRAM write protection. */
315 ret
= QLA_FUNCTION_FAILED
;
317 wprot_old
= cpu_to_le16(qla2x00_get_nvram_word(ha
, ha
->nvram_base
));
318 stat
= qla2x00_write_nvram_word_tmo(ha
, ha
->nvram_base
,
319 __constant_cpu_to_le16(0x1234), 100000);
320 wprot
= cpu_to_le16(qla2x00_get_nvram_word(ha
, ha
->nvram_base
));
321 if (stat
!= QLA_SUCCESS
|| wprot
!= 0x1234) {
323 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
324 qla2x00_nv_write(ha
, 0);
325 qla2x00_nv_write(ha
, 0);
326 for (word
= 0; word
< 8; word
++)
327 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
329 qla2x00_nv_deselect(ha
);
331 /* Enable protection register. */
332 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
333 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
334 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
335 for (word
= 0; word
< 8; word
++)
336 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
338 qla2x00_nv_deselect(ha
);
340 /* Clear protection register (ffff is cleared). */
341 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
342 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
343 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
344 for (word
= 0; word
< 8; word
++)
345 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
347 qla2x00_nv_deselect(ha
);
349 /* Wait for NVRAM to become ready. */
350 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
351 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
352 wait_cnt
= NVR_WAIT_CNT
;
355 ql_dbg(ql_dbg_user
, vha
, 0x708e,
356 "NVRAM didn't go ready...\n");
360 word
= RD_REG_WORD(®
->nvram
);
361 } while ((word
& NVR_DATA_IN
) == 0);
366 qla2x00_write_nvram_word(ha
, ha
->nvram_base
, wprot_old
);
372 qla2x00_set_nvram_protection(struct qla_hw_data
*ha
, int stat
)
374 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
375 uint32_t word
, wait_cnt
;
376 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
378 if (stat
!= QLA_SUCCESS
)
381 /* Set NVRAM write protection. */
383 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
384 qla2x00_nv_write(ha
, 0);
385 qla2x00_nv_write(ha
, 0);
386 for (word
= 0; word
< 8; word
++)
387 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
389 qla2x00_nv_deselect(ha
);
391 /* Enable protection register. */
392 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
393 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
394 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
395 for (word
= 0; word
< 8; word
++)
396 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
398 qla2x00_nv_deselect(ha
);
400 /* Enable protection register. */
401 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
402 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
403 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
404 for (word
= 0; word
< 8; word
++)
405 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
407 qla2x00_nv_deselect(ha
);
409 /* Wait for NVRAM to become ready. */
410 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
411 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
412 wait_cnt
= NVR_WAIT_CNT
;
415 ql_dbg(ql_dbg_user
, vha
, 0x708f,
416 "NVRAM didn't go ready...\n");
420 word
= RD_REG_WORD(®
->nvram
);
421 } while ((word
& NVR_DATA_IN
) == 0);
425 /*****************************************************************************/
426 /* Flash Manipulation Routines */
427 /*****************************************************************************/
429 static inline uint32_t
430 flash_conf_addr(struct qla_hw_data
*ha
, uint32_t faddr
)
432 return ha
->flash_conf_off
| faddr
;
435 static inline uint32_t
436 flash_data_addr(struct qla_hw_data
*ha
, uint32_t faddr
)
438 return ha
->flash_data_off
| faddr
;
441 static inline uint32_t
442 nvram_conf_addr(struct qla_hw_data
*ha
, uint32_t naddr
)
444 return ha
->nvram_conf_off
| naddr
;
447 static inline uint32_t
448 nvram_data_addr(struct qla_hw_data
*ha
, uint32_t naddr
)
450 return ha
->nvram_data_off
| naddr
;
454 qla24xx_read_flash_dword(struct qla_hw_data
*ha
, uint32_t addr
)
458 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
460 WRT_REG_DWORD(®
->flash_addr
, addr
& ~FARX_DATA_FLAG
);
461 /* Wait for READ cycle to complete. */
464 (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) == 0 &&
465 rval
== QLA_SUCCESS
; cnt
--) {
469 rval
= QLA_FUNCTION_TIMEOUT
;
473 /* TODO: What happens if we time out? */
475 if (rval
== QLA_SUCCESS
)
476 data
= RD_REG_DWORD(®
->flash_data
);
482 qla24xx_read_flash_data(scsi_qla_host_t
*vha
, uint32_t *dwptr
, uint32_t faddr
,
486 struct qla_hw_data
*ha
= vha
->hw
;
488 /* Dword reads to flash. */
489 for (i
= 0; i
< dwords
; i
++, faddr
++)
490 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
491 flash_data_addr(ha
, faddr
)));
497 qla24xx_write_flash_dword(struct qla_hw_data
*ha
, uint32_t addr
, uint32_t data
)
501 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
503 WRT_REG_DWORD(®
->flash_data
, data
);
504 RD_REG_DWORD(®
->flash_data
); /* PCI Posting. */
505 WRT_REG_DWORD(®
->flash_addr
, addr
| FARX_DATA_FLAG
);
506 /* Wait for Write cycle to complete. */
508 for (cnt
= 500000; (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) &&
509 rval
== QLA_SUCCESS
; cnt
--) {
513 rval
= QLA_FUNCTION_TIMEOUT
;
520 qla24xx_get_flash_manufacturer(struct qla_hw_data
*ha
, uint8_t *man_id
,
525 ids
= qla24xx_read_flash_dword(ha
, flash_conf_addr(ha
, 0x03ab));
527 *flash_id
= MSB(ids
);
529 /* Check if man_id and flash_id are valid. */
530 if (ids
!= 0xDEADDEAD && (*man_id
== 0 || *flash_id
== 0)) {
531 /* Read information using 0x9f opcode
532 * Device ID, Mfg ID would be read in the format:
533 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
534 * Example: ATMEL 0x00 01 45 1F
535 * Extract MFG and Dev ID from last two bytes.
537 ids
= qla24xx_read_flash_dword(ha
, flash_conf_addr(ha
, 0x009f));
539 *flash_id
= MSB(ids
);
544 qla2xxx_find_flt_start(scsi_qla_host_t
*vha
, uint32_t *start
)
546 const char *loc
, *locations
[] = { "DEF", "PCI" };
547 uint32_t pcihdr
, pcids
;
549 uint8_t *buf
, *bcode
, last_image
;
550 uint16_t cnt
, chksum
, *wptr
;
551 struct qla_flt_location
*fltl
;
552 struct qla_hw_data
*ha
= vha
->hw
;
553 struct req_que
*req
= ha
->req_q_map
[0];
556 * FLT-location structure resides after the last PCI region.
559 /* Begin with sane defaults. */
562 if (IS_QLA24XX_TYPE(ha
))
563 *start
= FA_FLASH_LAYOUT_ADDR_24
;
564 else if (IS_QLA25XX(ha
))
565 *start
= FA_FLASH_LAYOUT_ADDR
;
566 else if (IS_QLA81XX(ha
))
567 *start
= FA_FLASH_LAYOUT_ADDR_81
;
568 else if (IS_QLA82XX(ha
)) {
569 *start
= FA_FLASH_LAYOUT_ADDR_82
;
572 /* Begin with first PCI expansion ROM header. */
573 buf
= (uint8_t *)req
->ring
;
574 dcode
= (uint32_t *)req
->ring
;
578 /* Verify PCI expansion ROM header. */
579 qla24xx_read_flash_data(vha
, dcode
, pcihdr
>> 2, 0x20);
580 bcode
= buf
+ (pcihdr
% 4);
581 if (bcode
[0x0] != 0x55 || bcode
[0x1] != 0xaa)
584 /* Locate PCI data structure. */
585 pcids
= pcihdr
+ ((bcode
[0x19] << 8) | bcode
[0x18]);
586 qla24xx_read_flash_data(vha
, dcode
, pcids
>> 2, 0x20);
587 bcode
= buf
+ (pcihdr
% 4);
589 /* Validate signature of PCI data structure. */
590 if (bcode
[0x0] != 'P' || bcode
[0x1] != 'C' ||
591 bcode
[0x2] != 'I' || bcode
[0x3] != 'R')
594 last_image
= bcode
[0x15] & BIT_7
;
596 /* Locate next PCI expansion ROM. */
597 pcihdr
+= ((bcode
[0x11] << 8) | bcode
[0x10]) * 512;
598 } while (!last_image
);
600 /* Now verify FLT-location structure. */
601 fltl
= (struct qla_flt_location
*)req
->ring
;
602 qla24xx_read_flash_data(vha
, dcode
, pcihdr
>> 2,
603 sizeof(struct qla_flt_location
) >> 2);
604 if (fltl
->sig
[0] != 'Q' || fltl
->sig
[1] != 'F' ||
605 fltl
->sig
[2] != 'L' || fltl
->sig
[3] != 'T')
608 wptr
= (uint16_t *)req
->ring
;
609 cnt
= sizeof(struct qla_flt_location
) >> 1;
610 for (chksum
= 0; cnt
; cnt
--)
611 chksum
+= le16_to_cpu(*wptr
++);
613 ql_log(ql_log_fatal
, vha
, 0x0045,
614 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum
);
615 ql_dump_buffer(ql_dbg_init
+ ql_dbg_buffer
, vha
, 0x010e,
616 buf
, sizeof(struct qla_flt_location
));
617 return QLA_FUNCTION_FAILED
;
620 /* Good data. Use specified location. */
622 *start
= (le16_to_cpu(fltl
->start_hi
) << 16 |
623 le16_to_cpu(fltl
->start_lo
)) >> 2;
625 ql_dbg(ql_dbg_init
, vha
, 0x0046,
626 "FLTL[%s] = 0x%x.\n",
632 qla2xxx_get_flt_info(scsi_qla_host_t
*vha
, uint32_t flt_addr
)
634 const char *loc
, *locations
[] = { "DEF", "FLT" };
635 const uint32_t def_fw
[] =
636 { FA_RISC_CODE_ADDR
, FA_RISC_CODE_ADDR
, FA_RISC_CODE_ADDR_81
};
637 const uint32_t def_boot
[] =
638 { FA_BOOT_CODE_ADDR
, FA_BOOT_CODE_ADDR
, FA_BOOT_CODE_ADDR_81
};
639 const uint32_t def_vpd_nvram
[] =
640 { FA_VPD_NVRAM_ADDR
, FA_VPD_NVRAM_ADDR
, FA_VPD_NVRAM_ADDR_81
};
641 const uint32_t def_vpd0
[] =
642 { 0, 0, FA_VPD0_ADDR_81
};
643 const uint32_t def_vpd1
[] =
644 { 0, 0, FA_VPD1_ADDR_81
};
645 const uint32_t def_nvram0
[] =
646 { 0, 0, FA_NVRAM0_ADDR_81
};
647 const uint32_t def_nvram1
[] =
648 { 0, 0, FA_NVRAM1_ADDR_81
};
649 const uint32_t def_fdt
[] =
650 { FA_FLASH_DESCR_ADDR_24
, FA_FLASH_DESCR_ADDR
,
651 FA_FLASH_DESCR_ADDR_81
};
652 const uint32_t def_npiv_conf0
[] =
653 { FA_NPIV_CONF0_ADDR_24
, FA_NPIV_CONF0_ADDR
,
654 FA_NPIV_CONF0_ADDR_81
};
655 const uint32_t def_npiv_conf1
[] =
656 { FA_NPIV_CONF1_ADDR_24
, FA_NPIV_CONF1_ADDR
,
657 FA_NPIV_CONF1_ADDR_81
};
658 const uint32_t fcp_prio_cfg0
[] =
659 { FA_FCP_PRIO0_ADDR
, FA_FCP_PRIO0_ADDR_25
,
661 const uint32_t fcp_prio_cfg1
[] =
662 { FA_FCP_PRIO1_ADDR
, FA_FCP_PRIO1_ADDR_25
,
666 uint16_t cnt
, chksum
;
668 struct qla_flt_header
*flt
;
669 struct qla_flt_region
*region
;
670 struct qla_hw_data
*ha
= vha
->hw
;
671 struct req_que
*req
= ha
->req_q_map
[0];
676 else if (IS_QLA81XX(ha
))
679 /* Assign FCP prio region since older adapters may not have FLT, or
680 FCP prio region in it's FLT.
682 ha
->flt_region_fcp_prio
= ha
->flags
.port0
?
683 fcp_prio_cfg0
[def
] : fcp_prio_cfg1
[def
];
685 ha
->flt_region_flt
= flt_addr
;
686 wptr
= (uint16_t *)req
->ring
;
687 flt
= (struct qla_flt_header
*)req
->ring
;
688 region
= (struct qla_flt_region
*)&flt
[1];
689 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)req
->ring
,
690 flt_addr
<< 2, OPTROM_BURST_SIZE
);
691 if (*wptr
== __constant_cpu_to_le16(0xffff))
693 if (flt
->version
!= __constant_cpu_to_le16(1)) {
694 ql_log(ql_log_warn
, vha
, 0x0047,
695 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
696 le16_to_cpu(flt
->version
), le16_to_cpu(flt
->length
),
697 le16_to_cpu(flt
->checksum
));
701 cnt
= (sizeof(struct qla_flt_header
) + le16_to_cpu(flt
->length
)) >> 1;
702 for (chksum
= 0; cnt
; cnt
--)
703 chksum
+= le16_to_cpu(*wptr
++);
705 ql_log(ql_log_fatal
, vha
, 0x0048,
706 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
707 le16_to_cpu(flt
->version
), le16_to_cpu(flt
->length
),
708 le16_to_cpu(flt
->checksum
));
713 cnt
= le16_to_cpu(flt
->length
) / sizeof(struct qla_flt_region
);
714 for ( ; cnt
; cnt
--, region
++) {
715 /* Store addresses as DWORD offsets. */
716 start
= le32_to_cpu(region
->start
) >> 2;
717 ql_dbg(ql_dbg_init
, vha
, 0x0049,
718 "FLT[%02x]: start=0x%x "
719 "end=0x%x size=0x%x.\n", le32_to_cpu(region
->code
),
720 start
, le32_to_cpu(region
->end
) >> 2,
721 le32_to_cpu(region
->size
));
723 switch (le32_to_cpu(region
->code
) & 0xff) {
725 ha
->flt_region_fw
= start
;
727 case FLT_REG_BOOT_CODE
:
728 ha
->flt_region_boot
= start
;
731 ha
->flt_region_vpd_nvram
= start
;
735 ha
->flt_region_vpd
= start
;
740 if (!ha
->flags
.port0
)
741 ha
->flt_region_vpd
= start
;
743 case FLT_REG_NVRAM_0
:
745 ha
->flt_region_nvram
= start
;
747 case FLT_REG_NVRAM_1
:
748 if (!ha
->flags
.port0
)
749 ha
->flt_region_nvram
= start
;
752 ha
->flt_region_fdt
= start
;
754 case FLT_REG_NPIV_CONF_0
:
756 ha
->flt_region_npiv_conf
= start
;
758 case FLT_REG_NPIV_CONF_1
:
759 if (!ha
->flags
.port0
)
760 ha
->flt_region_npiv_conf
= start
;
762 case FLT_REG_GOLD_FW
:
763 ha
->flt_region_gold_fw
= start
;
765 case FLT_REG_FCP_PRIO_0
:
767 ha
->flt_region_fcp_prio
= start
;
769 case FLT_REG_FCP_PRIO_1
:
770 if (!ha
->flags
.port0
)
771 ha
->flt_region_fcp_prio
= start
;
773 case FLT_REG_BOOT_CODE_82XX
:
774 ha
->flt_region_boot
= start
;
776 case FLT_REG_FW_82XX
:
777 ha
->flt_region_fw
= start
;
779 case FLT_REG_GOLD_FW_82XX
:
780 ha
->flt_region_gold_fw
= start
;
782 case FLT_REG_BOOTLOAD_82XX
:
783 ha
->flt_region_bootload
= start
;
785 case FLT_REG_VPD_82XX
:
786 ha
->flt_region_vpd
= start
;
793 /* Use hardcoded defaults. */
795 ha
->flt_region_fw
= def_fw
[def
];
796 ha
->flt_region_boot
= def_boot
[def
];
797 ha
->flt_region_vpd_nvram
= def_vpd_nvram
[def
];
798 ha
->flt_region_vpd
= ha
->flags
.port0
?
799 def_vpd0
[def
] : def_vpd1
[def
];
800 ha
->flt_region_nvram
= ha
->flags
.port0
?
801 def_nvram0
[def
] : def_nvram1
[def
];
802 ha
->flt_region_fdt
= def_fdt
[def
];
803 ha
->flt_region_npiv_conf
= ha
->flags
.port0
?
804 def_npiv_conf0
[def
] : def_npiv_conf1
[def
];
806 ql_dbg(ql_dbg_init
, vha
, 0x004a,
807 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x.\n",
808 loc
, ha
->flt_region_boot
,
809 ha
->flt_region_fw
, ha
->flt_region_vpd_nvram
,
811 ql_dbg(ql_dbg_init
, vha
, 0x004b,
812 "nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
813 ha
->flt_region_nvram
,
814 ha
->flt_region_fdt
, ha
->flt_region_flt
,
815 ha
->flt_region_npiv_conf
, ha
->flt_region_fcp_prio
);
819 qla2xxx_get_fdt_info(scsi_qla_host_t
*vha
)
821 #define FLASH_BLK_SIZE_4K 0x1000
822 #define FLASH_BLK_SIZE_32K 0x8000
823 #define FLASH_BLK_SIZE_64K 0x10000
824 const char *loc
, *locations
[] = { "MID", "FDT" };
825 uint16_t cnt
, chksum
;
827 struct qla_fdt_layout
*fdt
;
828 uint8_t man_id
, flash_id
;
829 uint16_t mid
= 0, fid
= 0;
830 struct qla_hw_data
*ha
= vha
->hw
;
831 struct req_que
*req
= ha
->req_q_map
[0];
833 wptr
= (uint16_t *)req
->ring
;
834 fdt
= (struct qla_fdt_layout
*)req
->ring
;
835 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)req
->ring
,
836 ha
->flt_region_fdt
<< 2, OPTROM_BURST_SIZE
);
837 if (*wptr
== __constant_cpu_to_le16(0xffff))
839 if (fdt
->sig
[0] != 'Q' || fdt
->sig
[1] != 'L' || fdt
->sig
[2] != 'I' ||
843 for (cnt
= 0, chksum
= 0; cnt
< sizeof(struct qla_fdt_layout
) >> 1;
845 chksum
+= le16_to_cpu(*wptr
++);
847 ql_dbg(ql_dbg_init
, vha
, 0x004c,
848 "Inconsistent FDT detected:"
849 " checksum=0x%x id=%c version0x%x.\n", chksum
,
850 fdt
->sig
[0], le16_to_cpu(fdt
->version
));
851 ql_dump_buffer(ql_dbg_init
+ ql_dbg_buffer
, vha
, 0x0113,
852 (uint8_t *)fdt
, sizeof(*fdt
));
857 mid
= le16_to_cpu(fdt
->man_id
);
858 fid
= le16_to_cpu(fdt
->id
);
859 ha
->fdt_wrt_disable
= fdt
->wrt_disable_bits
;
860 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x0300 | fdt
->erase_cmd
);
861 ha
->fdt_block_size
= le32_to_cpu(fdt
->block_size
);
862 if (fdt
->unprotect_sec_cmd
) {
863 ha
->fdt_unprotect_sec_cmd
= flash_conf_addr(ha
, 0x0300 |
864 fdt
->unprotect_sec_cmd
);
865 ha
->fdt_protect_sec_cmd
= fdt
->protect_sec_cmd
?
866 flash_conf_addr(ha
, 0x0300 | fdt
->protect_sec_cmd
):
867 flash_conf_addr(ha
, 0x0336);
872 if (IS_QLA82XX(ha
)) {
873 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
876 qla24xx_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
879 ha
->fdt_wrt_disable
= 0x9c;
880 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x03d8);
882 case 0xbf: /* STT flash. */
883 if (flash_id
== 0x8e)
884 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
886 ha
->fdt_block_size
= FLASH_BLK_SIZE_32K
;
888 if (flash_id
== 0x80)
889 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x0352);
891 case 0x13: /* ST M25P80. */
892 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
894 case 0x1f: /* Atmel 26DF081A. */
895 ha
->fdt_block_size
= FLASH_BLK_SIZE_4K
;
896 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x0320);
897 ha
->fdt_unprotect_sec_cmd
= flash_conf_addr(ha
, 0x0339);
898 ha
->fdt_protect_sec_cmd
= flash_conf_addr(ha
, 0x0336);
901 /* Default to 64 kb sector size. */
902 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
906 ql_dbg(ql_dbg_init
, vha
, 0x004d,
907 "FDT[%s]: (0x%x/0x%x) erase=0x%x "
908 "pr=%x wrtd=0x%x blk=0x%x.\n",
910 ha
->fdt_erase_cmd
, ha
->fdt_protect_sec_cmd
,
911 ha
->fdt_wrt_disable
, ha
->fdt_block_size
);
916 qla2xxx_get_idc_param(scsi_qla_host_t
*vha
)
918 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
920 struct qla_hw_data
*ha
= vha
->hw
;
921 struct req_que
*req
= ha
->req_q_map
[0];
926 wptr
= (uint32_t *)req
->ring
;
927 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)req
->ring
,
928 QLA82XX_IDC_PARAM_ADDR
, 8);
930 if (*wptr
== __constant_cpu_to_le32(0xffffffff)) {
931 ha
->nx_dev_init_timeout
= QLA82XX_ROM_DEV_INIT_TIMEOUT
;
932 ha
->nx_reset_timeout
= QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT
;
934 ha
->nx_dev_init_timeout
= le32_to_cpu(*wptr
++);
935 ha
->nx_reset_timeout
= le32_to_cpu(*wptr
);
937 ql_dbg(ql_dbg_init
, vha
, 0x004e,
938 "nx_dev_init_timeout=%d "
939 "nx_reset_timeout=%d.\n", ha
->nx_dev_init_timeout
,
940 ha
->nx_reset_timeout
);
945 qla2xxx_get_flash_info(scsi_qla_host_t
*vha
)
949 struct qla_hw_data
*ha
= vha
->hw
;
951 if (!IS_QLA24XX_TYPE(ha
) && !IS_QLA25XX(ha
) && !IS_QLA8XXX_TYPE(ha
))
954 ret
= qla2xxx_find_flt_start(vha
, &flt_addr
);
955 if (ret
!= QLA_SUCCESS
)
958 qla2xxx_get_flt_info(vha
, flt_addr
);
959 qla2xxx_get_fdt_info(vha
);
960 qla2xxx_get_idc_param(vha
);
966 qla2xxx_flash_npiv_conf(scsi_qla_host_t
*vha
)
968 #define NPIV_CONFIG_SIZE (16*1024)
971 uint16_t cnt
, chksum
;
973 struct qla_npiv_header hdr
;
974 struct qla_npiv_entry
*entry
;
975 struct qla_hw_data
*ha
= vha
->hw
;
977 if (!IS_QLA24XX_TYPE(ha
) && !IS_QLA25XX(ha
) && !IS_QLA8XXX_TYPE(ha
))
980 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)&hdr
,
981 ha
->flt_region_npiv_conf
<< 2, sizeof(struct qla_npiv_header
));
982 if (hdr
.version
== __constant_cpu_to_le16(0xffff))
984 if (hdr
.version
!= __constant_cpu_to_le16(1)) {
985 ql_dbg(ql_dbg_user
, vha
, 0x7090,
986 "Unsupported NPIV-Config "
987 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
988 le16_to_cpu(hdr
.version
), le16_to_cpu(hdr
.entries
),
989 le16_to_cpu(hdr
.checksum
));
993 data
= kmalloc(NPIV_CONFIG_SIZE
, GFP_KERNEL
);
995 ql_log(ql_log_warn
, vha
, 0x7091,
996 "Unable to allocate memory for data.\n");
1000 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)data
,
1001 ha
->flt_region_npiv_conf
<< 2, NPIV_CONFIG_SIZE
);
1003 cnt
= (sizeof(struct qla_npiv_header
) + le16_to_cpu(hdr
.entries
) *
1004 sizeof(struct qla_npiv_entry
)) >> 1;
1005 for (wptr
= data
, chksum
= 0; cnt
; cnt
--)
1006 chksum
+= le16_to_cpu(*wptr
++);
1008 ql_dbg(ql_dbg_user
, vha
, 0x7092,
1009 "Inconsistent NPIV-Config "
1010 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1011 le16_to_cpu(hdr
.version
), le16_to_cpu(hdr
.entries
),
1012 le16_to_cpu(hdr
.checksum
));
1016 entry
= data
+ sizeof(struct qla_npiv_header
);
1017 cnt
= le16_to_cpu(hdr
.entries
);
1018 for (i
= 0; cnt
; cnt
--, entry
++, i
++) {
1020 struct fc_vport_identifiers vid
;
1021 struct fc_vport
*vport
;
1023 memcpy(&ha
->npiv_info
[i
], entry
, sizeof(struct qla_npiv_entry
));
1025 flags
= le16_to_cpu(entry
->flags
);
1026 if (flags
== 0xffff)
1028 if ((flags
& BIT_0
) == 0)
1031 memset(&vid
, 0, sizeof(vid
));
1032 vid
.roles
= FC_PORT_ROLE_FCP_INITIATOR
;
1033 vid
.vport_type
= FC_PORTTYPE_NPIV
;
1034 vid
.disable
= false;
1035 vid
.port_name
= wwn_to_u64(entry
->port_name
);
1036 vid
.node_name
= wwn_to_u64(entry
->node_name
);
1038 ql_dbg(ql_dbg_user
, vha
, 0x7093,
1039 "NPIV[%02x]: wwpn=%llx "
1040 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt
,
1041 (unsigned long long)vid
.port_name
,
1042 (unsigned long long)vid
.node_name
,
1043 le16_to_cpu(entry
->vf_id
),
1044 entry
->q_qos
, entry
->f_qos
);
1046 if (i
< QLA_PRECONFIG_VPORTS
) {
1047 vport
= fc_vport_create(vha
->host
, 0, &vid
);
1049 ql_log(ql_log_warn
, vha
, 0x7094,
1050 "NPIV-Config Failed to create vport [%02x]: "
1051 "wwpn=%llx wwnn=%llx.\n", cnt
,
1052 (unsigned long long)vid
.port_name
,
1053 (unsigned long long)vid
.node_name
);
1061 qla24xx_unprotect_flash(scsi_qla_host_t
*vha
)
1063 struct qla_hw_data
*ha
= vha
->hw
;
1064 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1066 if (ha
->flags
.fac_supported
)
1067 return qla81xx_fac_do_write_enable(vha
, 1);
1069 /* Enable flash write. */
1070 WRT_REG_DWORD(®
->ctrl_status
,
1071 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
1072 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1074 if (!ha
->fdt_wrt_disable
)
1077 /* Disable flash write-protection, first clear SR protection bit */
1078 qla24xx_write_flash_dword(ha
, flash_conf_addr(ha
, 0x101), 0);
1079 /* Then write zero again to clear remaining SR bits.*/
1080 qla24xx_write_flash_dword(ha
, flash_conf_addr(ha
, 0x101), 0);
1086 qla24xx_protect_flash(scsi_qla_host_t
*vha
)
1089 struct qla_hw_data
*ha
= vha
->hw
;
1090 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1092 if (ha
->flags
.fac_supported
)
1093 return qla81xx_fac_do_write_enable(vha
, 0);
1095 if (!ha
->fdt_wrt_disable
)
1096 goto skip_wrt_protect
;
1098 /* Enable flash write-protection and wait for completion. */
1099 qla24xx_write_flash_dword(ha
, flash_conf_addr(ha
, 0x101),
1100 ha
->fdt_wrt_disable
);
1101 for (cnt
= 300; cnt
&&
1102 qla24xx_read_flash_dword(ha
, flash_conf_addr(ha
, 0x005)) & BIT_0
;
1108 /* Disable flash write. */
1109 WRT_REG_DWORD(®
->ctrl_status
,
1110 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
1111 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1117 qla24xx_erase_sector(scsi_qla_host_t
*vha
, uint32_t fdata
)
1119 struct qla_hw_data
*ha
= vha
->hw
;
1120 uint32_t start
, finish
;
1122 if (ha
->flags
.fac_supported
) {
1124 finish
= start
+ (ha
->fdt_block_size
>> 2) - 1;
1125 return qla81xx_fac_erase_sector(vha
, flash_data_addr(ha
,
1126 start
), flash_data_addr(ha
, finish
));
1129 return qla24xx_write_flash_dword(ha
, ha
->fdt_erase_cmd
,
1130 (fdata
& 0xff00) | ((fdata
<< 16) & 0xff0000) |
1131 ((fdata
>> 16) & 0xff));
1135 qla24xx_write_flash_data(scsi_qla_host_t
*vha
, uint32_t *dwptr
, uint32_t faddr
,
1140 uint32_t sec_mask
, rest_addr
;
1142 dma_addr_t optrom_dma
;
1143 void *optrom
= NULL
;
1144 struct qla_hw_data
*ha
= vha
->hw
;
1146 /* Prepare burst-capable write on supported ISPs. */
1147 if ((IS_QLA25XX(ha
) || IS_QLA81XX(ha
)) && !(faddr
& 0xfff) &&
1148 dwords
> OPTROM_BURST_DWORDS
) {
1149 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
1150 &optrom_dma
, GFP_KERNEL
);
1152 ql_log(ql_log_warn
, vha
, 0x7095,
1153 "Unable to allocate "
1154 "memory for optrom burst write (%x KB).\n",
1155 OPTROM_BURST_SIZE
/ 1024);
1159 rest_addr
= (ha
->fdt_block_size
>> 2) - 1;
1160 sec_mask
= ~rest_addr
;
1162 ret
= qla24xx_unprotect_flash(vha
);
1163 if (ret
!= QLA_SUCCESS
) {
1164 ql_log(ql_log_warn
, vha
, 0x7096,
1165 "Unable to unprotect flash for update.\n");
1169 for (liter
= 0; liter
< dwords
; liter
++, faddr
++, dwptr
++) {
1170 fdata
= (faddr
& sec_mask
) << 2;
1172 /* Are we at the beginning of a sector? */
1173 if ((faddr
& rest_addr
) == 0) {
1174 /* Do sector unprotect. */
1175 if (ha
->fdt_unprotect_sec_cmd
)
1176 qla24xx_write_flash_dword(ha
,
1177 ha
->fdt_unprotect_sec_cmd
,
1178 (fdata
& 0xff00) | ((fdata
<< 16) &
1179 0xff0000) | ((fdata
>> 16) & 0xff));
1180 ret
= qla24xx_erase_sector(vha
, fdata
);
1181 if (ret
!= QLA_SUCCESS
) {
1182 ql_dbg(ql_dbg_user
, vha
, 0x7007,
1183 "Unable to erase erase sector: address=%x.\n",
1189 /* Go with burst-write. */
1190 if (optrom
&& (liter
+ OPTROM_BURST_DWORDS
) <= dwords
) {
1191 /* Copy data to DMA'ble buffer. */
1192 memcpy(optrom
, dwptr
, OPTROM_BURST_SIZE
);
1194 ret
= qla2x00_load_ram(vha
, optrom_dma
,
1195 flash_data_addr(ha
, faddr
),
1196 OPTROM_BURST_DWORDS
);
1197 if (ret
!= QLA_SUCCESS
) {
1198 ql_log(ql_log_warn
, vha
, 0x7097,
1199 "Unable to burst-write optrom segment "
1200 "(%x/%x/%llx).\n", ret
,
1201 flash_data_addr(ha
, faddr
),
1202 (unsigned long long)optrom_dma
);
1203 ql_log(ql_log_warn
, vha
, 0x7098,
1204 "Reverting to slow-write.\n");
1206 dma_free_coherent(&ha
->pdev
->dev
,
1207 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
1210 liter
+= OPTROM_BURST_DWORDS
- 1;
1211 faddr
+= OPTROM_BURST_DWORDS
- 1;
1212 dwptr
+= OPTROM_BURST_DWORDS
- 1;
1217 ret
= qla24xx_write_flash_dword(ha
,
1218 flash_data_addr(ha
, faddr
), cpu_to_le32(*dwptr
));
1219 if (ret
!= QLA_SUCCESS
) {
1220 ql_dbg(ql_dbg_user
, vha
, 0x7006,
1221 "Unable to program flash address=%x data=%x.\n",
1226 /* Do sector protect. */
1227 if (ha
->fdt_unprotect_sec_cmd
&&
1228 ((faddr
& rest_addr
) == rest_addr
))
1229 qla24xx_write_flash_dword(ha
,
1230 ha
->fdt_protect_sec_cmd
,
1231 (fdata
& 0xff00) | ((fdata
<< 16) &
1232 0xff0000) | ((fdata
>> 16) & 0xff));
1235 ret
= qla24xx_protect_flash(vha
);
1236 if (ret
!= QLA_SUCCESS
)
1237 ql_log(ql_log_warn
, vha
, 0x7099,
1238 "Unable to protect flash after update.\n");
1241 dma_free_coherent(&ha
->pdev
->dev
,
1242 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
1248 qla2x00_read_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1253 struct qla_hw_data
*ha
= vha
->hw
;
1255 /* Word reads to NVRAM via registers. */
1256 wptr
= (uint16_t *)buf
;
1257 qla2x00_lock_nvram_access(ha
);
1258 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++)
1259 wptr
[i
] = cpu_to_le16(qla2x00_get_nvram_word(ha
,
1261 qla2x00_unlock_nvram_access(ha
);
1267 qla24xx_read_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1272 struct qla_hw_data
*ha
= vha
->hw
;
1277 /* Dword reads to flash. */
1278 dwptr
= (uint32_t *)buf
;
1279 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++)
1280 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
1281 nvram_data_addr(ha
, naddr
)));
1287 qla2x00_write_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1293 unsigned long flags
;
1294 struct qla_hw_data
*ha
= vha
->hw
;
1298 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1299 qla2x00_lock_nvram_access(ha
);
1301 /* Disable NVRAM write-protection. */
1302 stat
= qla2x00_clear_nvram_protection(ha
);
1304 wptr
= (uint16_t *)buf
;
1305 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++) {
1306 qla2x00_write_nvram_word(ha
, naddr
,
1307 cpu_to_le16(*wptr
));
1311 /* Enable NVRAM write-protection. */
1312 qla2x00_set_nvram_protection(ha
, stat
);
1314 qla2x00_unlock_nvram_access(ha
);
1315 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1321 qla24xx_write_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1327 struct qla_hw_data
*ha
= vha
->hw
;
1328 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1335 /* Enable flash write. */
1336 WRT_REG_DWORD(®
->ctrl_status
,
1337 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
1338 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1340 /* Disable NVRAM write-protection. */
1341 qla24xx_write_flash_dword(ha
, nvram_conf_addr(ha
, 0x101), 0);
1342 qla24xx_write_flash_dword(ha
, nvram_conf_addr(ha
, 0x101), 0);
1344 /* Dword writes to flash. */
1345 dwptr
= (uint32_t *)buf
;
1346 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++, dwptr
++) {
1347 ret
= qla24xx_write_flash_dword(ha
,
1348 nvram_data_addr(ha
, naddr
), cpu_to_le32(*dwptr
));
1349 if (ret
!= QLA_SUCCESS
) {
1350 ql_dbg(ql_dbg_user
, vha
, 0x709a,
1351 "Unable to program nvram address=%x data=%x.\n",
1357 /* Enable NVRAM write-protection. */
1358 qla24xx_write_flash_dword(ha
, nvram_conf_addr(ha
, 0x101), 0x8c);
1360 /* Disable flash write. */
1361 WRT_REG_DWORD(®
->ctrl_status
,
1362 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
1363 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1369 qla25xx_read_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1374 struct qla_hw_data
*ha
= vha
->hw
;
1376 /* Dword reads to flash. */
1377 dwptr
= (uint32_t *)buf
;
1378 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++)
1379 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
1380 flash_data_addr(ha
, ha
->flt_region_vpd_nvram
| naddr
)));
1386 qla25xx_write_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1389 struct qla_hw_data
*ha
= vha
->hw
;
1390 #define RMW_BUFFER_SIZE (64 * 1024)
1393 dbuf
= vmalloc(RMW_BUFFER_SIZE
);
1395 return QLA_MEMORY_ALLOC_FAILED
;
1396 ha
->isp_ops
->read_optrom(vha
, dbuf
, ha
->flt_region_vpd_nvram
<< 2,
1398 memcpy(dbuf
+ (naddr
<< 2), buf
, bytes
);
1399 ha
->isp_ops
->write_optrom(vha
, dbuf
, ha
->flt_region_vpd_nvram
<< 2,
1407 qla2x00_flip_colors(struct qla_hw_data
*ha
, uint16_t *pflags
)
1409 if (IS_QLA2322(ha
)) {
1410 /* Flip all colors. */
1411 if (ha
->beacon_color_state
== QLA_LED_ALL_ON
) {
1413 ha
->beacon_color_state
= 0;
1414 *pflags
= GPIO_LED_ALL_OFF
;
1417 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1418 *pflags
= GPIO_LED_RGA_ON
;
1421 /* Flip green led only. */
1422 if (ha
->beacon_color_state
== QLA_LED_GRN_ON
) {
1424 ha
->beacon_color_state
= 0;
1425 *pflags
= GPIO_LED_GREEN_OFF_AMBER_OFF
;
1428 ha
->beacon_color_state
= QLA_LED_GRN_ON
;
1429 *pflags
= GPIO_LED_GREEN_ON_AMBER_OFF
;
1434 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1437 qla2x00_beacon_blink(struct scsi_qla_host
*vha
)
1439 uint16_t gpio_enable
;
1441 uint16_t led_color
= 0;
1442 unsigned long flags
;
1443 struct qla_hw_data
*ha
= vha
->hw
;
1444 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1449 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1451 /* Save the Original GPIOE. */
1452 if (ha
->pio_address
) {
1453 gpio_enable
= RD_REG_WORD_PIO(PIO_REG(ha
, gpioe
));
1454 gpio_data
= RD_REG_WORD_PIO(PIO_REG(ha
, gpiod
));
1456 gpio_enable
= RD_REG_WORD(®
->gpioe
);
1457 gpio_data
= RD_REG_WORD(®
->gpiod
);
1460 /* Set the modified gpio_enable values */
1461 gpio_enable
|= GPIO_LED_MASK
;
1463 if (ha
->pio_address
) {
1464 WRT_REG_WORD_PIO(PIO_REG(ha
, gpioe
), gpio_enable
);
1466 WRT_REG_WORD(®
->gpioe
, gpio_enable
);
1467 RD_REG_WORD(®
->gpioe
);
1470 qla2x00_flip_colors(ha
, &led_color
);
1472 /* Clear out any previously set LED color. */
1473 gpio_data
&= ~GPIO_LED_MASK
;
1475 /* Set the new input LED color to GPIOD. */
1476 gpio_data
|= led_color
;
1478 /* Set the modified gpio_data values */
1479 if (ha
->pio_address
) {
1480 WRT_REG_WORD_PIO(PIO_REG(ha
, gpiod
), gpio_data
);
1482 WRT_REG_WORD(®
->gpiod
, gpio_data
);
1483 RD_REG_WORD(®
->gpiod
);
1486 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1490 qla2x00_beacon_on(struct scsi_qla_host
*vha
)
1492 uint16_t gpio_enable
;
1494 unsigned long flags
;
1495 struct qla_hw_data
*ha
= vha
->hw
;
1496 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1498 ha
->fw_options
[1] &= ~FO1_SET_EMPHASIS_SWING
;
1499 ha
->fw_options
[1] |= FO1_DISABLE_GPIO6_7
;
1501 if (qla2x00_set_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
) {
1502 ql_log(ql_log_warn
, vha
, 0x709b,
1503 "Unable to update fw options (beacon on).\n");
1504 return QLA_FUNCTION_FAILED
;
1507 /* Turn off LEDs. */
1508 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1509 if (ha
->pio_address
) {
1510 gpio_enable
= RD_REG_WORD_PIO(PIO_REG(ha
, gpioe
));
1511 gpio_data
= RD_REG_WORD_PIO(PIO_REG(ha
, gpiod
));
1513 gpio_enable
= RD_REG_WORD(®
->gpioe
);
1514 gpio_data
= RD_REG_WORD(®
->gpiod
);
1516 gpio_enable
|= GPIO_LED_MASK
;
1518 /* Set the modified gpio_enable values. */
1519 if (ha
->pio_address
) {
1520 WRT_REG_WORD_PIO(PIO_REG(ha
, gpioe
), gpio_enable
);
1522 WRT_REG_WORD(®
->gpioe
, gpio_enable
);
1523 RD_REG_WORD(®
->gpioe
);
1526 /* Clear out previously set LED colour. */
1527 gpio_data
&= ~GPIO_LED_MASK
;
1528 if (ha
->pio_address
) {
1529 WRT_REG_WORD_PIO(PIO_REG(ha
, gpiod
), gpio_data
);
1531 WRT_REG_WORD(®
->gpiod
, gpio_data
);
1532 RD_REG_WORD(®
->gpiod
);
1534 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1537 * Let the per HBA timer kick off the blinking process based on
1538 * the following flags. No need to do anything else now.
1540 ha
->beacon_blink_led
= 1;
1541 ha
->beacon_color_state
= 0;
1547 qla2x00_beacon_off(struct scsi_qla_host
*vha
)
1549 int rval
= QLA_SUCCESS
;
1550 struct qla_hw_data
*ha
= vha
->hw
;
1552 ha
->beacon_blink_led
= 0;
1554 /* Set the on flag so when it gets flipped it will be off. */
1556 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1558 ha
->beacon_color_state
= QLA_LED_GRN_ON
;
1560 ha
->isp_ops
->beacon_blink(vha
); /* This turns green LED off */
1562 ha
->fw_options
[1] &= ~FO1_SET_EMPHASIS_SWING
;
1563 ha
->fw_options
[1] &= ~FO1_DISABLE_GPIO6_7
;
1565 rval
= qla2x00_set_fw_options(vha
, ha
->fw_options
);
1566 if (rval
!= QLA_SUCCESS
)
1567 ql_log(ql_log_warn
, vha
, 0x709c,
1568 "Unable to update fw options (beacon off).\n");
1574 qla24xx_flip_colors(struct qla_hw_data
*ha
, uint16_t *pflags
)
1576 /* Flip all colors. */
1577 if (ha
->beacon_color_state
== QLA_LED_ALL_ON
) {
1579 ha
->beacon_color_state
= 0;
1583 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1584 *pflags
= GPDX_LED_YELLOW_ON
| GPDX_LED_AMBER_ON
;
1589 qla24xx_beacon_blink(struct scsi_qla_host
*vha
)
1591 uint16_t led_color
= 0;
1593 unsigned long flags
;
1594 struct qla_hw_data
*ha
= vha
->hw
;
1595 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1597 /* Save the Original GPIOD. */
1598 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1599 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1601 /* Enable the gpio_data reg for update. */
1602 gpio_data
|= GPDX_LED_UPDATE_MASK
;
1604 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1605 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1607 /* Set the color bits. */
1608 qla24xx_flip_colors(ha
, &led_color
);
1610 /* Clear out any previously set LED color. */
1611 gpio_data
&= ~GPDX_LED_COLOR_MASK
;
1613 /* Set the new input LED color to GPIOD. */
1614 gpio_data
|= led_color
;
1616 /* Set the modified gpio_data values. */
1617 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1618 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1619 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1623 qla24xx_beacon_on(struct scsi_qla_host
*vha
)
1626 unsigned long flags
;
1627 struct qla_hw_data
*ha
= vha
->hw
;
1628 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1633 if (ha
->beacon_blink_led
== 0) {
1634 /* Enable firmware for update */
1635 ha
->fw_options
[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL
;
1637 if (qla2x00_set_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
)
1638 return QLA_FUNCTION_FAILED
;
1640 if (qla2x00_get_fw_options(vha
, ha
->fw_options
) !=
1642 ql_log(ql_log_warn
, vha
, 0x7009,
1643 "Unable to update fw options (beacon on).\n");
1644 return QLA_FUNCTION_FAILED
;
1647 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1648 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1650 /* Enable the gpio_data reg for update. */
1651 gpio_data
|= GPDX_LED_UPDATE_MASK
;
1652 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1653 RD_REG_DWORD(®
->gpiod
);
1655 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1658 /* So all colors blink together. */
1659 ha
->beacon_color_state
= 0;
1661 /* Let the per HBA timer kick off the blinking process. */
1662 ha
->beacon_blink_led
= 1;
1668 qla24xx_beacon_off(struct scsi_qla_host
*vha
)
1671 unsigned long flags
;
1672 struct qla_hw_data
*ha
= vha
->hw
;
1673 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1678 ha
->beacon_blink_led
= 0;
1679 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1681 ha
->isp_ops
->beacon_blink(vha
); /* Will flip to all off. */
1683 /* Give control back to firmware. */
1684 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1685 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1687 /* Disable the gpio_data reg for update. */
1688 gpio_data
&= ~GPDX_LED_UPDATE_MASK
;
1689 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1690 RD_REG_DWORD(®
->gpiod
);
1691 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1693 ha
->fw_options
[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL
;
1695 if (qla2x00_set_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
) {
1696 ql_log(ql_log_warn
, vha
, 0x704d,
1697 "Unable to update fw options (beacon on).\n");
1698 return QLA_FUNCTION_FAILED
;
1701 if (qla2x00_get_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
) {
1702 ql_log(ql_log_warn
, vha
, 0x704e,
1703 "Unable to update fw options (beacon on).\n");
1704 return QLA_FUNCTION_FAILED
;
1712 * Flash support routines
1716 * qla2x00_flash_enable() - Setup flash for reading and writing.
1720 qla2x00_flash_enable(struct qla_hw_data
*ha
)
1723 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1725 data
= RD_REG_WORD(®
->ctrl_status
);
1726 data
|= CSR_FLASH_ENABLE
;
1727 WRT_REG_WORD(®
->ctrl_status
, data
);
1728 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1732 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1736 qla2x00_flash_disable(struct qla_hw_data
*ha
)
1739 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1741 data
= RD_REG_WORD(®
->ctrl_status
);
1742 data
&= ~(CSR_FLASH_ENABLE
);
1743 WRT_REG_WORD(®
->ctrl_status
, data
);
1744 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1748 * qla2x00_read_flash_byte() - Reads a byte from flash
1750 * @addr: Address in flash to read
1752 * A word is read from the chip, but, only the lower byte is valid.
1754 * Returns the byte read from flash @addr.
1757 qla2x00_read_flash_byte(struct qla_hw_data
*ha
, uint32_t addr
)
1760 uint16_t bank_select
;
1761 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1763 bank_select
= RD_REG_WORD(®
->ctrl_status
);
1765 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1766 /* Specify 64K address range: */
1767 /* clear out Module Select and Flash Address bits [19:16]. */
1768 bank_select
&= ~0xf8;
1769 bank_select
|= addr
>> 12 & 0xf0;
1770 bank_select
|= CSR_FLASH_64K_BANK
;
1771 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1772 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1774 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1775 data
= RD_REG_WORD(®
->flash_data
);
1777 return (uint8_t)data
;
1780 /* Setup bit 16 of flash address. */
1781 if ((addr
& BIT_16
) && ((bank_select
& CSR_FLASH_64K_BANK
) == 0)) {
1782 bank_select
|= CSR_FLASH_64K_BANK
;
1783 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1784 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1785 } else if (((addr
& BIT_16
) == 0) &&
1786 (bank_select
& CSR_FLASH_64K_BANK
)) {
1787 bank_select
&= ~(CSR_FLASH_64K_BANK
);
1788 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1789 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1792 /* Always perform IO mapped accesses to the FLASH registers. */
1793 if (ha
->pio_address
) {
1796 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_address
), (uint16_t)addr
);
1798 data
= RD_REG_WORD_PIO(PIO_REG(ha
, flash_data
));
1801 data2
= RD_REG_WORD_PIO(PIO_REG(ha
, flash_data
));
1802 } while (data
!= data2
);
1804 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1805 data
= qla2x00_debounce_register(®
->flash_data
);
1808 return (uint8_t)data
;
1812 * qla2x00_write_flash_byte() - Write a byte to flash
1814 * @addr: Address in flash to write
1815 * @data: Data to write
1818 qla2x00_write_flash_byte(struct qla_hw_data
*ha
, uint32_t addr
, uint8_t data
)
1820 uint16_t bank_select
;
1821 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1823 bank_select
= RD_REG_WORD(®
->ctrl_status
);
1824 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1825 /* Specify 64K address range: */
1826 /* clear out Module Select and Flash Address bits [19:16]. */
1827 bank_select
&= ~0xf8;
1828 bank_select
|= addr
>> 12 & 0xf0;
1829 bank_select
|= CSR_FLASH_64K_BANK
;
1830 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1831 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1833 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1834 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1835 WRT_REG_WORD(®
->flash_data
, (uint16_t)data
);
1836 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1841 /* Setup bit 16 of flash address. */
1842 if ((addr
& BIT_16
) && ((bank_select
& CSR_FLASH_64K_BANK
) == 0)) {
1843 bank_select
|= CSR_FLASH_64K_BANK
;
1844 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1845 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1846 } else if (((addr
& BIT_16
) == 0) &&
1847 (bank_select
& CSR_FLASH_64K_BANK
)) {
1848 bank_select
&= ~(CSR_FLASH_64K_BANK
);
1849 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1850 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1853 /* Always perform IO mapped accesses to the FLASH registers. */
1854 if (ha
->pio_address
) {
1855 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_address
), (uint16_t)addr
);
1856 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_data
), (uint16_t)data
);
1858 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1859 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1860 WRT_REG_WORD(®
->flash_data
, (uint16_t)data
);
1861 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1866 * qla2x00_poll_flash() - Polls flash for completion.
1868 * @addr: Address in flash to poll
1869 * @poll_data: Data to be polled
1870 * @man_id: Flash manufacturer ID
1871 * @flash_id: Flash ID
1873 * This function polls the device until bit 7 of what is read matches data
1874 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1875 * out (a fatal error). The flash book recommeds reading bit 7 again after
1876 * reading bit 5 as a 1.
1878 * Returns 0 on success, else non-zero.
1881 qla2x00_poll_flash(struct qla_hw_data
*ha
, uint32_t addr
, uint8_t poll_data
,
1882 uint8_t man_id
, uint8_t flash_id
)
1890 /* Wait for 30 seconds for command to finish. */
1892 for (cnt
= 3000000; cnt
; cnt
--) {
1893 flash_data
= qla2x00_read_flash_byte(ha
, addr
);
1894 if ((flash_data
& BIT_7
) == poll_data
) {
1899 if (man_id
!= 0x40 && man_id
!= 0xda) {
1900 if ((flash_data
& BIT_5
) && cnt
> 2)
1911 * qla2x00_program_flash_address() - Programs a flash address
1913 * @addr: Address in flash to program
1914 * @data: Data to be written in flash
1915 * @man_id: Flash manufacturer ID
1916 * @flash_id: Flash ID
1918 * Returns 0 on success, else non-zero.
1921 qla2x00_program_flash_address(struct qla_hw_data
*ha
, uint32_t addr
,
1922 uint8_t data
, uint8_t man_id
, uint8_t flash_id
)
1924 /* Write Program Command Sequence. */
1925 if (IS_OEM_001(ha
)) {
1926 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1927 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1928 qla2x00_write_flash_byte(ha
, 0xaaa, 0xa0);
1929 qla2x00_write_flash_byte(ha
, addr
, data
);
1931 if (man_id
== 0xda && flash_id
== 0xc1) {
1932 qla2x00_write_flash_byte(ha
, addr
, data
);
1936 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1937 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1938 qla2x00_write_flash_byte(ha
, 0x5555, 0xa0);
1939 qla2x00_write_flash_byte(ha
, addr
, data
);
1945 /* Wait for write to complete. */
1946 return qla2x00_poll_flash(ha
, addr
, data
, man_id
, flash_id
);
1950 * qla2x00_erase_flash() - Erase the flash.
1952 * @man_id: Flash manufacturer ID
1953 * @flash_id: Flash ID
1955 * Returns 0 on success, else non-zero.
1958 qla2x00_erase_flash(struct qla_hw_data
*ha
, uint8_t man_id
, uint8_t flash_id
)
1960 /* Individual Sector Erase Command Sequence */
1961 if (IS_OEM_001(ha
)) {
1962 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1963 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1964 qla2x00_write_flash_byte(ha
, 0xaaa, 0x80);
1965 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1966 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1967 qla2x00_write_flash_byte(ha
, 0xaaa, 0x10);
1969 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1970 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1971 qla2x00_write_flash_byte(ha
, 0x5555, 0x80);
1972 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1973 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1974 qla2x00_write_flash_byte(ha
, 0x5555, 0x10);
1979 /* Wait for erase to complete. */
1980 return qla2x00_poll_flash(ha
, 0x00, 0x80, man_id
, flash_id
);
1984 * qla2x00_erase_flash_sector() - Erase a flash sector.
1986 * @addr: Flash sector to erase
1987 * @sec_mask: Sector address mask
1988 * @man_id: Flash manufacturer ID
1989 * @flash_id: Flash ID
1991 * Returns 0 on success, else non-zero.
1994 qla2x00_erase_flash_sector(struct qla_hw_data
*ha
, uint32_t addr
,
1995 uint32_t sec_mask
, uint8_t man_id
, uint8_t flash_id
)
1997 /* Individual Sector Erase Command Sequence */
1998 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1999 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
2000 qla2x00_write_flash_byte(ha
, 0x5555, 0x80);
2001 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
2002 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
2003 if (man_id
== 0x1f && flash_id
== 0x13)
2004 qla2x00_write_flash_byte(ha
, addr
& sec_mask
, 0x10);
2006 qla2x00_write_flash_byte(ha
, addr
& sec_mask
, 0x30);
2010 /* Wait for erase to complete. */
2011 return qla2x00_poll_flash(ha
, addr
, 0x80, man_id
, flash_id
);
2015 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2016 * @man_id: Flash manufacturer ID
2017 * @flash_id: Flash ID
2020 qla2x00_get_flash_manufacturer(struct qla_hw_data
*ha
, uint8_t *man_id
,
2023 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
2024 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
2025 qla2x00_write_flash_byte(ha
, 0x5555, 0x90);
2026 *man_id
= qla2x00_read_flash_byte(ha
, 0x0000);
2027 *flash_id
= qla2x00_read_flash_byte(ha
, 0x0001);
2028 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
2029 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
2030 qla2x00_write_flash_byte(ha
, 0x5555, 0xf0);
2034 qla2x00_read_flash_data(struct qla_hw_data
*ha
, uint8_t *tmp_buf
,
2035 uint32_t saddr
, uint32_t length
)
2037 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
2038 uint32_t midpoint
, ilength
;
2041 midpoint
= length
/ 2;
2043 WRT_REG_WORD(®
->nvram
, 0);
2044 RD_REG_WORD(®
->nvram
);
2045 for (ilength
= 0; ilength
< length
; saddr
++, ilength
++, tmp_buf
++) {
2046 if (ilength
== midpoint
) {
2047 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
2048 RD_REG_WORD(®
->nvram
);
2050 data
= qla2x00_read_flash_byte(ha
, saddr
);
2059 qla2x00_suspend_hba(struct scsi_qla_host
*vha
)
2062 unsigned long flags
;
2063 struct qla_hw_data
*ha
= vha
->hw
;
2064 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
2067 scsi_block_requests(vha
->host
);
2068 ha
->isp_ops
->disable_intrs(ha
);
2069 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2072 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2073 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
2074 RD_REG_WORD(®
->hccr
);
2075 if (IS_QLA2100(ha
) || IS_QLA2200(ha
) || IS_QLA2300(ha
)) {
2076 for (cnt
= 0; cnt
< 30000; cnt
++) {
2077 if ((RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) != 0)
2084 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2088 qla2x00_resume_hba(struct scsi_qla_host
*vha
)
2090 struct qla_hw_data
*ha
= vha
->hw
;
2093 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2094 set_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
);
2095 qla2xxx_wake_dpc(vha
);
2096 qla2x00_wait_for_chip_reset(vha
);
2097 scsi_unblock_requests(vha
->host
);
2101 qla2x00_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2102 uint32_t offset
, uint32_t length
)
2104 uint32_t addr
, midpoint
;
2106 struct qla_hw_data
*ha
= vha
->hw
;
2107 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
2110 qla2x00_suspend_hba(vha
);
2113 midpoint
= ha
->optrom_size
/ 2;
2115 qla2x00_flash_enable(ha
);
2116 WRT_REG_WORD(®
->nvram
, 0);
2117 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
2118 for (addr
= offset
, data
= buf
; addr
< length
; addr
++, data
++) {
2119 if (addr
== midpoint
) {
2120 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
2121 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
2124 *data
= qla2x00_read_flash_byte(ha
, addr
);
2126 qla2x00_flash_disable(ha
);
2129 qla2x00_resume_hba(vha
);
2135 qla2x00_write_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2136 uint32_t offset
, uint32_t length
)
2140 uint8_t man_id
, flash_id
, sec_number
, data
;
2142 uint32_t addr
, liter
, sec_mask
, rest_addr
;
2143 struct qla_hw_data
*ha
= vha
->hw
;
2144 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
2147 qla2x00_suspend_hba(vha
);
2152 /* Reset ISP chip. */
2153 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
2154 pci_read_config_word(ha
->pdev
, PCI_COMMAND
, &wd
);
2156 /* Go with write. */
2157 qla2x00_flash_enable(ha
);
2158 do { /* Loop once to provide quick error exit */
2159 /* Structure of flash memory based on manufacturer */
2160 if (IS_OEM_001(ha
)) {
2161 /* OEM variant with special flash part. */
2162 man_id
= flash_id
= 0;
2167 qla2x00_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
2169 case 0x20: /* ST flash. */
2170 if (flash_id
== 0xd2 || flash_id
== 0xe3) {
2172 * ST m29w008at part - 64kb sector size with
2173 * 32kb,8kb,8kb,16kb sectors at memory address
2181 * ST m29w010b part - 16kb sector size
2182 * Default to 16kb sectors
2187 case 0x40: /* Mostel flash. */
2188 /* Mostel v29c51001 part - 512 byte sector size. */
2192 case 0xbf: /* SST flash. */
2193 /* SST39sf10 part - 4kb sector size. */
2197 case 0xda: /* Winbond flash. */
2198 /* Winbond W29EE011 part - 256 byte sector size. */
2202 case 0xc2: /* Macronix flash. */
2203 /* 64k sector size. */
2204 if (flash_id
== 0x38 || flash_id
== 0x4f) {
2209 /* Fall through... */
2211 case 0x1f: /* Atmel flash. */
2212 /* 512k sector size. */
2213 if (flash_id
== 0x13) {
2214 rest_addr
= 0x7fffffff;
2215 sec_mask
= 0x80000000;
2218 /* Fall through... */
2220 case 0x01: /* AMD flash. */
2221 if (flash_id
== 0x38 || flash_id
== 0x40 ||
2223 /* Am29LV081 part - 64kb sector size. */
2224 /* Am29LV002BT part - 64kb sector size. */
2228 } else if (flash_id
== 0x3e) {
2230 * Am29LV008b part - 64kb sector size with
2231 * 32kb,8kb,8kb,16kb sector at memory address
2237 } else if (flash_id
== 0x20 || flash_id
== 0x6e) {
2239 * Am29LV010 part or AM29f010 - 16kb sector
2245 } else if (flash_id
== 0x6d) {
2246 /* Am29LV001 part - 8kb sector size. */
2252 /* Default to 16 kb sector size. */
2259 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
2260 if (qla2x00_erase_flash(ha
, man_id
, flash_id
)) {
2261 rval
= QLA_FUNCTION_FAILED
;
2266 for (addr
= offset
, liter
= 0; liter
< length
; liter
++,
2269 /* Are we at the beginning of a sector? */
2270 if ((addr
& rest_addr
) == 0) {
2271 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
2272 if (addr
>= 0x10000UL
) {
2273 if (((addr
>> 12) & 0xf0) &&
2275 flash_id
== 0x3e) ||
2277 flash_id
== 0xd2))) {
2279 if (sec_number
== 1) {
2300 } else if (addr
== ha
->optrom_size
/ 2) {
2301 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
2302 RD_REG_WORD(®
->nvram
);
2305 if (flash_id
== 0xda && man_id
== 0xc1) {
2306 qla2x00_write_flash_byte(ha
, 0x5555,
2308 qla2x00_write_flash_byte(ha
, 0x2aaa,
2310 qla2x00_write_flash_byte(ha
, 0x5555,
2312 } else if (!IS_QLA2322(ha
) && !IS_QLA6322(ha
)) {
2314 if (qla2x00_erase_flash_sector(ha
,
2315 addr
, sec_mask
, man_id
,
2317 rval
= QLA_FUNCTION_FAILED
;
2320 if (man_id
== 0x01 && flash_id
== 0x6d)
2325 if (man_id
== 0x01 && flash_id
== 0x6d) {
2326 if (sec_number
== 1 &&
2327 addr
== (rest_addr
- 1)) {
2330 } else if (sec_number
== 3 && (addr
& 0x7ffe)) {
2336 if (qla2x00_program_flash_address(ha
, addr
, data
,
2337 man_id
, flash_id
)) {
2338 rval
= QLA_FUNCTION_FAILED
;
2344 qla2x00_flash_disable(ha
);
2347 qla2x00_resume_hba(vha
);
2353 qla24xx_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2354 uint32_t offset
, uint32_t length
)
2356 struct qla_hw_data
*ha
= vha
->hw
;
2359 scsi_block_requests(vha
->host
);
2360 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2363 qla24xx_read_flash_data(vha
, (uint32_t *)buf
, offset
>> 2, length
>> 2);
2366 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2367 scsi_unblock_requests(vha
->host
);
2373 qla24xx_write_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2374 uint32_t offset
, uint32_t length
)
2377 struct qla_hw_data
*ha
= vha
->hw
;
2380 scsi_block_requests(vha
->host
);
2381 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2383 /* Go with write. */
2384 rval
= qla24xx_write_flash_data(vha
, (uint32_t *)buf
, offset
>> 2,
2387 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2388 scsi_unblock_requests(vha
->host
);
2394 qla25xx_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2395 uint32_t offset
, uint32_t length
)
2398 dma_addr_t optrom_dma
;
2401 uint32_t faddr
, left
, burst
;
2402 struct qla_hw_data
*ha
= vha
->hw
;
2404 if (IS_QLA25XX(ha
) || IS_QLA81XX(ha
))
2408 if (length
< OPTROM_BURST_SIZE
)
2412 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
2413 &optrom_dma
, GFP_KERNEL
);
2415 ql_log(ql_log_warn
, vha
, 0x00cc,
2416 "Unable to allocate memory for optrom burst read (%x KB).\n",
2417 OPTROM_BURST_SIZE
/ 1024);
2422 faddr
= offset
>> 2;
2424 burst
= OPTROM_BURST_DWORDS
;
2429 rval
= qla2x00_dump_ram(vha
, optrom_dma
,
2430 flash_data_addr(ha
, faddr
), burst
);
2432 ql_log(ql_log_warn
, vha
, 0x00f5,
2433 "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2434 rval
, flash_data_addr(ha
, faddr
),
2435 (unsigned long long)optrom_dma
);
2436 ql_log(ql_log_warn
, vha
, 0x00f6,
2437 "Reverting to slow-read.\n");
2439 dma_free_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
2440 optrom
, optrom_dma
);
2444 memcpy(pbuf
, optrom
, burst
* 4);
2451 dma_free_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
, optrom
,
2457 return qla24xx_read_optrom_data(vha
, buf
, offset
, length
);
2461 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2463 * @pcids: Pointer to the FCODE PCI data structure
2465 * The process of retrieving the FCODE version information is at best
2466 * described as interesting.
2468 * Within the first 100h bytes of the image an ASCII string is present
2469 * which contains several pieces of information including the FCODE
2470 * version. Unfortunately it seems the only reliable way to retrieve
2471 * the version is by scanning for another sentinel within the string,
2472 * the FCODE build date:
2474 * ... 2.00.02 10/17/02 ...
2476 * Returns QLA_SUCCESS on successful retrieval of version.
2479 qla2x00_get_fcode_version(struct qla_hw_data
*ha
, uint32_t pcids
)
2481 int ret
= QLA_FUNCTION_FAILED
;
2482 uint32_t istart
, iend
, iter
, vend
;
2483 uint8_t do_next
, rbyte
, *vbyte
;
2485 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2487 /* Skip the PCI data structure. */
2489 ((qla2x00_read_flash_byte(ha
, pcids
+ 0x0B) << 8) |
2490 qla2x00_read_flash_byte(ha
, pcids
+ 0x0A));
2491 iend
= istart
+ 0x100;
2493 /* Scan for the sentinel date string...eeewww. */
2496 while ((iter
< iend
) && !do_next
) {
2498 if (qla2x00_read_flash_byte(ha
, iter
) == '/') {
2499 if (qla2x00_read_flash_byte(ha
, iter
+ 2) ==
2502 else if (qla2x00_read_flash_byte(ha
,
2510 /* Backtrack to previous ' ' (space). */
2512 while ((iter
> istart
) && !do_next
) {
2514 if (qla2x00_read_flash_byte(ha
, iter
) == ' ')
2521 * Mark end of version tag, and find previous ' ' (space) or
2522 * string length (recent FCODE images -- major hack ahead!!!).
2526 while ((iter
> istart
) && !do_next
) {
2528 rbyte
= qla2x00_read_flash_byte(ha
, iter
);
2529 if (rbyte
== ' ' || rbyte
== 0xd || rbyte
== 0x10)
2535 /* Mark beginning of version tag, and copy data. */
2537 if ((vend
- iter
) &&
2538 ((vend
- iter
) < sizeof(ha
->fcode_revision
))) {
2539 vbyte
= ha
->fcode_revision
;
2540 while (iter
<= vend
) {
2541 *vbyte
++ = qla2x00_read_flash_byte(ha
, iter
);
2548 if (ret
!= QLA_SUCCESS
)
2549 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2553 qla2x00_get_flash_version(scsi_qla_host_t
*vha
, void *mbuf
)
2555 int ret
= QLA_SUCCESS
;
2556 uint8_t code_type
, last_image
;
2557 uint32_t pcihdr
, pcids
;
2560 struct qla_hw_data
*ha
= vha
->hw
;
2562 if (!ha
->pio_address
|| !mbuf
)
2563 return QLA_FUNCTION_FAILED
;
2565 memset(ha
->bios_revision
, 0, sizeof(ha
->bios_revision
));
2566 memset(ha
->efi_revision
, 0, sizeof(ha
->efi_revision
));
2567 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2568 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2570 qla2x00_flash_enable(ha
);
2572 /* Begin with first PCI expansion ROM header. */
2576 /* Verify PCI expansion ROM header. */
2577 if (qla2x00_read_flash_byte(ha
, pcihdr
) != 0x55 ||
2578 qla2x00_read_flash_byte(ha
, pcihdr
+ 0x01) != 0xaa) {
2580 ql_log(ql_log_fatal
, vha
, 0x0050,
2581 "No matching ROM signature.\n");
2582 ret
= QLA_FUNCTION_FAILED
;
2586 /* Locate PCI data structure. */
2588 ((qla2x00_read_flash_byte(ha
, pcihdr
+ 0x19) << 8) |
2589 qla2x00_read_flash_byte(ha
, pcihdr
+ 0x18));
2591 /* Validate signature of PCI data structure. */
2592 if (qla2x00_read_flash_byte(ha
, pcids
) != 'P' ||
2593 qla2x00_read_flash_byte(ha
, pcids
+ 0x1) != 'C' ||
2594 qla2x00_read_flash_byte(ha
, pcids
+ 0x2) != 'I' ||
2595 qla2x00_read_flash_byte(ha
, pcids
+ 0x3) != 'R') {
2596 /* Incorrect header. */
2597 ql_log(ql_log_fatal
, vha
, 0x0051,
2598 "PCI data struct not found pcir_adr=%x.\n", pcids
);
2599 ret
= QLA_FUNCTION_FAILED
;
2604 code_type
= qla2x00_read_flash_byte(ha
, pcids
+ 0x14);
2605 switch (code_type
) {
2606 case ROM_CODE_TYPE_BIOS
:
2607 /* Intel x86, PC-AT compatible. */
2608 ha
->bios_revision
[0] =
2609 qla2x00_read_flash_byte(ha
, pcids
+ 0x12);
2610 ha
->bios_revision
[1] =
2611 qla2x00_read_flash_byte(ha
, pcids
+ 0x13);
2612 ql_dbg(ql_dbg_init
, vha
, 0x0052,
2613 "Read BIOS %d.%d.\n",
2614 ha
->bios_revision
[1], ha
->bios_revision
[0]);
2616 case ROM_CODE_TYPE_FCODE
:
2617 /* Open Firmware standard for PCI (FCode). */
2619 qla2x00_get_fcode_version(ha
, pcids
);
2621 case ROM_CODE_TYPE_EFI
:
2622 /* Extensible Firmware Interface (EFI). */
2623 ha
->efi_revision
[0] =
2624 qla2x00_read_flash_byte(ha
, pcids
+ 0x12);
2625 ha
->efi_revision
[1] =
2626 qla2x00_read_flash_byte(ha
, pcids
+ 0x13);
2627 ql_dbg(ql_dbg_init
, vha
, 0x0053,
2628 "Read EFI %d.%d.\n",
2629 ha
->efi_revision
[1], ha
->efi_revision
[0]);
2632 ql_log(ql_log_warn
, vha
, 0x0054,
2633 "Unrecognized code type %x at pcids %x.\n",
2638 last_image
= qla2x00_read_flash_byte(ha
, pcids
+ 0x15) & BIT_7
;
2640 /* Locate next PCI expansion ROM. */
2641 pcihdr
+= ((qla2x00_read_flash_byte(ha
, pcids
+ 0x11) << 8) |
2642 qla2x00_read_flash_byte(ha
, pcids
+ 0x10)) * 512;
2643 } while (!last_image
);
2645 if (IS_QLA2322(ha
)) {
2646 /* Read firmware image information. */
2647 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2649 memset(dbyte
, 0, 8);
2650 dcode
= (uint16_t *)dbyte
;
2652 qla2x00_read_flash_data(ha
, dbyte
, ha
->flt_region_fw
* 4 + 10,
2654 ql_dbg(ql_dbg_init
+ ql_dbg_buffer
, vha
, 0x010a,
2656 "ver from flash:.\n");
2657 ql_dump_buffer(ql_dbg_init
+ ql_dbg_buffer
, vha
, 0x010b,
2658 (uint8_t *)dbyte
, 8);
2660 if ((dcode
[0] == 0xffff && dcode
[1] == 0xffff &&
2661 dcode
[2] == 0xffff && dcode
[3] == 0xffff) ||
2662 (dcode
[0] == 0 && dcode
[1] == 0 && dcode
[2] == 0 &&
2664 ql_log(ql_log_warn
, vha
, 0x0057,
2665 "Unrecognized fw revision at %x.\n",
2666 ha
->flt_region_fw
* 4);
2668 /* values are in big endian */
2669 ha
->fw_revision
[0] = dbyte
[0] << 16 | dbyte
[1];
2670 ha
->fw_revision
[1] = dbyte
[2] << 16 | dbyte
[3];
2671 ha
->fw_revision
[2] = dbyte
[4] << 16 | dbyte
[5];
2672 ql_dbg(ql_dbg_init
, vha
, 0x0058,
2674 "%d.%d.%d.\n", ha
->fw_revision
[0],
2675 ha
->fw_revision
[1], ha
->fw_revision
[2]);
2679 qla2x00_flash_disable(ha
);
2685 qla24xx_get_flash_version(scsi_qla_host_t
*vha
, void *mbuf
)
2687 int ret
= QLA_SUCCESS
;
2688 uint32_t pcihdr
, pcids
;
2691 uint8_t code_type
, last_image
;
2693 struct qla_hw_data
*ha
= vha
->hw
;
2699 return QLA_FUNCTION_FAILED
;
2701 memset(ha
->bios_revision
, 0, sizeof(ha
->bios_revision
));
2702 memset(ha
->efi_revision
, 0, sizeof(ha
->efi_revision
));
2703 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2704 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2708 /* Begin with first PCI expansion ROM header. */
2709 pcihdr
= ha
->flt_region_boot
<< 2;
2712 /* Verify PCI expansion ROM header. */
2713 qla24xx_read_flash_data(vha
, dcode
, pcihdr
>> 2, 0x20);
2714 bcode
= mbuf
+ (pcihdr
% 4);
2715 if (bcode
[0x0] != 0x55 || bcode
[0x1] != 0xaa) {
2717 ql_log(ql_log_fatal
, vha
, 0x0059,
2718 "No matching ROM signature.\n");
2719 ret
= QLA_FUNCTION_FAILED
;
2723 /* Locate PCI data structure. */
2724 pcids
= pcihdr
+ ((bcode
[0x19] << 8) | bcode
[0x18]);
2726 qla24xx_read_flash_data(vha
, dcode
, pcids
>> 2, 0x20);
2727 bcode
= mbuf
+ (pcihdr
% 4);
2729 /* Validate signature of PCI data structure. */
2730 if (bcode
[0x0] != 'P' || bcode
[0x1] != 'C' ||
2731 bcode
[0x2] != 'I' || bcode
[0x3] != 'R') {
2732 /* Incorrect header. */
2733 ql_log(ql_log_fatal
, vha
, 0x005a,
2734 "PCI data struct not found pcir_adr=%x.\n", pcids
);
2735 ret
= QLA_FUNCTION_FAILED
;
2740 code_type
= bcode
[0x14];
2741 switch (code_type
) {
2742 case ROM_CODE_TYPE_BIOS
:
2743 /* Intel x86, PC-AT compatible. */
2744 ha
->bios_revision
[0] = bcode
[0x12];
2745 ha
->bios_revision
[1] = bcode
[0x13];
2746 ql_dbg(ql_dbg_init
, vha
, 0x005b,
2747 "Read BIOS %d.%d.\n",
2748 ha
->bios_revision
[1], ha
->bios_revision
[0]);
2750 case ROM_CODE_TYPE_FCODE
:
2751 /* Open Firmware standard for PCI (FCode). */
2752 ha
->fcode_revision
[0] = bcode
[0x12];
2753 ha
->fcode_revision
[1] = bcode
[0x13];
2754 ql_dbg(ql_dbg_init
, vha
, 0x005c,
2755 "Read FCODE %d.%d.\n",
2756 ha
->fcode_revision
[1], ha
->fcode_revision
[0]);
2758 case ROM_CODE_TYPE_EFI
:
2759 /* Extensible Firmware Interface (EFI). */
2760 ha
->efi_revision
[0] = bcode
[0x12];
2761 ha
->efi_revision
[1] = bcode
[0x13];
2762 ql_dbg(ql_dbg_init
, vha
, 0x005d,
2763 "Read EFI %d.%d.\n",
2764 ha
->efi_revision
[1], ha
->efi_revision
[0]);
2767 ql_log(ql_log_warn
, vha
, 0x005e,
2768 "Unrecognized code type %x at pcids %x.\n",
2773 last_image
= bcode
[0x15] & BIT_7
;
2775 /* Locate next PCI expansion ROM. */
2776 pcihdr
+= ((bcode
[0x11] << 8) | bcode
[0x10]) * 512;
2777 } while (!last_image
);
2779 /* Read firmware image information. */
2780 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2783 qla24xx_read_flash_data(vha
, dcode
, ha
->flt_region_fw
+ 4, 4);
2784 for (i
= 0; i
< 4; i
++)
2785 dcode
[i
] = be32_to_cpu(dcode
[i
]);
2787 if ((dcode
[0] == 0xffffffff && dcode
[1] == 0xffffffff &&
2788 dcode
[2] == 0xffffffff && dcode
[3] == 0xffffffff) ||
2789 (dcode
[0] == 0 && dcode
[1] == 0 && dcode
[2] == 0 &&
2791 ql_log(ql_log_warn
, vha
, 0x005f,
2792 "Unrecognized fw revision at %x.\n",
2793 ha
->flt_region_fw
* 4);
2795 ha
->fw_revision
[0] = dcode
[0];
2796 ha
->fw_revision
[1] = dcode
[1];
2797 ha
->fw_revision
[2] = dcode
[2];
2798 ha
->fw_revision
[3] = dcode
[3];
2799 ql_dbg(ql_dbg_init
, vha
, 0x0060,
2800 "Firmware revision %d.%d.%d.%d.\n",
2801 ha
->fw_revision
[0], ha
->fw_revision
[1],
2802 ha
->fw_revision
[2], ha
->fw_revision
[3]);
2805 /* Check for golden firmware and get version if available */
2806 if (!IS_QLA81XX(ha
)) {
2807 /* Golden firmware is not present in non 81XX adapters */
2811 memset(ha
->gold_fw_version
, 0, sizeof(ha
->gold_fw_version
));
2813 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)dcode
,
2814 ha
->flt_region_gold_fw
<< 2, 32);
2816 if (dcode
[4] == 0xFFFFFFFF && dcode
[5] == 0xFFFFFFFF &&
2817 dcode
[6] == 0xFFFFFFFF && dcode
[7] == 0xFFFFFFFF) {
2818 ql_log(ql_log_warn
, vha
, 0x0056,
2819 "Unrecognized golden fw at 0x%x.\n",
2820 ha
->flt_region_gold_fw
* 4);
2824 for (i
= 4; i
< 8; i
++)
2825 ha
->gold_fw_version
[i
-4] = be32_to_cpu(dcode
[i
]);
2831 qla2xxx_is_vpd_valid(uint8_t *pos
, uint8_t *end
)
2833 if (pos
>= end
|| *pos
!= 0x82)
2837 if (pos
>= end
|| *pos
!= 0x90)
2841 if (pos
>= end
|| *pos
!= 0x78)
2848 qla2xxx_get_vpd_field(scsi_qla_host_t
*vha
, char *key
, char *str
, size_t size
)
2850 struct qla_hw_data
*ha
= vha
->hw
;
2851 uint8_t *pos
= ha
->vpd
;
2852 uint8_t *end
= pos
+ ha
->vpd_size
;
2855 if (!IS_FWI2_CAPABLE(ha
) || !qla2xxx_is_vpd_valid(pos
, end
))
2858 while (pos
< end
&& *pos
!= 0x78) {
2859 len
= (*pos
== 0x82) ? pos
[1] : pos
[2];
2861 if (!strncmp(pos
, key
, strlen(key
)))
2864 if (*pos
!= 0x90 && *pos
!= 0x91)
2870 if (pos
< end
- len
&& *pos
!= 0x78)
2871 return snprintf(str
, size
, "%.*s", len
, pos
+ 3);
2877 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t
*vha
)
2880 uint32_t fcp_prio_addr
;
2881 struct qla_hw_data
*ha
= vha
->hw
;
2883 if (!ha
->fcp_prio_cfg
) {
2884 ha
->fcp_prio_cfg
= vmalloc(FCP_PRIO_CFG_SIZE
);
2885 if (!ha
->fcp_prio_cfg
) {
2886 ql_log(ql_log_warn
, vha
, 0x00d5,
2887 "Unable to allocate memory for fcp priorty data (%x).\n",
2889 return QLA_FUNCTION_FAILED
;
2892 memset(ha
->fcp_prio_cfg
, 0, FCP_PRIO_CFG_SIZE
);
2894 fcp_prio_addr
= ha
->flt_region_fcp_prio
;
2896 /* first read the fcp priority data header from flash */
2897 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)ha
->fcp_prio_cfg
,
2898 fcp_prio_addr
<< 2, FCP_PRIO_CFG_HDR_SIZE
);
2900 if (!qla24xx_fcp_prio_cfg_valid(vha
, ha
->fcp_prio_cfg
, 0))
2903 /* read remaining FCP CMD config data from flash */
2904 fcp_prio_addr
+= (FCP_PRIO_CFG_HDR_SIZE
>> 2);
2905 len
= ha
->fcp_prio_cfg
->num_entries
* FCP_PRIO_CFG_ENTRY_SIZE
;
2906 max_len
= FCP_PRIO_CFG_SIZE
- FCP_PRIO_CFG_HDR_SIZE
;
2908 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)&ha
->fcp_prio_cfg
->entry
[0],
2909 fcp_prio_addr
<< 2, (len
< max_len
? len
: max_len
));
2911 /* revalidate the entire FCP priority config data, including entries */
2912 if (!qla24xx_fcp_prio_cfg_valid(vha
, ha
->fcp_prio_cfg
, 1))
2915 ha
->flags
.fcp_prio_enabled
= 1;
2918 vfree(ha
->fcp_prio_cfg
);
2919 ha
->fcp_prio_cfg
= NULL
;
2920 return QLA_FUNCTION_FAILED
;