4 /*-----------------------------------------------------------------------------
7 * Copyright (C) 2005 SBE, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * For further information, contact via email: support@sbei.com
20 * SBE, Inc. San Ramon, California U.S.A.
21 *-----------------------------------------------------------------------------
24 #include <linux/types.h>
26 #define VINT32 volatile u_int32_t
30 VINT32 gbl_cfg
; /* 00 Global Cfg */
31 VINT32 clkmon
; /* 01 Clk Monitor */
32 VINT32 rx_opt
; /* 02 RX Options */
33 VINT32 rx_line_cfg
; /* 03 RX Line Interface Cfg */
34 VINT32 tx_line_cfg
; /* 04 TX Line Interface Cfg */
35 VINT32 tx_frpass
; /* 05 TX Framing & Bypass Options */
36 VINT32 tx_time
; /* 06 TX Timing Options */
37 VINT32 intr_1
; /* 07 Intr Source #1 */
38 VINT32 intr_2
; /* 08 Intr Source #2 */
39 VINT32 intr_3
; /* 09 Intr Source #3 */
40 VINT32 mdiag
; /* 0A Master Diagnostics */
41 VINT32 mtest
; /* 0B Master Test */
42 VINT32 adiag
; /* 0C Analog Diagnostics */
43 VINT32 rev_id
; /* 0D Rev/Chip Id/Global PMON Update */
45 VINT32 reset
; /* 0E Reset */
46 VINT32 prgd_phctl
; /* 0F PRGD Positioning/Ctl & HDLC Ctl */
47 VINT32 cdrc_cfg
; /* 10 CDRC Cfg */
48 VINT32 cdrc_ien
; /* 11 CDRC Intr Enable */
49 VINT32 cdrc_ists
; /* 12 CDRC Intr Sts */
50 VINT32 cdrc_alos
; /* 13 CDRC Alternate Loss of Signal */
52 VINT32 rjat_ists
; /* 14 RJAT Intr Sts */
53 VINT32 rjat_n1clk
; /* 15 RJAT Reference Clk Divisor (N1) Ctl */
54 VINT32 rjat_n2clk
; /* 16 RJAT Output Clk Divisor (N2) Ctl */
55 VINT32 rjat_cfg
; /* 17 RJAT Cfg */
57 VINT32 tjat_ists
; /* 18 TJAT Intr Sts */
58 VINT32 tjat_n1clk
; /* 19 TJAT Reference Clk Divisor (N1) Ctl */
59 VINT32 tjat_n2clk
; /* 1A TJAT Output Clk Divisor (N2) Ctl */
60 VINT32 tjat_cfg
; /* 1B TJAT Cfg */
62 VINT32 rx_elst_cfg
; /* 1C RX-ELST Cfg */
63 VINT32 rx_elst_ists
; /* 1D RX-ELST Intr Sts */
64 VINT32 rx_elst_idle
; /* 1E RX-ELST Idle Code */
65 VINT32 _rx_elst_res1f
; /* 1F RX-ELST Reserved */
67 VINT32 tx_elst_cfg
; /* 20 TX-ELST Cfg */
68 VINT32 tx_elst_ists
; /* 21 TX-ELST Intr Sts */
69 VINT32 _tx_elst_res22
; /* 22 TX-ELST Reserved */
70 VINT32 _tx_elst_res23
; /* 23 TX-ELST Reserved */
71 VINT32 __res24
; /* 24 Reserved */
72 VINT32 __res25
; /* 25 Reserved */
73 VINT32 __res26
; /* 26 Reserved */
74 VINT32 __res27
; /* 27 Reserved */
76 VINT32 rxce1_ctl
; /* 28 RXCE RX Data Link 1 Ctl */
77 VINT32 rxce1_bits
; /* 29 RXCE RX Data Link 1 Bit Select */
78 VINT32 rxce2_ctl
; /* 2A RXCE RX Data Link 2 Ctl */
79 VINT32 rxce2_bits
; /* 2B RXCE RX Data Link 2 Bit Select */
80 VINT32 rxce3_ctl
; /* 2C RXCE RX Data Link 3 Ctl */
81 VINT32 rxce3_bits
; /* 2D RXCE RX Data Link 3 Bit Select */
82 VINT32 _rxce_res2E
; /* 2E RXCE Reserved */
83 VINT32 _rxce_res2F
; /* 2F RXCE Reserved */
85 VINT32 brif_cfg
; /* 30 BRIF RX Backplane Cfg */
86 VINT32 brif_fpcfg
; /* 31 BRIF RX Backplane Frame Pulse Cfg */
87 VINT32 brif_pfcfg
; /* 32 BRIF RX Backplane Parity/F-Bit Cfg */
88 VINT32 brif_tsoff
; /* 33 BRIF RX Backplane Time Slot Offset */
89 VINT32 brif_boff
; /* 34 BRIF RX Backplane Bit Offset */
90 VINT32 _brif_res35
; /* 35 BRIF RX Backplane Reserved */
91 VINT32 _brif_res36
; /* 36 BRIF RX Backplane Reserved */
92 VINT32 _brif_res37
; /* 37 BRIF RX Backplane Reserved */
94 VINT32 txci1_ctl
; /* 38 TXCI TX Data Link 1 Ctl */
95 VINT32 txci1_bits
; /* 39 TXCI TX Data Link 2 Bit Select */
96 VINT32 txci2_ctl
; /* 3A TXCI TX Data Link 1 Ctl */
97 VINT32 txci2_bits
; /* 3B TXCI TX Data Link 2 Bit Select */
98 VINT32 txci3_ctl
; /* 3C TXCI TX Data Link 1 Ctl */
99 VINT32 txci3_bits
; /* 3D TXCI TX Data Link 2 Bit Select */
100 VINT32 _txci_res3E
; /* 3E TXCI Reserved */
101 VINT32 _txci_res3F
; /* 3F TXCI Reserved */
103 VINT32 btif_cfg
; /* 40 BTIF TX Backplane Cfg */
104 VINT32 btif_fpcfg
; /* 41 BTIF TX Backplane Frame Pulse Cfg */
105 VINT32 btif_pcfgsts
; /* 42 BTIF TX Backplane Parity Cfg & Sts */
106 VINT32 btif_tsoff
; /* 43 BTIF TX Backplane Time Slot Offset */
107 VINT32 btif_boff
; /* 44 BTIF TX Backplane Bit Offset */
108 VINT32 _btif_res45
; /* 45 BTIF TX Backplane Reserved */
109 VINT32 _btif_res46
; /* 46 BTIF TX Backplane Reserved */
110 VINT32 _btif_res47
; /* 47 BTIF TX Backplane Reserved */
111 VINT32 t1_frmr_cfg
; /* 48 T1 FRMR Cfg */
112 VINT32 t1_frmr_ien
; /* 49 T1 FRMR Intr Enable */
113 VINT32 t1_frmr_ists
; /* 4A T1 FRMR Intr Sts */
114 VINT32 __res_4B
; /* 4B Reserved */
115 VINT32 ibcd_cfg
; /* 4C IBCD Cfg */
116 VINT32 ibcd_ies
; /* 4D IBCD Intr Enable/Sts */
117 VINT32 ibcd_act
; /* 4E IBCD Activate Code */
118 VINT32 ibcd_deact
; /* 4F IBCD Deactivate Code */
120 VINT32 sigx_cfg
; /* 50 SIGX Cfg/Change of Signaling State */
121 VINT32 sigx_acc_cos
; /* 51 SIGX uP Access Sts/Change of Signaling State */
122 VINT32 sigx_iac_cos
; /* 52 SIGX Channel Indirect
123 * Addr/Ctl/Change of Signaling State */
124 VINT32 sigx_idb_cos
; /* 53 SIGX Channel Indirect Data
125 * Buffer/Change of Signaling State */
127 VINT32 t1_xbas_cfg
; /* 54 T1 XBAS Cfg */
128 VINT32 t1_xbas_altx
; /* 55 T1 XBAS Alarm TX */
129 VINT32 t1_xibc_ctl
; /* 56 T1 XIBC Ctl */
130 VINT32 t1_xibc_lbcode
; /* 57 T1 XIBC Loopback Code */
132 VINT32 pmon_ies
; /* 58 PMON Intr Enable/Sts */
133 VINT32 pmon_fberr
; /* 59 PMON Framing Bit Err Cnt */
134 VINT32 pmon_feb_lsb
; /* 5A PMON OFF/COFA/Far End Block Err Cnt (LSB) */
135 VINT32 pmon_feb_msb
; /* 5B PMON OFF/COFA/Far End Block Err Cnt (MSB) */
136 VINT32 pmon_bed_lsb
; /* 5C PMON Bit/Err/CRCE Cnt (LSB) */
137 VINT32 pmon_bed_msb
; /* 5D PMON Bit/Err/CRCE Cnt (MSB) */
138 VINT32 pmon_lvc_lsb
; /* 5E PMON LVC Cnt (LSB) */
139 VINT32 pmon_lvc_msb
; /* 5F PMON LVC Cnt (MSB) */
141 VINT32 t1_almi_cfg
; /* 60 T1 ALMI Cfg */
142 VINT32 t1_almi_ien
; /* 61 T1 ALMI Intr Enable */
143 VINT32 t1_almi_ists
; /* 62 T1 ALMI Intr Sts */
144 VINT32 t1_almi_detsts
; /* 63 T1 ALMI Alarm Detection Sts */
146 VINT32 _t1_pdvd_res64
; /* 64 T1 PDVD Reserved */
147 VINT32 t1_pdvd_ies
; /* 65 T1 PDVD Intr Enable/Sts */
148 VINT32 _t1_xboc_res66
; /* 66 T1 XBOC Reserved */
149 VINT32 t1_xboc_code
; /* 67 T1 XBOC Code */
150 VINT32 _t1_xpde_res68
; /* 68 T1 XPDE Reserved */
151 VINT32 t1_xpde_ies
; /* 69 T1 XPDE Intr Enable/Sts */
153 VINT32 t1_rboc_ena
; /* 6A T1 RBOC Enable */
154 VINT32 t1_rboc_sts
; /* 6B T1 RBOC Code Sts */
156 VINT32 t1_tpsc_cfg
; /* 6C TPSC Cfg */
157 VINT32 t1_tpsc_sts
; /* 6D TPSC uP Access Sts */
158 VINT32 t1_tpsc_ciaddr
; /* 6E TPSC Channel Indirect
160 VINT32 t1_tpsc_cidata
; /* 6F TPSC Channel Indirect Data
162 VINT32 t1_rpsc_cfg
; /* 70 RPSC Cfg */
163 VINT32 t1_rpsc_sts
; /* 71 RPSC uP Access Sts */
164 VINT32 t1_rpsc_ciaddr
; /* 72 RPSC Channel Indirect
166 VINT32 t1_rpsc_cidata
; /* 73 RPSC Channel Indirect Data
168 VINT32 __res74
; /* 74 Reserved */
169 VINT32 __res75
; /* 75 Reserved */
170 VINT32 __res76
; /* 76 Reserved */
171 VINT32 __res77
; /* 77 Reserved */
173 VINT32 t1_aprm_cfg
; /* 78 T1 APRM Cfg/Ctl */
174 VINT32 t1_aprm_load
; /* 79 T1 APRM Manual Load */
175 VINT32 t1_aprm_ists
; /* 7A T1 APRM Intr Sts */
176 VINT32 t1_aprm_1sec_2
; /* 7B T1 APRM One Second Content Octet 2 */
177 VINT32 t1_aprm_1sec_3
; /* 7C T1 APRM One Second Content Octet 3 */
178 VINT32 t1_aprm_1sec_4
; /* 7D T1 APRM One Second Content Octet 4 */
179 VINT32 t1_aprm_1sec_5
; /* 7E T1 APRM One Second Content MSB (Octect 5) */
180 VINT32 t1_aprm_1sec_6
; /* 7F T1 APRM One Second Content MSB (Octect 6) */
182 VINT32 e1_tran_cfg
; /* 80 E1 TRAN Cfg */
183 VINT32 e1_tran_txalarm
; /* 81 E1 TRAN TX Alarm/Diagnostic Ctl */
184 VINT32 e1_tran_intctl
; /* 82 E1 TRAN International Ctl */
185 VINT32 e1_tran_extrab
; /* 83 E1 TRAN Extra Bits Ctl */
186 VINT32 e1_tran_ien
; /* 84 E1 TRAN Intr Enable */
187 VINT32 e1_tran_ists
; /* 85 E1 TRAN Intr Sts */
188 VINT32 e1_tran_nats
; /* 86 E1 TRAN National Bit Codeword
190 VINT32 e1_tran_nat
; /* 87 E1 TRAN National Bit Codeword */
191 VINT32 __res88
; /* 88 Reserved */
192 VINT32 __res89
; /* 89 Reserved */
193 VINT32 __res8A
; /* 8A Reserved */
194 VINT32 __res8B
; /* 8B Reserved */
196 VINT32 _t1_frmr_res8C
; /* 8C T1 FRMR Reserved */
197 VINT32 _t1_frmr_res8D
; /* 8D T1 FRMR Reserved */
198 VINT32 __res8E
; /* 8E Reserved */
199 VINT32 __res8F
; /* 8F Reserved */
201 VINT32 e1_frmr_aopts
; /* 90 E1 FRMR Frame Alignment Options */
202 VINT32 e1_frmr_mopts
; /* 91 E1 FRMR Maintenance Mode Options */
203 VINT32 e1_frmr_ien
; /* 92 E1 FRMR Framing Sts Intr Enable */
204 VINT32 e1_frmr_mien
; /* 93 E1 FRMR Maintenance/Alarm Sts Intr Enable */
205 VINT32 e1_frmr_ists
; /* 94 E1 FRMR Framing Sts Intr Indication */
206 VINT32 e1_frmr_mists
; /* 95 E1 FRMR Maintenance/Alarm Sts Indication Enable */
207 VINT32 e1_frmr_sts
; /* 96 E1 FRMR Framing Sts */
208 VINT32 e1_frmr_masts
; /* 97 E1 FRMR Maintenance/Alarm Sts */
209 VINT32 e1_frmr_nat_bits
; /* 98 E1 FRMR International/National Bits */
210 VINT32 e1_frmr_crc_lsb
; /* 99 E1 FRMR CRC Err Cnt - LSB */
211 VINT32 e1_frmr_crc_msb
; /* 9A E1 FRMR CRC Err Cnt - MSB */
212 VINT32 e1_frmr_nat_ien
; /* 9B E1 FRMR National Bit Codeword Intr Enables */
213 VINT32 e1_frmr_nat_ists
; /* 9C E1 FRMR National Bit Codeword Intr/Sts */
214 VINT32 e1_frmr_nat
; /* 9D E1 FRMR National Bit Codewords */
215 VINT32 e1_frmr_fp_ien
; /* 9E E1 FRMR Frame Pulse/Alarm Intr Enables */
216 VINT32 e1_frmr_fp_ists
; /* 9F E1 FRMR Frame Pulse/Alarm Intr/Sts */
218 VINT32 __resA0
; /* A0 Reserved */
219 VINT32 __resA1
; /* A1 Reserved */
220 VINT32 __resA2
; /* A2 Reserved */
221 VINT32 __resA3
; /* A3 Reserved */
222 VINT32 __resA4
; /* A4 Reserved */
223 VINT32 __resA5
; /* A5 Reserved */
224 VINT32 __resA6
; /* A6 Reserved */
225 VINT32 __resA7
; /* A7 Reserved */
227 VINT32 tdpr1_cfg
; /* A8 TDPR #1 Cfg */
228 VINT32 tdpr1_utl
; /* A9 TDPR #1 Upper TX Threshold */
229 VINT32 tdpr1_ltl
; /* AA TDPR #1 Lower TX Threshold */
230 VINT32 tdpr1_ien
; /* AB TDPR #1 Intr Enable */
231 VINT32 tdpr1_ists
; /* AC TDPR #1 Intr Sts/UDR Clear */
232 VINT32 tdpr1_data
; /* AD TDPR #1 TX Data */
233 VINT32 __resAE
; /* AE Reserved */
234 VINT32 __resAF
; /* AF Reserved */
235 VINT32 tdpr2_cfg
; /* B0 TDPR #2 Cfg */
236 VINT32 tdpr2_utl
; /* B1 TDPR #2 Upper TX Threshold */
237 VINT32 tdpr2_ltl
; /* B2 TDPR #2 Lower TX Threshold */
238 VINT32 tdpr2_ien
; /* B3 TDPR #2 Intr Enable */
239 VINT32 tdpr2_ists
; /* B4 TDPR #2 Intr Sts/UDR Clear */
240 VINT32 tdpr2_data
; /* B5 TDPR #2 TX Data */
241 VINT32 __resB6
; /* B6 Reserved */
242 VINT32 __resB7
; /* B7 Reserved1 */
243 VINT32 tdpr3_cfg
; /* B8 TDPR #3 Cfg */
244 VINT32 tdpr3_utl
; /* B9 TDPR #3 Upper TX Threshold */
245 VINT32 tdpr3_ltl
; /* BA TDPR #3 Lower TX Threshold */
246 VINT32 tdpr3_ien
; /* BB TDPR #3 Intr Enable */
247 VINT32 tdpr3_ists
; /* BC TDPR #3 Intr Sts/UDR Clear */
248 VINT32 tdpr3_data
; /* BD TDPR #3 TX Data */
249 VINT32 __resBE
; /* BE Reserved */
250 VINT32 __resBF
; /* BF Reserved */
252 VINT32 rdlc1_cfg
; /* C0 RDLC #1 Cfg */
253 VINT32 rdlc1_intctl
; /* C1 RDLC #1 Intr Ctl */
254 VINT32 rdlc1_sts
; /* C2 RDLC #1 Sts */
255 VINT32 rdlc1_data
; /* C3 RDLC #1 Data */
256 VINT32 rdlc1_paddr
; /* C4 RDLC #1 Primary Addr Match */
257 VINT32 rdlc1_saddr
; /* C5 RDLC #1 Secondary Addr Match */
258 VINT32 __resC6
; /* C6 Reserved */
259 VINT32 __resC7
; /* C7 Reserved */
260 VINT32 rdlc2_cfg
; /* C8 RDLC #2 Cfg */
261 VINT32 rdlc2_intctl
; /* C9 RDLC #2 Intr Ctl */
262 VINT32 rdlc2_sts
; /* CA RDLC #2 Sts */
263 VINT32 rdlc2_data
; /* CB RDLC #2 Data */
264 VINT32 rdlc2_paddr
; /* CC RDLC #2 Primary Addr Match */
265 VINT32 rdlc2_saddr
; /* CD RDLC #2 Secondary Addr Match */
266 VINT32 __resCE
; /* CE Reserved */
267 VINT32 __resCF
; /* CF Reserved */
268 VINT32 rdlc3_cfg
; /* D0 RDLC #3 Cfg */
269 VINT32 rdlc3_intctl
; /* D1 RDLC #3 Intr Ctl */
270 VINT32 rdlc3_sts
; /* D2 RDLC #3 Sts */
271 VINT32 rdlc3_data
; /* D3 RDLC #3 Data */
272 VINT32 rdlc3_paddr
; /* D4 RDLC #3 Primary Addr Match */
273 VINT32 rdlc3_saddr
; /* D5 RDLC #3 Secondary Addr Match */
275 VINT32 csu_cfg
; /* D6 CSU Cfg */
276 VINT32 _csu_resD7
; /* D7 CSU Reserved */
278 VINT32 rlps_idata3
; /* D8 RLPS Indirect Data, 24-31 */
279 VINT32 rlps_idata2
; /* D9 RLPS Indirect Data, 16-23 */
280 VINT32 rlps_idata1
; /* DA RLPS Indirect Data, 8-15 */
281 VINT32 rlps_idata0
; /* DB RLPS Indirect Data, 0-7 */
282 VINT32 rlps_eqvr
; /* DC RLPS Equalizer Voltage Reference
284 VINT32 _rlps_resDD
; /* DD RLPS Reserved */
285 VINT32 _rlps_resDE
; /* DE RLPS Reserved */
286 VINT32 _rlps_resDF
; /* DF RLPS Reserved */
288 VINT32 prgd_ctl
; /* E0 PRGD Ctl */
289 VINT32 prgd_ies
; /* E1 PRGD Intr Enable/Sts */
290 VINT32 prgd_shift_len
; /* E2 PRGD Shift Length */
291 VINT32 prgd_tap
; /* E3 PRGD Tap */
292 VINT32 prgd_errin
; /* E4 PRGD Err Insertion */
293 VINT32 _prgd_resE5
; /* E5 PRGD Reserved */
294 VINT32 _prgd_resE6
; /* E6 PRGD Reserved */
295 VINT32 _prgd_resE7
; /* E7 PRGD Reserved */
296 VINT32 prgd_patin1
; /* E8 PRGD Pattern Insertion #1 */
297 VINT32 prgd_patin2
; /* E9 PRGD Pattern Insertion #2 */
298 VINT32 prgd_patin3
; /* EA PRGD Pattern Insertion #3 */
299 VINT32 prgd_patin4
; /* EB PRGD Pattern Insertion #4 */
300 VINT32 prgd_patdet1
; /* EC PRGD Pattern Detector #1 */
301 VINT32 prgd_patdet2
; /* ED PRGD Pattern Detector #2 */
302 VINT32 prgd_patdet3
; /* EE PRGD Pattern Detector #3 */
303 VINT32 prgd_patdet4
; /* EF PRGD Pattern Detector #4 */
305 VINT32 xlpg_cfg
; /* F0 XLPG Line Driver Cfg */
306 VINT32 xlpg_ctlsts
; /* F1 XLPG Ctl/Sts */
307 VINT32 xlpg_pwave_addr
; /* F2 XLPG Pulse Waveform Storage Write Addr */
308 VINT32 xlpg_pwave_data
; /* F3 XLPG Pulse Waveform Storage Data */
309 VINT32 xlpg_atest_pctl
; /* F4 XLPG Analog Test Positive Ctl */
310 VINT32 xlpg_atest_nctl
; /* F5 XLPG Analog Test Negative Ctl */
311 VINT32 xlpg_fdata_sel
; /* F6 XLPG Fuse Data Select */
312 VINT32 _xlpg_resF7
; /* F7 XLPG Reserved */
314 VINT32 rlps_cfgsts
; /* F8 RLPS Cfg & Sts */
315 VINT32 rlps_alos_thresh
; /* F9 RLPS ALOS Detection/Clearance Threshold */
316 VINT32 rlps_alos_dper
; /* FA RLPS ALOS Detection Period */
317 VINT32 rlps_alos_cper
; /* FB RLPS ALOS Clearance Period */
318 VINT32 rlps_eq_iaddr
; /* FC RLPS Equalization Indirect Addr */
319 VINT32 rlps_eq_rwsel
; /* FD RLPS Equalization Read/WriteB Select */
320 VINT32 rlps_eq_ctlsts
; /* FE RLPS Equalizer Loop Sts & Ctl */
321 VINT32 rlps_eq_cfg
; /* FF RLPS Equalizer Cfg */
324 typedef struct s_comet_reg comet_t
;
326 /* 00AH: MDIAG Register bit definitions */
327 #define COMET_MDIAG_ID5 0x40
328 #define COMET_MDIAG_LBMASK 0x3F
329 #define COMET_MDIAG_PAYLB 0x20
330 #define COMET_MDIAG_LINELB 0x10
331 #define COMET_MDIAG_RAIS 0x08
332 #define COMET_MDIAG_DDLB 0x04
333 #define COMET_MDIAG_TXMFP 0x02
334 #define COMET_MDIAG_TXLOS 0x01
335 #define COMET_MDIAG_LBOFF 0x00
341 init_comet (void *, comet_t
*, u_int32_t
, int, u_int8_t
);
344 #endif /* _INC_COMET_H_ */