drivers/staging/rtl8187se/r8180_hw.h

   1 /*
   2         This is part of rtl8180 OpenSource driver.
   3         Copyright (C) Andrea Merello 2004-2005  <andreamrl@tiscali.it>
   4         Released under the terms of GPL (General Public Licence)
   5
   6         Parts of this driver are based on the GPL part of the
   7         official Realtek driver.
   8         Parts of this driver are based on the rtl8180 driver skeleton
   9         from Patric Schenke & Andres Salomon.
  10         Parts of this driver are based on the Intel Pro Wireless
  11         2100 GPL driver.
  12
  13         We want to tanks the Authors of those projects
  14         and the Ndiswrapper project Authors.
  15 */
  16
  17 /* Mariusz Matuszek added full registers definition with Realtek's name */
  18
  19 /* this file contains register definitions for the rtl8180 MAC controller */
  20 #ifndef R8180_HW
  21 #define R8180_HW
  22
  23
  24 #define BIT0    0x00000001
  25 #define BIT1    0x00000002
  26 #define BIT2    0x00000004
  27 #define BIT3    0x00000008
  28 #define BIT4    0x00000010
  29 #define BIT5    0x00000020
  30 #define BIT6    0x00000040
  31 #define BIT7    0x00000080
  32 #define BIT9    0x00000200
  33 #define BIT11   0x00000800
  34 #define BIT13   0x00002000
  35 #define BIT15   0x00008000
  36 #define BIT20   0x00100000
  37 #define BIT21   0x00200000
  38 #define BIT22   0x00400000
  39 #define BIT23   0x00800000
  40 #define BIT24   0x01000000
  41 #define BIT25   0x02000000
  42 #define BIT26   0x04000000
  43 #define BIT27   0x08000000
  44 #define BIT28   0x10000000
  45 #define BIT29   0x20000000
  46 #define BIT30   0x40000000
  47 #define BIT31   0x80000000
  48
  49 #define MAX_SLEEP_TIME (10000)
  50 #define MIN_SLEEP_TIME (50)
  51
  52 #define BB_HOST_BANG_EN (1<<2)
  53 #define BB_HOST_BANG_CLK (1<<1)
  54
  55 #define MAC0 0
  56 #define MAC4 4
  57
  58 #define CMD 0x37
  59 #define CMD_RST_SHIFT 4
  60 #define CMD_RX_ENABLE_SHIFT 3
  61 #define CMD_TX_ENABLE_SHIFT 2
  62
  63 #define EPROM_CMD 0x50
  64 #define EPROM_CMD_RESERVED_MASK ((1<<5)|(1<<4))
  65 #define EPROM_CMD_OPERATING_MODE_SHIFT 6
  66 #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
  67 #define EPROM_CMD_CONFIG 0x3
  68 #define EPROM_CMD_NORMAL 0
  69 #define EPROM_CMD_LOAD 1
  70 #define EPROM_CMD_PROGRAM 2
  71 #define EPROM_CS_SHIFT 3
  72 #define EPROM_CK_SHIFT 2
  73 #define EPROM_W_SHIFT 1
  74 #define EPROM_R_SHIFT 0
  75 #define CONFIG2_DMA_POLLING_MODE_SHIFT 3
  76
  77 #define INTA_TXOVERFLOW (1<<15)
  78 #define INTA_TIMEOUT (1<<14)
  79 #define INTA_HIPRIORITYDESCERR (1<<9)
  80 #define INTA_HIPRIORITYDESCOK (1<<8)
  81 #define INTA_NORMPRIORITYDESCERR (1<<7)
  82 #define INTA_NORMPRIORITYDESCOK (1<<6)
  83 #define INTA_RXOVERFLOW (1<<5)
  84 #define INTA_RXDESCERR (1<<4)
  85 #define INTA_LOWPRIORITYDESCERR (1<<3)
  86 #define INTA_LOWPRIORITYDESCOK (1<<2)
  87 #define INTA_RXOK (1)
  88 #define INTA_MASK 0x3c
  89
  90 #define RXRING_ADDR 0xe4 /* page 0 */
  91 #define PGSELECT 0x5e
  92 #define PGSELECT_PG_SHIFT 0
  93 #define RX_CONF 0x44
  94 #define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \
  95 (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23))
  96 #define RX_CHECK_BSSID_SHIFT 23
  97 #define ACCEPT_PWR_FRAME_SHIFT 22
  98 #define ACCEPT_MNG_FRAME_SHIFT 20
  99 #define ACCEPT_CTL_FRAME_SHIFT 19
 100 #define ACCEPT_DATA_FRAME_SHIFT 18
 101 #define ACCEPT_ICVERR_FRAME_SHIFT 12
 102 #define ACCEPT_CRCERR_FRAME_SHIFT 5
 103 #define ACCEPT_BCAST_FRAME_SHIFT 3
 104 #define ACCEPT_MCAST_FRAME_SHIFT 2
 105 #define ACCEPT_ALLMAC_FRAME_SHIFT 0
 106 #define ACCEPT_NICMAC_FRAME_SHIFT 1
 107
 108 #define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15))
 109 #define RX_FIFO_THRESHOLD_SHIFT 13
 110 #define RX_FIFO_THRESHOLD_NONE 7
 111 #define RX_AUTORESETPHY_SHIFT 28
 112
 113 #define TX_CONF 0x40
 114 #define TX_CONF_HEADER_AUTOICREMENT_SHIFT 30
 115 #define TX_LOOPBACK_SHIFT 17
 116 #define TX_LOOPBACK_NONE 0
 117 #define TX_LOOPBACK_CONTINUE 3
 118 #define TX_LOOPBACK_MASK ((1<<17)|(1<<18))
 119 #define TX_DPRETRY_SHIFT 0
 120 #define R8180_MAX_RETRY 255
 121 #define TX_RTSRETRY_SHIFT 8
 122 #define TX_NOICV_SHIFT 19
 123 #define TX_NOCRC_SHIFT 16
 124 #define TX_DMA_POLLING 0xd9
 125 #define TX_DMA_POLLING_BEACON_SHIFT 7
 126 #define TX_DMA_POLLING_HIPRIORITY_SHIFT 6
 127 #define TX_DMA_POLLING_NORMPRIORITY_SHIFT 5
 128 #define TX_DMA_POLLING_LOWPRIORITY_SHIFT 4
 129 #define TX_MANAGEPRIORITY_RING_ADDR 0x0C
 130 #define TX_BKPRIORITY_RING_ADDR 0x10
 131 #define TX_BEPRIORITY_RING_ADDR 0x14
 132 #define TX_VIPRIORITY_RING_ADDR 0x20
 133 #define TX_VOPRIORITY_RING_ADDR 0x24
 134 #define TX_HIGHPRIORITY_RING_ADDR 0x28
 135 #define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10))
 136 #define MAX_RX_DMA_2048 7
 137 #define MAX_RX_DMA_1024 6
 138 #define MAX_RX_DMA_SHIFT 10
 139 #define INT_TIMEOUT 0x48
 140 #define CONFIG3_CLKRUN_SHIFT 2
 141 #define CONFIG3_ANAPARAM_W_SHIFT 6
 142 #define ANAPARAM 0x54
 143 #define BEACON_INTERVAL 0x70
 144 #define BEACON_INTERVAL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)| \
 145 (1<<6)|(1<<7)|(1<<8)|(1<<9))
 146 #define ATIM_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)| \
 147 (1<<8)|(1<<9))
 148 #define ATIM 0x72
 149 #define EPROM_CS_SHIFT 3
 150 #define EPROM_CK_SHIFT 2
 151 #define PHY_ADR 0x7c
 152 #define SECURITY 0x5f /* 1209 this is sth wrong */
 153 #define SECURITY_WEP_TX_ENABLE_SHIFT 1
 154 #define SECURITY_WEP_RX_ENABLE_SHIFT 0
 155 #define SECURITY_ENCRYP_104 1
 156 #define SECURITY_ENCRYP_SHIFT 4
 157 #define SECURITY_ENCRYP_MASK ((1<<4)|(1<<5))
 158 #define KEY0 0x90  /* 1209 this is sth wrong */
 159 #define CONFIG2_ANTENNA_SHIFT 6
 160 #define TX_BEACON_RING_ADDR 0x4c
 161 #define CONFIG0_WEP40_SHIFT 7
 162 #define CONFIG0_WEP104_SHIFT 6
 163 #define AGCRESET_SHIFT 5
 164
 165
 166
 167 /*
 168  * Operational registers offsets in PCI (I/O) space.
 169  * RealTek names are used.
 170  */
 171
 172 #define TSFTR 0x0018
 173
 174 #define TLPDA 0x0020
 175
 176 #define BSSID 0x002E
 177
 178 #define CR 0x0037
 179
 180 #define RF_SW_CONFIG            0x8                     /* store data which is transmitted to RF for driver     */
 181 #define RF_SW_CFG_SI            BIT1
 182 #define EIFS                    0x2D                    /* Extended InterFrame Space Timer, in unit of 4 us.    */
 183
 184 #define BRSR                    0x34                    /* Basic rate set                                                                               */
 185
 186 #define IMR 0x006C
 187 #define ISR 0x003C
 188
 189 #define TCR 0x0040
 190
 191 #define RCR 0x0044
 192
 193 #define TimerInt 0x0048
 194
 195 #define CR9346 0x0050
 196
 197 #define CONFIG0 0x0051
 198 #define CONFIG2 0x0053
 199
 200 #define MSR 0x0058
 201
 202 #define CONFIG3 0x0059
 203 #define CONFIG4 0x005A
 204         /* SD3 szuyitasi: Mac0x57= CC -> B0 Mac0x60= D1 -> C6   */
 205         /* Mac0x60 = 0x000004C6 power save parameters                   */
 206         #define ANAPARM_ASIC_ON    0xB0054D00
 207         #define ANAPARM2_ASIC_ON  0x000004C6
 208
 209         #define ANAPARM_ON ANAPARM_ASIC_ON
 210         #define ANAPARM2_ON ANAPARM2_ASIC_ON
 211
 212 #define TESTR 0x005B
 213
 214 #define PSR 0x005E
 215
 216 #define BcnItv 0x0070
 217
 218 #define AtimWnd 0x0072
 219
 220 #define BintrItv 0x0074
 221
 222 #define PhyAddr 0x007C
 223 #define PhyDataR 0x007E
 224
 225 /* following are for rtl8185 */
 226 #define RFPinsOutput 0x80
 227 #define RFPinsEnable 0x82
 228 #define RF_TIMING 0x8c
 229 #define RFPinsSelect 0x84
 230 #define ANAPARAM2 0x60
 231 #define RF_PARA 0x88
 232 #define RFPinsInput 0x86
 233 #define GP_ENABLE 0x90
 234 #define GPIO 0x91
 235 #define SW_CONTROL_GPIO 0x400
 236 #define TX_ANTENNA 0x9f
 237 #define TX_GAIN_OFDM 0x9e
 238 #define TX_GAIN_CCK 0x9d
 239 #define WPA_CONFIG 0xb0
 240 #define TX_AGC_CTL 0x9c
 241 #define TX_AGC_CTL_PERPACKET_GAIN_SHIFT 0
 242 #define TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT 1
 243 #define TX_AGC_CTL_FEEDBACK_ANT 2
 244 #define RESP_RATE 0x34
 245 #define SIFS 0xb4
 246 #define DIFS 0xb5
 247
 248 #define SLOT 0xb6
 249 #define CW_CONF 0xbc
 250 #define CW_CONF_PERPACKET_RETRY_SHIFT 1
 251 #define CW_CONF_PERPACKET_CW_SHIFT 0
 252 #define CW_VAL 0xbd
 253 #define MAX_RESP_RATE_SHIFT 4
 254 #define MIN_RESP_RATE_SHIFT 0
 255 #define RATE_FALLBACK 0xbe
 256
 257 #define CONFIG5 0x00D8
 258
 259 #define PHYPR                   0xDA                    /* 0xDA - 0x0B PHY Parameter Register.  */
 260
 261 #define FEMR                    0x1D4   /* Function Event Mask register */
 262
 263 #define FFER 0x00FC
 264 #define FFER_END 0x00FF
 265
 266
 267
 268 /*
 269  * Bitmasks for specific register functions.
 270  * Names are derived from the register name and function name.
 271  *
 272  * <REGISTER>_<FUNCTION>[<bit>]
 273  *
 274  * this leads to some awkward names...
 275  */
 276
 277 #define BRSR_BPLCP  ((1 << 8))
 278 #define BRSR_MBR    ((1 << 1)|(1 << 0))
 279 #define BRSR_MBR_8185 ((1 << 11)|(1 << 10)|(1 << 9)|(1 << 8)|(1 << 7)|(1 << 6)|(1 << 5)|(1 << 4)|(1 << 3)|(1 << 2)|(1 << 1)|(1 << 0))
 280 #define BRSR_MBR0   ((1 << 0))
 281 #define BRSR_MBR1   ((1 << 1))
 282
 283 #define CR_RST      ((1 << 4))
 284 #define CR_RE       ((1 << 3))
 285 #define CR_TE       ((1 << 2))
 286 #define CR_MulRW    ((1 << 0))
 287
 288 #define IMR_Dot11hInt   ((1 << 25))                     /*802.11h Measurement Interrupt                                 */
 289 #define IMR_BcnDmaInt   ((1 << 24))                     /*Beacon DMA Interrupt */ /*What differenct between BcnDmaInt and BcnInt???     */
 290 #define IMR_WakeInt             ((1 << 23))                     /*Wake Up Interrupt                                                             */
 291 #define IMR_TXFOVW              ((1 << 22))                     /*Tx FIFO Overflow Interrupt                                    */
 292 #define IMR_TimeOut1    ((1 << 21))                     /*Time Out Interrupt 1                                                  */
 293 #define IMR_BcnInt              ((1 << 20))                     /*Beacon Time out Interrupt                                             */
 294 #define IMR_ATIMInt             ((1 << 19))                     /*ATIM Time Out Interrupt                                               */
 295 #define IMR_TBDER               ((1 << 18))                     /*Tx Beacon Descriptor Error Interrupt                  */
 296 #define IMR_TBDOK               ((1 << 17))                     /*Tx Beacon Descriptor OK Interrupt                             */
 297 #define IMR_THPDER              ((1 << 16))                     /*Tx High Priority Descriptor Error Interrupt   */
 298 #define IMR_THPDOK              ((1 << 15))                     /*Tx High Priority Descriptor OK Interrupt              */
 299 #define IMR_TVODER              ((1 << 14))                     /*Tx AC_VO Descriptor Error Interrupt                   */
 300 #define IMR_TVODOK              ((1 << 13))                     /*Tx AC_VO Descriptor OK Interrupt                              */
 301 #define IMR_FOVW                ((1 << 12))                     /*Rx FIFO Overflow Interrupt                                    */
 302 #define IMR_RDU                 ((1 << 11))                     /*Rx Descriptor Unavailable Interrupt                   */
 303 #define IMR_TVIDER              ((1 << 10))                     /*Tx AC_VI Descriptor Error Interrupt                   */
 304 #define IMR_TVIDOK              ((1 << 9))                      /*Tx AC_VI Descriptor OK Interrupt                              */
 305 #define IMR_RER                 ((1 << 8))                      /*Rx Error Interrupt                                                    */
 306 #define IMR_ROK                 ((1 << 7))                      /*Receive OK Interrupt                                                  */
 307 #define IMR_TBEDER              ((1 << 6))                      /*Tx AC_BE Descriptor Error Interrupt                   */
 308 #define IMR_TBEDOK              ((1 << 5))                      /*Tx AC_BE Descriptor OK Interrupt                              */
 309 #define IMR_TBKDER              ((1 << 4))                      /*Tx AC_BK Descriptor Error Interrupt                   */
 310 #define IMR_TBKDOK              ((1 << 3))                      /*Tx AC_BK Descriptor OK Interrupt                              */
 311 #define IMR_RQoSOK              ((1 << 2))                      /*Rx QoS OK Interrupt                                                   */
 312 #define IMR_TimeOut2    ((1 << 1))                      /*Time Out Interrupt 2                                                  */
 313 #define IMR_TimeOut3    ((1 << 0))                      /*Time Out Interrupt 3                                                  */
 314 #define IMR_TMGDOK      ((1 << 30))
 315 #define ISR_Dot11hInt   ((1 << 25))                     /*802.11h Measurement Interrupt                                 */
 316 #define ISR_BcnDmaInt   ((1 << 24))                     /*Beacon DMA Interrupt  */ /*What differenct between BcnDmaInt and BcnInt???    */
 317 #define ISR_WakeInt             ((1 << 23))                     /*Wake Up Interrupt                                                             */
 318 #define ISR_TXFOVW              ((1 << 22))                     /*Tx FIFO Overflow Interrupt                                    */
 319 #define ISR_TimeOut1    ((1 << 21))                     /*Time Out Interrupt 1                                                  */
 320 #define ISR_BcnInt              ((1 << 20))                     /*Beacon Time out Interrupt                                             */
 321 #define ISR_ATIMInt             ((1 << 19))                     /*ATIM Time Out Interrupt                                               */
 322 #define ISR_TBDER               ((1 << 18))                     /*Tx Beacon Descriptor Error Interrupt                  */
 323 #define ISR_TBDOK               ((1 << 17))                     /*Tx Beacon Descriptor OK Interrupt                             */
 324 #define ISR_THPDER              ((1 << 16))                     /*Tx High Priority Descriptor Error Interrupt   */
 325 #define ISR_THPDOK              ((1 << 15))                     /*Tx High Priority Descriptor OK Interrupt              */
 326 #define ISR_TVODER              ((1 << 14))                     /*Tx AC_VO Descriptor Error Interrupt                   */
 327 #define ISR_TVODOK              ((1 << 13))                     /*Tx AC_VO Descriptor OK Interrupt                              */
 328 #define ISR_FOVW                ((1 << 12))                     /*Rx FIFO Overflow Interrupt                                    */
 329 #define ISR_RDU                 ((1 << 11))                     /*Rx Descriptor Unavailable Interrupt                   */
 330 #define ISR_TVIDER              ((1 << 10))                     /*Tx AC_VI Descriptor Error Interrupt                   */
 331 #define ISR_TVIDOK              ((1 << 9))                      /*Tx AC_VI Descriptor OK Interrupt                              */
 332 #define ISR_RER                 ((1 << 8))                      /*Rx Error Interrupt                                                    */
 333 #define ISR_ROK                 ((1 << 7))                      /*Receive OK Interrupt                                                  */
 334 #define ISR_TBEDER              ((1 << 6))                      /*Tx AC_BE Descriptor Error Interrupt                   */
 335 #define ISR_TBEDOK              ((1 << 5))                      /*Tx AC_BE Descriptor OK Interrupt                              */
 336 #define ISR_TBKDER              ((1 << 4))                      /*Tx AC_BK Descriptor Error Interrupt                   */
 337 #define ISR_TBKDOK              ((1 << 3))                      /*Tx AC_BK Descriptor OK Interrupt                              */
 338 #define ISR_RQoSOK              ((1 << 2))                      /*Rx QoS OK Interrupt                                                   */
 339 #define ISR_TimeOut2    ((1 << 1))                      /*Time Out Interrupt 2                                                  */
 340 #define ISR_TimeOut3    ((1 << 0))                      /*Time Out Interrupt 3                                                  */
 341
 342 /* these definition is used for Tx/Rx test temporarily */
 343 #define ISR_TLPDER  ISR_TVIDER
 344 #define ISR_TLPDOK  ISR_TVIDOK
 345 #define ISR_TNPDER  ISR_TVODER
 346 #define ISR_TNPDOK  ISR_TVODOK
 347 #define ISR_TimeOut ISR_TimeOut1
 348 #define ISR_RXFOVW ISR_FOVW
 349
 350
 351 #define HW_VERID_R8180_F 3
 352 #define HW_VERID_R8180_ABCD 2
 353 #define HW_VERID_R8185_ABC 4
 354 #define HW_VERID_R8185_D 5
 355 #define HW_VERID_R8185B_B 6
 356
 357 #define TCR_CWMIN   ((1 << 31))
 358 #define TCR_SWSEQ   ((1 << 30))
 359 #define TCR_HWVERID_MASK ((1 << 27)|(1 << 26)|(1 << 25))
 360 #define TCR_HWVERID_SHIFT 25
 361 #define TCR_SAT     ((1 << 24))
 362 #define TCR_PLCP_LEN TCR_SAT /* rtl8180 */
 363 #define TCR_MXDMA_MASK   ((1 << 23)|(1 << 22)|(1 << 21))
 364 #define TCR_MXDMA_1024 6
 365 #define TCR_MXDMA_2048 7
 366 #define TCR_MXDMA_SHIFT  21
 367 #define TCR_DISCW   ((1 << 20))
 368 #define TCR_ICV     ((1 << 19))
 369 #define TCR_LBK     ((1 << 18)|(1 << 17))
 370 #define TCR_LBK1    ((1 << 18))
 371 #define TCR_LBK0    ((1 << 17))
 372 #define TCR_CRC     ((1 << 16))
 373 #define TCR_DPRETRY_MASK   ((1 << 15)|(1 << 14)|(1 << 13)|(1 << 12)|(1 << 11)|(1 << 10)|(1 << 9)|(1 << 8))
 374 #define TCR_RTSRETRY_MASK   ((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 6)|(1 << 7))
 375 #define TCR_PROBE_NOTIMESTAMP_SHIFT 29 /* rtl8185 */
 376
 377 #define RCR_ONLYERLPKT ((1 << 31))
 378 #define RCR_CS_SHIFT   29
 379 #define RCR_CS_MASK    ((1 << 30) | (1 << 29))
 380 #define RCR_ENMARP     ((1 << 28))
 381 #define RCR_CBSSID     ((1 << 23))
 382 #define RCR_APWRMGT    ((1 << 22))
 383 #define RCR_ADD3       ((1 << 21))
 384 #define RCR_AMF        ((1 << 20))
 385 #define RCR_ACF        ((1 << 19))
 386 #define RCR_ADF        ((1 << 18))
 387 #define RCR_RXFTH      ((1 << 15)|(1 << 14)|(1 << 13))
 388 #define RCR_RXFTH2     ((1 << 15))
 389 #define RCR_RXFTH1     ((1 << 14))
 390 #define RCR_RXFTH0     ((1 << 13))
 391 #define RCR_AICV       ((1 << 12))
 392 #define RCR_MXDMA      ((1 << 10)|(1 << 9)|(1 << 8))
 393 #define RCR_MXDMA2     ((1 << 10))
 394 #define RCR_MXDMA1     ((1 << 9))
 395 #define RCR_MXDMA0     ((1 << 8))
 396 #define RCR_9356SEL    ((1 << 6))
 397 #define RCR_ACRC32     ((1 << 5))
 398 #define RCR_AB         ((1 << 3))
 399 #define RCR_AM         ((1 << 2))
 400 #define RCR_APM        ((1 << 1))
 401 #define RCR_AAP        ((1 << 0))
 402
 403 #define CR9346_EEM     ((1 << 7)|(1 << 6))
 404 #define CR9346_EEM1    ((1 << 7))
 405 #define CR9346_EEM0    ((1 << 6))
 406 #define CR9346_EECS    ((1 << 3))
 407 #define CR9346_EESK    ((1 << 2))
 408 #define CR9346_EED1    ((1 << 1))
 409 #define CR9346_EED0    ((1 << 0))
 410
 411 #define CONFIG3_PARM_En    ((1 << 6))
 412 #define CONFIG3_FuncRegEn  ((1 << 1))
 413
 414 #define CONFIG4_PWRMGT     ((1 << 5))
 415
 416 #define MSR_LINK_MASK      ((1 << 2)|(1 << 3))
 417 #define MSR_LINK_MANAGED   2
 418 #define MSR_LINK_NONE      0
 419 #define MSR_LINK_SHIFT     2
 420 #define MSR_LINK_ADHOC     1
 421 #define MSR_LINK_MASTER    3
 422
 423 #define BcnItv_BcnItv      (0x01FF)
 424
 425 #define AtimWnd_AtimWnd    (0x01FF)
 426
 427 #define BintrItv_BintrItv  (0x01FF)
 428
 429 #define FEMR_INTR    ((1 << 15))
 430 #define FEMR_WKUP    ((1 << 14))
 431 #define FEMR_GWAKE   ((1 << 4))
 432
 433 #define FFER_INTR    ((1 << 15))
 434 #define FFER_GWAKE   ((1 << 4))
 435
 436 /* Three wire mode.                                     */
 437 #define SW_THREE_WIRE                   0
 438 #define HW_THREE_WIRE                   2
 439 /* RTL8187S by amy                                      */
 440 #define HW_THREE_WIRE_PI                5
 441 #define HW_THREE_WIRE_SI                6
 442 /* by amy                                                       */
 443 #define TCR_LRL_OFFSET          0
 444 #define TCR_SRL_OFFSET          8
 445 #define TCR_MXDMA_OFFSET        21
 446 #define TCR_DISReqQsize_OFFSET          28
 447 #define TCR_DurProcMode_OFFSET          30
 448
 449 #define RCR_MXDMA_OFFSET                                8
 450 #define RCR_FIFO_OFFSET                                 13
 451
 452 #define AckTimeOutReg   0x79            /* ACK timeout register, in unit of 4 us. */
 453
 454 #define RFTiming                        0x8C
 455
 456 #define TPPollStop              0x93
 457
 458 #define TXAGC_CTL               0x9C                    /*< RJ_TODO_8185B> TX_AGC_CONTROL (0x9C seems be removed at 8185B, see p37). */
 459 #define CCK_TXAGC               0x9D
 460 #define OFDM_TXAGC              0x9E
 461 #define ANTSEL                  0x9F
 462
 463 #define ACM_CONTROL             0x00BF      /* ACM Control Registe */
 464
 465 #define IntMig                  0xE2                    /* Interrupt Migration (0xE2 ~ 0xE3)    */
 466
 467 #define TID_AC_MAP              0xE8                    /* TID to AC Mapping Register                   */
 468
 469 #define ANAPARAM3               0xEE                    /* <RJ_TODO_8185B> How to use it?               */
 470
 471 #define AC_VO_PARAM             0xF0                    /* AC_VO Parameters Record                              */
 472 #define AC_VI_PARAM             0xF4                    /* AC_VI Parameters Record                              */
 473 #define AC_BE_PARAM             0xF8                    /* AC_BE Parameters Record                              */
 474 #define AC_BK_PARAM             0xFC                    /* AC_BK Parameters Record                              */
 475
 476 #define GPIOCtrl                        0x16B                   /*GPIO Control Register.                        */
 477 #define ARFR                    0x1E0   /* Auto Rate Fallback Register (0x1e0 ~ 0x1e2)  */
 478
 479 #define RFSW_CTRL                       0x272   /* 0x272-0x273.                                                         */
 480 #define SW_3W_DB0                       0x274   /* Software 3-wire data buffer bit 31~0.                */
 481 #define SW_3W_DB1                       0x278   /* Software 3-wire data buffer bit 63~32.       */
 482 #define SW_3W_CMD0                      0x27C   /* Software 3-wire Control/Status Register.     */
 483 #define SW_3W_CMD1                      0x27D   /* Software 3-wire Control/Status Register.     */
 484
 485 #define PI_DATA_READ            0X360   /* 0x360 - 0x361  Parallel Interface Data Register.     */
 486 #define SI_DATA_READ            0x362   /* 0x362 - 0x363  Serial Interface Data Register.       */
 487
 488 /*
 489 ----------------------------------------------------------------------------
 490                 8185B TPPollStop bits                                   (offset 0x93, 1 byte)
 491 ----------------------------------------------------------------------------
 492 */
 493 #define TPPOLLSTOP_BQ                   (0x01 << 7)
 494 #define TPPOLLSTOP_AC_VIQ               (0x01 << 4)
 495
 496 #define MSR_LINK_ENEDCA    (1<<4)
 497
 498 /*
 499 ----------------------------------------------------------------------------
 500                 8187B AC_XX_PARAM bits
 501 ----------------------------------------------------------------------------
 502 */
 503 #define AC_PARAM_TXOP_LIMIT_OFFSET              16
 504 #define AC_PARAM_ECW_MAX_OFFSET                 12
 505 #define AC_PARAM_ECW_MIN_OFFSET                 8
 506 #define AC_PARAM_AIFS_OFFSET                    0
 507
 508 /*
 509 ----------------------------------------------------------------------------
 510                 8187B ACM_CONTROL bits                                  (Offset 0xBF, 1 Byte)
 511 ----------------------------------------------------------------------------
 512 */
 513 #define VOQ_ACM_EN                              (0x01 << 7)     /*BIT7  */
 514 #define VIQ_ACM_EN                              (0x01 << 6)     /*BIT6  */
 515 #define BEQ_ACM_EN                              (0x01 << 5)     /*BIT5  */
 516 #define ACM_HW_EN                               (0x01 << 4)     /*BIT4  */
 517 #define VOQ_ACM_CTL                             (0x01 << 2)     /*BIT2  */      /* Set to 1 when AC_VO used time reaches or exceeds the admitted time   */
 518 #define VIQ_ACM_CTL                             (0x01 << 1)     /*BIT1  */      /* Set to 1 when AC_VI used time reaches or exceeds the admitted time   */
 519 #define BEQ_ACM_CTL                             (0x01 << 0)     /*BIT0  */      /* Set to 1 when AC_BE used time reaches or exceeds the admitted time   */
 520
 521
 522 /*
 523 ----------------------------------------------------------------------------
 524                 8185B SW_3W_CMD bits                                    (Offset 0x27C-0x27D, 16bit)
 525 ----------------------------------------------------------------------------
 526 */
 527 #define SW_3W_CMD0_HOLD         ((1 << 7))
 528 #define SW_3W_CMD1_RE           ((1 << 0)) /* BIT8              */
 529 #define SW_3W_CMD1_WE           ((1 << 1)) /* BIT9              */
 530 #define SW_3W_CMD1_DONE         ((1 << 2)) /* BIT10             */
 531
 532 #define BB_HOST_BANG_RW         (1 << 3)
 533
 534 /*
 535 ----------------------------------------------------------------------------
 536                 8185B RATE_FALLBACK_CTL bits                    (Offset 0xBE, 8bit)
 537 ----------------------------------------------------------------------------
 538 */
 539 #define RATE_FALLBACK_CTL_ENABLE                                ((1 << 7))
 540 #define RATE_FALLBACK_CTL_ENABLE_RTSCTS         ((1 << 6))
 541 /* Auto rate fallback per 2^n retry. */
 542 #define RATE_FALLBACK_CTL_AUTO_STEP0    0x00
 543 #define RATE_FALLBACK_CTL_AUTO_STEP1    0x01
 544 #define RATE_FALLBACK_CTL_AUTO_STEP2    0x02
 545 #define RATE_FALLBACK_CTL_AUTO_STEP3    0x03
 546
 547
 548 #define RTL8225z2_ANAPARAM_OFF  0x55480658
 549 #define RTL8225z2_ANAPARAM2_OFF 0x72003f70
 550 /* by amy for power save                */
 551 #define RF_CHANGE_BY_HW BIT30
 552 #define RF_CHANGE_BY_PS BIT29
 553 #define RF_CHANGE_BY_IPS BIT28
 554 /* by amy for power save                */
 555 /* by amy for antenna                   */
 556 #define EEPROM_SW_REVD_OFFSET 0x3f
 557 /*  BIT[8-9] is for SW Antenna Diversity. Only the value EEPROM_SW_AD_ENABLE means enable, other values are diable.                                     */
 558 #define EEPROM_SW_AD_MASK                       0x0300
 559 #define EEPROM_SW_AD_ENABLE                     0x0100
 560
 561 /* BIT[10-11] determine if Antenna 1 is the Default Antenna. Only the value EEPROM_DEF_ANT_1 means TRUE, other values are FALSE.        */
 562 #define EEPROM_DEF_ANT_MASK                     0x0C00
 563 #define EEPROM_DEF_ANT_1                        0x0400
 564 /*by amy for antenna                                                                                                                                                            */
 565 /* {by amy 080312                                                                                                                                                                       */
 566 /* 0x7C, 0x7D Crystal calibration and Tx Power tracking mechanism. Added by Roger. 2007.12.10.          */
 567 #define EEPROM_RSV                                              0x7C
 568 #define EEPROM_XTAL_CAL_XOUT_MASK       0x0F    /* 0x7C[3:0], Crystal calibration for Xout.                             */
 569 #define EEPROM_XTAL_CAL_XIN_MASK                0xF0    /* 0x7C[7:4], Crystal calibration for Xin.                      */
 570 #define EEPROM_THERMAL_METER_MASK       0x0F00  /* 0x7D[3:0], Thermal meter reference level.                    */
 571 #define EEPROM_XTAL_CAL_ENABLE          0x1000  /* 0x7D[4], Crystal calibration enabled/disabled BIT.   */
 572 #define EEPROM_THERMAL_METER_ENABLE     0x2000  /* 0x7D[5], Thermal meter enabled/disabled BIT.                 */
 573 #define EN_LPF_CAL                      0x238   /* Enable LPF Calibration.                                                                              */
 574 #define PWR_METER_EN            BIT1
 575 /* <RJ_TODO_8185B> where are false alarm counters in 8185B? */
 576 #define CCK_FALSE_ALARM         0xD0
 577 /* by amy 080312} */
 578
 579 /* YJ,add for Country IE, 080630 */
 580 #define EEPROM_COUNTRY_CODE  0x2E
 581 /* YJ,add,080630,end */
 582
 583 #endif