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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / tty / serial / netx-serial.c
blobd40da78e7c8513fb7fc8f1064ffda22e5827280e
1 /*
2 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18 #if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 #define SUPPORT_SYSRQ
20 #endif
21
22 #include <linux/device.h>
23 #include <linux/module.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/platform_device.h>
29 #include <linux/tty.h>
30 #include <linux/tty_flip.h>
31 #include <linux/serial_core.h>
32 #include <linux/serial.h>
33
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <mach/hardware.h>
37 #include <mach/netx-regs.h>
38
39 /* We've been assigned a range on the "Low-density serial ports" major */
40 #define SERIAL_NX_MAJOR 204
41 #define MINOR_START 170
42
43 enum uart_regs {
44 UART_DR = 0x00,
45 UART_SR = 0x04,
46 UART_LINE_CR = 0x08,
47 UART_BAUDDIV_MSB = 0x0c,
48 UART_BAUDDIV_LSB = 0x10,
49 UART_CR = 0x14,
50 UART_FR = 0x18,
51 UART_IIR = 0x1c,
52 UART_ILPR = 0x20,
53 UART_RTS_CR = 0x24,
54 UART_RTS_LEAD = 0x28,
55 UART_RTS_TRAIL = 0x2c,
56 UART_DRV_ENABLE = 0x30,
57 UART_BRM_CR = 0x34,
58 UART_RXFIFO_IRQLEVEL = 0x38,
59 UART_TXFIFO_IRQLEVEL = 0x3c,
60 };
61
62 #define SR_FE (1<<0)
63 #define SR_PE (1<<1)
64 #define SR_BE (1<<2)
65 #define SR_OE (1<<3)
66
67 #define LINE_CR_BRK (1<<0)
68 #define LINE_CR_PEN (1<<1)
69 #define LINE_CR_EPS (1<<2)
70 #define LINE_CR_STP2 (1<<3)
71 #define LINE_CR_FEN (1<<4)
72 #define LINE_CR_5BIT (0<<5)
73 #define LINE_CR_6BIT (1<<5)
74 #define LINE_CR_7BIT (2<<5)
75 #define LINE_CR_8BIT (3<<5)
76 #define LINE_CR_BITS_MASK (3<<5)
77
78 #define CR_UART_EN (1<<0)
79 #define CR_SIREN (1<<1)
80 #define CR_SIRLP (1<<2)
81 #define CR_MSIE (1<<3)
82 #define CR_RIE (1<<4)
83 #define CR_TIE (1<<5)
84 #define CR_RTIE (1<<6)
85 #define CR_LBE (1<<7)
86
87 #define FR_CTS (1<<0)
88 #define FR_DSR (1<<1)
89 #define FR_DCD (1<<2)
90 #define FR_BUSY (1<<3)
91 #define FR_RXFE (1<<4)
92 #define FR_TXFF (1<<5)
93 #define FR_RXFF (1<<6)
94 #define FR_TXFE (1<<7)
95
96 #define IIR_MIS (1<<0)
97 #define IIR_RIS (1<<1)
98 #define IIR_TIS (1<<2)
99 #define IIR_RTIS (1<<3)
100 #define IIR_MASK 0xf
101
102 #define RTS_CR_AUTO (1<<0)
103 #define RTS_CR_RTS (1<<1)
104 #define RTS_CR_COUNT (1<<2)
105 #define RTS_CR_MOD2 (1<<3)
106 #define RTS_CR_RTS_POL (1<<4)
107 #define RTS_CR_CTS_CTR (1<<5)
108 #define RTS_CR_CTS_POL (1<<6)
109 #define RTS_CR_STICK (1<<7)
110
111 #define UART_PORT_SIZE 0x40
112 #define DRIVER_NAME "netx-uart"
113
114 struct netx_port {
115 struct uart_port port;
116 };
117
118 static void netx_stop_tx(struct uart_port *port)
119 {
120 unsigned int val;
121 val = readl(port->membase + UART_CR);
122 writel(val & ~CR_TIE, port->membase + UART_CR);
123 }
124
125 static void netx_stop_rx(struct uart_port *port)
126 {
127 unsigned int val;
128 val = readl(port->membase + UART_CR);
129 writel(val & ~CR_RIE, port->membase + UART_CR);
130 }
131
132 static void netx_enable_ms(struct uart_port *port)
133 {
134 unsigned int val;
135 val = readl(port->membase + UART_CR);
136 writel(val | CR_MSIE, port->membase + UART_CR);
137 }
138
139 static inline void netx_transmit_buffer(struct uart_port *port)
140 {
141 struct circ_buf *xmit = &port->state->xmit;
142
143 if (port->x_char) {
144 writel(port->x_char, port->membase + UART_DR);
145 port->icount.tx++;
146 port->x_char = 0;
147 return;
148 }
149
150 if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
151 netx_stop_tx(port);
152 return;
153 }
154
155 do {
156 /* send xmit->buf[xmit->tail]
157 * out the port here */
158 writel(xmit->buf[xmit->tail], port->membase + UART_DR);
159 xmit->tail = (xmit->tail + 1) &
160 (UART_XMIT_SIZE - 1);
161 port->icount.tx++;
162 if (uart_circ_empty(xmit))
163 break;
164 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
165
166 if (uart_circ_empty(xmit))
167 netx_stop_tx(port);
168 }
169
170 static void netx_start_tx(struct uart_port *port)
171 {
172 writel(
173 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
174
175 if (!(readl(port->membase + UART_FR) & FR_TXFF))
176 netx_transmit_buffer(port);
177 }
178
179 static unsigned int netx_tx_empty(struct uart_port *port)
180 {
181 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
182 }
183
184 static void netx_txint(struct uart_port *port)
185 {
186 struct circ_buf *xmit = &port->state->xmit;
187
188 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
189 netx_stop_tx(port);
190 return;
191 }
192
193 netx_transmit_buffer(port);
194
195 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
196 uart_write_wakeup(port);
197 }
198
199 static void netx_rxint(struct uart_port *port)
200 {
201 unsigned char rx, flg, status;
202 struct tty_struct *tty = port->state->port.tty;
203
204 while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
205 rx = readl(port->membase + UART_DR);
206 flg = TTY_NORMAL;
207 port->icount.rx++;
208 status = readl(port->membase + UART_SR);
209 if (status & SR_BE) {
210 writel(0, port->membase + UART_SR);
211 if (uart_handle_break(port))
212 continue;
213 }
214
215 if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {
216
217 if (status & SR_PE)
218 port->icount.parity++;
219 else if (status & SR_FE)
220 port->icount.frame++;
221 if (status & SR_OE)
222 port->icount.overrun++;
223
224 status &= port->read_status_mask;
225
226 if (status & SR_BE)
227 flg = TTY_BREAK;
228 else if (status & SR_PE)
229 flg = TTY_PARITY;
230 else if (status & SR_FE)
231 flg = TTY_FRAME;
232 }
233
234 if (uart_handle_sysrq_char(port, rx))
235 continue;
236
237 uart_insert_char(port, status, SR_OE, rx, flg);
238 }
239
240 tty_flip_buffer_push(tty);
241 return;
242 }
243
244 static irqreturn_t netx_int(int irq, void *dev_id)
245 {
246 struct uart_port *port = dev_id;
247 unsigned long flags;
248 unsigned char status;
249
250 spin_lock_irqsave(&port->lock,flags);
251
252 status = readl(port->membase + UART_IIR) & IIR_MASK;
253 while (status) {
254 if (status & IIR_RIS)
255 netx_rxint(port);
256 if (status & IIR_TIS)
257 netx_txint(port);
258 if (status & IIR_MIS) {
259 if (readl(port->membase + UART_FR) & FR_CTS)
260 uart_handle_cts_change(port, 1);
261 else
262 uart_handle_cts_change(port, 0);
263 }
264 writel(0, port->membase + UART_IIR);
265 status = readl(port->membase + UART_IIR) & IIR_MASK;
266 }
267
268 spin_unlock_irqrestore(&port->lock,flags);
269 return IRQ_HANDLED;
270 }
271
272 static unsigned int netx_get_mctrl(struct uart_port *port)
273 {
274 unsigned int ret = TIOCM_DSR | TIOCM_CAR;
275
276 if (readl(port->membase + UART_FR) & FR_CTS)
277 ret |= TIOCM_CTS;
278
279 return ret;
280 }
281
282 static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
283 {
284 unsigned int val;
285
286 /* FIXME: Locking needed ? */
287 if (mctrl & TIOCM_RTS) {
288 val = readl(port->membase + UART_RTS_CR);
289 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
290 }
291 }
292
293 static void netx_break_ctl(struct uart_port *port, int break_state)
294 {
295 unsigned int line_cr;
296 spin_lock_irq(&port->lock);
297
298 line_cr = readl(port->membase + UART_LINE_CR);
299 if (break_state != 0)
300 line_cr |= LINE_CR_BRK;
301 else
302 line_cr &= ~LINE_CR_BRK;
303 writel(line_cr, port->membase + UART_LINE_CR);
304
305 spin_unlock_irq(&port->lock);
306 }
307
308 static int netx_startup(struct uart_port *port)
309 {
310 int ret;
311
312 ret = request_irq(port->irq, netx_int, 0,
313 DRIVER_NAME, port);
314 if (ret) {
315 dev_err(port->dev, "unable to grab irq%d\n",port->irq);
316 goto exit;
317 }
318
319 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
320 port->membase + UART_LINE_CR);
321
322 writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
323 port->membase + UART_CR);
324
325 exit:
326 return ret;
327 }
328
329 static void netx_shutdown(struct uart_port *port)
330 {
331 writel(0, port->membase + UART_CR) ;
332
333 free_irq(port->irq, port);
334 }
335
336 static void
337 netx_set_termios(struct uart_port *port, struct ktermios *termios,
338 struct ktermios *old)
339 {
340 unsigned int baud, quot;
341 unsigned char old_cr;
342 unsigned char line_cr = LINE_CR_FEN;
343 unsigned char rts_cr = 0;
344
345 switch (termios->c_cflag & CSIZE) {
346 case CS5:
347 line_cr |= LINE_CR_5BIT;
348 break;
349 case CS6:
350 line_cr |= LINE_CR_6BIT;
351 break;
352 case CS7:
353 line_cr |= LINE_CR_7BIT;
354 break;
355 case CS8:
356 line_cr |= LINE_CR_8BIT;
357 break;
358 }
359
360 if (termios->c_cflag & CSTOPB)
361 line_cr |= LINE_CR_STP2;
362
363 if (termios->c_cflag & PARENB) {
364 line_cr |= LINE_CR_PEN;
365 if (!(termios->c_cflag & PARODD))
366 line_cr |= LINE_CR_EPS;
367 }
368
369 if (termios->c_cflag & CRTSCTS)
370 rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;
371
372 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
373 quot = baud * 4096;
374 quot /= 1000;
375 quot *= 256;
376 quot /= 100000;
377
378 spin_lock_irq(&port->lock);
379
380 uart_update_timeout(port, termios->c_cflag, baud);
381
382 old_cr = readl(port->membase + UART_CR);
383
384 /* disable interrupts */
385 writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
386 port->membase + UART_CR);
387
388 /* drain transmitter */
389 while (readl(port->membase + UART_FR) & FR_BUSY);
390
391 /* disable UART */
392 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
393
394 /* modem status interrupts */
395 old_cr &= ~CR_MSIE;
396 if (UART_ENABLE_MS(port, termios->c_cflag))
397 old_cr |= CR_MSIE;
398
399 writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
400 writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
401 writel(line_cr, port->membase + UART_LINE_CR);
402
403 writel(rts_cr, port->membase + UART_RTS_CR);
404
405 /*
406 * Characters to ignore
407 */
408 port->ignore_status_mask = 0;
409 if (termios->c_iflag & IGNPAR)
410 port->ignore_status_mask |= SR_PE;
411 if (termios->c_iflag & IGNBRK) {
412 port->ignore_status_mask |= SR_BE;
413 /*
414 * If we're ignoring parity and break indicators,
415 * ignore overruns too (for real raw support).
416 */
417 if (termios->c_iflag & IGNPAR)
418 port->ignore_status_mask |= SR_PE;
419 }
420
421 port->read_status_mask = 0;
422 if (termios->c_iflag & (BRKINT | PARMRK))
423 port->read_status_mask |= SR_BE;
424 if (termios->c_iflag & INPCK)
425 port->read_status_mask |= SR_PE | SR_FE;
426
427 writel(old_cr, port->membase + UART_CR);
428
429 spin_unlock_irq(&port->lock);
430 }
431
432 static const char *netx_type(struct uart_port *port)
433 {
434 return port->type == PORT_NETX ? "NETX" : NULL;
435 }
436
437 static void netx_release_port(struct uart_port *port)
438 {
439 release_mem_region(port->mapbase, UART_PORT_SIZE);
440 }
441
442 static int netx_request_port(struct uart_port *port)
443 {
444 return request_mem_region(port->mapbase, UART_PORT_SIZE,
445 DRIVER_NAME) != NULL ? 0 : -EBUSY;
446 }
447
448 static void netx_config_port(struct uart_port *port, int flags)
449 {
450 if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
451 port->type = PORT_NETX;
452 }
453
454 static int
455 netx_verify_port(struct uart_port *port, struct serial_struct *ser)
456 {
457 int ret = 0;
458
459 if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
460 ret = -EINVAL;
461
462 return ret;
463 }
464
465 static struct uart_ops netx_pops = {
466 .tx_empty = netx_tx_empty,
467 .set_mctrl = netx_set_mctrl,
468 .get_mctrl = netx_get_mctrl,
469 .stop_tx = netx_stop_tx,
470 .start_tx = netx_start_tx,
471 .stop_rx = netx_stop_rx,
472 .enable_ms = netx_enable_ms,
473 .break_ctl = netx_break_ctl,
474 .startup = netx_startup,
475 .shutdown = netx_shutdown,
476 .set_termios = netx_set_termios,
477 .type = netx_type,
478 .release_port = netx_release_port,
479 .request_port = netx_request_port,
480 .config_port = netx_config_port,
481 .verify_port = netx_verify_port,
482 };
483
484 static struct netx_port netx_ports[] = {
485 {
486 .port = {
487 .type = PORT_NETX,
488 .iotype = UPIO_MEM,
489 .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
490 .mapbase = NETX_PA_UART0,
491 .irq = NETX_IRQ_UART0,
492 .uartclk = 100000000,
493 .fifosize = 16,
494 .flags = UPF_BOOT_AUTOCONF,
495 .ops = &netx_pops,
496 .line = 0,
497 },
498 }, {
499 .port = {
500 .type = PORT_NETX,
501 .iotype = UPIO_MEM,
502 .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
503 .mapbase = NETX_PA_UART1,
504 .irq = NETX_IRQ_UART1,
505 .uartclk = 100000000,
506 .fifosize = 16,
507 .flags = UPF_BOOT_AUTOCONF,
508 .ops = &netx_pops,
509 .line = 1,
510 },
511 }, {
512 .port = {
513 .type = PORT_NETX,
514 .iotype = UPIO_MEM,
515 .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
516 .mapbase = NETX_PA_UART2,
517 .irq = NETX_IRQ_UART2,
518 .uartclk = 100000000,
519 .fifosize = 16,
520 .flags = UPF_BOOT_AUTOCONF,
521 .ops = &netx_pops,
522 .line = 2,
523 },
524 }
525 };
526
527 #ifdef CONFIG_SERIAL_NETX_CONSOLE
528
529 static void netx_console_putchar(struct uart_port *port, int ch)
530 {
531 while (readl(port->membase + UART_FR) & FR_BUSY);
532 writel(ch, port->membase + UART_DR);
533 }
534
535 static void
536 netx_console_write(struct console *co, const char *s, unsigned int count)
537 {
538 struct uart_port *port = &netx_ports[co->index].port;
539 unsigned char cr_save;
540
541 cr_save = readl(port->membase + UART_CR);
542 writel(cr_save | CR_UART_EN, port->membase + UART_CR);
543
544 uart_console_write(port, s, count, netx_console_putchar);
545
546 while (readl(port->membase + UART_FR) & FR_BUSY);
547 writel(cr_save, port->membase + UART_CR);
548 }
549
550 static void __init
551 netx_console_get_options(struct uart_port *port, int *baud,
552 int *parity, int *bits, int *flow)
553 {
554 unsigned char line_cr;
555
556 *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
557 readl(port->membase + UART_BAUDDIV_LSB);
558 *baud *= 1000;
559 *baud /= 4096;
560 *baud *= 1000;
561 *baud /= 256;
562 *baud *= 100;
563
564 line_cr = readl(port->membase + UART_LINE_CR);
565 *parity = 'n';
566 if (line_cr & LINE_CR_PEN) {
567 if (line_cr & LINE_CR_EPS)
568 *parity = 'e';
569 else
570 *parity = 'o';
571 }
572
573 switch (line_cr & LINE_CR_BITS_MASK) {
574 case LINE_CR_8BIT:
575 *bits = 8;
576 break;
577 case LINE_CR_7BIT:
578 *bits = 7;
579 break;
580 case LINE_CR_6BIT:
581 *bits = 6;
582 break;
583 case LINE_CR_5BIT:
584 *bits = 5;
585 break;
586 }
587
588 if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
589 *flow = 'r';
590 }
591
592 static int __init
593 netx_console_setup(struct console *co, char *options)
594 {
595 struct netx_port *sport;
596 int baud = 9600;
597 int bits = 8;
598 int parity = 'n';
599 int flow = 'n';
600
601 /*
602 * Check whether an invalid uart number has been specified, and
603 * if so, search for the first available port that does have
604 * console support.
605 */
606 if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
607 co->index = 0;
608 sport = &netx_ports[co->index];
609
610 if (options) {
611 uart_parse_options(options, &baud, &parity, &bits, &flow);
612 } else {
613 /* if the UART is enabled, assume it has been correctly setup
614 * by the bootloader and get the options
615 */
616 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
617 netx_console_get_options(&sport->port, &baud,
618 &parity, &bits, &flow);
619 }
620
621 }
622
623 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
624 }
625
626 static struct uart_driver netx_reg;
627 static struct console netx_console = {
628 .name = "ttyNX",
629 .write = netx_console_write,
630 .device = uart_console_device,
631 .setup = netx_console_setup,
632 .flags = CON_PRINTBUFFER,
633 .index = -1,
634 .data = &netx_reg,
635 };
636
637 static int __init netx_console_init(void)
638 {
639 register_console(&netx_console);
640 return 0;
641 }
642 console_initcall(netx_console_init);
643
644 #define NETX_CONSOLE &netx_console
645 #else
646 #define NETX_CONSOLE NULL
647 #endif
648
649 static struct uart_driver netx_reg = {
650 .owner = THIS_MODULE,
651 .driver_name = DRIVER_NAME,
652 .dev_name = "ttyNX",
653 .major = SERIAL_NX_MAJOR,
654 .minor = MINOR_START,
655 .nr = ARRAY_SIZE(netx_ports),
656 .cons = NETX_CONSOLE,
657 };
658
659 static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
660 {
661 struct netx_port *sport = platform_get_drvdata(pdev);
662
663 if (sport)
664 uart_suspend_port(&netx_reg, &sport->port);
665
666 return 0;
667 }
668
669 static int serial_netx_resume(struct platform_device *pdev)
670 {
671 struct netx_port *sport = platform_get_drvdata(pdev);
672
673 if (sport)
674 uart_resume_port(&netx_reg, &sport->port);
675
676 return 0;
677 }
678
679 static int serial_netx_probe(struct platform_device *pdev)
680 {
681 struct uart_port *port = &netx_ports[pdev->id].port;
682
683 dev_info(&pdev->dev, "initialising\n");
684
685 port->dev = &pdev->dev;
686
687 writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
688 uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
689 platform_set_drvdata(pdev, &netx_ports[pdev->id]);
690
691 return 0;
692 }
693
694 static int serial_netx_remove(struct platform_device *pdev)
695 {
696 struct netx_port *sport = platform_get_drvdata(pdev);
697
698 platform_set_drvdata(pdev, NULL);
699
700 if (sport)
701 uart_remove_one_port(&netx_reg, &sport->port);
702
703 return 0;
704 }
705
706 static struct platform_driver serial_netx_driver = {
707 .probe = serial_netx_probe,
708 .remove = serial_netx_remove,
709
710 .suspend = serial_netx_suspend,
711 .resume = serial_netx_resume,
712
713 .driver = {
714 .name = DRIVER_NAME,
715 .owner = THIS_MODULE,
716 },
717 };
718
719 static int __init netx_serial_init(void)
720 {
721 int ret;
722
723 printk(KERN_INFO "Serial: NetX driver\n");
724
725 ret = uart_register_driver(&netx_reg);
726 if (ret)
727 return ret;
728
729 ret = platform_driver_register(&serial_netx_driver);
730 if (ret != 0)
731 uart_unregister_driver(&netx_reg);
732
733 return 0;
734 }
735
736 static void __exit netx_serial_exit(void)
737 {
738 platform_driver_unregister(&serial_netx_driver);
739 uart_unregister_driver(&netx_reg);
740 }
741
742 module_init(netx_serial_init);
743 module_exit(netx_serial_exit);
744
745 MODULE_AUTHOR("Sascha Hauer");
746 MODULE_DESCRIPTION("NetX serial port driver");
747 MODULE_LICENSE("GPL");
748 MODULE_ALIAS("platform:" DRIVER_NAME);