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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / usb / musb / musb_gadget.c
blobfdc2cddcf3eff82fd8cc53105b0f923c82e30f0e
1 /*
2 * MUSB OTG driver peripheral support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45
46 #include "musb_core.h"
47
48
49 /* MUSB PERIPHERAL status 3-mar-2006:
50 *
51 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
52 * Minor glitches:
53 *
54 * + remote wakeup to Linux hosts work, but saw USBCV failures;
55 * in one test run (operator error?)
56 * + endpoint halt tests -- in both usbtest and usbcv -- seem
57 * to break when dma is enabled ... is something wrongly
58 * clearing SENDSTALL?
59 *
60 * - Mass storage behaved ok when last tested. Network traffic patterns
61 * (with lots of short transfers etc) need retesting; they turn up the
62 * worst cases of the DMA, since short packets are typical but are not
63 * required.
64 *
65 * - TX/IN
66 * + both pio and dma behave in with network and g_zero tests
67 * + no cppi throughput issues other than no-hw-queueing
68 * + failed with FLAT_REG (DaVinci)
69 * + seems to behave with double buffering, PIO -and- CPPI
70 * + with gadgetfs + AIO, requests got lost?
71 *
72 * - RX/OUT
73 * + both pio and dma behave in with network and g_zero tests
74 * + dma is slow in typical case (short_not_ok is clear)
75 * + double buffering ok with PIO
76 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
77 * + request lossage observed with gadgetfs
78 *
79 * - ISO not tested ... might work, but only weakly isochronous
80 *
81 * - Gadget driver disabling of softconnect during bind() is ignored; so
82 * drivers can't hold off host requests until userspace is ready.
83 * (Workaround: they can turn it off later.)
84 *
85 * - PORTABILITY (assumes PIO works):
86 * + DaVinci, basically works with cppi dma
87 * + OMAP 2430, ditto with mentor dma
88 * + TUSB 6010, platform-specific dma in the works
89 */
90
91 /* ----------------------------------------------------------------------- */
92
93 #define is_buffer_mapped(req) (is_dma_capable() && \
94 (req->map_state != UN_MAPPED))
95
96 /* Maps the buffer to dma */
97
98 static inline void map_dma_buffer(struct musb_request *request,
99 struct musb *musb, struct musb_ep *musb_ep)
100 {
101 int compatible = true;
102 struct dma_controller *dma = musb->dma_controller;
103
104 request->map_state = UN_MAPPED;
105
106 if (!is_dma_capable() || !musb_ep->dma)
107 return;
108
109 /* Check if DMA engine can handle this request.
110 * DMA code must reject the USB request explicitly.
111 * Default behaviour is to map the request.
112 */
113 if (dma->is_compatible)
114 compatible = dma->is_compatible(musb_ep->dma,
115 musb_ep->packet_sz, request->request.buf,
116 request->request.length);
117 if (!compatible)
118 return;
119
120 if (request->request.dma == DMA_ADDR_INVALID) {
121 request->request.dma = dma_map_single(
122 musb->controller,
123 request->request.buf,
124 request->request.length,
125 request->tx
126 ? DMA_TO_DEVICE
127 : DMA_FROM_DEVICE);
128 request->map_state = MUSB_MAPPED;
129 } else {
130 dma_sync_single_for_device(musb->controller,
131 request->request.dma,
132 request->request.length,
133 request->tx
134 ? DMA_TO_DEVICE
135 : DMA_FROM_DEVICE);
136 request->map_state = PRE_MAPPED;
137 }
138 }
139
140 /* Unmap the buffer from dma and maps it back to cpu */
141 static inline void unmap_dma_buffer(struct musb_request *request,
142 struct musb *musb)
143 {
144 if (!is_buffer_mapped(request))
145 return;
146
147 if (request->request.dma == DMA_ADDR_INVALID) {
148 dev_vdbg(musb->controller,
149 "not unmapping a never mapped buffer\n");
150 return;
151 }
152 if (request->map_state == MUSB_MAPPED) {
153 dma_unmap_single(musb->controller,
154 request->request.dma,
155 request->request.length,
156 request->tx
157 ? DMA_TO_DEVICE
158 : DMA_FROM_DEVICE);
159 request->request.dma = DMA_ADDR_INVALID;
160 } else { /* PRE_MAPPED */
161 dma_sync_single_for_cpu(musb->controller,
162 request->request.dma,
163 request->request.length,
164 request->tx
165 ? DMA_TO_DEVICE
166 : DMA_FROM_DEVICE);
167 }
168 request->map_state = UN_MAPPED;
169 }
170
171 /*
172 * Immediately complete a request.
173 *
174 * @param request the request to complete
175 * @param status the status to complete the request with
176 * Context: controller locked, IRQs blocked.
177 */
178 void musb_g_giveback(
179 struct musb_ep *ep,
180 struct usb_request *request,
181 int status)
182 __releases(ep->musb->lock)
183 __acquires(ep->musb->lock)
184 {
185 struct musb_request *req;
186 struct musb *musb;
187 int busy = ep->busy;
188
189 req = to_musb_request(request);
190
191 list_del(&req->list);
192 if (req->request.status == -EINPROGRESS)
193 req->request.status = status;
194 musb = req->musb;
195
196 ep->busy = 1;
197 spin_unlock(&musb->lock);
198 unmap_dma_buffer(req, musb);
199 if (request->status == 0)
200 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
201 ep->end_point.name, request,
202 req->request.actual, req->request.length);
203 else
204 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
205 ep->end_point.name, request,
206 req->request.actual, req->request.length,
207 request->status);
208 req->request.complete(&req->ep->end_point, &req->request);
209 spin_lock(&musb->lock);
210 ep->busy = busy;
211 }
212
213 /* ----------------------------------------------------------------------- */
214
215 /*
216 * Abort requests queued to an endpoint using the status. Synchronous.
217 * caller locked controller and blocked irqs, and selected this ep.
218 */
219 static void nuke(struct musb_ep *ep, const int status)
220 {
221 struct musb *musb = ep->musb;
222 struct musb_request *req = NULL;
223 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
224
225 ep->busy = 1;
226
227 if (is_dma_capable() && ep->dma) {
228 struct dma_controller *c = ep->musb->dma_controller;
229 int value;
230
231 if (ep->is_in) {
232 /*
233 * The programming guide says that we must not clear
234 * the DMAMODE bit before DMAENAB, so we only
235 * clear it in the second write...
236 */
237 musb_writew(epio, MUSB_TXCSR,
238 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
239 musb_writew(epio, MUSB_TXCSR,
240 0 | MUSB_TXCSR_FLUSHFIFO);
241 } else {
242 musb_writew(epio, MUSB_RXCSR,
243 0 | MUSB_RXCSR_FLUSHFIFO);
244 musb_writew(epio, MUSB_RXCSR,
245 0 | MUSB_RXCSR_FLUSHFIFO);
246 }
247
248 value = c->channel_abort(ep->dma);
249 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
250 ep->name, value);
251 c->channel_release(ep->dma);
252 ep->dma = NULL;
253 }
254
255 while (!list_empty(&ep->req_list)) {
256 req = list_first_entry(&ep->req_list, struct musb_request, list);
257 musb_g_giveback(ep, &req->request, status);
258 }
259 }
260
261 /* ----------------------------------------------------------------------- */
262
263 /* Data transfers - pure PIO, pure DMA, or mixed mode */
264
265 /*
266 * This assumes the separate CPPI engine is responding to DMA requests
267 * from the usb core ... sequenced a bit differently from mentor dma.
268 */
269
270 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
271 {
272 if (can_bulk_split(musb, ep->type))
273 return ep->hw_ep->max_packet_sz_tx;
274 else
275 return ep->packet_sz;
276 }
277
278
279 #ifdef CONFIG_USB_INVENTRA_DMA
280
281 /* Peripheral tx (IN) using Mentor DMA works as follows:
282 Only mode 0 is used for transfers <= wPktSize,
283 mode 1 is used for larger transfers,
284
285 One of the following happens:
286 - Host sends IN token which causes an endpoint interrupt
287 -> TxAvail
288 -> if DMA is currently busy, exit.
289 -> if queue is non-empty, txstate().
290
291 - Request is queued by the gadget driver.
292 -> if queue was previously empty, txstate()
293
294 txstate()
295 -> start
296 /\ -> setup DMA
297 | (data is transferred to the FIFO, then sent out when
298 | IN token(s) are recd from Host.
299 | -> DMA interrupt on completion
300 | calls TxAvail.
301 | -> stop DMA, ~DMAENAB,
302 | -> set TxPktRdy for last short pkt or zlp
303 | -> Complete Request
304 | -> Continue next request (call txstate)
305 |___________________________________|
306
307 * Non-Mentor DMA engines can of course work differently, such as by
308 * upleveling from irq-per-packet to irq-per-buffer.
309 */
310
311 #endif
312
313 /*
314 * An endpoint is transmitting data. This can be called either from
315 * the IRQ routine or from ep.queue() to kickstart a request on an
316 * endpoint.
317 *
318 * Context: controller locked, IRQs blocked, endpoint selected
319 */
320 static void txstate(struct musb *musb, struct musb_request *req)
321 {
322 u8 epnum = req->epnum;
323 struct musb_ep *musb_ep;
324 void __iomem *epio = musb->endpoints[epnum].regs;
325 struct usb_request *request;
326 u16 fifo_count = 0, csr;
327 int use_dma = 0;
328
329 musb_ep = req->ep;
330
331 /* we shouldn't get here while DMA is active ... but we do ... */
332 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
333 dev_dbg(musb->controller, "dma pending...\n");
334 return;
335 }
336
337 /* read TXCSR before */
338 csr = musb_readw(epio, MUSB_TXCSR);
339
340 request = &req->request;
341 fifo_count = min(max_ep_writesize(musb, musb_ep),
342 (int)(request->length - request->actual));
343
344 if (csr & MUSB_TXCSR_TXPKTRDY) {
345 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
346 musb_ep->end_point.name, csr);
347 return;
348 }
349
350 if (csr & MUSB_TXCSR_P_SENDSTALL) {
351 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
352 musb_ep->end_point.name, csr);
353 return;
354 }
355
356 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
357 epnum, musb_ep->packet_sz, fifo_count,
358 csr);
359
360 #ifndef CONFIG_MUSB_PIO_ONLY
361 if (is_buffer_mapped(req)) {
362 struct dma_controller *c = musb->dma_controller;
363 size_t request_size;
364
365 /* setup DMA, then program endpoint CSR */
366 request_size = min_t(size_t, request->length - request->actual,
367 musb_ep->dma->max_len);
368
369 use_dma = (request->dma != DMA_ADDR_INVALID);
370
371 /* MUSB_TXCSR_P_ISO is still set correctly */
372
373 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
374 {
375 if (request_size < musb_ep->packet_sz)
376 musb_ep->dma->desired_mode = 0;
377 else
378 musb_ep->dma->desired_mode = 1;
379
380 use_dma = use_dma && c->channel_program(
381 musb_ep->dma, musb_ep->packet_sz,
382 musb_ep->dma->desired_mode,
383 request->dma + request->actual, request_size);
384 if (use_dma) {
385 if (musb_ep->dma->desired_mode == 0) {
386 /*
387 * We must not clear the DMAMODE bit
388 * before the DMAENAB bit -- and the
389 * latter doesn't always get cleared
390 * before we get here...
391 */
392 csr &= ~(MUSB_TXCSR_AUTOSET
393 | MUSB_TXCSR_DMAENAB);
394 musb_writew(epio, MUSB_TXCSR, csr
395 | MUSB_TXCSR_P_WZC_BITS);
396 csr &= ~MUSB_TXCSR_DMAMODE;
397 csr |= (MUSB_TXCSR_DMAENAB |
398 MUSB_TXCSR_MODE);
399 /* against programming guide */
400 } else {
401 csr |= (MUSB_TXCSR_DMAENAB
402 | MUSB_TXCSR_DMAMODE
403 | MUSB_TXCSR_MODE);
404 if (!musb_ep->hb_mult)
405 csr |= MUSB_TXCSR_AUTOSET;
406 }
407 csr &= ~MUSB_TXCSR_P_UNDERRUN;
408
409 musb_writew(epio, MUSB_TXCSR, csr);
410 }
411 }
412
413 #elif defined(CONFIG_USB_TI_CPPI_DMA)
414 /* program endpoint CSR first, then setup DMA */
415 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
416 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
417 MUSB_TXCSR_MODE;
418 musb_writew(epio, MUSB_TXCSR,
419 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
420 | csr);
421
422 /* ensure writebuffer is empty */
423 csr = musb_readw(epio, MUSB_TXCSR);
424
425 /* NOTE host side sets DMAENAB later than this; both are
426 * OK since the transfer dma glue (between CPPI and Mentor
427 * fifos) just tells CPPI it could start. Data only moves
428 * to the USB TX fifo when both fifos are ready.
429 */
430
431 /* "mode" is irrelevant here; handle terminating ZLPs like
432 * PIO does, since the hardware RNDIS mode seems unreliable
433 * except for the last-packet-is-already-short case.
434 */
435 use_dma = use_dma && c->channel_program(
436 musb_ep->dma, musb_ep->packet_sz,
437 0,
438 request->dma + request->actual,
439 request_size);
440 if (!use_dma) {
441 c->channel_release(musb_ep->dma);
442 musb_ep->dma = NULL;
443 csr &= ~MUSB_TXCSR_DMAENAB;
444 musb_writew(epio, MUSB_TXCSR, csr);
445 /* invariant: prequest->buf is non-null */
446 }
447 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
448 use_dma = use_dma && c->channel_program(
449 musb_ep->dma, musb_ep->packet_sz,
450 request->zero,
451 request->dma + request->actual,
452 request_size);
453 #endif
454 }
455 #endif
456
457 if (!use_dma) {
458 /*
459 * Unmap the dma buffer back to cpu if dma channel
460 * programming fails
461 */
462 unmap_dma_buffer(req, musb);
463
464 musb_write_fifo(musb_ep->hw_ep, fifo_count,
465 (u8 *) (request->buf + request->actual));
466 request->actual += fifo_count;
467 csr |= MUSB_TXCSR_TXPKTRDY;
468 csr &= ~MUSB_TXCSR_P_UNDERRUN;
469 musb_writew(epio, MUSB_TXCSR, csr);
470 }
471
472 /* host may already have the data when this message shows... */
473 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
474 musb_ep->end_point.name, use_dma ? "dma" : "pio",
475 request->actual, request->length,
476 musb_readw(epio, MUSB_TXCSR),
477 fifo_count,
478 musb_readw(epio, MUSB_TXMAXP));
479 }
480
481 /*
482 * FIFO state update (e.g. data ready).
483 * Called from IRQ, with controller locked.
484 */
485 void musb_g_tx(struct musb *musb, u8 epnum)
486 {
487 u16 csr;
488 struct musb_request *req;
489 struct usb_request *request;
490 u8 __iomem *mbase = musb->mregs;
491 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
492 void __iomem *epio = musb->endpoints[epnum].regs;
493 struct dma_channel *dma;
494
495 musb_ep_select(mbase, epnum);
496 req = next_request(musb_ep);
497 request = &req->request;
498
499 csr = musb_readw(epio, MUSB_TXCSR);
500 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
501
502 dma = is_dma_capable() ? musb_ep->dma : NULL;
503
504 /*
505 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
506 * probably rates reporting as a host error.
507 */
508 if (csr & MUSB_TXCSR_P_SENTSTALL) {
509 csr |= MUSB_TXCSR_P_WZC_BITS;
510 csr &= ~MUSB_TXCSR_P_SENTSTALL;
511 musb_writew(epio, MUSB_TXCSR, csr);
512 return;
513 }
514
515 if (csr & MUSB_TXCSR_P_UNDERRUN) {
516 /* We NAKed, no big deal... little reason to care. */
517 csr |= MUSB_TXCSR_P_WZC_BITS;
518 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
519 musb_writew(epio, MUSB_TXCSR, csr);
520 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
521 epnum, request);
522 }
523
524 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
525 /*
526 * SHOULD NOT HAPPEN... has with CPPI though, after
527 * changing SENDSTALL (and other cases); harmless?
528 */
529 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
530 return;
531 }
532
533 if (request) {
534 u8 is_dma = 0;
535
536 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
537 is_dma = 1;
538 csr |= MUSB_TXCSR_P_WZC_BITS;
539 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
540 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
541 musb_writew(epio, MUSB_TXCSR, csr);
542 /* Ensure writebuffer is empty. */
543 csr = musb_readw(epio, MUSB_TXCSR);
544 request->actual += musb_ep->dma->actual_len;
545 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
546 epnum, csr, musb_ep->dma->actual_len, request);
547 }
548
549 /*
550 * First, maybe a terminating short packet. Some DMA
551 * engines might handle this by themselves.
552 */
553 if ((request->zero && request->length
554 && (request->length % musb_ep->packet_sz == 0)
555 && (request->actual == request->length))
556 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
557 || (is_dma && (!dma->desired_mode ||
558 (request->actual &
559 (musb_ep->packet_sz - 1))))
560 #endif
561 ) {
562 /*
563 * On DMA completion, FIFO may not be
564 * available yet...
565 */
566 if (csr & MUSB_TXCSR_TXPKTRDY)
567 return;
568
569 dev_dbg(musb->controller, "sending zero pkt\n");
570 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
571 | MUSB_TXCSR_TXPKTRDY);
572 request->zero = 0;
573 }
574
575 if (request->actual == request->length) {
576 musb_g_giveback(musb_ep, request, 0);
577 /*
578 * In the giveback function the MUSB lock is
579 * released and acquired after sometime. During
580 * this time period the INDEX register could get
581 * changed by the gadget_queue function especially
582 * on SMP systems. Reselect the INDEX to be sure
583 * we are reading/modifying the right registers
584 */
585 musb_ep_select(mbase, epnum);
586 req = musb_ep->desc ? next_request(musb_ep) : NULL;
587 if (!req) {
588 dev_dbg(musb->controller, "%s idle now\n",
589 musb_ep->end_point.name);
590 return;
591 }
592 }
593
594 txstate(musb, req);
595 }
596 }
597
598 /* ------------------------------------------------------------ */
599
600 #ifdef CONFIG_USB_INVENTRA_DMA
601
602 /* Peripheral rx (OUT) using Mentor DMA works as follows:
603 - Only mode 0 is used.
604
605 - Request is queued by the gadget class driver.
606 -> if queue was previously empty, rxstate()
607
608 - Host sends OUT token which causes an endpoint interrupt
609 /\ -> RxReady
610 | -> if request queued, call rxstate
611 | /\ -> setup DMA
612 | | -> DMA interrupt on completion
613 | | -> RxReady
614 | | -> stop DMA
615 | | -> ack the read
616 | | -> if data recd = max expected
617 | | by the request, or host
618 | | sent a short packet,
619 | | complete the request,
620 | | and start the next one.
621 | |_____________________________________|
622 | else just wait for the host
623 | to send the next OUT token.
624 |__________________________________________________|
625
626 * Non-Mentor DMA engines can of course work differently.
627 */
628
629 #endif
630
631 /*
632 * Context: controller locked, IRQs blocked, endpoint selected
633 */
634 static void rxstate(struct musb *musb, struct musb_request *req)
635 {
636 const u8 epnum = req->epnum;
637 struct usb_request *request = &req->request;
638 struct musb_ep *musb_ep;
639 void __iomem *epio = musb->endpoints[epnum].regs;
640 unsigned fifo_count = 0;
641 u16 len;
642 u16 csr = musb_readw(epio, MUSB_RXCSR);
643 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
644 u8 use_mode_1;
645
646 if (hw_ep->is_shared_fifo)
647 musb_ep = &hw_ep->ep_in;
648 else
649 musb_ep = &hw_ep->ep_out;
650
651 len = musb_ep->packet_sz;
652
653 /* We shouldn't get here while DMA is active, but we do... */
654 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
655 dev_dbg(musb->controller, "DMA pending...\n");
656 return;
657 }
658
659 if (csr & MUSB_RXCSR_P_SENDSTALL) {
660 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
661 musb_ep->end_point.name, csr);
662 return;
663 }
664
665 if (is_cppi_enabled() && is_buffer_mapped(req)) {
666 struct dma_controller *c = musb->dma_controller;
667 struct dma_channel *channel = musb_ep->dma;
668
669 /* NOTE: CPPI won't actually stop advancing the DMA
670 * queue after short packet transfers, so this is almost
671 * always going to run as IRQ-per-packet DMA so that
672 * faults will be handled correctly.
673 */
674 if (c->channel_program(channel,
675 musb_ep->packet_sz,
676 !request->short_not_ok,
677 request->dma + request->actual,
678 request->length - request->actual)) {
679
680 /* make sure that if an rxpkt arrived after the irq,
681 * the cppi engine will be ready to take it as soon
682 * as DMA is enabled
683 */
684 csr &= ~(MUSB_RXCSR_AUTOCLEAR
685 | MUSB_RXCSR_DMAMODE);
686 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
687 musb_writew(epio, MUSB_RXCSR, csr);
688 return;
689 }
690 }
691
692 if (csr & MUSB_RXCSR_RXPKTRDY) {
693 len = musb_readw(epio, MUSB_RXCOUNT);
694
695 /*
696 * Enable Mode 1 on RX transfers only when short_not_ok flag
697 * is set. Currently short_not_ok flag is set only from
698 * file_storage and f_mass_storage drivers
699 */
700
701 if (request->short_not_ok && len == musb_ep->packet_sz)
702 use_mode_1 = 1;
703 else
704 use_mode_1 = 0;
705
706 if (request->actual < request->length) {
707 #ifdef CONFIG_USB_INVENTRA_DMA
708 if (is_buffer_mapped(req)) {
709 struct dma_controller *c;
710 struct dma_channel *channel;
711 int use_dma = 0;
712
713 c = musb->dma_controller;
714 channel = musb_ep->dma;
715
716 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
717 * mode 0 only. So we do not get endpoint interrupts due to DMA
718 * completion. We only get interrupts from DMA controller.
719 *
720 * We could operate in DMA mode 1 if we knew the size of the tranfer
721 * in advance. For mass storage class, request->length = what the host
722 * sends, so that'd work. But for pretty much everything else,
723 * request->length is routinely more than what the host sends. For
724 * most these gadgets, end of is signified either by a short packet,
725 * or filling the last byte of the buffer. (Sending extra data in
726 * that last pckate should trigger an overflow fault.) But in mode 1,
727 * we don't get DMA completion interrupt for short packets.
728 *
729 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
730 * to get endpoint interrupt on every DMA req, but that didn't seem
731 * to work reliably.
732 *
733 * REVISIT an updated g_file_storage can set req->short_not_ok, which
734 * then becomes usable as a runtime "use mode 1" hint...
735 */
736
737 /* Experimental: Mode1 works with mass storage use cases */
738 if (use_mode_1) {
739 csr |= MUSB_RXCSR_AUTOCLEAR;
740 musb_writew(epio, MUSB_RXCSR, csr);
741 csr |= MUSB_RXCSR_DMAENAB;
742 musb_writew(epio, MUSB_RXCSR, csr);
743
744 /*
745 * this special sequence (enabling and then
746 * disabling MUSB_RXCSR_DMAMODE) is required
747 * to get DMAReq to activate
748 */
749 musb_writew(epio, MUSB_RXCSR,
750 csr | MUSB_RXCSR_DMAMODE);
751 musb_writew(epio, MUSB_RXCSR, csr);
752
753 } else {
754 if (!musb_ep->hb_mult &&
755 musb_ep->hw_ep->rx_double_buffered)
756 csr |= MUSB_RXCSR_AUTOCLEAR;
757 csr |= MUSB_RXCSR_DMAENAB;
758 musb_writew(epio, MUSB_RXCSR, csr);
759 }
760
761 if (request->actual < request->length) {
762 int transfer_size = 0;
763 if (use_mode_1) {
764 transfer_size = min(request->length - request->actual,
765 channel->max_len);
766 musb_ep->dma->desired_mode = 1;
767 } else {
768 transfer_size = min(request->length - request->actual,
769 (unsigned)len);
770 musb_ep->dma->desired_mode = 0;
771 }
772
773 use_dma = c->channel_program(
774 channel,
775 musb_ep->packet_sz,
776 channel->desired_mode,
777 request->dma
778 + request->actual,
779 transfer_size);
780 }
781
782 if (use_dma)
783 return;
784 }
785 #elif defined(CONFIG_USB_UX500_DMA)
786 if ((is_buffer_mapped(req)) &&
787 (request->actual < request->length)) {
788
789 struct dma_controller *c;
790 struct dma_channel *channel;
791 int transfer_size = 0;
792
793 c = musb->dma_controller;
794 channel = musb_ep->dma;
795
796 /* In case first packet is short */
797 if (len < musb_ep->packet_sz)
798 transfer_size = len;
799 else if (request->short_not_ok)
800 transfer_size = min(request->length -
801 request->actual,
802 channel->max_len);
803 else
804 transfer_size = min(request->length -
805 request->actual,
806 (unsigned)len);
807
808 csr &= ~MUSB_RXCSR_DMAMODE;
809 csr |= (MUSB_RXCSR_DMAENAB |
810 MUSB_RXCSR_AUTOCLEAR);
811
812 musb_writew(epio, MUSB_RXCSR, csr);
813
814 if (transfer_size <= musb_ep->packet_sz) {
815 musb_ep->dma->desired_mode = 0;
816 } else {
817 musb_ep->dma->desired_mode = 1;
818 /* Mode must be set after DMAENAB */
819 csr |= MUSB_RXCSR_DMAMODE;
820 musb_writew(epio, MUSB_RXCSR, csr);
821 }
822
823 if (c->channel_program(channel,
824 musb_ep->packet_sz,
825 channel->desired_mode,
826 request->dma
827 + request->actual,
828 transfer_size))
829
830 return;
831 }
832 #endif /* Mentor's DMA */
833
834 fifo_count = request->length - request->actual;
835 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
836 musb_ep->end_point.name,
837 len, fifo_count,
838 musb_ep->packet_sz);
839
840 fifo_count = min_t(unsigned, len, fifo_count);
841
842 #ifdef CONFIG_USB_TUSB_OMAP_DMA
843 if (tusb_dma_omap() && is_buffer_mapped(req)) {
844 struct dma_controller *c = musb->dma_controller;
845 struct dma_channel *channel = musb_ep->dma;
846 u32 dma_addr = request->dma + request->actual;
847 int ret;
848
849 ret = c->channel_program(channel,
850 musb_ep->packet_sz,
851 channel->desired_mode,
852 dma_addr,
853 fifo_count);
854 if (ret)
855 return;
856 }
857 #endif
858 /*
859 * Unmap the dma buffer back to cpu if dma channel
860 * programming fails. This buffer is mapped if the
861 * channel allocation is successful
862 */
863 if (is_buffer_mapped(req)) {
864 unmap_dma_buffer(req, musb);
865
866 /*
867 * Clear DMAENAB and AUTOCLEAR for the
868 * PIO mode transfer
869 */
870 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
871 musb_writew(epio, MUSB_RXCSR, csr);
872 }
873
874 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
875 (request->buf + request->actual));
876 request->actual += fifo_count;
877
878 /* REVISIT if we left anything in the fifo, flush
879 * it and report -EOVERFLOW
880 */
881
882 /* ack the read! */
883 csr |= MUSB_RXCSR_P_WZC_BITS;
884 csr &= ~MUSB_RXCSR_RXPKTRDY;
885 musb_writew(epio, MUSB_RXCSR, csr);
886 }
887 }
888
889 /* reach the end or short packet detected */
890 if (request->actual == request->length || len < musb_ep->packet_sz)
891 musb_g_giveback(musb_ep, request, 0);
892 }
893
894 /*
895 * Data ready for a request; called from IRQ
896 */
897 void musb_g_rx(struct musb *musb, u8 epnum)
898 {
899 u16 csr;
900 struct musb_request *req;
901 struct usb_request *request;
902 void __iomem *mbase = musb->mregs;
903 struct musb_ep *musb_ep;
904 void __iomem *epio = musb->endpoints[epnum].regs;
905 struct dma_channel *dma;
906 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
907
908 if (hw_ep->is_shared_fifo)
909 musb_ep = &hw_ep->ep_in;
910 else
911 musb_ep = &hw_ep->ep_out;
912
913 musb_ep_select(mbase, epnum);
914
915 req = next_request(musb_ep);
916 if (!req)
917 return;
918
919 request = &req->request;
920
921 csr = musb_readw(epio, MUSB_RXCSR);
922 dma = is_dma_capable() ? musb_ep->dma : NULL;
923
924 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
925 csr, dma ? " (dma)" : "", request);
926
927 if (csr & MUSB_RXCSR_P_SENTSTALL) {
928 csr |= MUSB_RXCSR_P_WZC_BITS;
929 csr &= ~MUSB_RXCSR_P_SENTSTALL;
930 musb_writew(epio, MUSB_RXCSR, csr);
931 return;
932 }
933
934 if (csr & MUSB_RXCSR_P_OVERRUN) {
935 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
936 csr &= ~MUSB_RXCSR_P_OVERRUN;
937 musb_writew(epio, MUSB_RXCSR, csr);
938
939 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
940 if (request->status == -EINPROGRESS)
941 request->status = -EOVERFLOW;
942 }
943 if (csr & MUSB_RXCSR_INCOMPRX) {
944 /* REVISIT not necessarily an error */
945 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
946 }
947
948 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
949 /* "should not happen"; likely RXPKTRDY pending for DMA */
950 dev_dbg(musb->controller, "%s busy, csr %04x\n",
951 musb_ep->end_point.name, csr);
952 return;
953 }
954
955 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
956 csr &= ~(MUSB_RXCSR_AUTOCLEAR
957 | MUSB_RXCSR_DMAENAB
958 | MUSB_RXCSR_DMAMODE);
959 musb_writew(epio, MUSB_RXCSR,
960 MUSB_RXCSR_P_WZC_BITS | csr);
961
962 request->actual += musb_ep->dma->actual_len;
963
964 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
965 epnum, csr,
966 musb_readw(epio, MUSB_RXCSR),
967 musb_ep->dma->actual_len, request);
968
969 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
970 defined(CONFIG_USB_UX500_DMA)
971 /* Autoclear doesn't clear RxPktRdy for short packets */
972 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
973 || (dma->actual_len
974 & (musb_ep->packet_sz - 1))) {
975 /* ack the read! */
976 csr &= ~MUSB_RXCSR_RXPKTRDY;
977 musb_writew(epio, MUSB_RXCSR, csr);
978 }
979
980 /* incomplete, and not short? wait for next IN packet */
981 if ((request->actual < request->length)
982 && (musb_ep->dma->actual_len
983 == musb_ep->packet_sz)) {
984 /* In double buffer case, continue to unload fifo if
985 * there is Rx packet in FIFO.
986 **/
987 csr = musb_readw(epio, MUSB_RXCSR);
988 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
989 hw_ep->rx_double_buffered)
990 goto exit;
991 return;
992 }
993 #endif
994 musb_g_giveback(musb_ep, request, 0);
995 /*
996 * In the giveback function the MUSB lock is
997 * released and acquired after sometime. During
998 * this time period the INDEX register could get
999 * changed by the gadget_queue function especially
1000 * on SMP systems. Reselect the INDEX to be sure
1001 * we are reading/modifying the right registers
1002 */
1003 musb_ep_select(mbase, epnum);
1004
1005 req = next_request(musb_ep);
1006 if (!req)
1007 return;
1008 }
1009 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
1010 defined(CONFIG_USB_UX500_DMA)
1011 exit:
1012 #endif
1013 /* Analyze request */
1014 rxstate(musb, req);
1015 }
1016
1017 /* ------------------------------------------------------------ */
1018
1019 static int musb_gadget_enable(struct usb_ep *ep,
1020 const struct usb_endpoint_descriptor *desc)
1021 {
1022 unsigned long flags;
1023 struct musb_ep *musb_ep;
1024 struct musb_hw_ep *hw_ep;
1025 void __iomem *regs;
1026 struct musb *musb;
1027 void __iomem *mbase;
1028 u8 epnum;
1029 u16 csr;
1030 unsigned tmp;
1031 int status = -EINVAL;
1032
1033 if (!ep || !desc)
1034 return -EINVAL;
1035
1036 musb_ep = to_musb_ep(ep);
1037 hw_ep = musb_ep->hw_ep;
1038 regs = hw_ep->regs;
1039 musb = musb_ep->musb;
1040 mbase = musb->mregs;
1041 epnum = musb_ep->current_epnum;
1042
1043 spin_lock_irqsave(&musb->lock, flags);
1044
1045 if (musb_ep->desc) {
1046 status = -EBUSY;
1047 goto fail;
1048 }
1049 musb_ep->type = usb_endpoint_type(desc);
1050
1051 /* check direction and (later) maxpacket size against endpoint */
1052 if (usb_endpoint_num(desc) != epnum)
1053 goto fail;
1054
1055 /* REVISIT this rules out high bandwidth periodic transfers */
1056 tmp = usb_endpoint_maxp(desc);
1057 if (tmp & ~0x07ff) {
1058 int ok;
1059
1060 if (usb_endpoint_dir_in(desc))
1061 ok = musb->hb_iso_tx;
1062 else
1063 ok = musb->hb_iso_rx;
1064
1065 if (!ok) {
1066 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
1067 goto fail;
1068 }
1069 musb_ep->hb_mult = (tmp >> 11) & 3;
1070 } else {
1071 musb_ep->hb_mult = 0;
1072 }
1073
1074 musb_ep->packet_sz = tmp & 0x7ff;
1075 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
1076
1077 /* enable the interrupts for the endpoint, set the endpoint
1078 * packet size (or fail), set the mode, clear the fifo
1079 */
1080 musb_ep_select(mbase, epnum);
1081 if (usb_endpoint_dir_in(desc)) {
1082 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1083
1084 if (hw_ep->is_shared_fifo)
1085 musb_ep->is_in = 1;
1086 if (!musb_ep->is_in)
1087 goto fail;
1088
1089 if (tmp > hw_ep->max_packet_sz_tx) {
1090 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1091 goto fail;
1092 }
1093
1094 int_txe |= (1 << epnum);
1095 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1096
1097 /* REVISIT if can_bulk_split(), use by updating "tmp";
1098 * likewise high bandwidth periodic tx
1099 */
1100 /* Set TXMAXP with the FIFO size of the endpoint
1101 * to disable double buffering mode.
1102 */
1103 if (musb->double_buffer_not_ok)
1104 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1105 else
1106 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1107 | (musb_ep->hb_mult << 11));
1108
1109 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1110 if (musb_readw(regs, MUSB_TXCSR)
1111 & MUSB_TXCSR_FIFONOTEMPTY)
1112 csr |= MUSB_TXCSR_FLUSHFIFO;
1113 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1114 csr |= MUSB_TXCSR_P_ISO;
1115
1116 /* set twice in case of double buffering */
1117 musb_writew(regs, MUSB_TXCSR, csr);
1118 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1119 musb_writew(regs, MUSB_TXCSR, csr);
1120
1121 } else {
1122 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
1123
1124 if (hw_ep->is_shared_fifo)
1125 musb_ep->is_in = 0;
1126 if (musb_ep->is_in)
1127 goto fail;
1128
1129 if (tmp > hw_ep->max_packet_sz_rx) {
1130 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1131 goto fail;
1132 }
1133
1134 int_rxe |= (1 << epnum);
1135 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
1136
1137 /* REVISIT if can_bulk_combine() use by updating "tmp"
1138 * likewise high bandwidth periodic rx
1139 */
1140 /* Set RXMAXP with the FIFO size of the endpoint
1141 * to disable double buffering mode.
1142 */
1143 if (musb->double_buffer_not_ok)
1144 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1145 else
1146 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1147 | (musb_ep->hb_mult << 11));
1148
1149 /* force shared fifo to OUT-only mode */
1150 if (hw_ep->is_shared_fifo) {
1151 csr = musb_readw(regs, MUSB_TXCSR);
1152 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1153 musb_writew(regs, MUSB_TXCSR, csr);
1154 }
1155
1156 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1157 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1158 csr |= MUSB_RXCSR_P_ISO;
1159 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1160 csr |= MUSB_RXCSR_DISNYET;
1161
1162 /* set twice in case of double buffering */
1163 musb_writew(regs, MUSB_RXCSR, csr);
1164 musb_writew(regs, MUSB_RXCSR, csr);
1165 }
1166
1167 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1168 * for some reason you run out of channels here.
1169 */
1170 if (is_dma_capable() && musb->dma_controller) {
1171 struct dma_controller *c = musb->dma_controller;
1172
1173 musb_ep->dma = c->channel_alloc(c, hw_ep,
1174 (desc->bEndpointAddress & USB_DIR_IN));
1175 } else
1176 musb_ep->dma = NULL;
1177
1178 musb_ep->desc = desc;
1179 musb_ep->busy = 0;
1180 musb_ep->wedged = 0;
1181 status = 0;
1182
1183 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1184 musb_driver_name, musb_ep->end_point.name,
1185 ({ char *s; switch (musb_ep->type) {
1186 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1187 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1188 default: s = "iso"; break;
1189 }; s; }),
1190 musb_ep->is_in ? "IN" : "OUT",
1191 musb_ep->dma ? "dma, " : "",
1192 musb_ep->packet_sz);
1193
1194 schedule_work(&musb->irq_work);
1195
1196 fail:
1197 spin_unlock_irqrestore(&musb->lock, flags);
1198 return status;
1199 }
1200
1201 /*
1202 * Disable an endpoint flushing all requests queued.
1203 */
1204 static int musb_gadget_disable(struct usb_ep *ep)
1205 {
1206 unsigned long flags;
1207 struct musb *musb;
1208 u8 epnum;
1209 struct musb_ep *musb_ep;
1210 void __iomem *epio;
1211 int status = 0;
1212
1213 musb_ep = to_musb_ep(ep);
1214 musb = musb_ep->musb;
1215 epnum = musb_ep->current_epnum;
1216 epio = musb->endpoints[epnum].regs;
1217
1218 spin_lock_irqsave(&musb->lock, flags);
1219 musb_ep_select(musb->mregs, epnum);
1220
1221 /* zero the endpoint sizes */
1222 if (musb_ep->is_in) {
1223 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1224 int_txe &= ~(1 << epnum);
1225 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1226 musb_writew(epio, MUSB_TXMAXP, 0);
1227 } else {
1228 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1229 int_rxe &= ~(1 << epnum);
1230 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1231 musb_writew(epio, MUSB_RXMAXP, 0);
1232 }
1233
1234 musb_ep->desc = NULL;
1235
1236 /* abort all pending DMA and requests */
1237 nuke(musb_ep, -ESHUTDOWN);
1238
1239 schedule_work(&musb->irq_work);
1240
1241 spin_unlock_irqrestore(&(musb->lock), flags);
1242
1243 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1244
1245 return status;
1246 }
1247
1248 /*
1249 * Allocate a request for an endpoint.
1250 * Reused by ep0 code.
1251 */
1252 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1253 {
1254 struct musb_ep *musb_ep = to_musb_ep(ep);
1255 struct musb *musb = musb_ep->musb;
1256 struct musb_request *request = NULL;
1257
1258 request = kzalloc(sizeof *request, gfp_flags);
1259 if (!request) {
1260 dev_dbg(musb->controller, "not enough memory\n");
1261 return NULL;
1262 }
1263
1264 request->request.dma = DMA_ADDR_INVALID;
1265 request->epnum = musb_ep->current_epnum;
1266 request->ep = musb_ep;
1267
1268 return &request->request;
1269 }
1270
1271 /*
1272 * Free a request
1273 * Reused by ep0 code.
1274 */
1275 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1276 {
1277 kfree(to_musb_request(req));
1278 }
1279
1280 static LIST_HEAD(buffers);
1281
1282 struct free_record {
1283 struct list_head list;
1284 struct device *dev;
1285 unsigned bytes;
1286 dma_addr_t dma;
1287 };
1288
1289 /*
1290 * Context: controller locked, IRQs blocked.
1291 */
1292 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1293 {
1294 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1295 req->tx ? "TX/IN" : "RX/OUT",
1296 &req->request, req->request.length, req->epnum);
1297
1298 musb_ep_select(musb->mregs, req->epnum);
1299 if (req->tx)
1300 txstate(musb, req);
1301 else
1302 rxstate(musb, req);
1303 }
1304
1305 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1306 gfp_t gfp_flags)
1307 {
1308 struct musb_ep *musb_ep;
1309 struct musb_request *request;
1310 struct musb *musb;
1311 int status = 0;
1312 unsigned long lockflags;
1313
1314 if (!ep || !req)
1315 return -EINVAL;
1316 if (!req->buf)
1317 return -ENODATA;
1318
1319 musb_ep = to_musb_ep(ep);
1320 musb = musb_ep->musb;
1321
1322 request = to_musb_request(req);
1323 request->musb = musb;
1324
1325 if (request->ep != musb_ep)
1326 return -EINVAL;
1327
1328 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1329
1330 /* request is mine now... */
1331 request->request.actual = 0;
1332 request->request.status = -EINPROGRESS;
1333 request->epnum = musb_ep->current_epnum;
1334 request->tx = musb_ep->is_in;
1335
1336 map_dma_buffer(request, musb, musb_ep);
1337
1338 spin_lock_irqsave(&musb->lock, lockflags);
1339
1340 /* don't queue if the ep is down */
1341 if (!musb_ep->desc) {
1342 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1343 req, ep->name, "disabled");
1344 status = -ESHUTDOWN;
1345 goto cleanup;
1346 }
1347
1348 /* add request to the list */
1349 list_add_tail(&request->list, &musb_ep->req_list);
1350
1351 /* it this is the head of the queue, start i/o ... */
1352 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1353 musb_ep_restart(musb, request);
1354
1355 cleanup:
1356 spin_unlock_irqrestore(&musb->lock, lockflags);
1357 return status;
1358 }
1359
1360 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1361 {
1362 struct musb_ep *musb_ep = to_musb_ep(ep);
1363 struct musb_request *req = to_musb_request(request);
1364 struct musb_request *r;
1365 unsigned long flags;
1366 int status = 0;
1367 struct musb *musb = musb_ep->musb;
1368
1369 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1370 return -EINVAL;
1371
1372 spin_lock_irqsave(&musb->lock, flags);
1373
1374 list_for_each_entry(r, &musb_ep->req_list, list) {
1375 if (r == req)
1376 break;
1377 }
1378 if (r != req) {
1379 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1380 status = -EINVAL;
1381 goto done;
1382 }
1383
1384 /* if the hardware doesn't have the request, easy ... */
1385 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1386 musb_g_giveback(musb_ep, request, -ECONNRESET);
1387
1388 /* ... else abort the dma transfer ... */
1389 else if (is_dma_capable() && musb_ep->dma) {
1390 struct dma_controller *c = musb->dma_controller;
1391
1392 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1393 if (c->channel_abort)
1394 status = c->channel_abort(musb_ep->dma);
1395 else
1396 status = -EBUSY;
1397 if (status == 0)
1398 musb_g_giveback(musb_ep, request, -ECONNRESET);
1399 } else {
1400 /* NOTE: by sticking to easily tested hardware/driver states,
1401 * we leave counting of in-flight packets imprecise.
1402 */
1403 musb_g_giveback(musb_ep, request, -ECONNRESET);
1404 }
1405
1406 done:
1407 spin_unlock_irqrestore(&musb->lock, flags);
1408 return status;
1409 }
1410
1411 /*
1412 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1413 * data but will queue requests.
1414 *
1415 * exported to ep0 code
1416 */
1417 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1418 {
1419 struct musb_ep *musb_ep = to_musb_ep(ep);
1420 u8 epnum = musb_ep->current_epnum;
1421 struct musb *musb = musb_ep->musb;
1422 void __iomem *epio = musb->endpoints[epnum].regs;
1423 void __iomem *mbase;
1424 unsigned long flags;
1425 u16 csr;
1426 struct musb_request *request;
1427 int status = 0;
1428
1429 if (!ep)
1430 return -EINVAL;
1431 mbase = musb->mregs;
1432
1433 spin_lock_irqsave(&musb->lock, flags);
1434
1435 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1436 status = -EINVAL;
1437 goto done;
1438 }
1439
1440 musb_ep_select(mbase, epnum);
1441
1442 request = next_request(musb_ep);
1443 if (value) {
1444 if (request) {
1445 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1446 ep->name);
1447 status = -EAGAIN;
1448 goto done;
1449 }
1450 /* Cannot portably stall with non-empty FIFO */
1451 if (musb_ep->is_in) {
1452 csr = musb_readw(epio, MUSB_TXCSR);
1453 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1454 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1455 status = -EAGAIN;
1456 goto done;
1457 }
1458 }
1459 } else
1460 musb_ep->wedged = 0;
1461
1462 /* set/clear the stall and toggle bits */
1463 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1464 if (musb_ep->is_in) {
1465 csr = musb_readw(epio, MUSB_TXCSR);
1466 csr |= MUSB_TXCSR_P_WZC_BITS
1467 | MUSB_TXCSR_CLRDATATOG;
1468 if (value)
1469 csr |= MUSB_TXCSR_P_SENDSTALL;
1470 else
1471 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1472 | MUSB_TXCSR_P_SENTSTALL);
1473 csr &= ~MUSB_TXCSR_TXPKTRDY;
1474 musb_writew(epio, MUSB_TXCSR, csr);
1475 } else {
1476 csr = musb_readw(epio, MUSB_RXCSR);
1477 csr |= MUSB_RXCSR_P_WZC_BITS
1478 | MUSB_RXCSR_FLUSHFIFO
1479 | MUSB_RXCSR_CLRDATATOG;
1480 if (value)
1481 csr |= MUSB_RXCSR_P_SENDSTALL;
1482 else
1483 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1484 | MUSB_RXCSR_P_SENTSTALL);
1485 musb_writew(epio, MUSB_RXCSR, csr);
1486 }
1487
1488 /* maybe start the first request in the queue */
1489 if (!musb_ep->busy && !value && request) {
1490 dev_dbg(musb->controller, "restarting the request\n");
1491 musb_ep_restart(musb, request);
1492 }
1493
1494 done:
1495 spin_unlock_irqrestore(&musb->lock, flags);
1496 return status;
1497 }
1498
1499 /*
1500 * Sets the halt feature with the clear requests ignored
1501 */
1502 static int musb_gadget_set_wedge(struct usb_ep *ep)
1503 {
1504 struct musb_ep *musb_ep = to_musb_ep(ep);
1505
1506 if (!ep)
1507 return -EINVAL;
1508
1509 musb_ep->wedged = 1;
1510
1511 return usb_ep_set_halt(ep);
1512 }
1513
1514 static int musb_gadget_fifo_status(struct usb_ep *ep)
1515 {
1516 struct musb_ep *musb_ep = to_musb_ep(ep);
1517 void __iomem *epio = musb_ep->hw_ep->regs;
1518 int retval = -EINVAL;
1519
1520 if (musb_ep->desc && !musb_ep->is_in) {
1521 struct musb *musb = musb_ep->musb;
1522 int epnum = musb_ep->current_epnum;
1523 void __iomem *mbase = musb->mregs;
1524 unsigned long flags;
1525
1526 spin_lock_irqsave(&musb->lock, flags);
1527
1528 musb_ep_select(mbase, epnum);
1529 /* FIXME return zero unless RXPKTRDY is set */
1530 retval = musb_readw(epio, MUSB_RXCOUNT);
1531
1532 spin_unlock_irqrestore(&musb->lock, flags);
1533 }
1534 return retval;
1535 }
1536
1537 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1538 {
1539 struct musb_ep *musb_ep = to_musb_ep(ep);
1540 struct musb *musb = musb_ep->musb;
1541 u8 epnum = musb_ep->current_epnum;
1542 void __iomem *epio = musb->endpoints[epnum].regs;
1543 void __iomem *mbase;
1544 unsigned long flags;
1545 u16 csr, int_txe;
1546
1547 mbase = musb->mregs;
1548
1549 spin_lock_irqsave(&musb->lock, flags);
1550 musb_ep_select(mbase, (u8) epnum);
1551
1552 /* disable interrupts */
1553 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1554 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1555
1556 if (musb_ep->is_in) {
1557 csr = musb_readw(epio, MUSB_TXCSR);
1558 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1559 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1560 /*
1561 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1562 * to interrupt current FIFO loading, but not flushing
1563 * the already loaded ones.
1564 */
1565 csr &= ~MUSB_TXCSR_TXPKTRDY;
1566 musb_writew(epio, MUSB_TXCSR, csr);
1567 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1568 musb_writew(epio, MUSB_TXCSR, csr);
1569 }
1570 } else {
1571 csr = musb_readw(epio, MUSB_RXCSR);
1572 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1573 musb_writew(epio, MUSB_RXCSR, csr);
1574 musb_writew(epio, MUSB_RXCSR, csr);
1575 }
1576
1577 /* re-enable interrupt */
1578 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1579 spin_unlock_irqrestore(&musb->lock, flags);
1580 }
1581
1582 static const struct usb_ep_ops musb_ep_ops = {
1583 .enable = musb_gadget_enable,
1584 .disable = musb_gadget_disable,
1585 .alloc_request = musb_alloc_request,
1586 .free_request = musb_free_request,
1587 .queue = musb_gadget_queue,
1588 .dequeue = musb_gadget_dequeue,
1589 .set_halt = musb_gadget_set_halt,
1590 .set_wedge = musb_gadget_set_wedge,
1591 .fifo_status = musb_gadget_fifo_status,
1592 .fifo_flush = musb_gadget_fifo_flush
1593 };
1594
1595 /* ----------------------------------------------------------------------- */
1596
1597 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1598 {
1599 struct musb *musb = gadget_to_musb(gadget);
1600
1601 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1602 }
1603
1604 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1605 {
1606 struct musb *musb = gadget_to_musb(gadget);
1607 void __iomem *mregs = musb->mregs;
1608 unsigned long flags;
1609 int status = -EINVAL;
1610 u8 power, devctl;
1611 int retries;
1612
1613 spin_lock_irqsave(&musb->lock, flags);
1614
1615 switch (musb->xceiv->state) {
1616 case OTG_STATE_B_PERIPHERAL:
1617 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1618 * that's part of the standard usb 1.1 state machine, and
1619 * doesn't affect OTG transitions.
1620 */
1621 if (musb->may_wakeup && musb->is_suspended)
1622 break;
1623 goto done;
1624 case OTG_STATE_B_IDLE:
1625 /* Start SRP ... OTG not required. */
1626 devctl = musb_readb(mregs, MUSB_DEVCTL);
1627 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1628 devctl |= MUSB_DEVCTL_SESSION;
1629 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1630 devctl = musb_readb(mregs, MUSB_DEVCTL);
1631 retries = 100;
1632 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1633 devctl = musb_readb(mregs, MUSB_DEVCTL);
1634 if (retries-- < 1)
1635 break;
1636 }
1637 retries = 10000;
1638 while (devctl & MUSB_DEVCTL_SESSION) {
1639 devctl = musb_readb(mregs, MUSB_DEVCTL);
1640 if (retries-- < 1)
1641 break;
1642 }
1643
1644 spin_unlock_irqrestore(&musb->lock, flags);
1645 otg_start_srp(musb->xceiv);
1646 spin_lock_irqsave(&musb->lock, flags);
1647
1648 /* Block idling for at least 1s */
1649 musb_platform_try_idle(musb,
1650 jiffies + msecs_to_jiffies(1 * HZ));
1651
1652 status = 0;
1653 goto done;
1654 default:
1655 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1656 otg_state_string(musb->xceiv->state));
1657 goto done;
1658 }
1659
1660 status = 0;
1661
1662 power = musb_readb(mregs, MUSB_POWER);
1663 power |= MUSB_POWER_RESUME;
1664 musb_writeb(mregs, MUSB_POWER, power);
1665 dev_dbg(musb->controller, "issue wakeup\n");
1666
1667 /* FIXME do this next chunk in a timer callback, no udelay */
1668 mdelay(2);
1669
1670 power = musb_readb(mregs, MUSB_POWER);
1671 power &= ~MUSB_POWER_RESUME;
1672 musb_writeb(mregs, MUSB_POWER, power);
1673 done:
1674 spin_unlock_irqrestore(&musb->lock, flags);
1675 return status;
1676 }
1677
1678 static int
1679 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1680 {
1681 struct musb *musb = gadget_to_musb(gadget);
1682
1683 musb->is_self_powered = !!is_selfpowered;
1684 return 0;
1685 }
1686
1687 static void musb_pullup(struct musb *musb, int is_on)
1688 {
1689 u8 power;
1690
1691 power = musb_readb(musb->mregs, MUSB_POWER);
1692 if (is_on)
1693 power |= MUSB_POWER_SOFTCONN;
1694 else
1695 power &= ~MUSB_POWER_SOFTCONN;
1696
1697 /* FIXME if on, HdrcStart; if off, HdrcStop */
1698
1699 dev_dbg(musb->controller, "gadget D+ pullup %s\n",
1700 is_on ? "on" : "off");
1701 musb_writeb(musb->mregs, MUSB_POWER, power);
1702 }
1703
1704 #if 0
1705 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1706 {
1707 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1708
1709 /*
1710 * FIXME iff driver's softconnect flag is set (as it is during probe,
1711 * though that can clear it), just musb_pullup().
1712 */
1713
1714 return -EINVAL;
1715 }
1716 #endif
1717
1718 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1719 {
1720 struct musb *musb = gadget_to_musb(gadget);
1721
1722 if (!musb->xceiv->set_power)
1723 return -EOPNOTSUPP;
1724 return otg_set_power(musb->xceiv, mA);
1725 }
1726
1727 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1728 {
1729 struct musb *musb = gadget_to_musb(gadget);
1730 unsigned long flags;
1731
1732 is_on = !!is_on;
1733
1734 pm_runtime_get_sync(musb->controller);
1735
1736 /* NOTE: this assumes we are sensing vbus; we'd rather
1737 * not pullup unless the B-session is active.
1738 */
1739 spin_lock_irqsave(&musb->lock, flags);
1740 if (is_on != musb->softconnect) {
1741 musb->softconnect = is_on;
1742 musb_pullup(musb, is_on);
1743 }
1744 spin_unlock_irqrestore(&musb->lock, flags);
1745
1746 pm_runtime_put(musb->controller);
1747
1748 return 0;
1749 }
1750
1751 static int musb_gadget_start(struct usb_gadget *g,
1752 struct usb_gadget_driver *driver);
1753 static int musb_gadget_stop(struct usb_gadget *g,
1754 struct usb_gadget_driver *driver);
1755
1756 static const struct usb_gadget_ops musb_gadget_operations = {
1757 .get_frame = musb_gadget_get_frame,
1758 .wakeup = musb_gadget_wakeup,
1759 .set_selfpowered = musb_gadget_set_self_powered,
1760 /* .vbus_session = musb_gadget_vbus_session, */
1761 .vbus_draw = musb_gadget_vbus_draw,
1762 .pullup = musb_gadget_pullup,
1763 .udc_start = musb_gadget_start,
1764 .udc_stop = musb_gadget_stop,
1765 };
1766
1767 /* ----------------------------------------------------------------------- */
1768
1769 /* Registration */
1770
1771 /* Only this registration code "knows" the rule (from USB standards)
1772 * about there being only one external upstream port. It assumes
1773 * all peripheral ports are external...
1774 */
1775
1776 static void musb_gadget_release(struct device *dev)
1777 {
1778 /* kref_put(WHAT) */
1779 dev_dbg(dev, "%s\n", __func__);
1780 }
1781
1782
1783 static void __init
1784 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1785 {
1786 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1787
1788 memset(ep, 0, sizeof *ep);
1789
1790 ep->current_epnum = epnum;
1791 ep->musb = musb;
1792 ep->hw_ep = hw_ep;
1793 ep->is_in = is_in;
1794
1795 INIT_LIST_HEAD(&ep->req_list);
1796
1797 sprintf(ep->name, "ep%d%s", epnum,
1798 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1799 is_in ? "in" : "out"));
1800 ep->end_point.name = ep->name;
1801 INIT_LIST_HEAD(&ep->end_point.ep_list);
1802 if (!epnum) {
1803 ep->end_point.maxpacket = 64;
1804 ep->end_point.ops = &musb_g_ep0_ops;
1805 musb->g.ep0 = &ep->end_point;
1806 } else {
1807 if (is_in)
1808 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1809 else
1810 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1811 ep->end_point.ops = &musb_ep_ops;
1812 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1813 }
1814 }
1815
1816 /*
1817 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1818 * to the rest of the driver state.
1819 */
1820 static inline void __init musb_g_init_endpoints(struct musb *musb)
1821 {
1822 u8 epnum;
1823 struct musb_hw_ep *hw_ep;
1824 unsigned count = 0;
1825
1826 /* initialize endpoint list just once */
1827 INIT_LIST_HEAD(&(musb->g.ep_list));
1828
1829 for (epnum = 0, hw_ep = musb->endpoints;
1830 epnum < musb->nr_endpoints;
1831 epnum++, hw_ep++) {
1832 if (hw_ep->is_shared_fifo /* || !epnum */) {
1833 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1834 count++;
1835 } else {
1836 if (hw_ep->max_packet_sz_tx) {
1837 init_peripheral_ep(musb, &hw_ep->ep_in,
1838 epnum, 1);
1839 count++;
1840 }
1841 if (hw_ep->max_packet_sz_rx) {
1842 init_peripheral_ep(musb, &hw_ep->ep_out,
1843 epnum, 0);
1844 count++;
1845 }
1846 }
1847 }
1848 }
1849
1850 /* called once during driver setup to initialize and link into
1851 * the driver model; memory is zeroed.
1852 */
1853 int __init musb_gadget_setup(struct musb *musb)
1854 {
1855 int status;
1856
1857 /* REVISIT minor race: if (erroneously) setting up two
1858 * musb peripherals at the same time, only the bus lock
1859 * is probably held.
1860 */
1861
1862 musb->g.ops = &musb_gadget_operations;
1863 musb->g.max_speed = USB_SPEED_HIGH;
1864 musb->g.speed = USB_SPEED_UNKNOWN;
1865
1866 /* this "gadget" abstracts/virtualizes the controller */
1867 dev_set_name(&musb->g.dev, "gadget");
1868 musb->g.dev.parent = musb->controller;
1869 musb->g.dev.dma_mask = musb->controller->dma_mask;
1870 musb->g.dev.release = musb_gadget_release;
1871 musb->g.name = musb_driver_name;
1872
1873 if (is_otg_enabled(musb))
1874 musb->g.is_otg = 1;
1875
1876 musb_g_init_endpoints(musb);
1877
1878 musb->is_active = 0;
1879 musb_platform_try_idle(musb, 0);
1880
1881 status = device_register(&musb->g.dev);
1882 if (status != 0) {
1883 put_device(&musb->g.dev);
1884 return status;
1885 }
1886 status = usb_add_gadget_udc(musb->controller, &musb->g);
1887 if (status)
1888 goto err;
1889
1890 return 0;
1891 err:
1892 musb->g.dev.parent = NULL;
1893 device_unregister(&musb->g.dev);
1894 return status;
1895 }
1896
1897 void musb_gadget_cleanup(struct musb *musb)
1898 {
1899 usb_del_gadget_udc(&musb->g);
1900 if (musb->g.dev.parent)
1901 device_unregister(&musb->g.dev);
1902 }
1903
1904 /*
1905 * Register the gadget driver. Used by gadget drivers when
1906 * registering themselves with the controller.
1907 *
1908 * -EINVAL something went wrong (not driver)
1909 * -EBUSY another gadget is already using the controller
1910 * -ENOMEM no memory to perform the operation
1911 *
1912 * @param driver the gadget driver
1913 * @return <0 if error, 0 if everything is fine
1914 */
1915 static int musb_gadget_start(struct usb_gadget *g,
1916 struct usb_gadget_driver *driver)
1917 {
1918 struct musb *musb = gadget_to_musb(g);
1919 unsigned long flags;
1920 int retval = -EINVAL;
1921
1922 if (driver->max_speed < USB_SPEED_HIGH)
1923 goto err0;
1924
1925 pm_runtime_get_sync(musb->controller);
1926
1927 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1928
1929 musb->softconnect = 0;
1930 musb->gadget_driver = driver;
1931
1932 spin_lock_irqsave(&musb->lock, flags);
1933 musb->is_active = 1;
1934
1935 otg_set_peripheral(musb->xceiv, &musb->g);
1936 musb->xceiv->state = OTG_STATE_B_IDLE;
1937
1938 /*
1939 * FIXME this ignores the softconnect flag. Drivers are
1940 * allowed hold the peripheral inactive until for example
1941 * userspace hooks up printer hardware or DSP codecs, so
1942 * hosts only see fully functional devices.
1943 */
1944
1945 if (!is_otg_enabled(musb))
1946 musb_start(musb);
1947
1948 spin_unlock_irqrestore(&musb->lock, flags);
1949
1950 if (is_otg_enabled(musb)) {
1951 struct usb_hcd *hcd = musb_to_hcd(musb);
1952
1953 dev_dbg(musb->controller, "OTG startup...\n");
1954
1955 /* REVISIT: funcall to other code, which also
1956 * handles power budgeting ... this way also
1957 * ensures HdrcStart is indirectly called.
1958 */
1959 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1960 if (retval < 0) {
1961 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
1962 goto err2;
1963 }
1964
1965 if ((musb->xceiv->last_event == USB_EVENT_ID)
1966 && musb->xceiv->set_vbus)
1967 otg_set_vbus(musb->xceiv, 1);
1968
1969 hcd->self.uses_pio_for_control = 1;
1970 }
1971 if (musb->xceiv->last_event == USB_EVENT_NONE)
1972 pm_runtime_put(musb->controller);
1973
1974 return 0;
1975
1976 err2:
1977 if (!is_otg_enabled(musb))
1978 musb_stop(musb);
1979 err0:
1980 return retval;
1981 }
1982
1983 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1984 {
1985 int i;
1986 struct musb_hw_ep *hw_ep;
1987
1988 /* don't disconnect if it's not connected */
1989 if (musb->g.speed == USB_SPEED_UNKNOWN)
1990 driver = NULL;
1991 else
1992 musb->g.speed = USB_SPEED_UNKNOWN;
1993
1994 /* deactivate the hardware */
1995 if (musb->softconnect) {
1996 musb->softconnect = 0;
1997 musb_pullup(musb, 0);
1998 }
1999 musb_stop(musb);
2000
2001 /* killing any outstanding requests will quiesce the driver;
2002 * then report disconnect
2003 */
2004 if (driver) {
2005 for (i = 0, hw_ep = musb->endpoints;
2006 i < musb->nr_endpoints;
2007 i++, hw_ep++) {
2008 musb_ep_select(musb->mregs, i);
2009 if (hw_ep->is_shared_fifo /* || !epnum */) {
2010 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2011 } else {
2012 if (hw_ep->max_packet_sz_tx)
2013 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2014 if (hw_ep->max_packet_sz_rx)
2015 nuke(&hw_ep->ep_out, -ESHUTDOWN);
2016 }
2017 }
2018 }
2019 }
2020
2021 /*
2022 * Unregister the gadget driver. Used by gadget drivers when
2023 * unregistering themselves from the controller.
2024 *
2025 * @param driver the gadget driver to unregister
2026 */
2027 static int musb_gadget_stop(struct usb_gadget *g,
2028 struct usb_gadget_driver *driver)
2029 {
2030 struct musb *musb = gadget_to_musb(g);
2031 unsigned long flags;
2032
2033 if (musb->xceiv->last_event == USB_EVENT_NONE)
2034 pm_runtime_get_sync(musb->controller);
2035
2036 /*
2037 * REVISIT always use otg_set_peripheral() here too;
2038 * this needs to shut down the OTG engine.
2039 */
2040
2041 spin_lock_irqsave(&musb->lock, flags);
2042
2043 musb_hnp_stop(musb);
2044
2045 (void) musb_gadget_vbus_draw(&musb->g, 0);
2046
2047 musb->xceiv->state = OTG_STATE_UNDEFINED;
2048 stop_activity(musb, driver);
2049 otg_set_peripheral(musb->xceiv, NULL);
2050
2051 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
2052
2053 musb->is_active = 0;
2054 musb_platform_try_idle(musb, 0);
2055 spin_unlock_irqrestore(&musb->lock, flags);
2056
2057 if (is_otg_enabled(musb)) {
2058 usb_remove_hcd(musb_to_hcd(musb));
2059 /* FIXME we need to be able to register another
2060 * gadget driver here and have everything work;
2061 * that currently misbehaves.
2062 */
2063 }
2064
2065 if (!is_otg_enabled(musb))
2066 musb_stop(musb);
2067
2068 pm_runtime_put(musb->controller);
2069
2070 return 0;
2071 }
2072
2073 /* ----------------------------------------------------------------------- */
2074
2075 /* lifecycle operations called through plat_uds.c */
2076
2077 void musb_g_resume(struct musb *musb)
2078 {
2079 musb->is_suspended = 0;
2080 switch (musb->xceiv->state) {
2081 case OTG_STATE_B_IDLE:
2082 break;
2083 case OTG_STATE_B_WAIT_ACON:
2084 case OTG_STATE_B_PERIPHERAL:
2085 musb->is_active = 1;
2086 if (musb->gadget_driver && musb->gadget_driver->resume) {
2087 spin_unlock(&musb->lock);
2088 musb->gadget_driver->resume(&musb->g);
2089 spin_lock(&musb->lock);
2090 }
2091 break;
2092 default:
2093 WARNING("unhandled RESUME transition (%s)\n",
2094 otg_state_string(musb->xceiv->state));
2095 }
2096 }
2097
2098 /* called when SOF packets stop for 3+ msec */
2099 void musb_g_suspend(struct musb *musb)
2100 {
2101 u8 devctl;
2102
2103 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2104 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2105
2106 switch (musb->xceiv->state) {
2107 case OTG_STATE_B_IDLE:
2108 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2109 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2110 break;
2111 case OTG_STATE_B_PERIPHERAL:
2112 musb->is_suspended = 1;
2113 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2114 spin_unlock(&musb->lock);
2115 musb->gadget_driver->suspend(&musb->g);
2116 spin_lock(&musb->lock);
2117 }
2118 break;
2119 default:
2120 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2121 * A_PERIPHERAL may need care too
2122 */
2123 WARNING("unhandled SUSPEND transition (%s)\n",
2124 otg_state_string(musb->xceiv->state));
2125 }
2126 }
2127
2128 /* Called during SRP */
2129 void musb_g_wakeup(struct musb *musb)
2130 {
2131 musb_gadget_wakeup(&musb->g);
2132 }
2133
2134 /* called when VBUS drops below session threshold, and in other cases */
2135 void musb_g_disconnect(struct musb *musb)
2136 {
2137 void __iomem *mregs = musb->mregs;
2138 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2139
2140 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2141
2142 /* clear HR */
2143 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2144
2145 /* don't draw vbus until new b-default session */
2146 (void) musb_gadget_vbus_draw(&musb->g, 0);
2147
2148 musb->g.speed = USB_SPEED_UNKNOWN;
2149 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2150 spin_unlock(&musb->lock);
2151 musb->gadget_driver->disconnect(&musb->g);
2152 spin_lock(&musb->lock);
2153 }
2154
2155 switch (musb->xceiv->state) {
2156 default:
2157 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2158 otg_state_string(musb->xceiv->state));
2159 musb->xceiv->state = OTG_STATE_A_IDLE;
2160 MUSB_HST_MODE(musb);
2161 break;
2162 case OTG_STATE_A_PERIPHERAL:
2163 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2164 MUSB_HST_MODE(musb);
2165 break;
2166 case OTG_STATE_B_WAIT_ACON:
2167 case OTG_STATE_B_HOST:
2168 case OTG_STATE_B_PERIPHERAL:
2169 case OTG_STATE_B_IDLE:
2170 musb->xceiv->state = OTG_STATE_B_IDLE;
2171 break;
2172 case OTG_STATE_B_SRP_INIT:
2173 break;
2174 }
2175
2176 musb->is_active = 0;
2177 }
2178
2179 void musb_g_reset(struct musb *musb)
2180 __releases(musb->lock)
2181 __acquires(musb->lock)
2182 {
2183 void __iomem *mbase = musb->mregs;
2184 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2185 u8 power;
2186
2187 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
2188 (devctl & MUSB_DEVCTL_BDEVICE)
2189 ? "B-Device" : "A-Device",
2190 musb_readb(mbase, MUSB_FADDR),
2191 musb->gadget_driver
2192 ? musb->gadget_driver->driver.name
2193 : NULL
2194 );
2195
2196 /* report disconnect, if we didn't already (flushing EP state) */
2197 if (musb->g.speed != USB_SPEED_UNKNOWN)
2198 musb_g_disconnect(musb);
2199
2200 /* clear HR */
2201 else if (devctl & MUSB_DEVCTL_HR)
2202 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2203
2204
2205 /* what speed did we negotiate? */
2206 power = musb_readb(mbase, MUSB_POWER);
2207 musb->g.speed = (power & MUSB_POWER_HSMODE)
2208 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2209
2210 /* start in USB_STATE_DEFAULT */
2211 musb->is_active = 1;
2212 musb->is_suspended = 0;
2213 MUSB_DEV_MODE(musb);
2214 musb->address = 0;
2215 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2216
2217 musb->may_wakeup = 0;
2218 musb->g.b_hnp_enable = 0;
2219 musb->g.a_alt_hnp_support = 0;
2220 musb->g.a_hnp_support = 0;
2221
2222 /* Normal reset, as B-Device;
2223 * or else after HNP, as A-Device
2224 */
2225 if (devctl & MUSB_DEVCTL_BDEVICE) {
2226 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2227 musb->g.is_a_peripheral = 0;
2228 } else if (is_otg_enabled(musb)) {
2229 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2230 musb->g.is_a_peripheral = 1;
2231 } else
2232 WARN_ON(1);
2233
2234 /* start with default limits on VBUS power draw */
2235 (void) musb_gadget_vbus_draw(&musb->g,
2236 is_otg_enabled(musb) ? 8 : 100);
2237 }