?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / video / omap2 / dss / venc.c
blob928475b173c6d949089e61abc2f2cf06dfcd75a4
1 /*
2 * linux/drivers/video/omap2/dss/venc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * VENC settings from TI's DSS driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #define DSS_SUBSYS_NAME "VENC"
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/io.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
37
38 #include <video/omapdss.h>
39 #include <plat/cpu.h>
40
41 #include "dss.h"
42 #include "dss_features.h"
43
44 /* Venc registers */
45 #define VENC_REV_ID 0x00
46 #define VENC_STATUS 0x04
47 #define VENC_F_CONTROL 0x08
48 #define VENC_VIDOUT_CTRL 0x10
49 #define VENC_SYNC_CTRL 0x14
50 #define VENC_LLEN 0x1C
51 #define VENC_FLENS 0x20
52 #define VENC_HFLTR_CTRL 0x24
53 #define VENC_CC_CARR_WSS_CARR 0x28
54 #define VENC_C_PHASE 0x2C
55 #define VENC_GAIN_U 0x30
56 #define VENC_GAIN_V 0x34
57 #define VENC_GAIN_Y 0x38
58 #define VENC_BLACK_LEVEL 0x3C
59 #define VENC_BLANK_LEVEL 0x40
60 #define VENC_X_COLOR 0x44
61 #define VENC_M_CONTROL 0x48
62 #define VENC_BSTAMP_WSS_DATA 0x4C
63 #define VENC_S_CARR 0x50
64 #define VENC_LINE21 0x54
65 #define VENC_LN_SEL 0x58
66 #define VENC_L21__WC_CTL 0x5C
67 #define VENC_HTRIGGER_VTRIGGER 0x60
68 #define VENC_SAVID__EAVID 0x64
69 #define VENC_FLEN__FAL 0x68
70 #define VENC_LAL__PHASE_RESET 0x6C
71 #define VENC_HS_INT_START_STOP_X 0x70
72 #define VENC_HS_EXT_START_STOP_X 0x74
73 #define VENC_VS_INT_START_X 0x78
74 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
75 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
76 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
77 #define VENC_VS_EXT_STOP_Y 0x88
78 #define VENC_AVID_START_STOP_X 0x90
79 #define VENC_AVID_START_STOP_Y 0x94
80 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
81 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
82 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
83 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
84 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
85 #define VENC_GEN_CTRL 0xB8
86 #define VENC_OUTPUT_CONTROL 0xC4
87 #define VENC_OUTPUT_TEST 0xC8
88 #define VENC_DAC_B__DAC_C 0xC8
89
90 struct venc_config {
91 u32 f_control;
92 u32 vidout_ctrl;
93 u32 sync_ctrl;
94 u32 llen;
95 u32 flens;
96 u32 hfltr_ctrl;
97 u32 cc_carr_wss_carr;
98 u32 c_phase;
99 u32 gain_u;
100 u32 gain_v;
101 u32 gain_y;
102 u32 black_level;
103 u32 blank_level;
104 u32 x_color;
105 u32 m_control;
106 u32 bstamp_wss_data;
107 u32 s_carr;
108 u32 line21;
109 u32 ln_sel;
110 u32 l21__wc_ctl;
111 u32 htrigger_vtrigger;
112 u32 savid__eavid;
113 u32 flen__fal;
114 u32 lal__phase_reset;
115 u32 hs_int_start_stop_x;
116 u32 hs_ext_start_stop_x;
117 u32 vs_int_start_x;
118 u32 vs_int_stop_x__vs_int_start_y;
119 u32 vs_int_stop_y__vs_ext_start_x;
120 u32 vs_ext_stop_x__vs_ext_start_y;
121 u32 vs_ext_stop_y;
122 u32 avid_start_stop_x;
123 u32 avid_start_stop_y;
124 u32 fid_int_start_x__fid_int_start_y;
125 u32 fid_int_offset_y__fid_ext_start_x;
126 u32 fid_ext_start_y__fid_ext_offset_y;
127 u32 tvdetgp_int_start_stop_x;
128 u32 tvdetgp_int_start_stop_y;
129 u32 gen_ctrl;
130 };
131
132 /* from TRM */
133 static const struct venc_config venc_config_pal_trm = {
134 .f_control = 0,
135 .vidout_ctrl = 1,
136 .sync_ctrl = 0x40,
137 .llen = 0x35F, /* 863 */
138 .flens = 0x270, /* 624 */
139 .hfltr_ctrl = 0,
140 .cc_carr_wss_carr = 0x2F7225ED,
141 .c_phase = 0,
142 .gain_u = 0x111,
143 .gain_v = 0x181,
144 .gain_y = 0x140,
145 .black_level = 0x3B,
146 .blank_level = 0x3B,
147 .x_color = 0x7,
148 .m_control = 0x2,
149 .bstamp_wss_data = 0x3F,
150 .s_carr = 0x2A098ACB,
151 .line21 = 0,
152 .ln_sel = 0x01290015,
153 .l21__wc_ctl = 0x0000F603,
154 .htrigger_vtrigger = 0,
155
156 .savid__eavid = 0x06A70108,
157 .flen__fal = 0x00180270,
158 .lal__phase_reset = 0x00040135,
159 .hs_int_start_stop_x = 0x00880358,
160 .hs_ext_start_stop_x = 0x000F035F,
161 .vs_int_start_x = 0x01A70000,
162 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
163 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
164 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
165 .vs_ext_stop_y = 0x00000025,
166 .avid_start_stop_x = 0x03530083,
167 .avid_start_stop_y = 0x026C002E,
168 .fid_int_start_x__fid_int_start_y = 0x0001008A,
169 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
170 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
171
172 .tvdetgp_int_start_stop_x = 0x00140001,
173 .tvdetgp_int_start_stop_y = 0x00010001,
174 .gen_ctrl = 0x00FF0000,
175 };
176
177 /* from TRM */
178 static const struct venc_config venc_config_ntsc_trm = {
179 .f_control = 0,
180 .vidout_ctrl = 1,
181 .sync_ctrl = 0x8040,
182 .llen = 0x359,
183 .flens = 0x20C,
184 .hfltr_ctrl = 0,
185 .cc_carr_wss_carr = 0x043F2631,
186 .c_phase = 0,
187 .gain_u = 0x102,
188 .gain_v = 0x16C,
189 .gain_y = 0x12F,
190 .black_level = 0x43,
191 .blank_level = 0x38,
192 .x_color = 0x7,
193 .m_control = 0x1,
194 .bstamp_wss_data = 0x38,
195 .s_carr = 0x21F07C1F,
196 .line21 = 0,
197 .ln_sel = 0x01310011,
198 .l21__wc_ctl = 0x0000F003,
199 .htrigger_vtrigger = 0,
200
201 .savid__eavid = 0x069300F4,
202 .flen__fal = 0x0016020C,
203 .lal__phase_reset = 0x00060107,
204 .hs_int_start_stop_x = 0x008E0350,
205 .hs_ext_start_stop_x = 0x000F0359,
206 .vs_int_start_x = 0x01A00000,
207 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
208 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
209 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
210 .vs_ext_stop_y = 0x00000006,
211 .avid_start_stop_x = 0x03480078,
212 .avid_start_stop_y = 0x02060024,
213 .fid_int_start_x__fid_int_start_y = 0x0001008A,
214 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
215 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
216
217 .tvdetgp_int_start_stop_x = 0x00140001,
218 .tvdetgp_int_start_stop_y = 0x00010001,
219 .gen_ctrl = 0x00F90000,
220 };
221
222 static const struct venc_config venc_config_pal_bdghi = {
223 .f_control = 0,
224 .vidout_ctrl = 0,
225 .sync_ctrl = 0,
226 .hfltr_ctrl = 0,
227 .x_color = 0,
228 .line21 = 0,
229 .ln_sel = 21,
230 .htrigger_vtrigger = 0,
231 .tvdetgp_int_start_stop_x = 0x00140001,
232 .tvdetgp_int_start_stop_y = 0x00010001,
233 .gen_ctrl = 0x00FB0000,
234
235 .llen = 864-1,
236 .flens = 625-1,
237 .cc_carr_wss_carr = 0x2F7625ED,
238 .c_phase = 0xDF,
239 .gain_u = 0x111,
240 .gain_v = 0x181,
241 .gain_y = 0x140,
242 .black_level = 0x3e,
243 .blank_level = 0x3e,
244 .m_control = 0<<2 | 1<<1,
245 .bstamp_wss_data = 0x42,
246 .s_carr = 0x2a098acb,
247 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
248 .savid__eavid = 0x06A70108,
249 .flen__fal = 23<<16 | 624<<0,
250 .lal__phase_reset = 2<<17 | 310<<0,
251 .hs_int_start_stop_x = 0x00920358,
252 .hs_ext_start_stop_x = 0x000F035F,
253 .vs_int_start_x = 0x1a7<<16,
254 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
255 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
256 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
257 .vs_ext_stop_y = 0x05,
258 .avid_start_stop_x = 0x03530082,
259 .avid_start_stop_y = 0x0270002E,
260 .fid_int_start_x__fid_int_start_y = 0x0005008A,
261 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
262 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
263 };
264
265 const struct omap_video_timings omap_dss_pal_timings = {
266 .x_res = 720,
267 .y_res = 574,
268 .pixel_clock = 13500,
269 .hsw = 64,
270 .hfp = 12,
271 .hbp = 68,
272 .vsw = 5,
273 .vfp = 5,
274 .vbp = 41,
275 };
276 EXPORT_SYMBOL(omap_dss_pal_timings);
277
278 const struct omap_video_timings omap_dss_ntsc_timings = {
279 .x_res = 720,
280 .y_res = 482,
281 .pixel_clock = 13500,
282 .hsw = 64,
283 .hfp = 16,
284 .hbp = 58,
285 .vsw = 6,
286 .vfp = 6,
287 .vbp = 31,
288 };
289 EXPORT_SYMBOL(omap_dss_ntsc_timings);
290
291 static struct {
292 struct platform_device *pdev;
293 void __iomem *base;
294 struct mutex venc_lock;
295 u32 wss_data;
296 struct regulator *vdda_dac_reg;
297
298 struct clk *tv_dac_clk;
299 } venc;
300
301 static inline void venc_write_reg(int idx, u32 val)
302 {
303 __raw_writel(val, venc.base + idx);
304 }
305
306 static inline u32 venc_read_reg(int idx)
307 {
308 u32 l = __raw_readl(venc.base + idx);
309 return l;
310 }
311
312 static void venc_write_config(const struct venc_config *config)
313 {
314 DSSDBG("write venc conf\n");
315
316 venc_write_reg(VENC_LLEN, config->llen);
317 venc_write_reg(VENC_FLENS, config->flens);
318 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
319 venc_write_reg(VENC_C_PHASE, config->c_phase);
320 venc_write_reg(VENC_GAIN_U, config->gain_u);
321 venc_write_reg(VENC_GAIN_V, config->gain_v);
322 venc_write_reg(VENC_GAIN_Y, config->gain_y);
323 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
324 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
325 venc_write_reg(VENC_M_CONTROL, config->m_control);
326 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
327 venc.wss_data);
328 venc_write_reg(VENC_S_CARR, config->s_carr);
329 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
330 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
331 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
332 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
333 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
334 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
335 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
336 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
337 config->vs_int_stop_x__vs_int_start_y);
338 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
339 config->vs_int_stop_y__vs_ext_start_x);
340 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
341 config->vs_ext_stop_x__vs_ext_start_y);
342 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
343 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
344 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
345 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
346 config->fid_int_start_x__fid_int_start_y);
347 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
348 config->fid_int_offset_y__fid_ext_start_x);
349 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
350 config->fid_ext_start_y__fid_ext_offset_y);
351
352 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
353 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
354 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
355 venc_write_reg(VENC_X_COLOR, config->x_color);
356 venc_write_reg(VENC_LINE21, config->line21);
357 venc_write_reg(VENC_LN_SEL, config->ln_sel);
358 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
359 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
360 config->tvdetgp_int_start_stop_x);
361 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
362 config->tvdetgp_int_start_stop_y);
363 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
364 venc_write_reg(VENC_F_CONTROL, config->f_control);
365 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
366 }
367
368 static void venc_reset(void)
369 {
370 int t = 1000;
371
372 venc_write_reg(VENC_F_CONTROL, 1<<8);
373 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
374 if (--t == 0) {
375 DSSERR("Failed to reset venc\n");
376 return;
377 }
378 }
379
380 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
381 /* the magical sleep that makes things work */
382 /* XXX more info? What bug this circumvents? */
383 msleep(20);
384 #endif
385 }
386
387 static int venc_runtime_get(void)
388 {
389 int r;
390
391 DSSDBG("venc_runtime_get\n");
392
393 r = pm_runtime_get_sync(&venc.pdev->dev);
394 WARN_ON(r < 0);
395 return r < 0 ? r : 0;
396 }
397
398 static void venc_runtime_put(void)
399 {
400 int r;
401
402 DSSDBG("venc_runtime_put\n");
403
404 r = pm_runtime_put_sync(&venc.pdev->dev);
405 WARN_ON(r < 0);
406 }
407
408 static const struct venc_config *venc_timings_to_config(
409 struct omap_video_timings *timings)
410 {
411 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
412 return &venc_config_pal_trm;
413
414 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
415 return &venc_config_ntsc_trm;
416
417 BUG();
418 }
419
420 static int venc_power_on(struct omap_dss_device *dssdev)
421 {
422 u32 l;
423 int r;
424
425 venc_reset();
426 venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
427
428 dss_set_venc_output(dssdev->phy.venc.type);
429 dss_set_dac_pwrdn_bgz(1);
430
431 l = 0;
432
433 if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
434 l |= 1 << 1;
435 else /* S-Video */
436 l |= (1 << 0) | (1 << 2);
437
438 if (dssdev->phy.venc.invert_polarity == false)
439 l |= 1 << 3;
440
441 venc_write_reg(VENC_OUTPUT_CONTROL, l);
442
443 dispc_set_digit_size(dssdev->panel.timings.x_res,
444 dssdev->panel.timings.y_res/2);
445
446 regulator_enable(venc.vdda_dac_reg);
447
448 if (dssdev->platform_enable)
449 dssdev->platform_enable(dssdev);
450
451 r = dss_mgr_enable(dssdev->manager);
452 if (r)
453 goto err;
454
455 return 0;
456
457 err:
458 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
459 dss_set_dac_pwrdn_bgz(0);
460
461 if (dssdev->platform_disable)
462 dssdev->platform_disable(dssdev);
463
464 regulator_disable(venc.vdda_dac_reg);
465
466 return r;
467 }
468
469 static void venc_power_off(struct omap_dss_device *dssdev)
470 {
471 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
472 dss_set_dac_pwrdn_bgz(0);
473
474 dss_mgr_disable(dssdev->manager);
475
476 if (dssdev->platform_disable)
477 dssdev->platform_disable(dssdev);
478
479 regulator_disable(venc.vdda_dac_reg);
480 }
481
482 unsigned long venc_get_pixel_clock(void)
483 {
484 /* VENC Pixel Clock in Mhz */
485 return 13500000;
486 }
487
488 /* driver */
489 static int venc_panel_probe(struct omap_dss_device *dssdev)
490 {
491 dssdev->panel.timings = omap_dss_pal_timings;
492
493 return 0;
494 }
495
496 static void venc_panel_remove(struct omap_dss_device *dssdev)
497 {
498 }
499
500 static int venc_panel_enable(struct omap_dss_device *dssdev)
501 {
502 int r = 0;
503
504 DSSDBG("venc_enable_display\n");
505
506 mutex_lock(&venc.venc_lock);
507
508 r = omap_dss_start_device(dssdev);
509 if (r) {
510 DSSERR("failed to start device\n");
511 goto err0;
512 }
513
514 if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
515 r = -EINVAL;
516 goto err1;
517 }
518
519 r = venc_runtime_get();
520 if (r)
521 goto err1;
522
523 r = venc_power_on(dssdev);
524 if (r)
525 goto err2;
526
527 venc.wss_data = 0;
528
529 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
530
531 mutex_unlock(&venc.venc_lock);
532 return 0;
533 err2:
534 venc_runtime_put();
535 err1:
536 omap_dss_stop_device(dssdev);
537 err0:
538 mutex_unlock(&venc.venc_lock);
539
540 return r;
541 }
542
543 static void venc_panel_disable(struct omap_dss_device *dssdev)
544 {
545 DSSDBG("venc_disable_display\n");
546
547 mutex_lock(&venc.venc_lock);
548
549 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
550 goto end;
551
552 if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) {
553 /* suspended is the same as disabled with venc */
554 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
555 goto end;
556 }
557
558 venc_power_off(dssdev);
559
560 venc_runtime_put();
561
562 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
563
564 omap_dss_stop_device(dssdev);
565 end:
566 mutex_unlock(&venc.venc_lock);
567 }
568
569 static int venc_panel_suspend(struct omap_dss_device *dssdev)
570 {
571 venc_panel_disable(dssdev);
572 return 0;
573 }
574
575 static int venc_panel_resume(struct omap_dss_device *dssdev)
576 {
577 return venc_panel_enable(dssdev);
578 }
579
580 static void venc_get_timings(struct omap_dss_device *dssdev,
581 struct omap_video_timings *timings)
582 {
583 *timings = dssdev->panel.timings;
584 }
585
586 static void venc_set_timings(struct omap_dss_device *dssdev,
587 struct omap_video_timings *timings)
588 {
589 DSSDBG("venc_set_timings\n");
590
591 /* Reset WSS data when the TV standard changes. */
592 if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings)))
593 venc.wss_data = 0;
594
595 dssdev->panel.timings = *timings;
596 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
597 /* turn the venc off and on to get new timings to use */
598 venc_panel_disable(dssdev);
599 venc_panel_enable(dssdev);
600 }
601 }
602
603 static int venc_check_timings(struct omap_dss_device *dssdev,
604 struct omap_video_timings *timings)
605 {
606 DSSDBG("venc_check_timings\n");
607
608 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
609 return 0;
610
611 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
612 return 0;
613
614 return -EINVAL;
615 }
616
617 static u32 venc_get_wss(struct omap_dss_device *dssdev)
618 {
619 /* Invert due to VENC_L21_WC_CTL:INV=1 */
620 return (venc.wss_data >> 8) ^ 0xfffff;
621 }
622
623 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
624 {
625 const struct venc_config *config;
626 int r;
627
628 DSSDBG("venc_set_wss\n");
629
630 mutex_lock(&venc.venc_lock);
631
632 config = venc_timings_to_config(&dssdev->panel.timings);
633
634 /* Invert due to VENC_L21_WC_CTL:INV=1 */
635 venc.wss_data = (wss ^ 0xfffff) << 8;
636
637 r = venc_runtime_get();
638 if (r)
639 goto err;
640
641 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
642 venc.wss_data);
643
644 venc_runtime_put();
645
646 err:
647 mutex_unlock(&venc.venc_lock);
648
649 return r;
650 }
651
652 static struct omap_dss_driver venc_driver = {
653 .probe = venc_panel_probe,
654 .remove = venc_panel_remove,
655
656 .enable = venc_panel_enable,
657 .disable = venc_panel_disable,
658 .suspend = venc_panel_suspend,
659 .resume = venc_panel_resume,
660
661 .get_resolution = omapdss_default_get_resolution,
662 .get_recommended_bpp = omapdss_default_get_recommended_bpp,
663
664 .get_timings = venc_get_timings,
665 .set_timings = venc_set_timings,
666 .check_timings = venc_check_timings,
667
668 .get_wss = venc_get_wss,
669 .set_wss = venc_set_wss,
670
671 .driver = {
672 .name = "venc",
673 .owner = THIS_MODULE,
674 },
675 };
676 /* driver end */
677
678 int venc_init_display(struct omap_dss_device *dssdev)
679 {
680 DSSDBG("init_display\n");
681
682 if (venc.vdda_dac_reg == NULL) {
683 struct regulator *vdda_dac;
684
685 vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac");
686
687 if (IS_ERR(vdda_dac)) {
688 DSSERR("can't get VDDA_DAC regulator\n");
689 return PTR_ERR(vdda_dac);
690 }
691
692 venc.vdda_dac_reg = vdda_dac;
693 }
694
695 return 0;
696 }
697
698 void venc_dump_regs(struct seq_file *s)
699 {
700 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
701
702 if (cpu_is_omap44xx()) {
703 seq_printf(s, "VENC currently disabled on OMAP44xx\n");
704 return;
705 }
706
707 if (venc_runtime_get())
708 return;
709
710 DUMPREG(VENC_F_CONTROL);
711 DUMPREG(VENC_VIDOUT_CTRL);
712 DUMPREG(VENC_SYNC_CTRL);
713 DUMPREG(VENC_LLEN);
714 DUMPREG(VENC_FLENS);
715 DUMPREG(VENC_HFLTR_CTRL);
716 DUMPREG(VENC_CC_CARR_WSS_CARR);
717 DUMPREG(VENC_C_PHASE);
718 DUMPREG(VENC_GAIN_U);
719 DUMPREG(VENC_GAIN_V);
720 DUMPREG(VENC_GAIN_Y);
721 DUMPREG(VENC_BLACK_LEVEL);
722 DUMPREG(VENC_BLANK_LEVEL);
723 DUMPREG(VENC_X_COLOR);
724 DUMPREG(VENC_M_CONTROL);
725 DUMPREG(VENC_BSTAMP_WSS_DATA);
726 DUMPREG(VENC_S_CARR);
727 DUMPREG(VENC_LINE21);
728 DUMPREG(VENC_LN_SEL);
729 DUMPREG(VENC_L21__WC_CTL);
730 DUMPREG(VENC_HTRIGGER_VTRIGGER);
731 DUMPREG(VENC_SAVID__EAVID);
732 DUMPREG(VENC_FLEN__FAL);
733 DUMPREG(VENC_LAL__PHASE_RESET);
734 DUMPREG(VENC_HS_INT_START_STOP_X);
735 DUMPREG(VENC_HS_EXT_START_STOP_X);
736 DUMPREG(VENC_VS_INT_START_X);
737 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
738 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
739 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
740 DUMPREG(VENC_VS_EXT_STOP_Y);
741 DUMPREG(VENC_AVID_START_STOP_X);
742 DUMPREG(VENC_AVID_START_STOP_Y);
743 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
744 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
745 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
746 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
747 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
748 DUMPREG(VENC_GEN_CTRL);
749 DUMPREG(VENC_OUTPUT_CONTROL);
750 DUMPREG(VENC_OUTPUT_TEST);
751
752 venc_runtime_put();
753
754 #undef DUMPREG
755 }
756
757 static int venc_get_clocks(struct platform_device *pdev)
758 {
759 struct clk *clk;
760
761 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
762 clk = clk_get(&pdev->dev, "tv_dac_clk");
763 if (IS_ERR(clk)) {
764 DSSERR("can't get tv_dac_clk\n");
765 return PTR_ERR(clk);
766 }
767 } else {
768 clk = NULL;
769 }
770
771 venc.tv_dac_clk = clk;
772
773 return 0;
774 }
775
776 static void venc_put_clocks(void)
777 {
778 if (venc.tv_dac_clk)
779 clk_put(venc.tv_dac_clk);
780 }
781
782 /* VENC HW IP initialisation */
783 static int omap_venchw_probe(struct platform_device *pdev)
784 {
785 u8 rev_id;
786 struct resource *venc_mem;
787 int r;
788
789 venc.pdev = pdev;
790
791 mutex_init(&venc.venc_lock);
792
793 venc.wss_data = 0;
794
795 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
796 if (!venc_mem) {
797 DSSERR("can't get IORESOURCE_MEM VENC\n");
798 r = -EINVAL;
799 goto err_ioremap;
800 }
801 venc.base = ioremap(venc_mem->start, resource_size(venc_mem));
802 if (!venc.base) {
803 DSSERR("can't ioremap VENC\n");
804 r = -ENOMEM;
805 goto err_ioremap;
806 }
807
808 r = venc_get_clocks(pdev);
809 if (r)
810 goto err_get_clk;
811
812 pm_runtime_enable(&pdev->dev);
813
814 r = venc_runtime_get();
815 if (r)
816 goto err_get_venc;
817
818 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
819 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
820
821 venc_runtime_put();
822
823 return omap_dss_register_driver(&venc_driver);
824
825 err_get_venc:
826 pm_runtime_disable(&pdev->dev);
827 venc_put_clocks();
828 err_get_clk:
829 iounmap(venc.base);
830 err_ioremap:
831 return r;
832 }
833
834 static int omap_venchw_remove(struct platform_device *pdev)
835 {
836 if (venc.vdda_dac_reg != NULL) {
837 regulator_put(venc.vdda_dac_reg);
838 venc.vdda_dac_reg = NULL;
839 }
840 omap_dss_unregister_driver(&venc_driver);
841
842 pm_runtime_disable(&pdev->dev);
843 venc_put_clocks();
844
845 iounmap(venc.base);
846 return 0;
847 }
848
849 static int venc_runtime_suspend(struct device *dev)
850 {
851 if (venc.tv_dac_clk)
852 clk_disable(venc.tv_dac_clk);
853
854 dispc_runtime_put();
855 dss_runtime_put();
856
857 return 0;
858 }
859
860 static int venc_runtime_resume(struct device *dev)
861 {
862 int r;
863
864 r = dss_runtime_get();
865 if (r < 0)
866 goto err_get_dss;
867
868 r = dispc_runtime_get();
869 if (r < 0)
870 goto err_get_dispc;
871
872 if (venc.tv_dac_clk)
873 clk_enable(venc.tv_dac_clk);
874
875 return 0;
876
877 err_get_dispc:
878 dss_runtime_put();
879 err_get_dss:
880 return r;
881 }
882
883 static const struct dev_pm_ops venc_pm_ops = {
884 .runtime_suspend = venc_runtime_suspend,
885 .runtime_resume = venc_runtime_resume,
886 };
887
888 static struct platform_driver omap_venchw_driver = {
889 .probe = omap_venchw_probe,
890 .remove = omap_venchw_remove,
891 .driver = {
892 .name = "omapdss_venc",
893 .owner = THIS_MODULE,
894 .pm = &venc_pm_ops,
895 },
896 };
897
898 int venc_init_platform_driver(void)
899 {
900 if (cpu_is_omap44xx())
901 return 0;
902
903 return platform_driver_register(&omap_venchw_driver);
904 }
905
906 void venc_uninit_platform_driver(void)
907 {
908 if (cpu_is_omap44xx())
909 return;
910
911 return platform_driver_unregister(&omap_venchw_driver);
912 }