Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / drivers / watchdog / iTCO_vendor_support.c
blob481d1ad434640a3c58c1d1a58791f985d75567f5
1 /*
2 * intel TCO vendor specific watchdog driver support
4 * (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
17 * Includes, defines, variables, module parameters, ...
20 /* Module and version information */
21 #define DRV_NAME "iTCO_vendor_support"
22 #define DRV_VERSION "1.04"
23 #define PFX DRV_NAME ": "
25 /* Includes */
26 #include <linux/module.h> /* For module specific items */
27 #include <linux/moduleparam.h> /* For new moduleparam's */
28 #include <linux/types.h> /* For standard types (like size_t) */
29 #include <linux/errno.h> /* For the -ENODEV/... values */
30 #include <linux/kernel.h> /* For printk/panic/... */
31 #include <linux/init.h> /* For __init/__exit/... */
32 #include <linux/ioport.h> /* For io-port access */
33 #include <linux/io.h> /* For inb/outb/... */
35 #include "iTCO_vendor.h"
37 /* iTCO defines */
38 #define SMI_EN (acpibase + 0x30) /* SMI Control and Enable Register */
39 #define TCOBASE (acpibase + 0x60) /* TCO base address */
40 #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
42 /* List of vendor support modes */
43 /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
44 #define SUPERMICRO_OLD_BOARD 1
45 /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */
46 #define SUPERMICRO_NEW_BOARD 2
47 /* Broken BIOS */
48 #define BROKEN_BIOS 911
50 static int vendorsupport;
51 module_param(vendorsupport, int, 0);
52 MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default="
53 "0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+, "
54 "911=Broken SMI BIOS");
57 * Vendor Specific Support
61 * Vendor Support: 1
62 * Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE
63 * iTCO chipset: ICH2
65 * Code contributed by: R. Seretny <lkpatches@paypc.com>
66 * Documentation obtained by R. Seretny from SuperMicro Technical Support
68 * To enable Watchdog function:
69 * BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes
70 * This setting enables SMI to clear the watchdog expired flag.
71 * If BIOS or CPU fail which may cause SMI hang, then system will
72 * reboot. When application starts to use watchdog function,
73 * application has to take over the control from SMI.
75 * For P3TSSE, J36 jumper needs to be removed to enable the Watchdog
76 * function.
78 * Note: The system will reboot when Expire Flag is set TWICE.
79 * So, if the watchdog timer is 20 seconds, then the maximum hang
80 * time is about 40 seconds, and the minimum hang time is about
81 * 20.6 seconds.
84 static void supermicro_old_pre_start(unsigned long acpibase)
86 unsigned long val32;
88 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
89 val32 = inl(SMI_EN);
90 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
91 outl(val32, SMI_EN); /* Needed to activate watchdog */
94 static void supermicro_old_pre_stop(unsigned long acpibase)
96 unsigned long val32;
98 /* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */
99 val32 = inl(SMI_EN);
100 val32 |= 0x00002000; /* Turn on SMI clearing watchdog */
101 outl(val32, SMI_EN); /* Needed to deactivate watchdog */
105 * Vendor Support: 2
106 * Board: Super Micro Computer Inc. P4SBx, P4DPx
107 * iTCO chipset: ICH4
109 * Code contributed by: R. Seretny <lkpatches@paypc.com>
110 * Documentation obtained by R. Seretny from SuperMicro Technical Support
112 * To enable Watchdog function:
113 * 1. BIOS
114 * For P4SBx:
115 * BIOS setup -> Advanced -> Integrated Peripherals -> Watch Dog Feature
116 * For P4DPx:
117 * BIOS setup -> Advanced -> I/O Device Configuration -> Watch Dog
118 * This setting enables or disables Watchdog function. When enabled, the
119 * default watchdog timer is set to be 5 minutes (about 4m35s). It is
120 * enough to load and run the OS. The application (service or driver) has
121 * to take over the control once OS is running up and before watchdog
122 * expires.
124 * 2. JUMPER
125 * For P4SBx: JP39
126 * For P4DPx: JP37
127 * This jumper is used for safety. Closed is enabled. This jumper
128 * prevents user enables watchdog in BIOS by accident.
130 * To enable Watch Dog function, both BIOS and JUMPER must be enabled.
132 * The documentation lists motherboards P4SBx and P4DPx series as of
133 * 20-March-2002. However, this code works flawlessly with much newer
134 * motherboards, such as my X6DHR-8G2 (SuperServer 6014H-82).
136 * The original iTCO driver as written does not actually reset the
137 * watchdog timer on these machines, as a result they reboot after five
138 * minutes.
140 * NOTE: You may leave the Watchdog function disabled in the SuperMicro
141 * BIOS to avoid a "boot-race"... This driver will enable watchdog
142 * functionality even if it's disabled in the BIOS once the /dev/watchdog
143 * file is opened.
146 /* I/O Port's */
147 #define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */
148 #define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */
150 /* Control Register's */
151 #define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */
152 #define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */
154 #define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */
156 #define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */
158 #define SM_ENDWATCH 0xAA /* Watchdog lock control page */
160 #define SM_COUNTMODE 0xf5 /* Watchdog count mode select */
161 /* (Bit 3: 0 = seconds, 1 = minutes */
163 #define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */
165 #define SM_RESETCONTROL 0xf7 /* Watchdog reset control */
166 /* Bit 6: timer is reset by kbd interrupt */
167 /* Bit 7: timer is reset by mouse interrupt */
169 static void supermicro_new_unlock_watchdog(void)
171 /* Write 0x87 to port 0x2e twice */
172 outb(SM_WATCHPAGE, SM_REGINDEX);
173 outb(SM_WATCHPAGE, SM_REGINDEX);
174 /* Switch to watchdog control page */
175 outb(SM_CTLPAGESW, SM_REGINDEX);
176 outb(SM_CTLPAGE, SM_DATAIO);
179 static void supermicro_new_lock_watchdog(void)
181 outb(SM_ENDWATCH, SM_REGINDEX);
184 static void supermicro_new_pre_start(unsigned int heartbeat)
186 unsigned int val;
188 supermicro_new_unlock_watchdog();
190 /* Watchdog timer setting needs to be in seconds*/
191 outb(SM_COUNTMODE, SM_REGINDEX);
192 val = inb(SM_DATAIO);
193 val &= 0xF7;
194 outb(val, SM_DATAIO);
196 /* Write heartbeat interval to WDOG */
197 outb(SM_WATCHTIMER, SM_REGINDEX);
198 outb((heartbeat & 255), SM_DATAIO);
200 /* Make sure keyboard/mouse interrupts don't interfere */
201 outb(SM_RESETCONTROL, SM_REGINDEX);
202 val = inb(SM_DATAIO);
203 val &= 0x3f;
204 outb(val, SM_DATAIO);
206 /* enable watchdog by setting bit 0 of Watchdog Enable to 1 */
207 outb(SM_WATCHENABLE, SM_REGINDEX);
208 val = inb(SM_DATAIO);
209 val |= 0x01;
210 outb(val, SM_DATAIO);
212 supermicro_new_lock_watchdog();
215 static void supermicro_new_pre_stop(void)
217 unsigned int val;
219 supermicro_new_unlock_watchdog();
221 /* disable watchdog by setting bit 0 of Watchdog Enable to 0 */
222 outb(SM_WATCHENABLE, SM_REGINDEX);
223 val = inb(SM_DATAIO);
224 val &= 0xFE;
225 outb(val, SM_DATAIO);
227 supermicro_new_lock_watchdog();
230 static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat)
232 supermicro_new_unlock_watchdog();
234 /* reset watchdog timeout to heartveat value */
235 outb(SM_WATCHTIMER, SM_REGINDEX);
236 outb((heartbeat & 255), SM_DATAIO);
238 supermicro_new_lock_watchdog();
242 * Vendor Support: 911
243 * Board: Some Intel ICHx based motherboards
244 * iTCO chipset: ICH7+
246 * Some Intel motherboards have a broken BIOS implementation: i.e.
247 * the SMI handler clear's the TIMEOUT bit in the TC01_STS register
248 * and does not reload the time. Thus the TCO watchdog does not reboot
249 * the system.
251 * These are the conclusions of Andriy Gapon <avg@icyb.net.ua> after
252 * debugging: the SMI handler is quite simple - it tests value in
253 * TCO1_CNT against 0x800, i.e. checks TCO_TMR_HLT. If the bit is set
254 * the handler goes into an infinite loop, apparently to allow the
255 * second timeout and reboot. Otherwise it simply clears TIMEOUT bit
256 * in TCO1_STS and that's it.
257 * So the logic seems to be reversed, because it is hard to see how
258 * TIMEOUT can get set to 1 and SMI generated when TCO_TMR_HLT is set
259 * (other than a transitional effect).
261 * The only fix found to get the motherboard(s) to reboot is to put
262 * the glb_smi_en bit to 0. This is a dirty hack that bypasses the
263 * broken code by disabling Global SMI.
265 * WARNING: globally disabling SMI could possibly lead to dramatic
266 * problems, especially on laptops! I.e. various ACPI things where
267 * SMI is used for communication between OS and firmware.
269 * Don't use this fix if you don't need to!!!
272 static void broken_bios_start(unsigned long acpibase)
274 unsigned long val32;
276 val32 = inl(SMI_EN);
277 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI#
278 Bit 0: GBL_SMI_EN -> 0 = No SMI# will be generated by ICH. */
279 val32 &= 0xffffdffe;
280 outl(val32, SMI_EN);
283 static void broken_bios_stop(unsigned long acpibase)
285 unsigned long val32;
287 val32 = inl(SMI_EN);
288 /* Bit 13: TCO_EN -> 1 = Enables TCO logic generating an SMI#
289 Bit 0: GBL_SMI_EN -> 1 = Turn global SMI on again. */
290 val32 |= 0x00002001;
291 outl(val32, SMI_EN);
295 * Generic Support Functions
298 void iTCO_vendor_pre_start(unsigned long acpibase,
299 unsigned int heartbeat)
301 switch (vendorsupport) {
302 case SUPERMICRO_OLD_BOARD:
303 supermicro_old_pre_start(acpibase);
304 break;
305 case SUPERMICRO_NEW_BOARD:
306 supermicro_new_pre_start(heartbeat);
307 break;
308 case BROKEN_BIOS:
309 broken_bios_start(acpibase);
310 break;
313 EXPORT_SYMBOL(iTCO_vendor_pre_start);
315 void iTCO_vendor_pre_stop(unsigned long acpibase)
317 switch (vendorsupport) {
318 case SUPERMICRO_OLD_BOARD:
319 supermicro_old_pre_stop(acpibase);
320 break;
321 case SUPERMICRO_NEW_BOARD:
322 supermicro_new_pre_stop();
323 break;
324 case BROKEN_BIOS:
325 broken_bios_stop(acpibase);
326 break;
329 EXPORT_SYMBOL(iTCO_vendor_pre_stop);
331 void iTCO_vendor_pre_keepalive(unsigned long acpibase, unsigned int heartbeat)
333 if (vendorsupport == SUPERMICRO_NEW_BOARD)
334 supermicro_new_pre_set_heartbeat(heartbeat);
336 EXPORT_SYMBOL(iTCO_vendor_pre_keepalive);
338 void iTCO_vendor_pre_set_heartbeat(unsigned int heartbeat)
340 if (vendorsupport == SUPERMICRO_NEW_BOARD)
341 supermicro_new_pre_set_heartbeat(heartbeat);
343 EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat);
345 int iTCO_vendor_check_noreboot_on(void)
347 switch (vendorsupport) {
348 case SUPERMICRO_OLD_BOARD:
349 return 0;
350 default:
351 return 1;
354 EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on);
356 static int __init iTCO_vendor_init_module(void)
358 printk(KERN_INFO PFX "vendor-support=%d\n", vendorsupport);
359 return 0;
362 static void __exit iTCO_vendor_exit_module(void)
364 printk(KERN_INFO PFX "Module Unloaded\n");
367 module_init(iTCO_vendor_init_module);
368 module_exit(iTCO_vendor_exit_module);
370 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>, "
371 "R. Seretny <lkpatches@paypc.com>");
372 MODULE_DESCRIPTION("Intel TCO Vendor Specific WatchDog Timer Driver Support");
373 MODULE_VERSION(DRV_VERSION);
374 MODULE_LICENSE("GPL");