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Merge tag 'v3.3.7' into 3.3/master
[zen-stable.git] / sound / soc / codecs / wm8993.c
blob7c7fd925db8da78c1ad6bb08bdde66eb60d7210b
1 /*
2 * wm8993.c -- WM8993 ALSA SoC audio driver
3 *
4 * Copyright 2009, 2010 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/tlv.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/wm8993.h>
29
30 #include "wm8993.h"
31 #include "wm_hubs.h"
32
33 #define WM8993_NUM_SUPPLIES 6
34 static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
35 "DCVDD",
36 "DBVDD",
37 "AVDD1",
38 "AVDD2",
39 "CPVDD",
40 "SPKVDD",
41 };
42
43 static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = {
44 0x8993, /* R0 - Software Reset */
45 0x0000, /* R1 - Power Management (1) */
46 0x6000, /* R2 - Power Management (2) */
47 0x0000, /* R3 - Power Management (3) */
48 0x4050, /* R4 - Audio Interface (1) */
49 0x4000, /* R5 - Audio Interface (2) */
50 0x01C8, /* R6 - Clocking 1 */
51 0x0000, /* R7 - Clocking 2 */
52 0x0000, /* R8 - Audio Interface (3) */
53 0x0040, /* R9 - Audio Interface (4) */
54 0x0004, /* R10 - DAC CTRL */
55 0x00C0, /* R11 - Left DAC Digital Volume */
56 0x00C0, /* R12 - Right DAC Digital Volume */
57 0x0000, /* R13 - Digital Side Tone */
58 0x0300, /* R14 - ADC CTRL */
59 0x00C0, /* R15 - Left ADC Digital Volume */
60 0x00C0, /* R16 - Right ADC Digital Volume */
61 0x0000, /* R17 */
62 0x0000, /* R18 - GPIO CTRL 1 */
63 0x0010, /* R19 - GPIO1 */
64 0x0000, /* R20 - IRQ_DEBOUNCE */
65 0x0000, /* R21 */
66 0x8000, /* R22 - GPIOCTRL 2 */
67 0x0800, /* R23 - GPIO_POL */
68 0x008B, /* R24 - Left Line Input 1&2 Volume */
69 0x008B, /* R25 - Left Line Input 3&4 Volume */
70 0x008B, /* R26 - Right Line Input 1&2 Volume */
71 0x008B, /* R27 - Right Line Input 3&4 Volume */
72 0x006D, /* R28 - Left Output Volume */
73 0x006D, /* R29 - Right Output Volume */
74 0x0066, /* R30 - Line Outputs Volume */
75 0x0020, /* R31 - HPOUT2 Volume */
76 0x0079, /* R32 - Left OPGA Volume */
77 0x0079, /* R33 - Right OPGA Volume */
78 0x0003, /* R34 - SPKMIXL Attenuation */
79 0x0003, /* R35 - SPKMIXR Attenuation */
80 0x0011, /* R36 - SPKOUT Mixers */
81 0x0100, /* R37 - SPKOUT Boost */
82 0x0079, /* R38 - Speaker Volume Left */
83 0x0079, /* R39 - Speaker Volume Right */
84 0x0000, /* R40 - Input Mixer2 */
85 0x0000, /* R41 - Input Mixer3 */
86 0x0000, /* R42 - Input Mixer4 */
87 0x0000, /* R43 - Input Mixer5 */
88 0x0000, /* R44 - Input Mixer6 */
89 0x0000, /* R45 - Output Mixer1 */
90 0x0000, /* R46 - Output Mixer2 */
91 0x0000, /* R47 - Output Mixer3 */
92 0x0000, /* R48 - Output Mixer4 */
93 0x0000, /* R49 - Output Mixer5 */
94 0x0000, /* R50 - Output Mixer6 */
95 0x0000, /* R51 - HPOUT2 Mixer */
96 0x0000, /* R52 - Line Mixer1 */
97 0x0000, /* R53 - Line Mixer2 */
98 0x0000, /* R54 - Speaker Mixer */
99 0x0000, /* R55 - Additional Control */
100 0x0000, /* R56 - AntiPOP1 */
101 0x0000, /* R57 - AntiPOP2 */
102 0x0000, /* R58 - MICBIAS */
103 0x0000, /* R59 */
104 0x0000, /* R60 - FLL Control 1 */
105 0x0000, /* R61 - FLL Control 2 */
106 0x0000, /* R62 - FLL Control 3 */
107 0x2EE0, /* R63 - FLL Control 4 */
108 0x0002, /* R64 - FLL Control 5 */
109 0x2287, /* R65 - Clocking 3 */
110 0x025F, /* R66 - Clocking 4 */
111 0x0000, /* R67 - MW Slave Control */
112 0x0000, /* R68 */
113 0x0002, /* R69 - Bus Control 1 */
114 0x0000, /* R70 - Write Sequencer 0 */
115 0x0000, /* R71 - Write Sequencer 1 */
116 0x0000, /* R72 - Write Sequencer 2 */
117 0x0000, /* R73 - Write Sequencer 3 */
118 0x0000, /* R74 - Write Sequencer 4 */
119 0x0000, /* R75 - Write Sequencer 5 */
120 0x1F25, /* R76 - Charge Pump 1 */
121 0x0000, /* R77 */
122 0x0000, /* R78 */
123 0x0000, /* R79 */
124 0x0000, /* R80 */
125 0x0000, /* R81 - Class W 0 */
126 0x0000, /* R82 */
127 0x0000, /* R83 */
128 0x0000, /* R84 - DC Servo 0 */
129 0x054A, /* R85 - DC Servo 1 */
130 0x0000, /* R86 */
131 0x0000, /* R87 - DC Servo 3 */
132 0x0000, /* R88 - DC Servo Readback 0 */
133 0x0000, /* R89 - DC Servo Readback 1 */
134 0x0000, /* R90 - DC Servo Readback 2 */
135 0x0000, /* R91 */
136 0x0000, /* R92 */
137 0x0000, /* R93 */
138 0x0000, /* R94 */
139 0x0000, /* R95 */
140 0x0100, /* R96 - Analogue HP 0 */
141 0x0000, /* R97 */
142 0x0000, /* R98 - EQ1 */
143 0x000C, /* R99 - EQ2 */
144 0x000C, /* R100 - EQ3 */
145 0x000C, /* R101 - EQ4 */
146 0x000C, /* R102 - EQ5 */
147 0x000C, /* R103 - EQ6 */
148 0x0FCA, /* R104 - EQ7 */
149 0x0400, /* R105 - EQ8 */
150 0x00D8, /* R106 - EQ9 */
151 0x1EB5, /* R107 - EQ10 */
152 0xF145, /* R108 - EQ11 */
153 0x0B75, /* R109 - EQ12 */
154 0x01C5, /* R110 - EQ13 */
155 0x1C58, /* R111 - EQ14 */
156 0xF373, /* R112 - EQ15 */
157 0x0A54, /* R113 - EQ16 */
158 0x0558, /* R114 - EQ17 */
159 0x168E, /* R115 - EQ18 */
160 0xF829, /* R116 - EQ19 */
161 0x07AD, /* R117 - EQ20 */
162 0x1103, /* R118 - EQ21 */
163 0x0564, /* R119 - EQ22 */
164 0x0559, /* R120 - EQ23 */
165 0x4000, /* R121 - EQ24 */
166 0x0000, /* R122 - Digital Pulls */
167 0x0F08, /* R123 - DRC Control 1 */
168 0x0000, /* R124 - DRC Control 2 */
169 0x0080, /* R125 - DRC Control 3 */
170 0x0000, /* R126 - DRC Control 4 */
171 };
172
173 static struct {
174 int ratio;
175 int clk_sys_rate;
176 } clk_sys_rates[] = {
177 { 64, 0 },
178 { 128, 1 },
179 { 192, 2 },
180 { 256, 3 },
181 { 384, 4 },
182 { 512, 5 },
183 { 768, 6 },
184 { 1024, 7 },
185 { 1408, 8 },
186 { 1536, 9 },
187 };
188
189 static struct {
190 int rate;
191 int sample_rate;
192 } sample_rates[] = {
193 { 8000, 0 },
194 { 11025, 1 },
195 { 12000, 1 },
196 { 16000, 2 },
197 { 22050, 3 },
198 { 24000, 3 },
199 { 32000, 4 },
200 { 44100, 5 },
201 { 48000, 5 },
202 };
203
204 static struct {
205 int div; /* *10 due to .5s */
206 int bclk_div;
207 } bclk_divs[] = {
208 { 10, 0 },
209 { 15, 1 },
210 { 20, 2 },
211 { 30, 3 },
212 { 40, 4 },
213 { 55, 5 },
214 { 60, 6 },
215 { 80, 7 },
216 { 110, 8 },
217 { 120, 9 },
218 { 160, 10 },
219 { 220, 11 },
220 { 240, 12 },
221 { 320, 13 },
222 { 440, 14 },
223 { 480, 15 },
224 };
225
226 struct wm8993_priv {
227 struct wm_hubs_data hubs_data;
228 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
229 struct wm8993_platform_data pdata;
230 enum snd_soc_control_type control_type;
231 int master;
232 int sysclk_source;
233 int tdm_slots;
234 int tdm_width;
235 unsigned int mclk_rate;
236 unsigned int sysclk_rate;
237 unsigned int fs;
238 unsigned int bclk;
239 int class_w_users;
240 unsigned int fll_fref;
241 unsigned int fll_fout;
242 int fll_src;
243 };
244
245 static int wm8993_volatile(struct snd_soc_codec *codec, unsigned int reg)
246 {
247 switch (reg) {
248 case WM8993_SOFTWARE_RESET:
249 case WM8993_DC_SERVO_0:
250 case WM8993_DC_SERVO_READBACK_0:
251 case WM8993_DC_SERVO_READBACK_1:
252 case WM8993_DC_SERVO_READBACK_2:
253 return 1;
254 default:
255 return 0;
256 }
257 }
258
259 struct _fll_div {
260 u16 fll_fratio;
261 u16 fll_outdiv;
262 u16 fll_clk_ref_div;
263 u16 n;
264 u16 k;
265 };
266
267 /* The size in bits of the FLL divide multiplied by 10
268 * to allow rounding later */
269 #define FIXED_FLL_SIZE ((1 << 16) * 10)
270
271 static struct {
272 unsigned int min;
273 unsigned int max;
274 u16 fll_fratio;
275 int ratio;
276 } fll_fratios[] = {
277 { 0, 64000, 4, 16 },
278 { 64000, 128000, 3, 8 },
279 { 128000, 256000, 2, 4 },
280 { 256000, 1000000, 1, 2 },
281 { 1000000, 13500000, 0, 1 },
282 };
283
284 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
285 unsigned int Fout)
286 {
287 u64 Kpart;
288 unsigned int K, Ndiv, Nmod, target;
289 unsigned int div;
290 int i;
291
292 /* Fref must be <=13.5MHz */
293 div = 1;
294 fll_div->fll_clk_ref_div = 0;
295 while ((Fref / div) > 13500000) {
296 div *= 2;
297 fll_div->fll_clk_ref_div++;
298
299 if (div > 8) {
300 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
301 Fref);
302 return -EINVAL;
303 }
304 }
305
306 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
307
308 /* Apply the division for our remaining calculations */
309 Fref /= div;
310
311 /* Fvco should be 90-100MHz; don't check the upper bound */
312 div = 0;
313 target = Fout * 2;
314 while (target < 90000000) {
315 div++;
316 target *= 2;
317 if (div > 7) {
318 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
319 Fout);
320 return -EINVAL;
321 }
322 }
323 fll_div->fll_outdiv = div;
324
325 pr_debug("Fvco=%dHz\n", target);
326
327 /* Find an appropriate FLL_FRATIO and factor it out of the target */
328 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
329 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
330 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
331 target /= fll_fratios[i].ratio;
332 break;
333 }
334 }
335 if (i == ARRAY_SIZE(fll_fratios)) {
336 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
337 return -EINVAL;
338 }
339
340 /* Now, calculate N.K */
341 Ndiv = target / Fref;
342
343 fll_div->n = Ndiv;
344 Nmod = target % Fref;
345 pr_debug("Nmod=%d\n", Nmod);
346
347 /* Calculate fractional part - scale up so we can round. */
348 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
349
350 do_div(Kpart, Fref);
351
352 K = Kpart & 0xFFFFFFFF;
353
354 if ((K % 10) >= 5)
355 K += 5;
356
357 /* Move down to proper range now rounding is done */
358 fll_div->k = K / 10;
359
360 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
361 fll_div->n, fll_div->k,
362 fll_div->fll_fratio, fll_div->fll_outdiv,
363 fll_div->fll_clk_ref_div);
364
365 return 0;
366 }
367
368 static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
369 unsigned int Fref, unsigned int Fout)
370 {
371 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
372 u16 reg1, reg4, reg5;
373 struct _fll_div fll_div;
374 int ret;
375
376 /* Any change? */
377 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
378 return 0;
379
380 /* Disable the FLL */
381 if (Fout == 0) {
382 dev_dbg(codec->dev, "FLL disabled\n");
383 wm8993->fll_fref = 0;
384 wm8993->fll_fout = 0;
385
386 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
387 reg1 &= ~WM8993_FLL_ENA;
388 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
389
390 return 0;
391 }
392
393 ret = fll_factors(&fll_div, Fref, Fout);
394 if (ret != 0)
395 return ret;
396
397 reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5);
398 reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
399
400 switch (fll_id) {
401 case WM8993_FLL_MCLK:
402 break;
403
404 case WM8993_FLL_LRCLK:
405 reg5 |= 1;
406 break;
407
408 case WM8993_FLL_BCLK:
409 reg5 |= 2;
410 break;
411
412 default:
413 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
414 return -EINVAL;
415 }
416
417 /* Any FLL configuration change requires that the FLL be
418 * disabled first. */
419 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
420 reg1 &= ~WM8993_FLL_ENA;
421 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
422
423 /* Apply the configuration */
424 if (fll_div.k)
425 reg1 |= WM8993_FLL_FRAC_MASK;
426 else
427 reg1 &= ~WM8993_FLL_FRAC_MASK;
428 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
429
430 snd_soc_write(codec, WM8993_FLL_CONTROL_2,
431 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
432 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
433 snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
434
435 reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4);
436 reg4 &= ~WM8993_FLL_N_MASK;
437 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
438 snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4);
439
440 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
441 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
442 snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5);
443
444 /* Enable the FLL */
445 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
446
447 /* Both overestimates */
448 if (Fref < 1000000)
449 msleep(3);
450 else
451 msleep(1);
452
453 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
454
455 wm8993->fll_fref = Fref;
456 wm8993->fll_fout = Fout;
457 wm8993->fll_src = source;
458
459 return 0;
460 }
461
462 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
463 unsigned int Fref, unsigned int Fout)
464 {
465 return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout);
466 }
467
468 static int configure_clock(struct snd_soc_codec *codec)
469 {
470 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
471 unsigned int reg;
472
473 /* This should be done on init() for bypass paths */
474 switch (wm8993->sysclk_source) {
475 case WM8993_SYSCLK_MCLK:
476 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
477
478 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
479 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
480 if (wm8993->mclk_rate > 13500000) {
481 reg |= WM8993_MCLK_DIV;
482 wm8993->sysclk_rate = wm8993->mclk_rate / 2;
483 } else {
484 reg &= ~WM8993_MCLK_DIV;
485 wm8993->sysclk_rate = wm8993->mclk_rate;
486 }
487 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
488 break;
489
490 case WM8993_SYSCLK_FLL:
491 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
492 wm8993->fll_fout);
493
494 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
495 reg |= WM8993_SYSCLK_SRC;
496 if (wm8993->fll_fout > 13500000) {
497 reg |= WM8993_MCLK_DIV;
498 wm8993->sysclk_rate = wm8993->fll_fout / 2;
499 } else {
500 reg &= ~WM8993_MCLK_DIV;
501 wm8993->sysclk_rate = wm8993->fll_fout;
502 }
503 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
504 break;
505
506 default:
507 dev_err(codec->dev, "System clock not configured\n");
508 return -EINVAL;
509 }
510
511 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
512
513 return 0;
514 }
515
516 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
517 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
518 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
519 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
520 static const unsigned int drc_max_tlv[] = {
521 TLV_DB_RANGE_HEAD(2),
522 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
523 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
524 };
525 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
526 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
527 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
528 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
529 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
530
531 static const char *dac_deemph_text[] = {
532 "None",
533 "32kHz",
534 "44.1kHz",
535 "48kHz",
536 };
537
538 static const struct soc_enum dac_deemph =
539 SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
540
541 static const char *adc_hpf_text[] = {
542 "Hi-Fi",
543 "Voice 1",
544 "Voice 2",
545 "Voice 3",
546 };
547
548 static const struct soc_enum adc_hpf =
549 SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
550
551 static const char *drc_path_text[] = {
552 "ADC",
553 "DAC"
554 };
555
556 static const struct soc_enum drc_path =
557 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
558
559 static const char *drc_r0_text[] = {
560 "1",
561 "1/2",
562 "1/4",
563 "1/8",
564 "1/16",
565 "0",
566 };
567
568 static const struct soc_enum drc_r0 =
569 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
570
571 static const char *drc_r1_text[] = {
572 "1",
573 "1/2",
574 "1/4",
575 "1/8",
576 "0",
577 };
578
579 static const struct soc_enum drc_r1 =
580 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
581
582 static const char *drc_attack_text[] = {
583 "Reserved",
584 "181us",
585 "363us",
586 "726us",
587 "1.45ms",
588 "2.9ms",
589 "5.8ms",
590 "11.6ms",
591 "23.2ms",
592 "46.4ms",
593 "92.8ms",
594 "185.6ms",
595 };
596
597 static const struct soc_enum drc_attack =
598 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
599
600 static const char *drc_decay_text[] = {
601 "186ms",
602 "372ms",
603 "743ms",
604 "1.49s",
605 "2.97ms",
606 "5.94ms",
607 "11.89ms",
608 "23.78ms",
609 "47.56ms",
610 };
611
612 static const struct soc_enum drc_decay =
613 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
614
615 static const char *drc_ff_text[] = {
616 "5 samples",
617 "9 samples",
618 };
619
620 static const struct soc_enum drc_ff =
621 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
622
623 static const char *drc_qr_rate_text[] = {
624 "0.725ms",
625 "1.45ms",
626 "5.8ms",
627 };
628
629 static const struct soc_enum drc_qr_rate =
630 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
631
632 static const char *drc_smooth_text[] = {
633 "Low",
634 "Medium",
635 "High",
636 };
637
638 static const struct soc_enum drc_smooth =
639 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
640
641 static const struct snd_kcontrol_new wm8993_snd_controls[] = {
642 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
643 5, 9, 12, 0, sidetone_tlv),
644
645 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
646 SOC_ENUM("DRC Path", drc_path),
647 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
648 2, 60, 1, drc_comp_threash),
649 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
650 11, 30, 1, drc_comp_amp),
651 SOC_ENUM("DRC R0", drc_r0),
652 SOC_ENUM("DRC R1", drc_r1),
653 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
654 drc_min_tlv),
655 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
656 drc_max_tlv),
657 SOC_ENUM("DRC Attack Rate", drc_attack),
658 SOC_ENUM("DRC Decay Rate", drc_decay),
659 SOC_ENUM("DRC FF Delay", drc_ff),
660 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
661 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
662 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
663 drc_qr_tlv),
664 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
665 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
666 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
667 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
668 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
669 drc_startup_tlv),
670
671 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
672
673 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
674 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
675 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
676 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
677
678 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
679 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
680 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
681 dac_boost_tlv),
682 SOC_ENUM("DAC Deemphasis", dac_deemph),
683
684 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
685 2, 1, 1, wm_hubs_spkmix_tlv),
686
687 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
688 2, 1, 1, wm_hubs_spkmix_tlv),
689 };
690
691 static const struct snd_kcontrol_new wm8993_eq_controls[] = {
692 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
693 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
694 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
695 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
696 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
697 };
698
699 static int clk_sys_event(struct snd_soc_dapm_widget *w,
700 struct snd_kcontrol *kcontrol, int event)
701 {
702 struct snd_soc_codec *codec = w->codec;
703
704 switch (event) {
705 case SND_SOC_DAPM_PRE_PMU:
706 return configure_clock(codec);
707
708 case SND_SOC_DAPM_POST_PMD:
709 break;
710 }
711
712 return 0;
713 }
714
715 /*
716 * When used with DAC outputs only the WM8993 charge pump supports
717 * operation in class W mode, providing very low power consumption
718 * when used with digital sources. Enable and disable this mode
719 * automatically depending on the mixer configuration.
720 *
721 * Currently the only supported paths are the direct DAC->headphone
722 * paths (which provide minimum power consumption anyway).
723 */
724 static int class_w_put(struct snd_kcontrol *kcontrol,
725 struct snd_ctl_elem_value *ucontrol)
726 {
727 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
728 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
729 struct snd_soc_codec *codec = widget->codec;
730 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
731 int ret;
732
733 /* Turn it off if we're using the main output mixer */
734 if (ucontrol->value.integer.value[0] == 0) {
735 if (wm8993->class_w_users == 0) {
736 dev_dbg(codec->dev, "Disabling Class W\n");
737 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
738 WM8993_CP_DYN_FREQ |
739 WM8993_CP_DYN_V,
740 0);
741 }
742 wm8993->class_w_users++;
743 wm8993->hubs_data.class_w = true;
744 }
745
746 /* Implement the change */
747 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
748
749 /* Enable it if we're using the direct DAC path */
750 if (ucontrol->value.integer.value[0] == 1) {
751 if (wm8993->class_w_users == 1) {
752 dev_dbg(codec->dev, "Enabling Class W\n");
753 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
754 WM8993_CP_DYN_FREQ |
755 WM8993_CP_DYN_V,
756 WM8993_CP_DYN_FREQ |
757 WM8993_CP_DYN_V);
758 }
759 wm8993->class_w_users--;
760 wm8993->hubs_data.class_w = false;
761 }
762
763 dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
764 wm8993->class_w_users);
765
766 return ret;
767 }
768
769 #define SOC_DAPM_ENUM_W(xname, xenum) \
770 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
771 .info = snd_soc_info_enum_double, \
772 .get = snd_soc_dapm_get_enum_double, \
773 .put = class_w_put, \
774 .private_value = (unsigned long)&xenum }
775
776 static const char *hp_mux_text[] = {
777 "Mixer",
778 "DAC",
779 };
780
781 static const struct soc_enum hpl_enum =
782 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
783
784 static const struct snd_kcontrol_new hpl_mux =
785 SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
786
787 static const struct soc_enum hpr_enum =
788 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
789
790 static const struct snd_kcontrol_new hpr_mux =
791 SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
792
793 static const struct snd_kcontrol_new left_speaker_mixer[] = {
794 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
795 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
796 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
797 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
798 };
799
800 static const struct snd_kcontrol_new right_speaker_mixer[] = {
801 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
802 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
803 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
804 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
805 };
806
807 static const char *aif_text[] = {
808 "Left", "Right"
809 };
810
811 static const struct soc_enum aifoutl_enum =
812 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text);
813
814 static const struct snd_kcontrol_new aifoutl_mux =
815 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
816
817 static const struct soc_enum aifoutr_enum =
818 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text);
819
820 static const struct snd_kcontrol_new aifoutr_mux =
821 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
822
823 static const struct soc_enum aifinl_enum =
824 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text);
825
826 static const struct snd_kcontrol_new aifinl_mux =
827 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
828
829 static const struct soc_enum aifinr_enum =
830 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text);
831
832 static const struct snd_kcontrol_new aifinr_mux =
833 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
834
835 static const char *sidetone_text[] = {
836 "None", "Left", "Right"
837 };
838
839 static const struct soc_enum sidetonel_enum =
840 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text);
841
842 static const struct snd_kcontrol_new sidetonel_mux =
843 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
844
845 static const struct soc_enum sidetoner_enum =
846 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text);
847
848 static const struct snd_kcontrol_new sidetoner_mux =
849 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
850
851 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
852 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
853 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
854 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
855 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
856 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
857
858 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
859 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
860
861 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
862 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
863
864 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
865 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
866
867 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
868 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
869
870 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
871 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
872
873 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
874 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
875
876 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
877 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
878
879 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
880 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
881
882 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
883 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
884 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
885 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
886 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
887 };
888
889 static const struct snd_soc_dapm_route routes[] = {
890 { "MICBIAS1", NULL, "VMID" },
891 { "MICBIAS2", NULL, "VMID" },
892
893 { "ADCL", NULL, "CLK_SYS" },
894 { "ADCL", NULL, "CLK_DSP" },
895 { "ADCR", NULL, "CLK_SYS" },
896 { "ADCR", NULL, "CLK_DSP" },
897
898 { "AIFOUTL Mux", "Left", "ADCL" },
899 { "AIFOUTL Mux", "Right", "ADCR" },
900 { "AIFOUTR Mux", "Left", "ADCL" },
901 { "AIFOUTR Mux", "Right", "ADCR" },
902
903 { "AIFOUTL", NULL, "AIFOUTL Mux" },
904 { "AIFOUTR", NULL, "AIFOUTR Mux" },
905
906 { "DACL Mux", "Left", "AIFINL" },
907 { "DACL Mux", "Right", "AIFINR" },
908 { "DACR Mux", "Left", "AIFINL" },
909 { "DACR Mux", "Right", "AIFINR" },
910
911 { "DACL Sidetone", "Left", "ADCL" },
912 { "DACL Sidetone", "Right", "ADCR" },
913 { "DACR Sidetone", "Left", "ADCL" },
914 { "DACR Sidetone", "Right", "ADCR" },
915
916 { "DACL", NULL, "CLK_SYS" },
917 { "DACL", NULL, "CLK_DSP" },
918 { "DACL", NULL, "DACL Mux" },
919 { "DACL", NULL, "DACL Sidetone" },
920 { "DACR", NULL, "CLK_SYS" },
921 { "DACR", NULL, "CLK_DSP" },
922 { "DACR", NULL, "DACR Mux" },
923 { "DACR", NULL, "DACR Sidetone" },
924
925 { "Left Output Mixer", "DAC Switch", "DACL" },
926
927 { "Right Output Mixer", "DAC Switch", "DACR" },
928
929 { "Left Output PGA", NULL, "CLK_SYS" },
930
931 { "Right Output PGA", NULL, "CLK_SYS" },
932
933 { "SPKL", "DAC Switch", "DACL" },
934 { "SPKL", NULL, "CLK_SYS" },
935
936 { "SPKR", "DAC Switch", "DACR" },
937 { "SPKR", NULL, "CLK_SYS" },
938
939 { "Left Headphone Mux", "DAC", "DACL" },
940 { "Right Headphone Mux", "DAC", "DACR" },
941 };
942
943 static int wm8993_set_bias_level(struct snd_soc_codec *codec,
944 enum snd_soc_bias_level level)
945 {
946 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
947 int ret;
948
949 switch (level) {
950 case SND_SOC_BIAS_ON:
951 case SND_SOC_BIAS_PREPARE:
952 /* VMID=2*40k */
953 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
954 WM8993_VMID_SEL_MASK, 0x2);
955 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
956 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
957 break;
958
959 case SND_SOC_BIAS_STANDBY:
960 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
961 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
962 wm8993->supplies);
963 if (ret != 0)
964 return ret;
965
966 snd_soc_cache_sync(codec);
967
968 /* Tune DC servo configuration */
969 snd_soc_write(codec, 0x44, 3);
970 snd_soc_write(codec, 0x56, 3);
971 snd_soc_write(codec, 0x44, 0);
972
973 /* Bring up VMID with fast soft start */
974 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
975 WM8993_STARTUP_BIAS_ENA |
976 WM8993_VMID_BUF_ENA |
977 WM8993_VMID_RAMP_MASK |
978 WM8993_BIAS_SRC,
979 WM8993_STARTUP_BIAS_ENA |
980 WM8993_VMID_BUF_ENA |
981 WM8993_VMID_RAMP_MASK |
982 WM8993_BIAS_SRC);
983
984 /* If either line output is single ended we
985 * need the VMID buffer */
986 if (!wm8993->pdata.lineout1_diff ||
987 !wm8993->pdata.lineout2_diff)
988 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
989 WM8993_LINEOUT_VMID_BUF_ENA,
990 WM8993_LINEOUT_VMID_BUF_ENA);
991
992 /* VMID=2*40k */
993 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
994 WM8993_VMID_SEL_MASK |
995 WM8993_BIAS_ENA,
996 WM8993_BIAS_ENA | 0x2);
997 msleep(32);
998
999 /* Switch to normal bias */
1000 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1001 WM8993_BIAS_SRC |
1002 WM8993_STARTUP_BIAS_ENA, 0);
1003 }
1004
1005 /* VMID=2*240k */
1006 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1007 WM8993_VMID_SEL_MASK, 0x4);
1008
1009 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1010 WM8993_TSHUT_ENA, 0);
1011 break;
1012
1013 case SND_SOC_BIAS_OFF:
1014 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1015 WM8993_LINEOUT_VMID_BUF_ENA, 0);
1016
1017 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1018 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1019 0);
1020
1021 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1022 WM8993_STARTUP_BIAS_ENA |
1023 WM8993_VMID_BUF_ENA |
1024 WM8993_VMID_RAMP_MASK |
1025 WM8993_BIAS_SRC, 0);
1026
1027 #ifdef CONFIG_REGULATOR
1028 /* Post 2.6.34 we will be able to get a callback when
1029 * the regulators are disabled which we can use but
1030 * for now just assume that the power will be cut if
1031 * the regulator API is in use.
1032 */
1033 codec->cache_sync = 1;
1034 #endif
1035
1036 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
1037 wm8993->supplies);
1038 break;
1039 }
1040
1041 codec->dapm.bias_level = level;
1042
1043 return 0;
1044 }
1045
1046 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1047 int clk_id, unsigned int freq, int dir)
1048 {
1049 struct snd_soc_codec *codec = codec_dai->codec;
1050 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1051
1052 switch (clk_id) {
1053 case WM8993_SYSCLK_MCLK:
1054 wm8993->mclk_rate = freq;
1055 case WM8993_SYSCLK_FLL:
1056 wm8993->sysclk_source = clk_id;
1057 break;
1058
1059 default:
1060 return -EINVAL;
1061 }
1062
1063 return 0;
1064 }
1065
1066 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1067 unsigned int fmt)
1068 {
1069 struct snd_soc_codec *codec = dai->codec;
1070 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1071 unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1072 unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1073
1074 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1075 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1076 aif4 &= ~WM8993_LRCLK_DIR;
1077
1078 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1079 case SND_SOC_DAIFMT_CBS_CFS:
1080 wm8993->master = 0;
1081 break;
1082 case SND_SOC_DAIFMT_CBS_CFM:
1083 aif4 |= WM8993_LRCLK_DIR;
1084 wm8993->master = 1;
1085 break;
1086 case SND_SOC_DAIFMT_CBM_CFS:
1087 aif1 |= WM8993_BCLK_DIR;
1088 wm8993->master = 1;
1089 break;
1090 case SND_SOC_DAIFMT_CBM_CFM:
1091 aif1 |= WM8993_BCLK_DIR;
1092 aif4 |= WM8993_LRCLK_DIR;
1093 wm8993->master = 1;
1094 break;
1095 default:
1096 return -EINVAL;
1097 }
1098
1099 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1100 case SND_SOC_DAIFMT_DSP_B:
1101 aif1 |= WM8993_AIF_LRCLK_INV;
1102 case SND_SOC_DAIFMT_DSP_A:
1103 aif1 |= 0x18;
1104 break;
1105 case SND_SOC_DAIFMT_I2S:
1106 aif1 |= 0x10;
1107 break;
1108 case SND_SOC_DAIFMT_RIGHT_J:
1109 break;
1110 case SND_SOC_DAIFMT_LEFT_J:
1111 aif1 |= 0x8;
1112 break;
1113 default:
1114 return -EINVAL;
1115 }
1116
1117 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1118 case SND_SOC_DAIFMT_DSP_A:
1119 case SND_SOC_DAIFMT_DSP_B:
1120 /* frame inversion not valid for DSP modes */
1121 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1122 case SND_SOC_DAIFMT_NB_NF:
1123 break;
1124 case SND_SOC_DAIFMT_IB_NF:
1125 aif1 |= WM8993_AIF_BCLK_INV;
1126 break;
1127 default:
1128 return -EINVAL;
1129 }
1130 break;
1131
1132 case SND_SOC_DAIFMT_I2S:
1133 case SND_SOC_DAIFMT_RIGHT_J:
1134 case SND_SOC_DAIFMT_LEFT_J:
1135 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1136 case SND_SOC_DAIFMT_NB_NF:
1137 break;
1138 case SND_SOC_DAIFMT_IB_IF:
1139 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1140 break;
1141 case SND_SOC_DAIFMT_IB_NF:
1142 aif1 |= WM8993_AIF_BCLK_INV;
1143 break;
1144 case SND_SOC_DAIFMT_NB_IF:
1145 aif1 |= WM8993_AIF_LRCLK_INV;
1146 break;
1147 default:
1148 return -EINVAL;
1149 }
1150 break;
1151 default:
1152 return -EINVAL;
1153 }
1154
1155 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1156 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1157
1158 return 0;
1159 }
1160
1161 static int wm8993_hw_params(struct snd_pcm_substream *substream,
1162 struct snd_pcm_hw_params *params,
1163 struct snd_soc_dai *dai)
1164 {
1165 struct snd_soc_codec *codec = dai->codec;
1166 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1167 int ret, i, best, best_val, cur_val;
1168 unsigned int clocking1, clocking3, aif1, aif4;
1169
1170 clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1);
1171 clocking1 &= ~WM8993_BCLK_DIV_MASK;
1172
1173 clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3);
1174 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1175
1176 aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1177 aif1 &= ~WM8993_AIF_WL_MASK;
1178
1179 aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1180 aif4 &= ~WM8993_LRCLK_RATE_MASK;
1181
1182 /* What BCLK do we need? */
1183 wm8993->fs = params_rate(params);
1184 wm8993->bclk = 2 * wm8993->fs;
1185 if (wm8993->tdm_slots) {
1186 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1187 wm8993->tdm_slots, wm8993->tdm_width);
1188 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1189 } else {
1190 switch (params_format(params)) {
1191 case SNDRV_PCM_FORMAT_S16_LE:
1192 wm8993->bclk *= 16;
1193 break;
1194 case SNDRV_PCM_FORMAT_S20_3LE:
1195 wm8993->bclk *= 20;
1196 aif1 |= 0x8;
1197 break;
1198 case SNDRV_PCM_FORMAT_S24_LE:
1199 wm8993->bclk *= 24;
1200 aif1 |= 0x10;
1201 break;
1202 case SNDRV_PCM_FORMAT_S32_LE:
1203 wm8993->bclk *= 32;
1204 aif1 |= 0x18;
1205 break;
1206 default:
1207 return -EINVAL;
1208 }
1209 }
1210
1211 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1212
1213 ret = configure_clock(codec);
1214 if (ret != 0)
1215 return ret;
1216
1217 /* Select nearest CLK_SYS_RATE */
1218 best = 0;
1219 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1220 - wm8993->fs);
1221 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1222 cur_val = abs((wm8993->sysclk_rate /
1223 clk_sys_rates[i].ratio) - wm8993->fs);
1224 if (cur_val < best_val) {
1225 best = i;
1226 best_val = cur_val;
1227 }
1228 }
1229 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1230 clk_sys_rates[best].ratio);
1231 clocking3 |= (clk_sys_rates[best].clk_sys_rate
1232 << WM8993_CLK_SYS_RATE_SHIFT);
1233
1234 /* SAMPLE_RATE */
1235 best = 0;
1236 best_val = abs(wm8993->fs - sample_rates[0].rate);
1237 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1238 /* Closest match */
1239 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1240 if (cur_val < best_val) {
1241 best = i;
1242 best_val = cur_val;
1243 }
1244 }
1245 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1246 sample_rates[best].rate);
1247 clocking3 |= (sample_rates[best].sample_rate
1248 << WM8993_SAMPLE_RATE_SHIFT);
1249
1250 /* BCLK_DIV */
1251 best = 0;
1252 best_val = INT_MAX;
1253 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1254 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1255 - wm8993->bclk;
1256 if (cur_val < 0) /* Table is sorted */
1257 break;
1258 if (cur_val < best_val) {
1259 best = i;
1260 best_val = cur_val;
1261 }
1262 }
1263 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1264 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1265 bclk_divs[best].div, wm8993->bclk);
1266 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1267
1268 /* LRCLK is a simple fraction of BCLK */
1269 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1270 aif4 |= wm8993->bclk / wm8993->fs;
1271
1272 snd_soc_write(codec, WM8993_CLOCKING_1, clocking1);
1273 snd_soc_write(codec, WM8993_CLOCKING_3, clocking3);
1274 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1275 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1276
1277 /* ReTune Mobile? */
1278 if (wm8993->pdata.num_retune_configs) {
1279 u16 eq1 = snd_soc_read(codec, WM8993_EQ1);
1280 struct wm8993_retune_mobile_setting *s;
1281
1282 best = 0;
1283 best_val = abs(wm8993->pdata.retune_configs[0].rate
1284 - wm8993->fs);
1285 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1286 cur_val = abs(wm8993->pdata.retune_configs[i].rate
1287 - wm8993->fs);
1288 if (cur_val < best_val) {
1289 best_val = cur_val;
1290 best = i;
1291 }
1292 }
1293 s = &wm8993->pdata.retune_configs[best];
1294
1295 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1296 s->name, s->rate);
1297
1298 /* Disable EQ while we reconfigure */
1299 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1300
1301 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1302 snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]);
1303
1304 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1305 }
1306
1307 return 0;
1308 }
1309
1310 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1311 {
1312 struct snd_soc_codec *codec = codec_dai->codec;
1313 unsigned int reg;
1314
1315 reg = snd_soc_read(codec, WM8993_DAC_CTRL);
1316
1317 if (mute)
1318 reg |= WM8993_DAC_MUTE;
1319 else
1320 reg &= ~WM8993_DAC_MUTE;
1321
1322 snd_soc_write(codec, WM8993_DAC_CTRL, reg);
1323
1324 return 0;
1325 }
1326
1327 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1328 unsigned int rx_mask, int slots, int slot_width)
1329 {
1330 struct snd_soc_codec *codec = dai->codec;
1331 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1332 int aif1 = 0;
1333 int aif2 = 0;
1334
1335 /* Don't need to validate anything if we're turning off TDM */
1336 if (slots == 0) {
1337 wm8993->tdm_slots = 0;
1338 goto out;
1339 }
1340
1341 /* Note that we allow configurations we can't handle ourselves -
1342 * for example, we can generate clocks for slots 2 and up even if
1343 * we can't use those slots ourselves.
1344 */
1345 aif1 |= WM8993_AIFADC_TDM;
1346 aif2 |= WM8993_AIFDAC_TDM;
1347
1348 switch (rx_mask) {
1349 case 3:
1350 break;
1351 case 0xc:
1352 aif1 |= WM8993_AIFADC_TDM_CHAN;
1353 break;
1354 default:
1355 return -EINVAL;
1356 }
1357
1358
1359 switch (tx_mask) {
1360 case 3:
1361 break;
1362 case 0xc:
1363 aif2 |= WM8993_AIFDAC_TDM_CHAN;
1364 break;
1365 default:
1366 return -EINVAL;
1367 }
1368
1369 out:
1370 wm8993->tdm_width = slot_width;
1371 wm8993->tdm_slots = slots / 2;
1372
1373 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1,
1374 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1375 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2,
1376 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1377
1378 return 0;
1379 }
1380
1381 static const struct snd_soc_dai_ops wm8993_ops = {
1382 .set_sysclk = wm8993_set_sysclk,
1383 .set_fmt = wm8993_set_dai_fmt,
1384 .hw_params = wm8993_hw_params,
1385 .digital_mute = wm8993_digital_mute,
1386 .set_pll = wm8993_set_fll,
1387 .set_tdm_slot = wm8993_set_tdm_slot,
1388 };
1389
1390 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1391
1392 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1393 SNDRV_PCM_FMTBIT_S20_3LE |\
1394 SNDRV_PCM_FMTBIT_S24_LE |\
1395 SNDRV_PCM_FMTBIT_S32_LE)
1396
1397 static struct snd_soc_dai_driver wm8993_dai = {
1398 .name = "wm8993-hifi",
1399 .playback = {
1400 .stream_name = "Playback",
1401 .channels_min = 1,
1402 .channels_max = 2,
1403 .rates = WM8993_RATES,
1404 .formats = WM8993_FORMATS,
1405 },
1406 .capture = {
1407 .stream_name = "Capture",
1408 .channels_min = 1,
1409 .channels_max = 2,
1410 .rates = WM8993_RATES,
1411 .formats = WM8993_FORMATS,
1412 },
1413 .ops = &wm8993_ops,
1414 .symmetric_rates = 1,
1415 };
1416
1417 static int wm8993_probe(struct snd_soc_codec *codec)
1418 {
1419 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1420 struct snd_soc_dapm_context *dapm = &codec->dapm;
1421 int ret, i, val;
1422
1423 wm8993->hubs_data.hp_startup_mode = 1;
1424 wm8993->hubs_data.dcs_codes_l = -2;
1425 wm8993->hubs_data.dcs_codes_r = -2;
1426 wm8993->hubs_data.series_startup = 1;
1427
1428 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1429 if (ret != 0) {
1430 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1431 return ret;
1432 }
1433
1434 for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1435 wm8993->supplies[i].supply = wm8993_supply_names[i];
1436
1437 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8993->supplies),
1438 wm8993->supplies);
1439 if (ret != 0) {
1440 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1441 return ret;
1442 }
1443
1444 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1445 wm8993->supplies);
1446 if (ret != 0) {
1447 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1448 goto err_get;
1449 }
1450
1451 val = snd_soc_read(codec, WM8993_SOFTWARE_RESET);
1452 if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
1453 dev_err(codec->dev, "Invalid ID register value %x\n", val);
1454 ret = -EINVAL;
1455 goto err_enable;
1456 }
1457
1458 ret = snd_soc_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
1459 if (ret != 0)
1460 goto err_enable;
1461
1462 codec->cache_only = 1;
1463
1464 /* By default we're using the output mixers */
1465 wm8993->class_w_users = 2;
1466
1467 /* Latch volume update bits and default ZC on */
1468 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1469 WM8993_DAC_VU, WM8993_DAC_VU);
1470 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1471 WM8993_ADC_VU, WM8993_ADC_VU);
1472
1473 /* Manualy manage the HPOUT sequencing for independent stereo
1474 * control. */
1475 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
1476 WM8993_HPOUT1_AUTO_PU, 0);
1477
1478 /* Use automatic clock configuration */
1479 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1480
1481 wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
1482 wm8993->pdata.lineout2_diff,
1483 wm8993->pdata.lineout1fb,
1484 wm8993->pdata.lineout2fb,
1485 wm8993->pdata.jd_scthr,
1486 wm8993->pdata.jd_thr,
1487 wm8993->pdata.micbias1_lvl,
1488 wm8993->pdata.micbias2_lvl);
1489
1490 ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1491 if (ret != 0)
1492 goto err_enable;
1493
1494 snd_soc_add_controls(codec, wm8993_snd_controls,
1495 ARRAY_SIZE(wm8993_snd_controls));
1496 if (wm8993->pdata.num_retune_configs != 0) {
1497 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1498 } else {
1499 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1500 snd_soc_add_controls(codec, wm8993_eq_controls,
1501 ARRAY_SIZE(wm8993_eq_controls));
1502 }
1503
1504 snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
1505 ARRAY_SIZE(wm8993_dapm_widgets));
1506 wm_hubs_add_analogue_controls(codec);
1507
1508 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1509 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1510 wm8993->pdata.lineout2_diff);
1511
1512 return 0;
1513
1514 err_enable:
1515 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1516 err_get:
1517 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1518 return ret;
1519 }
1520
1521 static int wm8993_remove(struct snd_soc_codec *codec)
1522 {
1523 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1524
1525 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1526 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1527 return 0;
1528 }
1529
1530 #ifdef CONFIG_PM
1531 static int wm8993_suspend(struct snd_soc_codec *codec)
1532 {
1533 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1534 int fll_fout = wm8993->fll_fout;
1535 int fll_fref = wm8993->fll_fref;
1536 int ret;
1537
1538 /* Stop the FLL in an orderly fashion */
1539 ret = _wm8993_set_fll(codec, 0, 0, 0, 0);
1540 if (ret != 0) {
1541 dev_err(codec->dev, "Failed to stop FLL\n");
1542 return ret;
1543 }
1544
1545 wm8993->fll_fout = fll_fout;
1546 wm8993->fll_fref = fll_fref;
1547
1548 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1549
1550 return 0;
1551 }
1552
1553 static int wm8993_resume(struct snd_soc_codec *codec)
1554 {
1555 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1556 int ret;
1557
1558 wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1559
1560 /* Restart the FLL? */
1561 if (wm8993->fll_fout) {
1562 int fll_fout = wm8993->fll_fout;
1563 int fll_fref = wm8993->fll_fref;
1564
1565 wm8993->fll_fref = 0;
1566 wm8993->fll_fout = 0;
1567
1568 ret = _wm8993_set_fll(codec, 0, wm8993->fll_src,
1569 fll_fref, fll_fout);
1570 if (ret != 0)
1571 dev_err(codec->dev, "Failed to restart FLL\n");
1572 }
1573
1574 return 0;
1575 }
1576 #else
1577 #define wm8993_suspend NULL
1578 #define wm8993_resume NULL
1579 #endif
1580
1581 static struct snd_soc_codec_driver soc_codec_dev_wm8993 = {
1582 .probe = wm8993_probe,
1583 .remove = wm8993_remove,
1584 .suspend = wm8993_suspend,
1585 .resume = wm8993_resume,
1586 .set_bias_level = wm8993_set_bias_level,
1587 .reg_cache_size = ARRAY_SIZE(wm8993_reg_defaults),
1588 .reg_word_size = sizeof(u16),
1589 .reg_cache_default = wm8993_reg_defaults,
1590 .volatile_register = wm8993_volatile,
1591 };
1592
1593 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1594 static __devinit int wm8993_i2c_probe(struct i2c_client *i2c,
1595 const struct i2c_device_id *id)
1596 {
1597 struct wm8993_priv *wm8993;
1598 int ret;
1599
1600 wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv),
1601 GFP_KERNEL);
1602 if (wm8993 == NULL)
1603 return -ENOMEM;
1604
1605 i2c_set_clientdata(i2c, wm8993);
1606
1607 ret = snd_soc_register_codec(&i2c->dev,
1608 &soc_codec_dev_wm8993, &wm8993_dai, 1);
1609 return ret;
1610 }
1611
1612 static __devexit int wm8993_i2c_remove(struct i2c_client *client)
1613 {
1614 snd_soc_unregister_codec(&client->dev);
1615 kfree(i2c_get_clientdata(client));
1616 return 0;
1617 }
1618
1619 static const struct i2c_device_id wm8993_i2c_id[] = {
1620 { "wm8993", 0 },
1621 { }
1622 };
1623 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1624
1625 static struct i2c_driver wm8993_i2c_driver = {
1626 .driver = {
1627 .name = "wm8993",
1628 .owner = THIS_MODULE,
1629 },
1630 .probe = wm8993_i2c_probe,
1631 .remove = __devexit_p(wm8993_i2c_remove),
1632 .id_table = wm8993_i2c_id,
1633 };
1634 #endif
1635
1636 static int __init wm8993_modinit(void)
1637 {
1638 int ret = 0;
1639 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1640 ret = i2c_add_driver(&wm8993_i2c_driver);
1641 if (ret != 0) {
1642 pr_err("WM8993: Unable to register I2C driver: %d\n",
1643 ret);
1644 }
1645 #endif
1646 return ret;
1647 }
1648 module_init(wm8993_modinit);
1649
1650 static void __exit wm8993_exit(void)
1651 {
1652 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1653 i2c_del_driver(&wm8993_i2c_driver);
1654 #endif
1655 }
1656 module_exit(wm8993_exit);
1657
1658
1659 MODULE_DESCRIPTION("ASoC WM8993 driver");
1660 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1661 MODULE_LICENSE("GPL");