arch/x86/include/asm/mpspec_def.h

   1 #ifndef _ASM_X86_MPSPEC_DEF_H
   2 #define _ASM_X86_MPSPEC_DEF_H
   3
   4 /*
   5  * Structure definitions for SMP machines following the
   6  * Intel Multiprocessing Specification 1.1 and 1.4.
   7  */
   8
   9 /*
  10  * This tag identifies where the SMP configuration
  11  * information is.
  12  */
  13
  14 #define SMP_MAGIC_IDENT (('_'<<24) | ('P'<<16) | ('M'<<8) | '_')
  15
  16 #ifdef CONFIG_X86_32
  17 # define MAX_MPC_ENTRY 1024
  18 #endif
  19
  20 /* Intel MP Floating Pointer Structure */
  21 struct mpf_intel {
  22         char signature[4];              /* "_MP_"                       */
  23         unsigned int physptr;           /* Configuration table address  */
  24         unsigned char length;           /* Our length (paragraphs)      */
  25         unsigned char specification;    /* Specification version        */
  26         unsigned char checksum;         /* Checksum (makes sum 0)       */
  27         unsigned char feature1;         /* Standard or configuration ?  */
  28         unsigned char feature2;         /* Bit7 set for IMCR|PIC        */
  29         unsigned char feature3;         /* Unused (0)                   */
  30         unsigned char feature4;         /* Unused (0)                   */
  31         unsigned char feature5;         /* Unused (0)                   */
  32 };
  33
  34 #define MPC_SIGNATURE "PCMP"
  35
  36 struct mpc_table {
  37         char signature[4];
  38         unsigned short length;          /* Size of table */
  39         char spec;                      /* 0x01 */
  40         char checksum;
  41         char oem[8];
  42         char productid[12];
  43         unsigned int oemptr;            /* 0 if not present */
  44         unsigned short oemsize;         /* 0 if not present */
  45         unsigned short oemcount;
  46         unsigned int lapic;             /* APIC address */
  47         unsigned int reserved;
  48 };
  49
  50 /* Followed by entries */
  51
  52 #define MP_PROCESSOR            0
  53 #define MP_BUS                  1
  54 #define MP_IOAPIC               2
  55 #define MP_INTSRC               3
  56 #define MP_LINTSRC              4
  57 /* Used by IBM NUMA-Q to describe node locality */
  58 #define MP_TRANSLATION          192
  59
  60 #define CPU_ENABLED             1       /* Processor is available */
  61 #define CPU_BOOTPROCESSOR       2       /* Processor is the BP */
  62
  63 #define CPU_STEPPING_MASK       0x000F
  64 #define CPU_MODEL_MASK          0x00F0
  65 #define CPU_FAMILY_MASK         0x0F00
  66
  67 struct mpc_cpu {
  68         unsigned char type;
  69         unsigned char apicid;           /* Local APIC number */
  70         unsigned char apicver;          /* Its versions */
  71         unsigned char cpuflag;
  72         unsigned int cpufeature;
  73         unsigned int featureflag;       /* CPUID feature value */
  74         unsigned int reserved[2];
  75 };
  76
  77 struct mpc_bus {
  78         unsigned char type;
  79         unsigned char busid;
  80         unsigned char bustype[6];
  81 };
  82
  83 /* List of Bus Type string values, Intel MP Spec. */
  84 #define BUSTYPE_EISA    "EISA"
  85 #define BUSTYPE_ISA     "ISA"
  86 #define BUSTYPE_INTERN  "INTERN"        /* Internal BUS */
  87 #define BUSTYPE_MCA     "MCA"
  88 #define BUSTYPE_VL      "VL"            /* Local bus */
  89 #define BUSTYPE_PCI     "PCI"
  90 #define BUSTYPE_PCMCIA  "PCMCIA"
  91 #define BUSTYPE_CBUS    "CBUS"
  92 #define BUSTYPE_CBUSII  "CBUSII"
  93 #define BUSTYPE_FUTURE  "FUTURE"
  94 #define BUSTYPE_MBI     "MBI"
  95 #define BUSTYPE_MBII    "MBII"
  96 #define BUSTYPE_MPI     "MPI"
  97 #define BUSTYPE_MPSA    "MPSA"
  98 #define BUSTYPE_NUBUS   "NUBUS"
  99 #define BUSTYPE_TC      "TC"
 100 #define BUSTYPE_VME     "VME"
 101 #define BUSTYPE_XPRESS  "XPRESS"
 102
 103 #define MPC_APIC_USABLE         0x01
 104
 105 struct mpc_ioapic {
 106         unsigned char type;
 107         unsigned char apicid;
 108         unsigned char apicver;
 109         unsigned char flags;
 110         unsigned int apicaddr;
 111 };
 112
 113 struct mpc_intsrc {
 114         unsigned char type;
 115         unsigned char irqtype;
 116         unsigned short irqflag;
 117         unsigned char srcbus;
 118         unsigned char srcbusirq;
 119         unsigned char dstapic;
 120         unsigned char dstirq;
 121 };
 122
 123 enum mp_irq_source_types {
 124         mp_INT = 0,
 125         mp_NMI = 1,
 126         mp_SMI = 2,
 127         mp_ExtINT = 3
 128 };
 129
 130 #define MP_IRQDIR_DEFAULT       0
 131 #define MP_IRQDIR_HIGH          1
 132 #define MP_IRQDIR_LOW           3
 133
 134 #define MP_APIC_ALL     0xFF
 135
 136 struct mpc_lintsrc {
 137         unsigned char type;
 138         unsigned char irqtype;
 139         unsigned short irqflag;
 140         unsigned char srcbusid;
 141         unsigned char srcbusirq;
 142         unsigned char destapic;
 143         unsigned char destapiclint;
 144 };
 145
 146 #define MPC_OEM_SIGNATURE "_OEM"
 147
 148 struct mpc_oemtable {
 149         char signature[4];
 150         unsigned short length;          /* Size of table */
 151         char  rev;                      /* 0x01 */
 152         char  checksum;
 153         char  mpc[8];
 154 };
 155
 156 /*
 157  *      Default configurations
 158  *
 159  *      1       2 CPU ISA 82489DX
 160  *      2       2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
 161  *      3       2 CPU EISA 82489DX
 162  *      4       2 CPU MCA 82489DX
 163  *      5       2 CPU ISA+PCI
 164  *      6       2 CPU EISA+PCI
 165  *      7       2 CPU MCA+PCI
 166  */
 167
 168 enum mp_bustype {
 169         MP_BUS_ISA = 1,
 170         MP_BUS_EISA,
 171         MP_BUS_PCI,
 172         MP_BUS_MCA,
 173 };
 174 #endif /* _ASM_X86_MPSPEC_DEF_H */