arch/x86/include/asm/pci_x86.h

   1 /*
   2  *      Low-Level PCI Access for i386 machines.
   3  *
   4  *      (c) 1999 Martin Mares <mj@ucw.cz>
   5  */
   6
   7 #undef DEBUG
   8
   9 #ifdef DEBUG
  10 #define DBG(x...) printk(x)
  11 #else
  12 #define DBG(x...)
  13 #endif
  14
  15 #define PCI_PROBE_BIOS          0x0001
  16 #define PCI_PROBE_CONF1         0x0002
  17 #define PCI_PROBE_CONF2         0x0004
  18 #define PCI_PROBE_MMCONF        0x0008
  19 #define PCI_PROBE_MASK          0x000f
  20 #define PCI_PROBE_NOEARLY       0x0010
  21
  22 #define PCI_NO_CHECKS           0x0400
  23 #define PCI_USE_PIRQ_MASK       0x0800
  24 #define PCI_ASSIGN_ROMS         0x1000
  25 #define PCI_BIOS_IRQ_SCAN       0x2000
  26 #define PCI_ASSIGN_ALL_BUSSES   0x4000
  27 #define PCI_CAN_SKIP_ISA_ALIGN  0x8000
  28 #define PCI_USE__CRS            0x10000
  29 #define PCI_CHECK_ENABLE_AMD_MMCONF     0x20000
  30 #define PCI_HAS_IO_ECS          0x40000
  31 #define PCI_NOASSIGN_ROMS       0x80000
  32 #define PCI_ROOT_NO_CRS         0x100000
  33 #define PCI_NOASSIGN_BARS       0x200000
  34
  35 extern unsigned int pci_probe;
  36 extern unsigned long pirq_table_addr;
  37
  38 enum pci_bf_sort_state {
  39         pci_bf_sort_default,
  40         pci_force_nobf,
  41         pci_force_bf,
  42         pci_dmi_bf,
  43 };
  44
  45 /* pci-i386.c */
  46
  47 extern unsigned int pcibios_max_latency;
  48
  49 void pcibios_resource_survey(void);
  50 void pcibios_set_cache_line_size(void);
  51
  52 /* pci-pc.c */
  53
  54 extern int pcibios_last_bus;
  55 extern struct pci_bus *pci_root_bus;
  56 extern struct pci_ops pci_root_ops;
  57
  58 void pcibios_scan_specific_bus(int busn);
  59
  60 /* pci-irq.c */
  61
  62 struct irq_info {
  63         u8 bus, devfn;                  /* Bus, device and function */
  64         struct {
  65                 u8 link;                /* IRQ line ID, chipset dependent,
  66                                            0 = not routed */
  67                 u16 bitmap;             /* Available IRQs */
  68         } __attribute__((packed)) irq[4];
  69         u8 slot;                        /* Slot number, 0=onboard */
  70         u8 rfu;
  71 } __attribute__((packed));
  72
  73 struct irq_routing_table {
  74         u32 signature;                  /* PIRQ_SIGNATURE should be here */
  75         u16 version;                    /* PIRQ_VERSION */
  76         u16 size;                       /* Table size in bytes */
  77         u8 rtr_bus, rtr_devfn;          /* Where the interrupt router lies */
  78         u16 exclusive_irqs;             /* IRQs devoted exclusively to
  79                                            PCI usage */
  80         u16 rtr_vendor, rtr_device;     /* Vendor and device ID of
  81                                            interrupt router */
  82         u32 miniport_data;              /* Crap */
  83         u8 rfu[11];
  84         u8 checksum;                    /* Modulo 256 checksum must give 0 */
  85         struct irq_info slots[0];
  86 } __attribute__((packed));
  87
  88 extern unsigned int pcibios_irq_mask;
  89
  90 extern raw_spinlock_t pci_config_lock;
  91
  92 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
  93 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
  94
  95 struct pci_raw_ops {
  96         int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
  97                                                 int reg, int len, u32 *val);
  98         int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
  99                                                 int reg, int len, u32 val);
 100 };
 101
 102 extern const struct pci_raw_ops *raw_pci_ops;
 103 extern const struct pci_raw_ops *raw_pci_ext_ops;
 104
 105 extern const struct pci_raw_ops pci_direct_conf1;
 106 extern bool port_cf9_safe;
 107
 108 /* arch_initcall level */
 109 extern int pci_direct_probe(void);
 110 extern void pci_direct_init(int type);
 111 extern void pci_pcbios_init(void);
 112 extern void __init dmi_check_pciprobe(void);
 113 extern void __init dmi_check_skip_isa_align(void);
 114
 115 /* some common used subsys_initcalls */
 116 extern int __init pci_acpi_init(void);
 117 extern void __init pcibios_irq_init(void);
 118 extern int __init pcibios_init(void);
 119 extern int pci_legacy_init(void);
 120 extern void pcibios_fixup_irqs(void);
 121
 122 /* pci-mmconfig.c */
 123
 124 /* "PCI MMCONFIG %04x [bus %02x-%02x]" */
 125 #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
 126
 127 struct pci_mmcfg_region {
 128         struct list_head list;
 129         struct resource res;
 130         u64 address;
 131         char __iomem *virt;
 132         u16 segment;
 133         u8 start_bus;
 134         u8 end_bus;
 135         char name[PCI_MMCFG_RESOURCE_NAME_LEN];
 136 };
 137
 138 extern int __init pci_mmcfg_arch_init(void);
 139 extern void __init pci_mmcfg_arch_free(void);
 140 extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
 141
 142 extern struct list_head pci_mmcfg_list;
 143
 144 #define PCI_MMCFG_BUS_OFFSET(bus)      ((bus) << 20)
 145
 146 /*
 147  * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
 148  * on their northbrige except through the * %eax register. As such, you MUST
 149  * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
 150  * accessor functions.
 151  * In fact just use pci_config_*, nothing else please.
 152  */
 153 static inline unsigned char mmio_config_readb(void __iomem *pos)
 154 {
 155         u8 val;
 156         asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
 157         return val;
 158 }
 159
 160 static inline unsigned short mmio_config_readw(void __iomem *pos)
 161 {
 162         u16 val;
 163         asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
 164         return val;
 165 }
 166
 167 static inline unsigned int mmio_config_readl(void __iomem *pos)
 168 {
 169         u32 val;
 170         asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
 171         return val;
 172 }
 173
 174 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
 175 {
 176         asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
 177 }
 178
 179 static inline void mmio_config_writew(void __iomem *pos, u16 val)
 180 {
 181         asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
 182 }
 183
 184 static inline void mmio_config_writel(void __iomem *pos, u32 val)
 185 {
 186         asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
 187 }
 188
 189 #ifdef CONFIG_PCI
 190 # ifdef CONFIG_ACPI
 191 #  define x86_default_pci_init          pci_acpi_init
 192 # else
 193 #  define x86_default_pci_init          pci_legacy_init
 194 # endif
 195 # define x86_default_pci_init_irq       pcibios_irq_init
 196 # define x86_default_pci_fixup_irqs     pcibios_fixup_irqs
 197 #else
 198 # define x86_default_pci_init           NULL
 199 # define x86_default_pci_init_irq       NULL
 200 # define x86_default_pci_fixup_irqs     NULL
 201 #endif