arch/x86/include/asm/spinlock.h

   1 #ifndef _ASM_X86_SPINLOCK_H
   2 #define _ASM_X86_SPINLOCK_H
   3
   4 #include <linux/atomic.h>
   5 #include <asm/page.h>
   6 #include <asm/processor.h>
   7 #include <linux/compiler.h>
   8 #include <asm/paravirt.h>
   9 /*
  10  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  11  *
  12  * Simple spin lock operations.  There are two variants, one clears IRQ's
  13  * on the local processor, one does not.
  14  *
  15  * These are fair FIFO ticket locks, which are currently limited to 256
  16  * CPUs.
  17  *
  18  * (the type definitions are in asm/spinlock_types.h)
  19  */
  20
  21 #ifdef CONFIG_X86_32
  22 # define LOCK_PTR_REG "a"
  23 # define REG_PTR_MODE "k"
  24 #else
  25 # define LOCK_PTR_REG "D"
  26 # define REG_PTR_MODE "q"
  27 #endif
  28
  29 #if defined(CONFIG_X86_32) && \
  30         (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
  31 /*
  32  * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
  33  * (PPro errata 66, 92)
  34  */
  35 # define UNLOCK_LOCK_PREFIX LOCK_PREFIX
  36 #else
  37 # define UNLOCK_LOCK_PREFIX
  38 #endif
  39
  40 /*
  41  * Ticket locks are conceptually two parts, one indicating the current head of
  42  * the queue, and the other indicating the current tail. The lock is acquired
  43  * by atomically noting the tail and incrementing it by one (thus adding
  44  * ourself to the queue and noting our position), then waiting until the head
  45  * becomes equal to the the initial value of the tail.
  46  *
  47  * We use an xadd covering *both* parts of the lock, to increment the tail and
  48  * also load the position of the head, which takes care of memory ordering
  49  * issues and should be optimal for the uncontended case. Note the tail must be
  50  * in the high part, because a wide xadd increment of the low part would carry
  51  * up and contaminate the high part.
  52  */
  53 static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
  54 {
  55         register struct __raw_tickets inc = { .tail = 1 };
  56
  57         inc = xadd(&lock->tickets, inc);
  58
  59         for (;;) {
  60                 if (inc.head == inc.tail)
  61                         break;
  62                 cpu_relax();
  63                 inc.head = ACCESS_ONCE(lock->tickets.head);
  64         }
  65         barrier();              /* make sure nothing creeps before the lock is taken */
  66 }
  67
  68 static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
  69 {
  70         arch_spinlock_t old, new;
  71
  72         old.tickets = ACCESS_ONCE(lock->tickets);
  73         if (old.tickets.head != old.tickets.tail)
  74                 return 0;
  75
  76         new.head_tail = old.head_tail + (1 << TICKET_SHIFT);
  77
  78         /* cmpxchg is a full barrier, so nothing can move before it */
  79         return cmpxchg(&lock->head_tail, old.head_tail, new.head_tail) == old.head_tail;
  80 }
  81
  82 #if (NR_CPUS < 256)
  83 static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
  84 {
  85         asm volatile(UNLOCK_LOCK_PREFIX "incb %0"
  86                      : "+m" (lock->head_tail)
  87                      :
  88                      : "memory", "cc");
  89 }
  90 #else
  91 static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
  92 {
  93         asm volatile(UNLOCK_LOCK_PREFIX "incw %0"
  94                      : "+m" (lock->head_tail)
  95                      :
  96                      : "memory", "cc");
  97 }
  98 #endif
  99
 100 static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
 101 {
 102         struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
 103
 104         return !!(tmp.tail ^ tmp.head);
 105 }
 106
 107 static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
 108 {
 109         struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
 110
 111         return ((tmp.tail - tmp.head) & TICKET_MASK) > 1;
 112 }
 113
 114 #ifndef CONFIG_PARAVIRT_SPINLOCKS
 115
 116 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 117 {
 118         return __ticket_spin_is_locked(lock);
 119 }
 120
 121 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 122 {
 123         return __ticket_spin_is_contended(lock);
 124 }
 125 #define arch_spin_is_contended  arch_spin_is_contended
 126
 127 static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
 128 {
 129         __ticket_spin_lock(lock);
 130 }
 131
 132 static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
 133 {
 134         return __ticket_spin_trylock(lock);
 135 }
 136
 137 static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
 138 {
 139         __ticket_spin_unlock(lock);
 140 }
 141
 142 static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
 143                                                   unsigned long flags)
 144 {
 145         arch_spin_lock(lock);
 146 }
 147
 148 #endif  /* CONFIG_PARAVIRT_SPINLOCKS */
 149
 150 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
 151 {
 152         while (arch_spin_is_locked(lock))
 153                 cpu_relax();
 154 }
 155
 156 /*
 157  * Read-write spinlocks, allowing multiple readers
 158  * but only one writer.
 159  *
 160  * NOTE! it is quite common to have readers in interrupts
 161  * but no interrupt writers. For those circumstances we
 162  * can "mix" irq-safe locks - any writer needs to get a
 163  * irq-safe write-lock, but readers can get non-irqsafe
 164  * read-locks.
 165  *
 166  * On x86, we implement read-write locks as a 32-bit counter
 167  * with the high bit (sign) being the "contended" bit.
 168  */
 169
 170 /**
 171  * read_can_lock - would read_trylock() succeed?
 172  * @lock: the rwlock in question.
 173  */
 174 static inline int arch_read_can_lock(arch_rwlock_t *lock)
 175 {
 176         return lock->lock > 0;
 177 }
 178
 179 /**
 180  * write_can_lock - would write_trylock() succeed?
 181  * @lock: the rwlock in question.
 182  */
 183 static inline int arch_write_can_lock(arch_rwlock_t *lock)
 184 {
 185         return lock->write == WRITE_LOCK_CMP;
 186 }
 187
 188 static inline void arch_read_lock(arch_rwlock_t *rw)
 189 {
 190         asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t"
 191                      "jns 1f\n"
 192                      "call __read_lock_failed\n\t"
 193                      "1:\n"
 194                      ::LOCK_PTR_REG (rw) : "memory");
 195 }
 196
 197 static inline void arch_write_lock(arch_rwlock_t *rw)
 198 {
 199         asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t"
 200                      "jz 1f\n"
 201                      "call __write_lock_failed\n\t"
 202                      "1:\n"
 203                      ::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS)
 204                      : "memory");
 205 }
 206
 207 static inline int arch_read_trylock(arch_rwlock_t *lock)
 208 {
 209         READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock;
 210
 211         if (READ_LOCK_ATOMIC(dec_return)(count) >= 0)
 212                 return 1;
 213         READ_LOCK_ATOMIC(inc)(count);
 214         return 0;
 215 }
 216
 217 static inline int arch_write_trylock(arch_rwlock_t *lock)
 218 {
 219         atomic_t *count = (atomic_t *)&lock->write;
 220
 221         if (atomic_sub_and_test(WRITE_LOCK_CMP, count))
 222                 return 1;
 223         atomic_add(WRITE_LOCK_CMP, count);
 224         return 0;
 225 }
 226
 227 static inline void arch_read_unlock(arch_rwlock_t *rw)
 228 {
 229         asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0"
 230                      :"+m" (rw->lock) : : "memory");
 231 }
 232
 233 static inline void arch_write_unlock(arch_rwlock_t *rw)
 234 {
 235         asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0"
 236                      : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory");
 237 }
 238
 239 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
 240 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 241
 242 #undef READ_LOCK_SIZE
 243 #undef READ_LOCK_ATOMIC
 244 #undef WRITE_LOCK_ADD
 245 #undef WRITE_LOCK_SUB
 246 #undef WRITE_LOCK_CMP
 247
 248 #define arch_spin_relax(lock)   cpu_relax()
 249 #define arch_read_relax(lock)   cpu_relax()
 250 #define arch_write_relax(lock)  cpu_relax()
 251
 252 /* The {read|write|spin}_lock() on x86 are full memory barriers. */
 253 static inline void smp_mb__after_lock(void) { }
 254 #define ARCH_HAS_SMP_MB_AFTER_LOCK
 255
 256 #endif /* _ASM_X86_SPINLOCK_H */