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uwb: Use kcalloc instead of kzalloc to allocate array
[zen-stable.git] / arch / x86 / include / asm / uv / uv_bau.h
blob8e862aaf0d905555e23265df00e139346d9b6649
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Broadcast Assist Unit definitions
7 *
8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
9 */
10
11 #ifndef _ASM_X86_UV_UV_BAU_H
12 #define _ASM_X86_UV_UV_BAU_H
13
14 #include <linux/bitmap.h>
15 #define BITSPERBYTE 8
16
17 /*
18 * Broadcast Assist Unit messaging structures
19 *
20 * Selective Broadcast activations are induced by software action
21 * specifying a particular 8-descriptor "set" via a 6-bit index written
22 * to an MMR.
23 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
24 * each 6-bit index value. These descriptor sets are mapped in sequence
25 * starting with set 0 located at the address specified in the
26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
28 *
29 * We will use one set for sending BAU messages from each of the
30 * cpu's on the uvhub.
31 *
32 * TLB shootdown will use the first of the 8 descriptors of each set.
33 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
34 */
35
36 #define MAX_CPUS_PER_UVHUB 64
37 #define MAX_CPUS_PER_SOCKET 32
38 #define ADP_SZ 64 /* hardware-provided max. */
39 #define UV_CPUS_PER_AS 32 /* hardware-provided max. */
40 #define ITEMS_PER_DESC 8
41 /* the 'throttle' to prevent the hardware stay-busy bug */
42 #define MAX_BAU_CONCURRENT 3
43 #define UV_ACT_STATUS_MASK 0x3
44 #define UV_ACT_STATUS_SIZE 2
45 #define UV_DISTRIBUTION_SIZE 256
46 #define UV_SW_ACK_NPENDING 8
47 #define UV1_NET_ENDPOINT_INTD 0x38
48 #define UV2_NET_ENDPOINT_INTD 0x28
49 #define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51 #define UV_DESC_PSHIFT 49
52 #define UV_PAYLOADQ_PNODE_SHIFT 49
53 #define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54 #define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55 #define UV_BAU_TUNABLES_DIR "sgi_uv"
56 #define UV_BAU_TUNABLES_FILE "bau_tunables"
57 #define WHITESPACE " \t\n"
58 #define uv_mmask ((1UL << uv_hub_info->m_val) - 1)
59 #define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
60 #define cpubit_isset(cpu, bau_local_cpumask) \
61 test_bit((cpu), (bau_local_cpumask).bits)
62
63 /* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */
64 /*
65 * UV2: Bit 19 selects between
66 * (0): 10 microsecond timebase and
67 * (1): 80 microseconds
68 * we're using 655us, similar to UV1: 65 units of 10us
69 */
70 #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
71 #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
72
73 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
74 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
75 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
76
77 #define BAU_MISC_CONTROL_MULT_MASK 3
78
79 #define UVH_AGING_PRESCALE_SEL 0x000000b000UL
80 /* [30:28] URGENCY_7 an index into a table of times */
81 #define BAU_URGENCY_7_SHIFT 28
82 #define BAU_URGENCY_7_MASK 7
83
84 #define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
85 /* [45:40] BAU - BAU transaction timeout select - a multiplier */
86 #define BAU_TRANS_SHIFT 40
87 #define BAU_TRANS_MASK 0x3f
88
89 /*
90 * shorten some awkward names
91 */
92 #define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
93 #define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
94 #define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
95 #define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
96 #define write_gmmr uv_write_global_mmr64
97 #define write_lmmr uv_write_local_mmr
98 #define read_lmmr uv_read_local_mmr
99 #define read_gmmr uv_read_global_mmr64
100
101 /*
102 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
103 */
104 #define DS_IDLE 0
105 #define DS_ACTIVE 1
106 #define DS_DESTINATION_TIMEOUT 2
107 #define DS_SOURCE_TIMEOUT 3
108 /*
109 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
110 * values 1 and 3 will not occur
111 * Decoded meaning ERROR BUSY AUX ERR
112 * ------------------------------- ---- ----- -------
113 * IDLE 0 0 0
114 * BUSY (active) 0 1 0
115 * SW Ack Timeout (destination) 1 0 0
116 * SW Ack INTD rejected (strong NACK) 1 0 1
117 * Source Side Time Out Detected 1 1 0
118 * Destination Side PUT Failed 1 1 1
119 */
120 #define UV2H_DESC_IDLE 0
121 #define UV2H_DESC_BUSY 2
122 #define UV2H_DESC_DEST_TIMEOUT 4
123 #define UV2H_DESC_DEST_STRONG_NACK 5
124 #define UV2H_DESC_SOURCE_TIMEOUT 6
125 #define UV2H_DESC_DEST_PUT_ERR 7
126
127 /*
128 * delay for 'plugged' timeout retries, in microseconds
129 */
130 #define PLUGGED_DELAY 10
131
132 /*
133 * threshholds at which to use IPI to free resources
134 */
135 /* after this # consecutive 'plugged' timeouts, use IPI to release resources */
136 #define PLUGSB4RESET 100
137 /* after this many consecutive timeouts, use IPI to release resources */
138 #define TIMEOUTSB4RESET 1
139 /* at this number uses of IPI to release resources, giveup the request */
140 #define IPI_RESET_LIMIT 1
141 /* after this # consecutive successes, bump up the throttle if it was lowered */
142 #define COMPLETE_THRESHOLD 5
143
144 #define UV_LB_SUBNODEID 0x10
145
146 /* these two are the same for UV1 and UV2: */
147 #define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
148 #define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
149 /* 4 bits of software ack period */
150 #define UV2_ACK_MASK 0x7UL
151 #define UV2_ACK_UNITS_SHFT 3
152 #define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
153 #define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
154
155 /*
156 * number of entries in the destination side payload queue
157 */
158 #define DEST_Q_SIZE 20
159 /*
160 * number of destination side software ack resources
161 */
162 #define DEST_NUM_RESOURCES 8
163 /*
164 * completion statuses for sending a TLB flush message
165 */
166 #define FLUSH_RETRY_PLUGGED 1
167 #define FLUSH_RETRY_TIMEOUT 2
168 #define FLUSH_GIVEUP 3
169 #define FLUSH_COMPLETE 4
170
171 /*
172 * tuning the action when the numalink network is extremely delayed
173 */
174 #define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in
175 microseconds */
176 #define CONGESTED_REPS 10 /* long delays averaged over
177 this many broadcasts */
178 #define CONGESTED_PERIOD 30 /* time for the bau to be
179 disabled, in seconds */
180 /* see msg_type: */
181 #define MSG_NOOP 0
182 #define MSG_REGULAR 1
183 #define MSG_RETRY 2
184
185 /*
186 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
187 * If the 'multilevel' flag in the header portion of the descriptor
188 * has been set to 0, then endpoint multi-unicast mode is selected.
189 * The distribution specification (32 bytes) is interpreted as a 256-bit
190 * distribution vector. Adjacent bits correspond to consecutive even numbered
191 * nodeIDs. The result of adding the index of a given bit to the 15-bit
192 * 'base_dest_nasid' field of the header corresponds to the
193 * destination nodeID associated with that specified bit.
194 */
195 struct pnmask {
196 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
197 };
198
199 /*
200 * mask of cpu's on a uvhub
201 * (during initialization we need to check that unsigned long has
202 * enough bits for max. cpu's per uvhub)
203 */
204 struct bau_local_cpumask {
205 unsigned long bits;
206 };
207
208 /*
209 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
210 * only 12 bytes (96 bits) of the payload area are usable.
211 * An additional 3 bytes (bits 27:4) of the header address are carried
212 * to the next bytes of the destination payload queue.
213 * And an additional 2 bytes of the header Suppl_A field are also
214 * carried to the destination payload queue.
215 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
216 * of the destination payload queue, which is written by the hardware
217 * with the s/w ack resource bit vector.
218 * [ effective message contents (16 bytes (128 bits) maximum), not counting
219 * the s/w ack bit vector ]
220 */
221
222 /*
223 * The payload is software-defined for INTD transactions
224 */
225 struct bau_msg_payload {
226 unsigned long address; /* signifies a page or all
227 TLB's of the cpu */
228 /* 64 bits */
229 unsigned short sending_cpu; /* filled in by sender */
230 /* 16 bits */
231 unsigned short acknowledge_count; /* filled in by destination */
232 /* 16 bits */
233 unsigned int reserved1:32; /* not usable */
234 };
235
236
237 /*
238 * Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
239 * see table 4.2.3.0.1 in broacast_assist spec.
240 */
241 struct bau_msg_header {
242 unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
243 /* bits 5:0 */
244 unsigned int base_dest_nasid:15; /* nasid of the first bit */
245 /* bits 20:6 */ /* in uvhub map */
246 unsigned int command:8; /* message type */
247 /* bits 28:21 */
248 /* 0x38: SN3net EndPoint Message */
249 unsigned int rsvd_1:3; /* must be zero */
250 /* bits 31:29 */
251 /* int will align on 32 bits */
252 unsigned int rsvd_2:9; /* must be zero */
253 /* bits 40:32 */
254 /* Suppl_A is 56-41 */
255 unsigned int sequence:16; /* message sequence number */
256 /* bits 56:41 */ /* becomes bytes 16-17 of msg */
257 /* Address field (96:57) is
258 never used as an address
259 (these are address bits
260 42:3) */
261
262 unsigned int rsvd_3:1; /* must be zero */
263 /* bit 57 */
264 /* address bits 27:4 are payload */
265 /* these next 24 (58-81) bits become bytes 12-14 of msg */
266 /* bits 65:58 land in byte 12 */
267 unsigned int replied_to:1; /* sent as 0 by the source to
268 byte 12 */
269 /* bit 58 */
270 unsigned int msg_type:3; /* software type of the
271 message */
272 /* bits 61:59 */
273 unsigned int canceled:1; /* message canceled, resource
274 is to be freed*/
275 /* bit 62 */
276 unsigned int payload_1a:1; /* not currently used */
277 /* bit 63 */
278 unsigned int payload_1b:2; /* not currently used */
279 /* bits 65:64 */
280
281 /* bits 73:66 land in byte 13 */
282 unsigned int payload_1ca:6; /* not currently used */
283 /* bits 71:66 */
284 unsigned int payload_1c:2; /* not currently used */
285 /* bits 73:72 */
286
287 /* bits 81:74 land in byte 14 */
288 unsigned int payload_1d:6; /* not currently used */
289 /* bits 79:74 */
290 unsigned int payload_1e:2; /* not currently used */
291 /* bits 81:80 */
292
293 unsigned int rsvd_4:7; /* must be zero */
294 /* bits 88:82 */
295 unsigned int swack_flag:1; /* software acknowledge flag */
296 /* bit 89 */
297 /* INTD trasactions at
298 destination are to wait for
299 software acknowledge */
300 unsigned int rsvd_5:6; /* must be zero */
301 /* bits 95:90 */
302 unsigned int rsvd_6:5; /* must be zero */
303 /* bits 100:96 */
304 unsigned int int_both:1; /* if 1, interrupt both sockets
305 on the uvhub */
306 /* bit 101*/
307 unsigned int fairness:3; /* usually zero */
308 /* bits 104:102 */
309 unsigned int multilevel:1; /* multi-level multicast
310 format */
311 /* bit 105 */
312 /* 0 for TLB: endpoint multi-unicast messages */
313 unsigned int chaining:1; /* next descriptor is part of
314 this activation*/
315 /* bit 106 */
316 unsigned int rsvd_7:21; /* must be zero */
317 /* bits 127:107 */
318 };
319
320 /*
321 * The activation descriptor:
322 * The format of the message to send, plus all accompanying control
323 * Should be 64 bytes
324 */
325 struct bau_desc {
326 struct pnmask distribution;
327 /*
328 * message template, consisting of header and payload:
329 */
330 struct bau_msg_header header;
331 struct bau_msg_payload payload;
332 };
333 /*
334 * -payload-- ---------header------
335 * bytes 0-11 bits 41-56 bits 58-81
336 * A B (2) C (3)
337 *
338 * A/B/C are moved to:
339 * A C B
340 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
341 * ------------payload queue-----------
342 */
343
344 /*
345 * The payload queue on the destination side is an array of these.
346 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
347 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
348 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
349 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
350 * swack_vec and payload_2)
351 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
352 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
353 * operation."
354 */
355 struct bau_pq_entry {
356 unsigned long address; /* signifies a page or all TLB's
357 of the cpu */
358 /* 64 bits, bytes 0-7 */
359 unsigned short sending_cpu; /* cpu that sent the message */
360 /* 16 bits, bytes 8-9 */
361 unsigned short acknowledge_count; /* filled in by destination */
362 /* 16 bits, bytes 10-11 */
363 /* these next 3 bytes come from bits 58-81 of the message header */
364 unsigned short replied_to:1; /* sent as 0 by the source */
365 unsigned short msg_type:3; /* software message type */
366 unsigned short canceled:1; /* sent as 0 by the source */
367 unsigned short unused1:3; /* not currently using */
368 /* byte 12 */
369 unsigned char unused2a; /* not currently using */
370 /* byte 13 */
371 unsigned char unused2; /* not currently using */
372 /* byte 14 */
373 unsigned char swack_vec; /* filled in by the hardware */
374 /* byte 15 (bits 127:120) */
375 unsigned short sequence; /* message sequence number */
376 /* bytes 16-17 */
377 unsigned char unused4[2]; /* not currently using bytes 18-19 */
378 /* bytes 18-19 */
379 int number_of_cpus; /* filled in at destination */
380 /* 32 bits, bytes 20-23 (aligned) */
381 unsigned char unused5[8]; /* not using */
382 /* bytes 24-31 */
383 };
384
385 struct msg_desc {
386 struct bau_pq_entry *msg;
387 int msg_slot;
388 int swack_slot;
389 struct bau_pq_entry *queue_first;
390 struct bau_pq_entry *queue_last;
391 };
392
393 struct reset_args {
394 int sender;
395 };
396
397 /*
398 * This structure is allocated per_cpu for UV TLB shootdown statistics.
399 */
400 struct ptc_stats {
401 /* sender statistics */
402 unsigned long s_giveup; /* number of fall backs to
403 IPI-style flushes */
404 unsigned long s_requestor; /* number of shootdown
405 requests */
406 unsigned long s_stimeout; /* source side timeouts */
407 unsigned long s_dtimeout; /* destination side timeouts */
408 unsigned long s_time; /* time spent in sending side */
409 unsigned long s_retriesok; /* successful retries */
410 unsigned long s_ntargcpu; /* total number of cpu's
411 targeted */
412 unsigned long s_ntargself; /* times the sending cpu was
413 targeted */
414 unsigned long s_ntarglocals; /* targets of cpus on the local
415 blade */
416 unsigned long s_ntargremotes; /* targets of cpus on remote
417 blades */
418 unsigned long s_ntarglocaluvhub; /* targets of the local hub */
419 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
420 unsigned long s_ntarguvhub; /* total number of uvhubs
421 targeted */
422 unsigned long s_ntarguvhub16; /* number of times target
423 hubs >= 16*/
424 unsigned long s_ntarguvhub8; /* number of times target
425 hubs >= 8 */
426 unsigned long s_ntarguvhub4; /* number of times target
427 hubs >= 4 */
428 unsigned long s_ntarguvhub2; /* number of times target
429 hubs >= 2 */
430 unsigned long s_ntarguvhub1; /* number of times target
431 hubs == 1 */
432 unsigned long s_resets_plug; /* ipi-style resets from plug
433 state */
434 unsigned long s_resets_timeout; /* ipi-style resets from
435 timeouts */
436 unsigned long s_busy; /* status stayed busy past
437 s/w timer */
438 unsigned long s_throttles; /* waits in throttle */
439 unsigned long s_retry_messages; /* retry broadcasts */
440 unsigned long s_bau_reenabled; /* for bau enable/disable */
441 unsigned long s_bau_disabled; /* for bau enable/disable */
442 /* destination statistics */
443 unsigned long d_alltlb; /* times all tlb's on this
444 cpu were flushed */
445 unsigned long d_onetlb; /* times just one tlb on this
446 cpu was flushed */
447 unsigned long d_multmsg; /* interrupts with multiple
448 messages */
449 unsigned long d_nomsg; /* interrupts with no message */
450 unsigned long d_time; /* time spent on destination
451 side */
452 unsigned long d_requestee; /* number of messages
453 processed */
454 unsigned long d_retries; /* number of retry messages
455 processed */
456 unsigned long d_canceled; /* number of messages canceled
457 by retries */
458 unsigned long d_nocanceled; /* retries that found nothing
459 to cancel */
460 unsigned long d_resets; /* number of ipi-style requests
461 processed */
462 unsigned long d_rcanceled; /* number of messages canceled
463 by resets */
464 };
465
466 struct tunables {
467 int *tunp;
468 int deflt;
469 };
470
471 struct hub_and_pnode {
472 short uvhub;
473 short pnode;
474 };
475
476 struct socket_desc {
477 short num_cpus;
478 short cpu_number[MAX_CPUS_PER_SOCKET];
479 };
480
481 struct uvhub_desc {
482 unsigned short socket_mask;
483 short num_cpus;
484 short uvhub;
485 short pnode;
486 struct socket_desc socket[2];
487 };
488
489 /*
490 * one per-cpu; to locate the software tables
491 */
492 struct bau_control {
493 struct bau_desc *descriptor_base;
494 struct bau_pq_entry *queue_first;
495 struct bau_pq_entry *queue_last;
496 struct bau_pq_entry *bau_msg_head;
497 struct bau_control *uvhub_master;
498 struct bau_control *socket_master;
499 struct ptc_stats *statp;
500 cpumask_t *cpumask;
501 unsigned long timeout_interval;
502 unsigned long set_bau_on_time;
503 atomic_t active_descriptor_count;
504 int plugged_tries;
505 int timeout_tries;
506 int ipi_attempts;
507 int conseccompletes;
508 int baudisabled;
509 int set_bau_off;
510 short cpu;
511 short osnode;
512 short uvhub_cpu;
513 short uvhub;
514 short cpus_in_socket;
515 short cpus_in_uvhub;
516 short partition_base_pnode;
517 unsigned short message_number;
518 unsigned short uvhub_quiesce;
519 short socket_acknowledge_count[DEST_Q_SIZE];
520 cycles_t send_message;
521 spinlock_t uvhub_lock;
522 spinlock_t queue_lock;
523 /* tunables */
524 int max_concurr;
525 int max_concurr_const;
526 int plugged_delay;
527 int plugsb4reset;
528 int timeoutsb4reset;
529 int ipi_reset_limit;
530 int complete_threshold;
531 int cong_response_us;
532 int cong_reps;
533 int cong_period;
534 cycles_t period_time;
535 long period_requests;
536 struct hub_and_pnode *thp;
537 };
538
539 static inline unsigned long read_mmr_uv2_status(void)
540 {
541 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
542 }
543
544 static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
545 {
546 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
547 }
548
549 static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
550 {
551 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
552 }
553
554 static inline void write_mmr_activation(unsigned long index)
555 {
556 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
557 }
558
559 static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
560 {
561 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
562 }
563
564 static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
565 {
566 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
567 }
568
569 static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
570 {
571 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
572 }
573
574 static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
575 {
576 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
577 }
578
579 static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
580 {
581 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
582 }
583
584 static inline unsigned long read_mmr_misc_control(int pnode)
585 {
586 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
587 }
588
589 static inline void write_mmr_sw_ack(unsigned long mr)
590 {
591 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
592 }
593
594 static inline unsigned long read_mmr_sw_ack(void)
595 {
596 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
597 }
598
599 static inline unsigned long read_gmmr_sw_ack(int pnode)
600 {
601 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
602 }
603
604 static inline void write_mmr_data_config(int pnode, unsigned long mr)
605 {
606 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
607 }
608
609 static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
610 {
611 return constant_test_bit(uvhub, &dstp->bits[0]);
612 }
613 static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
614 {
615 __set_bit(pnode, &dstp->bits[0]);
616 }
617 static inline void bau_uvhubs_clear(struct pnmask *dstp,
618 int nbits)
619 {
620 bitmap_zero(&dstp->bits[0], nbits);
621 }
622 static inline int bau_uvhub_weight(struct pnmask *dstp)
623 {
624 return bitmap_weight((unsigned long *)&dstp->bits[0],
625 UV_DISTRIBUTION_SIZE);
626 }
627
628 static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
629 {
630 bitmap_zero(&dstp->bits, nbits);
631 }
632
633 extern void uv_bau_message_intr1(void);
634 extern void uv_bau_timeout_intr1(void);
635
636 struct atomic_short {
637 short counter;
638 };
639
640 /*
641 * atomic_read_short - read a short atomic variable
642 * @v: pointer of type atomic_short
643 *
644 * Atomically reads the value of @v.
645 */
646 static inline int atomic_read_short(const struct atomic_short *v)
647 {
648 return v->counter;
649 }
650
651 /*
652 * atom_asr - add and return a short int
653 * @i: short value to add
654 * @v: pointer of type atomic_short
655 *
656 * Atomically adds @i to @v and returns @i + @v
657 */
658 static inline int atom_asr(short i, struct atomic_short *v)
659 {
660 return i + xadd(&v->counter, i);
661 }
662
663 /*
664 * conditionally add 1 to *v, unless *v is >= u
665 * return 0 if we cannot add 1 to *v because it is >= u
666 * return 1 if we can add 1 to *v because it is < u
667 * the add is atomic
668 *
669 * This is close to atomic_add_unless(), but this allows the 'u' value
670 * to be lowered below the current 'v'. atomic_add_unless can only stop
671 * on equal.
672 */
673 static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
674 {
675 spin_lock(lock);
676 if (atomic_read(v) >= u) {
677 spin_unlock(lock);
678 return 0;
679 }
680 atomic_inc(v);
681 spin_unlock(lock);
682 return 1;
683 }
684
685 #endif /* _ASM_X86_UV_UV_BAU_H */