uwb: Use kcalloc instead of kzalloc to allocate array
[zen-stable.git] / drivers / infiniband / hw / cxgb3 / tcb.h
blobc702dc199e184f3caaf0b65ecf24895dd9f0fc5c
1 /*
2 * Copyright (c) 2007 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
32 #ifndef _TCB_DEFS_H
33 #define _TCB_DEFS_H
35 #define W_TCB_T_STATE 0
36 #define S_TCB_T_STATE 0
37 #define M_TCB_T_STATE 0xfULL
38 #define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE)
40 #define W_TCB_TIMER 0
41 #define S_TCB_TIMER 4
42 #define M_TCB_TIMER 0x1ULL
43 #define V_TCB_TIMER(x) ((x) << S_TCB_TIMER)
45 #define W_TCB_DACK_TIMER 0
46 #define S_TCB_DACK_TIMER 5
47 #define M_TCB_DACK_TIMER 0x1ULL
48 #define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER)
50 #define W_TCB_DEL_FLAG 0
51 #define S_TCB_DEL_FLAG 6
52 #define M_TCB_DEL_FLAG 0x1ULL
53 #define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG)
55 #define W_TCB_L2T_IX 0
56 #define S_TCB_L2T_IX 7
57 #define M_TCB_L2T_IX 0x7ffULL
58 #define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX)
60 #define W_TCB_SMAC_SEL 0
61 #define S_TCB_SMAC_SEL 18
62 #define M_TCB_SMAC_SEL 0x3ULL
63 #define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL)
65 #define W_TCB_TOS 0
66 #define S_TCB_TOS 20
67 #define M_TCB_TOS 0x3fULL
68 #define V_TCB_TOS(x) ((x) << S_TCB_TOS)
70 #define W_TCB_MAX_RT 0
71 #define S_TCB_MAX_RT 26
72 #define M_TCB_MAX_RT 0xfULL
73 #define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT)
75 #define W_TCB_T_RXTSHIFT 0
76 #define S_TCB_T_RXTSHIFT 30
77 #define M_TCB_T_RXTSHIFT 0xfULL
78 #define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT)
80 #define W_TCB_T_DUPACKS 1
81 #define S_TCB_T_DUPACKS 2
82 #define M_TCB_T_DUPACKS 0xfULL
83 #define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS)
85 #define W_TCB_T_MAXSEG 1
86 #define S_TCB_T_MAXSEG 6
87 #define M_TCB_T_MAXSEG 0xfULL
88 #define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG)
90 #define W_TCB_T_FLAGS1 1
91 #define S_TCB_T_FLAGS1 10
92 #define M_TCB_T_FLAGS1 0xffffffffULL
93 #define V_TCB_T_FLAGS1(x) ((x) << S_TCB_T_FLAGS1)
95 #define W_TCB_T_MIGRATION 1
96 #define S_TCB_T_MIGRATION 20
97 #define M_TCB_T_MIGRATION 0x1ULL
98 #define V_TCB_T_MIGRATION(x) ((x) << S_TCB_T_MIGRATION)
100 #define W_TCB_T_FLAGS2 2
101 #define S_TCB_T_FLAGS2 10
102 #define M_TCB_T_FLAGS2 0x7fULL
103 #define V_TCB_T_FLAGS2(x) ((x) << S_TCB_T_FLAGS2)
105 #define W_TCB_SND_SCALE 2
106 #define S_TCB_SND_SCALE 17
107 #define M_TCB_SND_SCALE 0xfULL
108 #define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE)
110 #define W_TCB_RCV_SCALE 2
111 #define S_TCB_RCV_SCALE 21
112 #define M_TCB_RCV_SCALE 0xfULL
113 #define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE)
115 #define W_TCB_SND_UNA_RAW 2
116 #define S_TCB_SND_UNA_RAW 25
117 #define M_TCB_SND_UNA_RAW 0x7ffffffULL
118 #define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW)
120 #define W_TCB_SND_NXT_RAW 3
121 #define S_TCB_SND_NXT_RAW 20
122 #define M_TCB_SND_NXT_RAW 0x7ffffffULL
123 #define V_TCB_SND_NXT_RAW(x) ((x) << S_TCB_SND_NXT_RAW)
125 #define W_TCB_RCV_NXT 4
126 #define S_TCB_RCV_NXT 15
127 #define M_TCB_RCV_NXT 0xffffffffULL
128 #define V_TCB_RCV_NXT(x) ((x) << S_TCB_RCV_NXT)
130 #define W_TCB_RCV_ADV 5
131 #define S_TCB_RCV_ADV 15
132 #define M_TCB_RCV_ADV 0xffffULL
133 #define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV)
135 #define W_TCB_SND_MAX_RAW 5
136 #define S_TCB_SND_MAX_RAW 31
137 #define M_TCB_SND_MAX_RAW 0x7ffffffULL
138 #define V_TCB_SND_MAX_RAW(x) ((x) << S_TCB_SND_MAX_RAW)
140 #define W_TCB_SND_CWND 6
141 #define S_TCB_SND_CWND 26
142 #define M_TCB_SND_CWND 0x7ffffffULL
143 #define V_TCB_SND_CWND(x) ((x) << S_TCB_SND_CWND)
145 #define W_TCB_SND_SSTHRESH 7
146 #define S_TCB_SND_SSTHRESH 21
147 #define M_TCB_SND_SSTHRESH 0x7ffffffULL
148 #define V_TCB_SND_SSTHRESH(x) ((x) << S_TCB_SND_SSTHRESH)
150 #define W_TCB_T_RTT_TS_RECENT_AGE 8
151 #define S_TCB_T_RTT_TS_RECENT_AGE 16
152 #define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL
153 #define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE)
155 #define W_TCB_T_RTSEQ_RECENT 9
156 #define S_TCB_T_RTSEQ_RECENT 16
157 #define M_TCB_T_RTSEQ_RECENT 0xffffffffULL
158 #define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT)
160 #define W_TCB_T_SRTT 10
161 #define S_TCB_T_SRTT 16
162 #define M_TCB_T_SRTT 0xffffULL
163 #define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT)
165 #define W_TCB_T_RTTVAR 11
166 #define S_TCB_T_RTTVAR 0
167 #define M_TCB_T_RTTVAR 0xffffULL
168 #define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR)
170 #define W_TCB_TS_LAST_ACK_SENT_RAW 11
171 #define S_TCB_TS_LAST_ACK_SENT_RAW 16
172 #define M_TCB_TS_LAST_ACK_SENT_RAW 0x7ffffffULL
173 #define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW)
175 #define W_TCB_DIP 12
176 #define S_TCB_DIP 11
177 #define M_TCB_DIP 0xffffffffULL
178 #define V_TCB_DIP(x) ((x) << S_TCB_DIP)
180 #define W_TCB_SIP 13
181 #define S_TCB_SIP 11
182 #define M_TCB_SIP 0xffffffffULL
183 #define V_TCB_SIP(x) ((x) << S_TCB_SIP)
185 #define W_TCB_DP 14
186 #define S_TCB_DP 11
187 #define M_TCB_DP 0xffffULL
188 #define V_TCB_DP(x) ((x) << S_TCB_DP)
190 #define W_TCB_SP 14
191 #define S_TCB_SP 27
192 #define M_TCB_SP 0xffffULL
193 #define V_TCB_SP(x) ((x) << S_TCB_SP)
195 #define W_TCB_TIMESTAMP 15
196 #define S_TCB_TIMESTAMP 11
197 #define M_TCB_TIMESTAMP 0xffffffffULL
198 #define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP)
200 #define W_TCB_TIMESTAMP_OFFSET 16
201 #define S_TCB_TIMESTAMP_OFFSET 11
202 #define M_TCB_TIMESTAMP_OFFSET 0xfULL
203 #define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET)
205 #define W_TCB_TX_MAX 16
206 #define S_TCB_TX_MAX 15
207 #define M_TCB_TX_MAX 0xffffffffULL
208 #define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX)
210 #define W_TCB_TX_HDR_PTR_RAW 17
211 #define S_TCB_TX_HDR_PTR_RAW 15
212 #define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL
213 #define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW)
215 #define W_TCB_TX_LAST_PTR_RAW 18
216 #define S_TCB_TX_LAST_PTR_RAW 0
217 #define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL
218 #define V_TCB_TX_LAST_PTR_RAW(x) ((x) << S_TCB_TX_LAST_PTR_RAW)
220 #define W_TCB_TX_COMPACT 18
221 #define S_TCB_TX_COMPACT 17
222 #define M_TCB_TX_COMPACT 0x1ULL
223 #define V_TCB_TX_COMPACT(x) ((x) << S_TCB_TX_COMPACT)
225 #define W_TCB_RX_COMPACT 18
226 #define S_TCB_RX_COMPACT 18
227 #define M_TCB_RX_COMPACT 0x1ULL
228 #define V_TCB_RX_COMPACT(x) ((x) << S_TCB_RX_COMPACT)
230 #define W_TCB_RCV_WND 18
231 #define S_TCB_RCV_WND 19
232 #define M_TCB_RCV_WND 0x7ffffffULL
233 #define V_TCB_RCV_WND(x) ((x) << S_TCB_RCV_WND)
235 #define W_TCB_RX_HDR_OFFSET 19
236 #define S_TCB_RX_HDR_OFFSET 14
237 #define M_TCB_RX_HDR_OFFSET 0x7ffffffULL
238 #define V_TCB_RX_HDR_OFFSET(x) ((x) << S_TCB_RX_HDR_OFFSET)
240 #define W_TCB_RX_FRAG0_START_IDX_RAW 20
241 #define S_TCB_RX_FRAG0_START_IDX_RAW 9
242 #define M_TCB_RX_FRAG0_START_IDX_RAW 0x7ffffffULL
243 #define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((x) << S_TCB_RX_FRAG0_START_IDX_RAW)
245 #define W_TCB_RX_FRAG1_START_IDX_OFFSET 21
246 #define S_TCB_RX_FRAG1_START_IDX_OFFSET 4
247 #define M_TCB_RX_FRAG1_START_IDX_OFFSET 0x7ffffffULL
248 #define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((x) << S_TCB_RX_FRAG1_START_IDX_OFFSET)
250 #define W_TCB_RX_FRAG0_LEN 21
251 #define S_TCB_RX_FRAG0_LEN 31
252 #define M_TCB_RX_FRAG0_LEN 0x7ffffffULL
253 #define V_TCB_RX_FRAG0_LEN(x) ((x) << S_TCB_RX_FRAG0_LEN)
255 #define W_TCB_RX_FRAG1_LEN 22
256 #define S_TCB_RX_FRAG1_LEN 26
257 #define M_TCB_RX_FRAG1_LEN 0x7ffffffULL
258 #define V_TCB_RX_FRAG1_LEN(x) ((x) << S_TCB_RX_FRAG1_LEN)
260 #define W_TCB_NEWRENO_RECOVER 23
261 #define S_TCB_NEWRENO_RECOVER 21
262 #define M_TCB_NEWRENO_RECOVER 0x7ffffffULL
263 #define V_TCB_NEWRENO_RECOVER(x) ((x) << S_TCB_NEWRENO_RECOVER)
265 #define W_TCB_PDU_HAVE_LEN 24
266 #define S_TCB_PDU_HAVE_LEN 16
267 #define M_TCB_PDU_HAVE_LEN 0x1ULL
268 #define V_TCB_PDU_HAVE_LEN(x) ((x) << S_TCB_PDU_HAVE_LEN)
270 #define W_TCB_PDU_LEN 24
271 #define S_TCB_PDU_LEN 17
272 #define M_TCB_PDU_LEN 0xffffULL
273 #define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN)
275 #define W_TCB_RX_QUIESCE 25
276 #define S_TCB_RX_QUIESCE 1
277 #define M_TCB_RX_QUIESCE 0x1ULL
278 #define V_TCB_RX_QUIESCE(x) ((x) << S_TCB_RX_QUIESCE)
280 #define W_TCB_RX_PTR_RAW 25
281 #define S_TCB_RX_PTR_RAW 2
282 #define M_TCB_RX_PTR_RAW 0x1ffffULL
283 #define V_TCB_RX_PTR_RAW(x) ((x) << S_TCB_RX_PTR_RAW)
285 #define W_TCB_CPU_NO 25
286 #define S_TCB_CPU_NO 19
287 #define M_TCB_CPU_NO 0x7fULL
288 #define V_TCB_CPU_NO(x) ((x) << S_TCB_CPU_NO)
290 #define W_TCB_ULP_TYPE 25
291 #define S_TCB_ULP_TYPE 26
292 #define M_TCB_ULP_TYPE 0xfULL
293 #define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE)
295 #define W_TCB_RX_FRAG1_PTR_RAW 25
296 #define S_TCB_RX_FRAG1_PTR_RAW 30
297 #define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL
298 #define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW)
300 #define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26
301 #define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15
302 #define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0x7ffffffULL
303 #define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW)
305 #define W_TCB_RX_FRAG2_PTR_RAW 27
306 #define S_TCB_RX_FRAG2_PTR_RAW 10
307 #define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL
308 #define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW)
310 #define W_TCB_RX_FRAG2_LEN_RAW 27
311 #define S_TCB_RX_FRAG2_LEN_RAW 27
312 #define M_TCB_RX_FRAG2_LEN_RAW 0x7ffffffULL
313 #define V_TCB_RX_FRAG2_LEN_RAW(x) ((x) << S_TCB_RX_FRAG2_LEN_RAW)
315 #define W_TCB_RX_FRAG3_PTR_RAW 28
316 #define S_TCB_RX_FRAG3_PTR_RAW 22
317 #define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL
318 #define V_TCB_RX_FRAG3_PTR_RAW(x) ((x) << S_TCB_RX_FRAG3_PTR_RAW)
320 #define W_TCB_RX_FRAG3_LEN_RAW 29
321 #define S_TCB_RX_FRAG3_LEN_RAW 7
322 #define M_TCB_RX_FRAG3_LEN_RAW 0x7ffffffULL
323 #define V_TCB_RX_FRAG3_LEN_RAW(x) ((x) << S_TCB_RX_FRAG3_LEN_RAW)
325 #define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30
326 #define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 2
327 #define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0x7ffffffULL
328 #define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW)
330 #define W_TCB_PDU_HDR_LEN 30
331 #define S_TCB_PDU_HDR_LEN 29
332 #define M_TCB_PDU_HDR_LEN 0xffULL
333 #define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN)
335 #define W_TCB_SLUSH1 31
336 #define S_TCB_SLUSH1 5
337 #define M_TCB_SLUSH1 0x7ffffULL
338 #define V_TCB_SLUSH1(x) ((x) << S_TCB_SLUSH1)
340 #define W_TCB_ULP_RAW 31
341 #define S_TCB_ULP_RAW 24
342 #define M_TCB_ULP_RAW 0xffULL
343 #define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW)
345 #define W_TCB_DDP_RDMAP_VERSION 25
346 #define S_TCB_DDP_RDMAP_VERSION 30
347 #define M_TCB_DDP_RDMAP_VERSION 0x1ULL
348 #define V_TCB_DDP_RDMAP_VERSION(x) ((x) << S_TCB_DDP_RDMAP_VERSION)
350 #define W_TCB_MARKER_ENABLE_RX 25
351 #define S_TCB_MARKER_ENABLE_RX 31
352 #define M_TCB_MARKER_ENABLE_RX 0x1ULL
353 #define V_TCB_MARKER_ENABLE_RX(x) ((x) << S_TCB_MARKER_ENABLE_RX)
355 #define W_TCB_MARKER_ENABLE_TX 26
356 #define S_TCB_MARKER_ENABLE_TX 0
357 #define M_TCB_MARKER_ENABLE_TX 0x1ULL
358 #define V_TCB_MARKER_ENABLE_TX(x) ((x) << S_TCB_MARKER_ENABLE_TX)
360 #define W_TCB_CRC_ENABLE 26
361 #define S_TCB_CRC_ENABLE 1
362 #define M_TCB_CRC_ENABLE 0x1ULL
363 #define V_TCB_CRC_ENABLE(x) ((x) << S_TCB_CRC_ENABLE)
365 #define W_TCB_IRS_ULP 26
366 #define S_TCB_IRS_ULP 2
367 #define M_TCB_IRS_ULP 0x1ffULL
368 #define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP)
370 #define W_TCB_ISS_ULP 26
371 #define S_TCB_ISS_ULP 11
372 #define M_TCB_ISS_ULP 0x1ffULL
373 #define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP)
375 #define W_TCB_TX_PDU_LEN 26
376 #define S_TCB_TX_PDU_LEN 20
377 #define M_TCB_TX_PDU_LEN 0x3fffULL
378 #define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN)
380 #define W_TCB_TX_PDU_OUT 27
381 #define S_TCB_TX_PDU_OUT 2
382 #define M_TCB_TX_PDU_OUT 0x1ULL
383 #define V_TCB_TX_PDU_OUT(x) ((x) << S_TCB_TX_PDU_OUT)
385 #define W_TCB_CQ_IDX_SQ 27
386 #define S_TCB_CQ_IDX_SQ 3
387 #define M_TCB_CQ_IDX_SQ 0xffffULL
388 #define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ)
390 #define W_TCB_CQ_IDX_RQ 27
391 #define S_TCB_CQ_IDX_RQ 19
392 #define M_TCB_CQ_IDX_RQ 0xffffULL
393 #define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ)
395 #define W_TCB_QP_ID 28
396 #define S_TCB_QP_ID 3
397 #define M_TCB_QP_ID 0xffffULL
398 #define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID)
400 #define W_TCB_PD_ID 28
401 #define S_TCB_PD_ID 19
402 #define M_TCB_PD_ID 0xffffULL
403 #define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID)
405 #define W_TCB_STAG 29
406 #define S_TCB_STAG 3
407 #define M_TCB_STAG 0xffffffffULL
408 #define V_TCB_STAG(x) ((x) << S_TCB_STAG)
410 #define W_TCB_RQ_START 30
411 #define S_TCB_RQ_START 3
412 #define M_TCB_RQ_START 0x3ffffffULL
413 #define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START)
415 #define W_TCB_RQ_MSN 30
416 #define S_TCB_RQ_MSN 29
417 #define M_TCB_RQ_MSN 0x3ffULL
418 #define V_TCB_RQ_MSN(x) ((x) << S_TCB_RQ_MSN)
420 #define W_TCB_RQ_MAX_OFFSET 31
421 #define S_TCB_RQ_MAX_OFFSET 7
422 #define M_TCB_RQ_MAX_OFFSET 0xfULL
423 #define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET)
425 #define W_TCB_RQ_WRITE_PTR 31
426 #define S_TCB_RQ_WRITE_PTR 11
427 #define M_TCB_RQ_WRITE_PTR 0x3ffULL
428 #define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR)
430 #define W_TCB_INB_WRITE_PERM 31
431 #define S_TCB_INB_WRITE_PERM 21
432 #define M_TCB_INB_WRITE_PERM 0x1ULL
433 #define V_TCB_INB_WRITE_PERM(x) ((x) << S_TCB_INB_WRITE_PERM)
435 #define W_TCB_INB_READ_PERM 31
436 #define S_TCB_INB_READ_PERM 22
437 #define M_TCB_INB_READ_PERM 0x1ULL
438 #define V_TCB_INB_READ_PERM(x) ((x) << S_TCB_INB_READ_PERM)
440 #define W_TCB_ORD_L_BIT_VLD 31
441 #define S_TCB_ORD_L_BIT_VLD 23
442 #define M_TCB_ORD_L_BIT_VLD 0x1ULL
443 #define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD)
445 #define W_TCB_RDMAP_OPCODE 31
446 #define S_TCB_RDMAP_OPCODE 24
447 #define M_TCB_RDMAP_OPCODE 0xfULL
448 #define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE)
450 #define W_TCB_TX_FLUSH 31
451 #define S_TCB_TX_FLUSH 28
452 #define M_TCB_TX_FLUSH 0x1ULL
453 #define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH)
455 #define W_TCB_TX_OOS_RXMT 31
456 #define S_TCB_TX_OOS_RXMT 29
457 #define M_TCB_TX_OOS_RXMT 0x1ULL
458 #define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT)
460 #define W_TCB_TX_OOS_TXMT 31
461 #define S_TCB_TX_OOS_TXMT 30
462 #define M_TCB_TX_OOS_TXMT 0x1ULL
463 #define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT)
465 #define W_TCB_SLUSH_AUX2 31
466 #define S_TCB_SLUSH_AUX2 31
467 #define M_TCB_SLUSH_AUX2 0x1ULL
468 #define V_TCB_SLUSH_AUX2(x) ((x) << S_TCB_SLUSH_AUX2)
470 #define W_TCB_RX_FRAG1_PTR_RAW2 25
471 #define S_TCB_RX_FRAG1_PTR_RAW2 30
472 #define M_TCB_RX_FRAG1_PTR_RAW2 0x1ffffULL
473 #define V_TCB_RX_FRAG1_PTR_RAW2(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW2)
475 #define W_TCB_RX_DDP_FLAGS 26
476 #define S_TCB_RX_DDP_FLAGS 15
477 #define M_TCB_RX_DDP_FLAGS 0x3ffULL
478 #define V_TCB_RX_DDP_FLAGS(x) ((x) << S_TCB_RX_DDP_FLAGS)
480 #define W_TCB_SLUSH_AUX3 26
481 #define S_TCB_SLUSH_AUX3 31
482 #define M_TCB_SLUSH_AUX3 0x1ffULL
483 #define V_TCB_SLUSH_AUX3(x) ((x) << S_TCB_SLUSH_AUX3)
485 #define W_TCB_RX_DDP_BUF0_OFFSET 27
486 #define S_TCB_RX_DDP_BUF0_OFFSET 8
487 #define M_TCB_RX_DDP_BUF0_OFFSET 0x3fffffULL
488 #define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET)
490 #define W_TCB_RX_DDP_BUF0_LEN 27
491 #define S_TCB_RX_DDP_BUF0_LEN 30
492 #define M_TCB_RX_DDP_BUF0_LEN 0x3fffffULL
493 #define V_TCB_RX_DDP_BUF0_LEN(x) ((x) << S_TCB_RX_DDP_BUF0_LEN)
495 #define W_TCB_RX_DDP_BUF1_OFFSET 28
496 #define S_TCB_RX_DDP_BUF1_OFFSET 20
497 #define M_TCB_RX_DDP_BUF1_OFFSET 0x3fffffULL
498 #define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET)
500 #define W_TCB_RX_DDP_BUF1_LEN 29
501 #define S_TCB_RX_DDP_BUF1_LEN 10
502 #define M_TCB_RX_DDP_BUF1_LEN 0x3fffffULL
503 #define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN)
505 #define W_TCB_RX_DDP_BUF0_TAG 30
506 #define S_TCB_RX_DDP_BUF0_TAG 0
507 #define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL
508 #define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG)
510 #define W_TCB_RX_DDP_BUF1_TAG 31
511 #define S_TCB_RX_DDP_BUF1_TAG 0
512 #define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL
513 #define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG)
515 #define S_TF_DACK 10
516 #define V_TF_DACK(x) ((x) << S_TF_DACK)
518 #define S_TF_NAGLE 11
519 #define V_TF_NAGLE(x) ((x) << S_TF_NAGLE)
521 #define S_TF_RECV_SCALE 12
522 #define V_TF_RECV_SCALE(x) ((x) << S_TF_RECV_SCALE)
524 #define S_TF_RECV_TSTMP 13
525 #define V_TF_RECV_TSTMP(x) ((x) << S_TF_RECV_TSTMP)
527 #define S_TF_RECV_SACK 14
528 #define V_TF_RECV_SACK(x) ((x) << S_TF_RECV_SACK)
530 #define S_TF_TURBO 15
531 #define V_TF_TURBO(x) ((x) << S_TF_TURBO)
533 #define S_TF_KEEPALIVE 16
534 #define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE)
536 #define S_TF_TCAM_BYPASS 17
537 #define V_TF_TCAM_BYPASS(x) ((x) << S_TF_TCAM_BYPASS)
539 #define S_TF_CORE_FIN 18
540 #define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN)
542 #define S_TF_CORE_MORE 19
543 #define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE)
545 #define S_TF_MIGRATING 20
546 #define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING)
548 #define S_TF_ACTIVE_OPEN 21
549 #define V_TF_ACTIVE_OPEN(x) ((x) << S_TF_ACTIVE_OPEN)
551 #define S_TF_ASK_MODE 22
552 #define V_TF_ASK_MODE(x) ((x) << S_TF_ASK_MODE)
554 #define S_TF_NON_OFFLOAD 23
555 #define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD)
557 #define S_TF_MOD_SCHD 24
558 #define V_TF_MOD_SCHD(x) ((x) << S_TF_MOD_SCHD)
560 #define S_TF_MOD_SCHD_REASON0 25
561 #define V_TF_MOD_SCHD_REASON0(x) ((x) << S_TF_MOD_SCHD_REASON0)
563 #define S_TF_MOD_SCHD_REASON1 26
564 #define V_TF_MOD_SCHD_REASON1(x) ((x) << S_TF_MOD_SCHD_REASON1)
566 #define S_TF_MOD_SCHD_RX 27
567 #define V_TF_MOD_SCHD_RX(x) ((x) << S_TF_MOD_SCHD_RX)
569 #define S_TF_CORE_PUSH 28
570 #define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH)
572 #define S_TF_RCV_COALESCE_ENABLE 29
573 #define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE)
575 #define S_TF_RCV_COALESCE_PUSH 30
576 #define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH)
578 #define S_TF_RCV_COALESCE_LAST_PSH 31
579 #define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH)
581 #define S_TF_RCV_COALESCE_HEARTBEAT 32
582 #define V_TF_RCV_COALESCE_HEARTBEAT(x) ((x) << S_TF_RCV_COALESCE_HEARTBEAT)
584 #define S_TF_HALF_CLOSE 33
585 #define V_TF_HALF_CLOSE(x) ((x) << S_TF_HALF_CLOSE)
587 #define S_TF_DACK_MSS 34
588 #define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS)
590 #define S_TF_CCTRL_SEL0 35
591 #define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0)
593 #define S_TF_CCTRL_SEL1 36
594 #define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1)
596 #define S_TF_TCP_NEWRENO_FAST_RECOVERY 37
597 #define V_TF_TCP_NEWRENO_FAST_RECOVERY(x) ((x) << S_TF_TCP_NEWRENO_FAST_RECOVERY)
599 #define S_TF_TX_PACE_AUTO 38
600 #define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO)
602 #define S_TF_PEER_FIN_HELD 39
603 #define V_TF_PEER_FIN_HELD(x) ((x) << S_TF_PEER_FIN_HELD)
605 #define S_TF_CORE_URG 40
606 #define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG)
608 #define S_TF_RDMA_ERROR 41
609 #define V_TF_RDMA_ERROR(x) ((x) << S_TF_RDMA_ERROR)
611 #define S_TF_SSWS_DISABLED 42
612 #define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED)
614 #define S_TF_DUPACK_COUNT_ODD 43
615 #define V_TF_DUPACK_COUNT_ODD(x) ((x) << S_TF_DUPACK_COUNT_ODD)
617 #define S_TF_TX_CHANNEL 44
618 #define V_TF_TX_CHANNEL(x) ((x) << S_TF_TX_CHANNEL)
620 #define S_TF_RX_CHANNEL 45
621 #define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL)
623 #define S_TF_TX_PACE_FIXED 46
624 #define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED)
626 #define S_TF_RDMA_FLM_ERROR 47
627 #define V_TF_RDMA_FLM_ERROR(x) ((x) << S_TF_RDMA_FLM_ERROR)
629 #define S_TF_RX_FLOW_CONTROL_DISABLE 48
630 #define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE)
632 #endif /* _TCB_DEFS_H */