drivers/net/myri10ge/myri10ge_mcp.h

   1 #ifndef __MYRI10GE_MCP_H__
   2 #define __MYRI10GE_MCP_H__
   3
   4 #define MXGEFW_VERSION_MAJOR    1
   5 #define MXGEFW_VERSION_MINOR    4
   6
   7 /* 8 Bytes */
   8 struct mcp_dma_addr {
   9         __be32 high;
  10         __be32 low;
  11 };
  12
  13 /* 4 Bytes */
  14 struct mcp_slot {
  15         __sum16 checksum;
  16         __be16 length;
  17 };
  18
  19 /* 64 Bytes */
  20 struct mcp_cmd {
  21         __be32 cmd;
  22         __be32 data0;           /* will be low portion if data > 32 bits */
  23         /* 8 */
  24         __be32 data1;           /* will be high portion if data > 32 bits */
  25         __be32 data2;           /* currently unused.. */
  26         /* 16 */
  27         struct mcp_dma_addr response_addr;
  28         /* 24 */
  29         u8 pad[40];
  30 };
  31
  32 /* 8 Bytes */
  33 struct mcp_cmd_response {
  34         __be32 data;
  35         __be32 result;
  36 };
  37
  38 /*
  39  * flags used in mcp_kreq_ether_send_t:
  40  *
  41  * The SMALL flag is only needed in the first segment. It is raised
  42  * for packets that are total less or equal 512 bytes.
  43  *
  44  * The CKSUM flag must be set in all segments.
  45  *
  46  * The PADDED flags is set if the packet needs to be padded, and it
  47  * must be set for all segments.
  48  *
  49  * The  MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
  50  * length of all previous segments was odd.
  51  */
  52
  53 #define MXGEFW_FLAGS_SMALL      0x1
  54 #define MXGEFW_FLAGS_TSO_HDR    0x1
  55 #define MXGEFW_FLAGS_FIRST      0x2
  56 #define MXGEFW_FLAGS_ALIGN_ODD  0x4
  57 #define MXGEFW_FLAGS_CKSUM      0x8
  58 #define MXGEFW_FLAGS_TSO_LAST   0x8
  59 #define MXGEFW_FLAGS_NO_TSO     0x10
  60 #define MXGEFW_FLAGS_TSO_CHOP   0x10
  61 #define MXGEFW_FLAGS_TSO_PLD    0x20
  62
  63 #define MXGEFW_SEND_SMALL_SIZE  1520
  64 #define MXGEFW_MAX_MTU          9400
  65
  66 union mcp_pso_or_cumlen {
  67         u16 pseudo_hdr_offset;
  68         u16 cum_len;
  69 };
  70
  71 #define MXGEFW_MAX_SEND_DESC 12
  72 #define MXGEFW_PAD          2
  73
  74 /* 16 Bytes */
  75 struct mcp_kreq_ether_send {
  76         __be32 addr_high;
  77         __be32 addr_low;
  78         __be16 pseudo_hdr_offset;
  79         __be16 length;
  80         u8 pad;
  81         u8 rdma_count;
  82         u8 cksum_offset;        /* where to start computing cksum */
  83         u8 flags;               /* as defined above */
  84 };
  85
  86 /* 8 Bytes */
  87 struct mcp_kreq_ether_recv {
  88         __be32 addr_high;
  89         __be32 addr_low;
  90 };
  91
  92 /* Commands */
  93
  94 #define MXGEFW_BOOT_HANDOFF     0xfc0000
  95 #define MXGEFW_BOOT_DUMMY_RDMA  0xfc01c0
  96
  97 #define MXGEFW_ETH_CMD          0xf80000
  98 #define MXGEFW_ETH_SEND_4       0x200000
  99 #define MXGEFW_ETH_SEND_1       0x240000
 100 #define MXGEFW_ETH_SEND_2       0x280000
 101 #define MXGEFW_ETH_SEND_3       0x2c0000
 102 #define MXGEFW_ETH_RECV_SMALL   0x300000
 103 #define MXGEFW_ETH_RECV_BIG     0x340000
 104
 105 #define MXGEFW_ETH_SEND(n)              (0x200000 + (((n) & 0x03) * 0x40000))
 106 #define MXGEFW_ETH_SEND_OFFSET(n)       (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
 107
 108 enum myri10ge_mcp_cmd_type {
 109         MXGEFW_CMD_NONE = 0,
 110         /* Reset the mcp, it is left in a safe state, waiting
 111          * for the driver to set all its parameters */
 112         MXGEFW_CMD_RESET,
 113
 114         /* get the version number of the current firmware..
 115          * (may be available in the eeprom strings..? */
 116         MXGEFW_GET_MCP_VERSION,
 117
 118         /* Parameters which must be set by the driver before it can
 119          * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
 120          * MXGEFW_CMD_RESET is issued */
 121
 122         MXGEFW_CMD_SET_INTRQ_DMA,
 123         MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */
 124         MXGEFW_CMD_SET_SMALL_BUFFER_SIZE,       /* in bytes */
 125
 126         /* Parameters which refer to lanai SRAM addresses where the
 127          * driver must issue PIO writes for various things */
 128
 129         MXGEFW_CMD_GET_SEND_OFFSET,
 130         MXGEFW_CMD_GET_SMALL_RX_OFFSET,
 131         MXGEFW_CMD_GET_BIG_RX_OFFSET,
 132         MXGEFW_CMD_GET_IRQ_ACK_OFFSET,
 133         MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
 134
 135         /* Parameters which refer to rings stored on the MCP,
 136          * and whose size is controlled by the mcp */
 137
 138         MXGEFW_CMD_GET_SEND_RING_SIZE,  /* in bytes */
 139         MXGEFW_CMD_GET_RX_RING_SIZE,    /* in bytes */
 140
 141         /* Parameters which refer to rings stored in the host,
 142          * and whose size is controlled by the host.  Note that
 143          * all must be physically contiguous and must contain
 144          * a power of 2 number of entries.  */
 145
 146         MXGEFW_CMD_SET_INTRQ_SIZE,      /* in bytes */
 147 #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK  (1 << 31)
 148
 149         /* command to bring ethernet interface up.  Above parameters
 150          * (plus mtu & mac address) must have been exchanged prior
 151          * to issuing this command  */
 152         MXGEFW_CMD_ETHERNET_UP,
 153
 154         /* command to bring ethernet interface down.  No further sends
 155          * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
 156          * is issued, and all interrupt queues must be flushed prior
 157          * to ack'ing this command */
 158
 159         MXGEFW_CMD_ETHERNET_DOWN,
 160
 161         /* commands the driver may issue live, without resetting
 162          * the nic.  Note that increasing the mtu "live" should
 163          * only be done if the driver has already supplied buffers
 164          * sufficiently large to handle the new mtu.  Decreasing
 165          * the mtu live is safe */
 166
 167         MXGEFW_CMD_SET_MTU,
 168         MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET,  /* in microseconds */
 169         MXGEFW_CMD_SET_STATS_INTERVAL,  /* in microseconds */
 170         MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,      /* replaced by SET_STATS_DMA_V2 */
 171
 172         MXGEFW_ENABLE_PROMISC,
 173         MXGEFW_DISABLE_PROMISC,
 174         MXGEFW_SET_MAC_ADDRESS,
 175
 176         MXGEFW_ENABLE_FLOW_CONTROL,
 177         MXGEFW_DISABLE_FLOW_CONTROL,
 178
 179         /* do a DMA test
 180          * data0,data1 = DMA address
 181          * data2       = RDMA length (MSH), WDMA length (LSH)
 182          * command return data = repetitions (MSH), 0.5-ms ticks (LSH)
 183          */
 184         MXGEFW_DMA_TEST,
 185
 186         MXGEFW_ENABLE_ALLMULTI,
 187         MXGEFW_DISABLE_ALLMULTI,
 188
 189         /* returns MXGEFW_CMD_ERROR_MULTICAST
 190          * if there is no room in the cache
 191          * data0,MSH(data1) = multicast group address */
 192         MXGEFW_JOIN_MULTICAST_GROUP,
 193         /* returns MXGEFW_CMD_ERROR_MULTICAST
 194          * if the address is not in the cache,
 195          * or is equal to FF-FF-FF-FF-FF-FF
 196          * data0,MSH(data1) = multicast group address */
 197         MXGEFW_LEAVE_MULTICAST_GROUP,
 198         MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
 199
 200         MXGEFW_CMD_SET_STATS_DMA_V2,
 201         /* data0, data1 = bus addr,
 202          * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
 203          * adding new stuff to mcp_irq_data without changing the ABI */
 204
 205         MXGEFW_CMD_UNALIGNED_TEST,
 206         /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
 207          * chipset */
 208
 209         MXGEFW_CMD_UNALIGNED_STATUS,
 210         /* return data = boolean, true if the chipset is known to be unaligned */
 211
 212         MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS,
 213         /* data0 = number of big buffers to use.  It must be 0 or a power of 2.
 214          * 0 indicates that the NIC consumes as many buffers as they are required
 215          * for packet. This is the default behavior.
 216          * A power of 2 number indicates that the NIC always uses the specified
 217          * number of buffers for each big receive packet.
 218          * It is up to the driver to ensure that this value is big enough for
 219          * the NIC to be able to receive maximum-sized packets.
 220          */
 221
 222         MXGEFW_CMD_GET_MAX_RSS_QUEUES,
 223         MXGEFW_CMD_ENABLE_RSS_QUEUES,
 224         /* data0 = number of slices n (0, 1, ..., n-1) to enable
 225          * data1 = interrupt mode.
 226          * 0=share one INTx/MSI, 1=use one MSI-X per queue.
 227          * If all queues share one interrupt, the driver must have set
 228          * RSS_SHARED_INTERRUPT_DMA before enabling queues.
 229          */
 230 #define MXGEFW_SLICE_INTR_MODE_SHARED 0
 231 #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 1
 232
 233         MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET,
 234         MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA,
 235         /* data0, data1 = bus address lsw, msw */
 236         MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
 237         /* get the offset of the indirection table */
 238         MXGEFW_CMD_SET_RSS_TABLE_SIZE,
 239         /* set the size of the indirection table */
 240         MXGEFW_CMD_GET_RSS_KEY_OFFSET,
 241         /* get the offset of the secret key */
 242         MXGEFW_CMD_RSS_KEY_UPDATED,
 243         /* tell nic that the secret key's been updated */
 244         MXGEFW_CMD_SET_RSS_ENABLE,
 245         /* data0 = enable/disable rss
 246          * 0: disable rss.  nic does not distribute receive packets.
 247          * 1: enable rss.  nic distributes receive packets among queues.
 248          * data1 = hash type
 249          * 1: IPV4            (required by RSS)
 250          * 2: TCP_IPV4        (required by RSS)
 251          * 3: IPV4 | TCP_IPV4 (required by RSS)
 252          * 4: source port
 253          */
 254 #define MXGEFW_RSS_HASH_TYPE_IPV4      0x1
 255 #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4  0x2
 256 #define MXGEFW_RSS_HASH_TYPE_SRC_PORT  0x4
 257
 258         MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
 259         /* Return data = the max. size of the entire headers of a IPv6 TSO packet.
 260          * If the header size of a IPv6 TSO packet is larger than the specified
 261          * value, then the driver must not use TSO.
 262          * This size restriction only applies to IPv6 TSO.
 263          * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC
 264          * always has enough header buffer to store maximum-sized headers.
 265          */
 266
 267         MXGEFW_CMD_SET_TSO_MODE,
 268         /* data0 = TSO mode.
 269          * 0: Linux/FreeBSD style (NIC default)
 270          * 1: NDIS/NetBSD style
 271          */
 272 #define MXGEFW_TSO_MODE_LINUX  0
 273 #define MXGEFW_TSO_MODE_NDIS   1
 274
 275         MXGEFW_CMD_MDIO_READ,
 276         /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
 277         MXGEFW_CMD_MDIO_WRITE,
 278         /* data0 = dev_addr,  data1 = register/addr, data2 = value  */
 279
 280         MXGEFW_CMD_XFP_I2C_READ,
 281         /* Starts to get a fresh copy of one byte or of the whole xfp i2c table, the
 282          * obtained data is cached inside the xaui-xfi chip :
 283          *   data0 : "all" flag : 0 => get one byte, 1=> get 256 bytes,
 284          *   data1 : if (data0 == 0): index of byte to refresh [ not used otherwise ]
 285          * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
 286          * During the i2c operation,  MXGEFW_CMD_XFP_I2C_READ or MXGEFW_CMD_XFP_BYTE attempts
 287          *  will return MXGEFW_CMD_ERROR_BUSY
 288          */
 289         MXGEFW_CMD_XFP_BYTE,
 290         /* Return the last obtained copy of a given byte in the xfp i2c table
 291          * (copy cached during the last relevant MXGEFW_CMD_XFP_I2C_READ)
 292          *   data0 : index of the desired table entry
 293          *  Return data = the byte stored at the requested index in the table
 294          */
 295
 296         MXGEFW_CMD_GET_VPUMP_OFFSET,
 297         /* Return data = NIC memory offset of mcp_vpump_public_global */
 298         MXGEFW_CMD_RESET_VPUMP,
 299         /* Resets the VPUMP state */
 300
 301         MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE,
 302         /* data0 = mcp_slot type to use.
 303          * 0 = the default 4B mcp_slot
 304          * 1 = 8B mcp_slot_8
 305          */
 306 #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN        0
 307 #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH  1
 308
 309         MXGEFW_CMD_SET_THROTTLE_FACTOR,
 310         /* set the throttle factor for ethp_z8e
 311          * data0 = throttle_factor
 312          * throttle_factor = 256 * pcie-raw-speed / tx_speed
 313          * tx_speed = 256 * pcie-raw-speed / throttle_factor
 314          *
 315          * For PCI-E x8: pcie-raw-speed == 16Gb/s
 316          * For PCI-E x4: pcie-raw-speed == 8Gb/s
 317          *
 318          * ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
 319          * ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
 320          *
 321          * with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
 322          * with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
 323          */
 324
 325         MXGEFW_CMD_VPUMP_UP,
 326         /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
 327         MXGEFW_CMD_GET_VPUMP_CLK,
 328         /* Get the lanai clock */
 329
 330         MXGEFW_CMD_GET_DCA_OFFSET,
 331         /* offset of dca control for WDMAs */
 332 };
 333
 334 enum myri10ge_mcp_cmd_status {
 335         MXGEFW_CMD_OK = 0,
 336         MXGEFW_CMD_UNKNOWN,
 337         MXGEFW_CMD_ERROR_RANGE,
 338         MXGEFW_CMD_ERROR_BUSY,
 339         MXGEFW_CMD_ERROR_EMPTY,
 340         MXGEFW_CMD_ERROR_CLOSED,
 341         MXGEFW_CMD_ERROR_HASH_ERROR,
 342         MXGEFW_CMD_ERROR_BAD_PORT,
 343         MXGEFW_CMD_ERROR_RESOURCES,
 344         MXGEFW_CMD_ERROR_MULTICAST,
 345         MXGEFW_CMD_ERROR_UNALIGNED,
 346         MXGEFW_CMD_ERROR_NO_MDIO,
 347         MXGEFW_CMD_ERROR_XFP_FAILURE,
 348         MXGEFW_CMD_ERROR_XFP_ABSENT,
 349         MXGEFW_CMD_ERROR_BAD_PCIE_LINK
 350 };
 351
 352 #define MXGEFW_OLD_IRQ_DATA_LEN 40
 353
 354 struct mcp_irq_data {
 355         /* add new counters at the beginning */
 356         __be32 future_use[1];
 357         __be32 dropped_pause;
 358         __be32 dropped_unicast_filtered;
 359         __be32 dropped_bad_crc32;
 360         __be32 dropped_bad_phy;
 361         __be32 dropped_multicast_filtered;
 362         /* 40 Bytes */
 363         __be32 send_done_count;
 364
 365 #define MXGEFW_LINK_DOWN 0
 366 #define MXGEFW_LINK_UP 1
 367 #define MXGEFW_LINK_MYRINET 2
 368 #define MXGEFW_LINK_UNKNOWN 3
 369         __be32 link_up;
 370         __be32 dropped_link_overflow;
 371         __be32 dropped_link_error_or_filtered;
 372         __be32 dropped_runt;
 373         __be32 dropped_overrun;
 374         __be32 dropped_no_small_buffer;
 375         __be32 dropped_no_big_buffer;
 376         __be32 rdma_tags_available;
 377
 378         u8 tx_stopped;
 379         u8 link_down;
 380         u8 stats_updated;
 381         u8 valid;
 382 };
 383
 384 #endif                          /* __MYRI10GE_MCP_H__ */