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arcmsr_hba: Missing slab.h include
[zen-stable.git] / drivers / spi / spi_s3c64xx.c
blob97365815a729a2d3c17d47d3815ffa38ff6c6526
1 /* linux/drivers/spi/spi_s3c64xx.c
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/workqueue.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/spi/spi.h>
29
30 #include <mach/dma.h>
31 #include <plat/s3c64xx-spi.h>
32
33 /* Registers and bit-fields */
34
35 #define S3C64XX_SPI_CH_CFG 0x00
36 #define S3C64XX_SPI_CLK_CFG 0x04
37 #define S3C64XX_SPI_MODE_CFG 0x08
38 #define S3C64XX_SPI_SLAVE_SEL 0x0C
39 #define S3C64XX_SPI_INT_EN 0x10
40 #define S3C64XX_SPI_STATUS 0x14
41 #define S3C64XX_SPI_TX_DATA 0x18
42 #define S3C64XX_SPI_RX_DATA 0x1C
43 #define S3C64XX_SPI_PACKET_CNT 0x20
44 #define S3C64XX_SPI_PENDING_CLR 0x24
45 #define S3C64XX_SPI_SWAP_CFG 0x28
46 #define S3C64XX_SPI_FB_CLK 0x2C
47
48 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
49 #define S3C64XX_SPI_CH_SW_RST (1<<5)
50 #define S3C64XX_SPI_CH_SLAVE (1<<4)
51 #define S3C64XX_SPI_CPOL_L (1<<3)
52 #define S3C64XX_SPI_CPHA_B (1<<2)
53 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
54 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
55
56 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
57 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
58 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
59 #define S3C64XX_SPI_PSR_MASK 0xff
60
61 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
62 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
63 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
64 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
65 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
66 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
67 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
68 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
69 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
70 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
71 #define S3C64XX_SPI_MODE_4BURST (1<<0)
72
73 #define S3C64XX_SPI_SLAVE_AUTO (1<<1)
74 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
75
76 #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
77
78 #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
79 (c)->regs + S3C64XX_SPI_SLAVE_SEL)
80
81 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
88
89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
93 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
94 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
95
96 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
97
98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
102 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
103
104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
105 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
106 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
107 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
109 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
110 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
111 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
112
113 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
114
115 #define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
116 (((i)->fifo_lvl_mask + 1))) \
117 ? 1 : 0)
118
119 #define S3C64XX_SPI_ST_TX_DONE(v, i) ((((v) >> (i)->rx_lvl_offset) & \
120 (((i)->fifo_lvl_mask + 1) << 1)) \
121 ? 1 : 0)
122 #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
123 #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
124
125 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
126 #define S3C64XX_SPI_TRAILCNT_OFF 19
127
128 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
129
130 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
131
132 #define SUSPND (1<<0)
133 #define SPIBUSY (1<<1)
134 #define RXBUSY (1<<2)
135 #define TXBUSY (1<<3)
136
137 /**
138 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
139 * @clk: Pointer to the spi clock.
140 * @src_clk: Pointer to the clock used to generate SPI signals.
141 * @master: Pointer to the SPI Protocol master.
142 * @workqueue: Work queue for the SPI xfer requests.
143 * @cntrlr_info: Platform specific data for the controller this driver manages.
144 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
145 * @work: Work
146 * @queue: To log SPI xfer requests.
147 * @lock: Controller specific lock.
148 * @state: Set of FLAGS to indicate status.
149 * @rx_dmach: Controller's DMA channel for Rx.
150 * @tx_dmach: Controller's DMA channel for Tx.
151 * @sfr_start: BUS address of SPI controller regs.
152 * @regs: Pointer to ioremap'ed controller registers.
153 * @xfer_completion: To indicate completion of xfer task.
154 * @cur_mode: Stores the active configuration of the controller.
155 * @cur_bpw: Stores the active bits per word settings.
156 * @cur_speed: Stores the active xfer clock speed.
157 */
158 struct s3c64xx_spi_driver_data {
159 void __iomem *regs;
160 struct clk *clk;
161 struct clk *src_clk;
162 struct platform_device *pdev;
163 struct spi_master *master;
164 struct workqueue_struct *workqueue;
165 struct s3c64xx_spi_info *cntrlr_info;
166 struct spi_device *tgl_spi;
167 struct work_struct work;
168 struct list_head queue;
169 spinlock_t lock;
170 enum dma_ch rx_dmach;
171 enum dma_ch tx_dmach;
172 unsigned long sfr_start;
173 struct completion xfer_completion;
174 unsigned state;
175 unsigned cur_mode, cur_bpw;
176 unsigned cur_speed;
177 };
178
179 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
180 .name = "samsung-spi-dma",
181 };
182
183 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
184 {
185 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
186 void __iomem *regs = sdd->regs;
187 unsigned long loops;
188 u32 val;
189
190 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
191
192 val = readl(regs + S3C64XX_SPI_CH_CFG);
193 val |= S3C64XX_SPI_CH_SW_RST;
194 val &= ~S3C64XX_SPI_CH_HS_EN;
195 writel(val, regs + S3C64XX_SPI_CH_CFG);
196
197 /* Flush TxFIFO*/
198 loops = msecs_to_loops(1);
199 do {
200 val = readl(regs + S3C64XX_SPI_STATUS);
201 } while (TX_FIFO_LVL(val, sci) && loops--);
202
203 /* Flush RxFIFO*/
204 loops = msecs_to_loops(1);
205 do {
206 val = readl(regs + S3C64XX_SPI_STATUS);
207 if (RX_FIFO_LVL(val, sci))
208 readl(regs + S3C64XX_SPI_RX_DATA);
209 else
210 break;
211 } while (loops--);
212
213 val = readl(regs + S3C64XX_SPI_CH_CFG);
214 val &= ~S3C64XX_SPI_CH_SW_RST;
215 writel(val, regs + S3C64XX_SPI_CH_CFG);
216
217 val = readl(regs + S3C64XX_SPI_MODE_CFG);
218 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
219 writel(val, regs + S3C64XX_SPI_MODE_CFG);
220
221 val = readl(regs + S3C64XX_SPI_CH_CFG);
222 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
223 writel(val, regs + S3C64XX_SPI_CH_CFG);
224 }
225
226 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
227 struct spi_device *spi,
228 struct spi_transfer *xfer, int dma_mode)
229 {
230 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
231 void __iomem *regs = sdd->regs;
232 u32 modecfg, chcfg;
233
234 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
235 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
236
237 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
238 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
239
240 if (dma_mode) {
241 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
242 } else {
243 /* Always shift in data in FIFO, even if xfer is Tx only,
244 * this helps setting PCKT_CNT value for generating clocks
245 * as exactly needed.
246 */
247 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
248 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
249 | S3C64XX_SPI_PACKET_CNT_EN,
250 regs + S3C64XX_SPI_PACKET_CNT);
251 }
252
253 if (xfer->tx_buf != NULL) {
254 sdd->state |= TXBUSY;
255 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
256 if (dma_mode) {
257 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
258 s3c2410_dma_config(sdd->tx_dmach, 1);
259 s3c2410_dma_enqueue(sdd->tx_dmach, (void *)sdd,
260 xfer->tx_dma, xfer->len);
261 s3c2410_dma_ctrl(sdd->tx_dmach, S3C2410_DMAOP_START);
262 } else {
263 unsigned char *buf = (unsigned char *) xfer->tx_buf;
264 int i = 0;
265 while (i < xfer->len)
266 writeb(buf[i++], regs + S3C64XX_SPI_TX_DATA);
267 }
268 }
269
270 if (xfer->rx_buf != NULL) {
271 sdd->state |= RXBUSY;
272
273 if (sci->high_speed && sdd->cur_speed >= 30000000UL
274 && !(sdd->cur_mode & SPI_CPHA))
275 chcfg |= S3C64XX_SPI_CH_HS_EN;
276
277 if (dma_mode) {
278 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
279 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
280 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
281 | S3C64XX_SPI_PACKET_CNT_EN,
282 regs + S3C64XX_SPI_PACKET_CNT);
283 s3c2410_dma_config(sdd->rx_dmach, 1);
284 s3c2410_dma_enqueue(sdd->rx_dmach, (void *)sdd,
285 xfer->rx_dma, xfer->len);
286 s3c2410_dma_ctrl(sdd->rx_dmach, S3C2410_DMAOP_START);
287 }
288 }
289
290 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
291 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
292 }
293
294 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
295 struct spi_device *spi)
296 {
297 struct s3c64xx_spi_csinfo *cs;
298
299 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
300 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
301 /* Deselect the last toggled device */
302 cs = sdd->tgl_spi->controller_data;
303 cs->set_level(cs->line,
304 spi->mode & SPI_CS_HIGH ? 0 : 1);
305 }
306 sdd->tgl_spi = NULL;
307 }
308
309 cs = spi->controller_data;
310 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
311 }
312
313 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
314 struct spi_transfer *xfer, int dma_mode)
315 {
316 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
317 void __iomem *regs = sdd->regs;
318 unsigned long val;
319 int ms;
320
321 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
322 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
323 ms += 5; /* some tolerance */
324
325 if (dma_mode) {
326 val = msecs_to_jiffies(ms) + 10;
327 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
328 } else {
329 val = msecs_to_loops(ms);
330 do {
331 val = readl(regs + S3C64XX_SPI_STATUS);
332 } while (RX_FIFO_LVL(val, sci) < xfer->len && --val);
333 }
334
335 if (!val)
336 return -EIO;
337
338 if (dma_mode) {
339 u32 status;
340
341 /*
342 * DmaTx returns after simply writing data in the FIFO,
343 * w/o waiting for real transmission on the bus to finish.
344 * DmaRx returns only after Dma read data from FIFO which
345 * needs bus transmission to finish, so we don't worry if
346 * Xfer involved Rx(with or without Tx).
347 */
348 if (xfer->rx_buf == NULL) {
349 val = msecs_to_loops(10);
350 status = readl(regs + S3C64XX_SPI_STATUS);
351 while ((TX_FIFO_LVL(status, sci)
352 || !S3C64XX_SPI_ST_TX_DONE(status, sci))
353 && --val) {
354 cpu_relax();
355 status = readl(regs + S3C64XX_SPI_STATUS);
356 }
357
358 if (!val)
359 return -EIO;
360 }
361 } else {
362 unsigned char *buf;
363 int i;
364
365 /* If it was only Tx */
366 if (xfer->rx_buf == NULL) {
367 sdd->state &= ~TXBUSY;
368 return 0;
369 }
370
371 i = 0;
372 buf = xfer->rx_buf;
373 while (i < xfer->len)
374 buf[i++] = readb(regs + S3C64XX_SPI_RX_DATA);
375
376 sdd->state &= ~RXBUSY;
377 }
378
379 return 0;
380 }
381
382 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
383 struct spi_device *spi)
384 {
385 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
386
387 if (sdd->tgl_spi == spi)
388 sdd->tgl_spi = NULL;
389
390 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
391 }
392
393 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
394 {
395 void __iomem *regs = sdd->regs;
396 u32 val;
397
398 /* Disable Clock */
399 val = readl(regs + S3C64XX_SPI_CLK_CFG);
400 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
401 writel(val, regs + S3C64XX_SPI_CLK_CFG);
402
403 /* Set Polarity and Phase */
404 val = readl(regs + S3C64XX_SPI_CH_CFG);
405 val &= ~(S3C64XX_SPI_CH_SLAVE |
406 S3C64XX_SPI_CPOL_L |
407 S3C64XX_SPI_CPHA_B);
408
409 if (sdd->cur_mode & SPI_CPOL)
410 val |= S3C64XX_SPI_CPOL_L;
411
412 if (sdd->cur_mode & SPI_CPHA)
413 val |= S3C64XX_SPI_CPHA_B;
414
415 writel(val, regs + S3C64XX_SPI_CH_CFG);
416
417 /* Set Channel & DMA Mode */
418 val = readl(regs + S3C64XX_SPI_MODE_CFG);
419 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
420 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
421
422 switch (sdd->cur_bpw) {
423 case 32:
424 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
425 break;
426 case 16:
427 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
428 break;
429 default:
430 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
431 break;
432 }
433 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; /* Always 8bits wide */
434
435 writel(val, regs + S3C64XX_SPI_MODE_CFG);
436
437 /* Configure Clock */
438 val = readl(regs + S3C64XX_SPI_CLK_CFG);
439 val &= ~S3C64XX_SPI_PSR_MASK;
440 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
441 & S3C64XX_SPI_PSR_MASK);
442 writel(val, regs + S3C64XX_SPI_CLK_CFG);
443
444 /* Enable Clock */
445 val = readl(regs + S3C64XX_SPI_CLK_CFG);
446 val |= S3C64XX_SPI_ENCLK_ENABLE;
447 writel(val, regs + S3C64XX_SPI_CLK_CFG);
448 }
449
450 void s3c64xx_spi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id,
451 int size, enum s3c2410_dma_buffresult res)
452 {
453 struct s3c64xx_spi_driver_data *sdd = buf_id;
454 unsigned long flags;
455
456 spin_lock_irqsave(&sdd->lock, flags);
457
458 if (res == S3C2410_RES_OK)
459 sdd->state &= ~RXBUSY;
460 else
461 dev_err(&sdd->pdev->dev, "DmaAbrtRx-%d\n", size);
462
463 /* If the other done */
464 if (!(sdd->state & TXBUSY))
465 complete(&sdd->xfer_completion);
466
467 spin_unlock_irqrestore(&sdd->lock, flags);
468 }
469
470 void s3c64xx_spi_dma_txcb(struct s3c2410_dma_chan *chan, void *buf_id,
471 int size, enum s3c2410_dma_buffresult res)
472 {
473 struct s3c64xx_spi_driver_data *sdd = buf_id;
474 unsigned long flags;
475
476 spin_lock_irqsave(&sdd->lock, flags);
477
478 if (res == S3C2410_RES_OK)
479 sdd->state &= ~TXBUSY;
480 else
481 dev_err(&sdd->pdev->dev, "DmaAbrtTx-%d \n", size);
482
483 /* If the other done */
484 if (!(sdd->state & RXBUSY))
485 complete(&sdd->xfer_completion);
486
487 spin_unlock_irqrestore(&sdd->lock, flags);
488 }
489
490 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
491
492 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
493 struct spi_message *msg)
494 {
495 struct device *dev = &sdd->pdev->dev;
496 struct spi_transfer *xfer;
497
498 if (msg->is_dma_mapped)
499 return 0;
500
501 /* First mark all xfer unmapped */
502 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
503 xfer->rx_dma = XFER_DMAADDR_INVALID;
504 xfer->tx_dma = XFER_DMAADDR_INVALID;
505 }
506
507 /* Map until end or first fail */
508 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
509
510 if (xfer->tx_buf != NULL) {
511 xfer->tx_dma = dma_map_single(dev, xfer->tx_buf,
512 xfer->len, DMA_TO_DEVICE);
513 if (dma_mapping_error(dev, xfer->tx_dma)) {
514 dev_err(dev, "dma_map_single Tx failed\n");
515 xfer->tx_dma = XFER_DMAADDR_INVALID;
516 return -ENOMEM;
517 }
518 }
519
520 if (xfer->rx_buf != NULL) {
521 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
522 xfer->len, DMA_FROM_DEVICE);
523 if (dma_mapping_error(dev, xfer->rx_dma)) {
524 dev_err(dev, "dma_map_single Rx failed\n");
525 dma_unmap_single(dev, xfer->tx_dma,
526 xfer->len, DMA_TO_DEVICE);
527 xfer->tx_dma = XFER_DMAADDR_INVALID;
528 xfer->rx_dma = XFER_DMAADDR_INVALID;
529 return -ENOMEM;
530 }
531 }
532 }
533
534 return 0;
535 }
536
537 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
538 struct spi_message *msg)
539 {
540 struct device *dev = &sdd->pdev->dev;
541 struct spi_transfer *xfer;
542
543 if (msg->is_dma_mapped)
544 return;
545
546 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
547
548 if (xfer->rx_buf != NULL
549 && xfer->rx_dma != XFER_DMAADDR_INVALID)
550 dma_unmap_single(dev, xfer->rx_dma,
551 xfer->len, DMA_FROM_DEVICE);
552
553 if (xfer->tx_buf != NULL
554 && xfer->tx_dma != XFER_DMAADDR_INVALID)
555 dma_unmap_single(dev, xfer->tx_dma,
556 xfer->len, DMA_TO_DEVICE);
557 }
558 }
559
560 static void handle_msg(struct s3c64xx_spi_driver_data *sdd,
561 struct spi_message *msg)
562 {
563 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
564 struct spi_device *spi = msg->spi;
565 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
566 struct spi_transfer *xfer;
567 int status = 0, cs_toggle = 0;
568 u32 speed;
569 u8 bpw;
570
571 /* If Master's(controller) state differs from that needed by Slave */
572 if (sdd->cur_speed != spi->max_speed_hz
573 || sdd->cur_mode != spi->mode
574 || sdd->cur_bpw != spi->bits_per_word) {
575 sdd->cur_bpw = spi->bits_per_word;
576 sdd->cur_speed = spi->max_speed_hz;
577 sdd->cur_mode = spi->mode;
578 s3c64xx_spi_config(sdd);
579 }
580
581 /* Map all the transfers if needed */
582 if (s3c64xx_spi_map_mssg(sdd, msg)) {
583 dev_err(&spi->dev,
584 "Xfer: Unable to map message buffers!\n");
585 status = -ENOMEM;
586 goto out;
587 }
588
589 /* Configure feedback delay */
590 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
591
592 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
593
594 unsigned long flags;
595 int use_dma;
596
597 INIT_COMPLETION(sdd->xfer_completion);
598
599 /* Only BPW and Speed may change across transfers */
600 bpw = xfer->bits_per_word ? : spi->bits_per_word;
601 speed = xfer->speed_hz ? : spi->max_speed_hz;
602
603 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
604 sdd->cur_bpw = bpw;
605 sdd->cur_speed = speed;
606 s3c64xx_spi_config(sdd);
607 }
608
609 /* Polling method for xfers not bigger than FIFO capacity */
610 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
611 use_dma = 0;
612 else
613 use_dma = 1;
614
615 spin_lock_irqsave(&sdd->lock, flags);
616
617 /* Pending only which is to be done */
618 sdd->state &= ~RXBUSY;
619 sdd->state &= ~TXBUSY;
620
621 enable_datapath(sdd, spi, xfer, use_dma);
622
623 /* Slave Select */
624 enable_cs(sdd, spi);
625
626 /* Start the signals */
627 S3C64XX_SPI_ACT(sdd);
628
629 spin_unlock_irqrestore(&sdd->lock, flags);
630
631 status = wait_for_xfer(sdd, xfer, use_dma);
632
633 /* Quiese the signals */
634 S3C64XX_SPI_DEACT(sdd);
635
636 if (status) {
637 dev_err(&spi->dev, "I/O Error: "
638 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
639 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
640 (sdd->state & RXBUSY) ? 'f' : 'p',
641 (sdd->state & TXBUSY) ? 'f' : 'p',
642 xfer->len);
643
644 if (use_dma) {
645 if (xfer->tx_buf != NULL
646 && (sdd->state & TXBUSY))
647 s3c2410_dma_ctrl(sdd->tx_dmach,
648 S3C2410_DMAOP_FLUSH);
649 if (xfer->rx_buf != NULL
650 && (sdd->state & RXBUSY))
651 s3c2410_dma_ctrl(sdd->rx_dmach,
652 S3C2410_DMAOP_FLUSH);
653 }
654
655 goto out;
656 }
657
658 if (xfer->delay_usecs)
659 udelay(xfer->delay_usecs);
660
661 if (xfer->cs_change) {
662 /* Hint that the next mssg is gonna be
663 for the same device */
664 if (list_is_last(&xfer->transfer_list,
665 &msg->transfers))
666 cs_toggle = 1;
667 else
668 disable_cs(sdd, spi);
669 }
670
671 msg->actual_length += xfer->len;
672
673 flush_fifo(sdd);
674 }
675
676 out:
677 if (!cs_toggle || status)
678 disable_cs(sdd, spi);
679 else
680 sdd->tgl_spi = spi;
681
682 s3c64xx_spi_unmap_mssg(sdd, msg);
683
684 msg->status = status;
685
686 if (msg->complete)
687 msg->complete(msg->context);
688 }
689
690 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
691 {
692 if (s3c2410_dma_request(sdd->rx_dmach,
693 &s3c64xx_spi_dma_client, NULL) < 0) {
694 dev_err(&sdd->pdev->dev, "cannot get RxDMA\n");
695 return 0;
696 }
697 s3c2410_dma_set_buffdone_fn(sdd->rx_dmach, s3c64xx_spi_dma_rxcb);
698 s3c2410_dma_devconfig(sdd->rx_dmach, S3C2410_DMASRC_HW,
699 sdd->sfr_start + S3C64XX_SPI_RX_DATA);
700
701 if (s3c2410_dma_request(sdd->tx_dmach,
702 &s3c64xx_spi_dma_client, NULL) < 0) {
703 dev_err(&sdd->pdev->dev, "cannot get TxDMA\n");
704 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
705 return 0;
706 }
707 s3c2410_dma_set_buffdone_fn(sdd->tx_dmach, s3c64xx_spi_dma_txcb);
708 s3c2410_dma_devconfig(sdd->tx_dmach, S3C2410_DMASRC_MEM,
709 sdd->sfr_start + S3C64XX_SPI_TX_DATA);
710
711 return 1;
712 }
713
714 static void s3c64xx_spi_work(struct work_struct *work)
715 {
716 struct s3c64xx_spi_driver_data *sdd = container_of(work,
717 struct s3c64xx_spi_driver_data, work);
718 unsigned long flags;
719
720 /* Acquire DMA channels */
721 while (!acquire_dma(sdd))
722 msleep(10);
723
724 spin_lock_irqsave(&sdd->lock, flags);
725
726 while (!list_empty(&sdd->queue)
727 && !(sdd->state & SUSPND)) {
728
729 struct spi_message *msg;
730
731 msg = container_of(sdd->queue.next, struct spi_message, queue);
732
733 list_del_init(&msg->queue);
734
735 /* Set Xfer busy flag */
736 sdd->state |= SPIBUSY;
737
738 spin_unlock_irqrestore(&sdd->lock, flags);
739
740 handle_msg(sdd, msg);
741
742 spin_lock_irqsave(&sdd->lock, flags);
743
744 sdd->state &= ~SPIBUSY;
745 }
746
747 spin_unlock_irqrestore(&sdd->lock, flags);
748
749 /* Free DMA channels */
750 s3c2410_dma_free(sdd->tx_dmach, &s3c64xx_spi_dma_client);
751 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
752 }
753
754 static int s3c64xx_spi_transfer(struct spi_device *spi,
755 struct spi_message *msg)
756 {
757 struct s3c64xx_spi_driver_data *sdd;
758 unsigned long flags;
759
760 sdd = spi_master_get_devdata(spi->master);
761
762 spin_lock_irqsave(&sdd->lock, flags);
763
764 if (sdd->state & SUSPND) {
765 spin_unlock_irqrestore(&sdd->lock, flags);
766 return -ESHUTDOWN;
767 }
768
769 msg->status = -EINPROGRESS;
770 msg->actual_length = 0;
771
772 list_add_tail(&msg->queue, &sdd->queue);
773
774 queue_work(sdd->workqueue, &sdd->work);
775
776 spin_unlock_irqrestore(&sdd->lock, flags);
777
778 return 0;
779 }
780
781 /*
782 * Here we only check the validity of requested configuration
783 * and save the configuration in a local data-structure.
784 * The controller is actually configured only just before we
785 * get a message to transfer.
786 */
787 static int s3c64xx_spi_setup(struct spi_device *spi)
788 {
789 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
790 struct s3c64xx_spi_driver_data *sdd;
791 struct s3c64xx_spi_info *sci;
792 struct spi_message *msg;
793 u32 psr, speed;
794 unsigned long flags;
795 int err = 0;
796
797 if (cs == NULL || cs->set_level == NULL) {
798 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
799 return -ENODEV;
800 }
801
802 sdd = spi_master_get_devdata(spi->master);
803 sci = sdd->cntrlr_info;
804
805 spin_lock_irqsave(&sdd->lock, flags);
806
807 list_for_each_entry(msg, &sdd->queue, queue) {
808 /* Is some mssg is already queued for this device */
809 if (msg->spi == spi) {
810 dev_err(&spi->dev,
811 "setup: attempt while mssg in queue!\n");
812 spin_unlock_irqrestore(&sdd->lock, flags);
813 return -EBUSY;
814 }
815 }
816
817 if (sdd->state & SUSPND) {
818 spin_unlock_irqrestore(&sdd->lock, flags);
819 dev_err(&spi->dev,
820 "setup: SPI-%d not active!\n", spi->master->bus_num);
821 return -ESHUTDOWN;
822 }
823
824 spin_unlock_irqrestore(&sdd->lock, flags);
825
826 if (spi->bits_per_word != 8
827 && spi->bits_per_word != 16
828 && spi->bits_per_word != 32) {
829 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
830 spi->bits_per_word);
831 err = -EINVAL;
832 goto setup_exit;
833 }
834
835 /* Check if we can provide the requested rate */
836 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); /* Max possible */
837
838 if (spi->max_speed_hz > speed)
839 spi->max_speed_hz = speed;
840
841 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
842 psr &= S3C64XX_SPI_PSR_MASK;
843 if (psr == S3C64XX_SPI_PSR_MASK)
844 psr--;
845
846 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
847 if (spi->max_speed_hz < speed) {
848 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
849 psr++;
850 } else {
851 err = -EINVAL;
852 goto setup_exit;
853 }
854 }
855
856 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
857 if (spi->max_speed_hz >= speed)
858 spi->max_speed_hz = speed;
859 else
860 err = -EINVAL;
861
862 setup_exit:
863
864 /* setup() returns with device de-selected */
865 disable_cs(sdd, spi);
866
867 return err;
868 }
869
870 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
871 {
872 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
873 void __iomem *regs = sdd->regs;
874 unsigned int val;
875
876 sdd->cur_speed = 0;
877
878 S3C64XX_SPI_DEACT(sdd);
879
880 /* Disable Interrupts - we use Polling if not DMA mode */
881 writel(0, regs + S3C64XX_SPI_INT_EN);
882
883 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
884 regs + S3C64XX_SPI_CLK_CFG);
885 writel(0, regs + S3C64XX_SPI_MODE_CFG);
886 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
887
888 /* Clear any irq pending bits */
889 writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
890 regs + S3C64XX_SPI_PENDING_CLR);
891
892 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
893
894 val = readl(regs + S3C64XX_SPI_MODE_CFG);
895 val &= ~S3C64XX_SPI_MODE_4BURST;
896 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
897 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
898 writel(val, regs + S3C64XX_SPI_MODE_CFG);
899
900 flush_fifo(sdd);
901 }
902
903 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
904 {
905 struct resource *mem_res, *dmatx_res, *dmarx_res;
906 struct s3c64xx_spi_driver_data *sdd;
907 struct s3c64xx_spi_info *sci;
908 struct spi_master *master;
909 int ret;
910
911 if (pdev->id < 0) {
912 dev_err(&pdev->dev,
913 "Invalid platform device id-%d\n", pdev->id);
914 return -ENODEV;
915 }
916
917 if (pdev->dev.platform_data == NULL) {
918 dev_err(&pdev->dev, "platform_data missing!\n");
919 return -ENODEV;
920 }
921
922 /* Check for availability of necessary resource */
923
924 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
925 if (dmatx_res == NULL) {
926 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
927 return -ENXIO;
928 }
929
930 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
931 if (dmarx_res == NULL) {
932 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
933 return -ENXIO;
934 }
935
936 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
937 if (mem_res == NULL) {
938 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
939 return -ENXIO;
940 }
941
942 master = spi_alloc_master(&pdev->dev,
943 sizeof(struct s3c64xx_spi_driver_data));
944 if (master == NULL) {
945 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
946 return -ENOMEM;
947 }
948
949 sci = pdev->dev.platform_data;
950
951 platform_set_drvdata(pdev, master);
952
953 sdd = spi_master_get_devdata(master);
954 sdd->master = master;
955 sdd->cntrlr_info = sci;
956 sdd->pdev = pdev;
957 sdd->sfr_start = mem_res->start;
958 sdd->tx_dmach = dmatx_res->start;
959 sdd->rx_dmach = dmarx_res->start;
960
961 sdd->cur_bpw = 8;
962
963 master->bus_num = pdev->id;
964 master->setup = s3c64xx_spi_setup;
965 master->transfer = s3c64xx_spi_transfer;
966 master->num_chipselect = sci->num_cs;
967 master->dma_alignment = 8;
968 /* the spi->mode bits understood by this driver: */
969 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
970
971 if (request_mem_region(mem_res->start,
972 resource_size(mem_res), pdev->name) == NULL) {
973 dev_err(&pdev->dev, "Req mem region failed\n");
974 ret = -ENXIO;
975 goto err0;
976 }
977
978 sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
979 if (sdd->regs == NULL) {
980 dev_err(&pdev->dev, "Unable to remap IO\n");
981 ret = -ENXIO;
982 goto err1;
983 }
984
985 if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
986 dev_err(&pdev->dev, "Unable to config gpio\n");
987 ret = -EBUSY;
988 goto err2;
989 }
990
991 /* Setup clocks */
992 sdd->clk = clk_get(&pdev->dev, "spi");
993 if (IS_ERR(sdd->clk)) {
994 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
995 ret = PTR_ERR(sdd->clk);
996 goto err3;
997 }
998
999 if (clk_enable(sdd->clk)) {
1000 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1001 ret = -EBUSY;
1002 goto err4;
1003 }
1004
1005 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name);
1006 if (IS_ERR(sdd->src_clk)) {
1007 dev_err(&pdev->dev,
1008 "Unable to acquire clock '%s'\n", sci->src_clk_name);
1009 ret = PTR_ERR(sdd->src_clk);
1010 goto err5;
1011 }
1012
1013 if (clk_enable(sdd->src_clk)) {
1014 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n",
1015 sci->src_clk_name);
1016 ret = -EBUSY;
1017 goto err6;
1018 }
1019
1020 sdd->workqueue = create_singlethread_workqueue(
1021 dev_name(master->dev.parent));
1022 if (sdd->workqueue == NULL) {
1023 dev_err(&pdev->dev, "Unable to create workqueue\n");
1024 ret = -ENOMEM;
1025 goto err7;
1026 }
1027
1028 /* Setup Deufult Mode */
1029 s3c64xx_spi_hwinit(sdd, pdev->id);
1030
1031 spin_lock_init(&sdd->lock);
1032 init_completion(&sdd->xfer_completion);
1033 INIT_WORK(&sdd->work, s3c64xx_spi_work);
1034 INIT_LIST_HEAD(&sdd->queue);
1035
1036 if (spi_register_master(master)) {
1037 dev_err(&pdev->dev, "cannot register SPI master\n");
1038 ret = -EBUSY;
1039 goto err8;
1040 }
1041
1042 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1043 "with %d Slaves attached\n",
1044 pdev->id, master->num_chipselect);
1045 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1046 mem_res->end, mem_res->start,
1047 sdd->rx_dmach, sdd->tx_dmach);
1048
1049 return 0;
1050
1051 err8:
1052 destroy_workqueue(sdd->workqueue);
1053 err7:
1054 clk_disable(sdd->src_clk);
1055 err6:
1056 clk_put(sdd->src_clk);
1057 err5:
1058 clk_disable(sdd->clk);
1059 err4:
1060 clk_put(sdd->clk);
1061 err3:
1062 err2:
1063 iounmap((void *) sdd->regs);
1064 err1:
1065 release_mem_region(mem_res->start, resource_size(mem_res));
1066 err0:
1067 platform_set_drvdata(pdev, NULL);
1068 spi_master_put(master);
1069
1070 return ret;
1071 }
1072
1073 static int s3c64xx_spi_remove(struct platform_device *pdev)
1074 {
1075 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1076 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1077 struct resource *mem_res;
1078 unsigned long flags;
1079
1080 spin_lock_irqsave(&sdd->lock, flags);
1081 sdd->state |= SUSPND;
1082 spin_unlock_irqrestore(&sdd->lock, flags);
1083
1084 while (sdd->state & SPIBUSY)
1085 msleep(10);
1086
1087 spi_unregister_master(master);
1088
1089 destroy_workqueue(sdd->workqueue);
1090
1091 clk_disable(sdd->src_clk);
1092 clk_put(sdd->src_clk);
1093
1094 clk_disable(sdd->clk);
1095 clk_put(sdd->clk);
1096
1097 iounmap((void *) sdd->regs);
1098
1099 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1100 if (mem_res != NULL)
1101 release_mem_region(mem_res->start, resource_size(mem_res));
1102
1103 platform_set_drvdata(pdev, NULL);
1104 spi_master_put(master);
1105
1106 return 0;
1107 }
1108
1109 #ifdef CONFIG_PM
1110 static int s3c64xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1111 {
1112 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1113 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1114 unsigned long flags;
1115
1116 spin_lock_irqsave(&sdd->lock, flags);
1117 sdd->state |= SUSPND;
1118 spin_unlock_irqrestore(&sdd->lock, flags);
1119
1120 while (sdd->state & SPIBUSY)
1121 msleep(10);
1122
1123 /* Disable the clock */
1124 clk_disable(sdd->src_clk);
1125 clk_disable(sdd->clk);
1126
1127 sdd->cur_speed = 0; /* Output Clock is stopped */
1128
1129 return 0;
1130 }
1131
1132 static int s3c64xx_spi_resume(struct platform_device *pdev)
1133 {
1134 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1135 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1136 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1137 unsigned long flags;
1138
1139 sci->cfg_gpio(pdev);
1140
1141 /* Enable the clock */
1142 clk_enable(sdd->src_clk);
1143 clk_enable(sdd->clk);
1144
1145 s3c64xx_spi_hwinit(sdd, pdev->id);
1146
1147 spin_lock_irqsave(&sdd->lock, flags);
1148 sdd->state &= ~SUSPND;
1149 spin_unlock_irqrestore(&sdd->lock, flags);
1150
1151 return 0;
1152 }
1153 #else
1154 #define s3c64xx_spi_suspend NULL
1155 #define s3c64xx_spi_resume NULL
1156 #endif /* CONFIG_PM */
1157
1158 static struct platform_driver s3c64xx_spi_driver = {
1159 .driver = {
1160 .name = "s3c64xx-spi",
1161 .owner = THIS_MODULE,
1162 },
1163 .remove = s3c64xx_spi_remove,
1164 .suspend = s3c64xx_spi_suspend,
1165 .resume = s3c64xx_spi_resume,
1166 };
1167 MODULE_ALIAS("platform:s3c64xx-spi");
1168
1169 static int __init s3c64xx_spi_init(void)
1170 {
1171 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1172 }
1173 module_init(s3c64xx_spi_init);
1174
1175 static void __exit s3c64xx_spi_exit(void)
1176 {
1177 platform_driver_unregister(&s3c64xx_spi_driver);
1178 }
1179 module_exit(s3c64xx_spi_exit);
1180
1181 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1182 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1183 MODULE_LICENSE("GPL");