drivers/media/rc/ite-cir.h

   1 /*
   2  * Driver for ITE Tech Inc. IT8712F/IT8512F CIR
   3  *
   4  * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of the
   9  * License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  19  * USA.
  20  */
  21
  22 /* platform driver name to register */
  23 #define ITE_DRIVER_NAME "ite-cir"
  24
  25 /* logging macros */
  26 #define ite_pr(level, text, ...) \
  27         printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
  28 #define ite_dbg(text, ...) do { \
  29         if (debug) \
  30                 printk(KERN_DEBUG \
  31                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \
  32 } while (0)
  33
  34 #define ite_dbg_verbose(text, ...) do {\
  35         if (debug > 1) \
  36                 printk(KERN_DEBUG \
  37                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \
  38 } while (0)
  39
  40 /* FIFO sizes */
  41 #define ITE_TX_FIFO_LEN 32
  42 #define ITE_RX_FIFO_LEN 32
  43
  44 /* interrupt types */
  45 #define ITE_IRQ_TX_FIFO        1
  46 #define ITE_IRQ_RX_FIFO        2
  47 #define ITE_IRQ_RX_FIFO_OVERRUN    4
  48
  49 /* forward declaration */
  50 struct ite_dev;
  51
  52 /* struct for storing the parameters of different recognized devices */
  53 struct ite_dev_params {
  54         /* model of the device */
  55         const char *model;
  56
  57         /* size of the I/O region */
  58         int io_region_size;
  59
  60         /* true if the hardware supports transmission */
  61         bool hw_tx_capable;
  62
  63         /* base sampling period, in ns */
  64         u32 sample_period;
  65
  66         /* rx low carrier frequency, in Hz, 0 means no demodulation */
  67         unsigned int rx_low_carrier_freq;
  68
  69         /* tx high carrier frequency, in Hz, 0 means no demodulation */
  70         unsigned int rx_high_carrier_freq;
  71
  72         /* tx carrier frequency, in Hz */
  73         unsigned int tx_carrier_freq;
  74
  75         /* duty cycle, 0-100 */
  76         int tx_duty_cycle;
  77
  78         /* hw-specific operation function pointers; most of these must be
  79          * called while holding the spin lock, except for the TX FIFO length
  80          * one */
  81         /* get pending interrupt causes */
  82         int (*get_irq_causes) (struct ite_dev *dev);
  83
  84         /* enable rx */
  85         void (*enable_rx) (struct ite_dev *dev);
  86
  87         /* make rx enter the idle state; keep listening for a pulse, but stop
  88          * streaming space bytes */
  89         void (*idle_rx) (struct ite_dev *dev);
  90
  91         /* disable rx completely */
  92         void (*disable_rx) (struct ite_dev *dev);
  93
  94         /* read bytes from RX FIFO; return read count */
  95         int (*get_rx_bytes) (struct ite_dev *dev, u8 *buf, int buf_size);
  96
  97         /* enable tx FIFO space available interrupt */
  98         void (*enable_tx_interrupt) (struct ite_dev *dev);
  99
 100         /* disable tx FIFO space available interrupt */
 101         void (*disable_tx_interrupt) (struct ite_dev *dev);
 102
 103         /* get number of full TX FIFO slots */
 104         int (*get_tx_used_slots) (struct ite_dev *dev);
 105
 106         /* put a byte to the TX FIFO */
 107         void (*put_tx_byte) (struct ite_dev *dev, u8 value);
 108
 109         /* disable hardware completely */
 110         void (*disable) (struct ite_dev *dev);
 111
 112         /* initialize the hardware */
 113         void (*init_hardware) (struct ite_dev *dev);
 114
 115         /* set the carrier parameters */
 116         void (*set_carrier_params) (struct ite_dev *dev, bool high_freq,
 117                                     bool use_demodulator, u8 carrier_freq_bits,
 118                                     u8 allowance_bits, u8 pulse_width_bits);
 119 };
 120
 121 /* ITE CIR device structure */
 122 struct ite_dev {
 123         struct pnp_dev *pdev;
 124         struct rc_dev *rdev;
 125         struct ir_raw_event rawir;
 126
 127         /* sync data */
 128         spinlock_t lock;
 129         bool in_use, transmitting;
 130
 131         /* transmit support */
 132         int tx_fifo_allowance;
 133         wait_queue_head_t tx_queue, tx_ended;
 134
 135         /* hardware I/O settings */
 136         unsigned long cir_addr;
 137         int cir_irq;
 138
 139         /* overridable copy of model parameters */
 140         struct ite_dev_params params;
 141 };
 142
 143 /* common values for all kinds of hardware */
 144
 145 /* baud rate divisor default */
 146 #define ITE_BAUDRATE_DIVISOR            1
 147
 148 /* low-speed carrier frequency limits (Hz) */
 149 #define ITE_LCF_MIN_CARRIER_FREQ        27000
 150 #define ITE_LCF_MAX_CARRIER_FREQ        58000
 151
 152 /* high-speed carrier frequency limits (Hz) */
 153 #define ITE_HCF_MIN_CARRIER_FREQ        400000
 154 #define ITE_HCF_MAX_CARRIER_FREQ        500000
 155
 156 /* default carrier freq for when demodulator is off (Hz) */
 157 #define ITE_DEFAULT_CARRIER_FREQ        38000
 158
 159 /* default idling timeout in ns (0.2 seconds) */
 160 #define ITE_IDLE_TIMEOUT                200000000UL
 161
 162 /* limit timeout values */
 163 #define ITE_MIN_IDLE_TIMEOUT            100000000UL
 164 #define ITE_MAX_IDLE_TIMEOUT            1000000000UL
 165
 166 /* convert bits to us */
 167 #define ITE_BITS_TO_NS(bits, sample_period) \
 168 ((u32) ((bits) * ITE_BAUDRATE_DIVISOR * sample_period))
 169
 170 /*
 171  * n in RDCR produces a tolerance of +/- n * 6.25% around the center
 172  * carrier frequency...
 173  *
 174  * From two limit frequencies, L (low) and H (high), we can get both the
 175  * center frequency F = (L + H) / 2 and the variation from the center
 176  * frequency A = (H - L) / (H + L). We can use this in order to honor the
 177  * s_rx_carrier_range() call in ir-core. We'll suppose that any request
 178  * setting L=0 means we must shut down the demodulator.
 179  */
 180 #define ITE_RXDCR_PER_10000_STEP 625
 181
 182 /* high speed carrier freq values */
 183 #define ITE_CFQ_400             0x03
 184 #define ITE_CFQ_450             0x08
 185 #define ITE_CFQ_480             0x0b
 186 #define ITE_CFQ_500             0x0d
 187
 188 /* values for pulse widths */
 189 #define ITE_TXMPW_A             0x02
 190 #define ITE_TXMPW_B             0x03
 191 #define ITE_TXMPW_C             0x04
 192 #define ITE_TXMPW_D             0x05
 193 #define ITE_TXMPW_E             0x06
 194
 195 /* values for demodulator carrier range allowance */
 196 #define ITE_RXDCR_DEFAULT       0x01    /* default carrier range */
 197 #define ITE_RXDCR_MAX           0x07    /* default carrier range */
 198
 199 /* DR TX bits */
 200 #define ITE_TX_PULSE            0x00
 201 #define ITE_TX_SPACE            0x80
 202 #define ITE_TX_MAX_RLE          0x80
 203 #define ITE_TX_RLE_MASK         0x7f
 204
 205 /*
 206  * IT8712F
 207  *
 208  * hardware data obtained from:
 209  *
 210  * IT8712F
 211  * Environment Control – Low Pin Count Input / Output
 212  * (EC - LPC I/O)
 213  * Preliminary Specification V0. 81
 214  */
 215
 216 /* register offsets */
 217 #define IT87_DR         0x00    /* data register */
 218 #define IT87_IER        0x01    /* interrupt enable register */
 219 #define IT87_RCR        0x02    /* receiver control register */
 220 #define IT87_TCR1       0x03    /* transmitter control register 1 */
 221 #define IT87_TCR2       0x04    /* transmitter control register 2 */
 222 #define IT87_TSR        0x05    /* transmitter status register */
 223 #define IT87_RSR        0x06    /* receiver status register */
 224 #define IT87_BDLR       0x05    /* baud rate divisor low byte register */
 225 #define IT87_BDHR       0x06    /* baud rate divisor high byte register */
 226 #define IT87_IIR        0x07    /* interrupt identification register */
 227
 228 #define IT87_IOREG_LENGTH 0x08  /* length of register file */
 229
 230 /* IER bits */
 231 #define IT87_TLDLIE     0x01    /* transmitter low data interrupt enable */
 232 #define IT87_RDAIE      0x02    /* receiver data available interrupt enable */
 233 #define IT87_RFOIE      0x04    /* receiver FIFO overrun interrupt enable */
 234 #define IT87_IEC        0x08    /* interrupt enable control */
 235 #define IT87_BR         0x10    /* baud rate register enable */
 236 #define IT87_RESET      0x20    /* reset */
 237
 238 /* RCR bits */
 239 #define IT87_RXDCR      0x07    /* receiver demodulation carrier range mask */
 240 #define IT87_RXACT      0x08    /* receiver active */
 241 #define IT87_RXEND      0x10    /* receiver demodulation enable */
 242 #define IT87_RXEN       0x20    /* receiver enable */
 243 #define IT87_HCFS       0x40    /* high-speed carrier frequency select */
 244 #define IT87_RDWOS      0x80    /* receiver data without sync */
 245
 246 /* TCR1 bits */
 247 #define IT87_TXMPM      0x03    /* transmitter modulation pulse mode mask */
 248 #define IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
 249 #define IT87_TXENDF     0x04    /* transmitter deferral */
 250 #define IT87_TXRLE      0x08    /* transmitter run length enable */
 251 #define IT87_FIFOTL     0x30    /* FIFO level threshold mask */
 252 #define IT87_FIFOTL_DEFAULT 0x20        /* FIFO level threshold default
 253                                          * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
 254                                          * 0x30 -> 25 */
 255 #define IT87_ILE        0x40    /* internal loopback enable */
 256 #define IT87_FIFOCLR    0x80    /* FIFO clear bit */
 257
 258 /* TCR2 bits */
 259 #define IT87_TXMPW      0x07    /* transmitter modulation pulse width mask */
 260 #define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
 261 #define IT87_CFQ        0xf8    /* carrier frequency mask */
 262 #define IT87_CFQ_SHIFT  3       /* carrier frequency bit shift */
 263
 264 /* TSR bits */
 265 #define IT87_TXFBC      0x3f    /* transmitter FIFO byte count mask */
 266
 267 /* RSR bits */
 268 #define IT87_RXFBC      0x3f    /* receiver FIFO byte count mask */
 269 #define IT87_RXFTO      0x80    /* receiver FIFO time-out */
 270
 271 /* IIR bits */
 272 #define IT87_IP         0x01    /* interrupt pending */
 273 #define IT87_II         0x06    /* interrupt identification mask */
 274 #define IT87_II_NOINT   0x00    /* no interrupt */
 275 #define IT87_II_TXLDL   0x02    /* transmitter low data level */
 276 #define IT87_II_RXDS    0x04    /* receiver data stored */
 277 #define IT87_II_RXFO    0x06    /* receiver FIFO overrun */
 278
 279 /*
 280  * IT8512E/F
 281  *
 282  * Hardware data obtained from:
 283  *
 284  * IT8512E/F
 285  * Embedded Controller
 286  * Preliminary Specification V0.4.1
 287  *
 288  * Note that the CIR registers are not directly available to the host, because
 289  * they only are accessible to the integrated microcontroller. Thus, in order
 290  * use it, some kind of bridging is required. As the bridging may depend on
 291  * the controller firmware in use, we are going to use the PNP ID in order to
 292  * determine the strategy and ports available. See after these generic
 293  * IT8512E/F register definitions for register definitions for those
 294  * strategies.
 295  */
 296
 297 /* register offsets */
 298 #define IT85_C0DR       0x00    /* data register */
 299 #define IT85_C0MSTCR    0x01    /* master control register */
 300 #define IT85_C0IER      0x02    /* interrupt enable register */
 301 #define IT85_C0IIR      0x03    /* interrupt identification register */
 302 #define IT85_C0CFR      0x04    /* carrier frequency register */
 303 #define IT85_C0RCR      0x05    /* receiver control register */
 304 #define IT85_C0TCR      0x06    /* transmitter control register */
 305 #define IT85_C0SCK      0x07    /* slow clock control register */
 306 #define IT85_C0BDLR     0x08    /* baud rate divisor low byte register */
 307 #define IT85_C0BDHR     0x09    /* baud rate divisor high byte register */
 308 #define IT85_C0TFSR     0x0a    /* transmitter FIFO status register */
 309 #define IT85_C0RFSR     0x0b    /* receiver FIFO status register */
 310 #define IT85_C0WCL      0x0d    /* wakeup code length register */
 311 #define IT85_C0WCR      0x0e    /* wakeup code read/write register */
 312 #define IT85_C0WPS      0x0f    /* wakeup power control/status register */
 313
 314 #define IT85_IOREG_LENGTH 0x10  /* length of register file */
 315
 316 /* C0MSTCR bits */
 317 #define IT85_RESET      0x01    /* reset */
 318 #define IT85_FIFOCLR    0x02    /* FIFO clear bit */
 319 #define IT85_FIFOTL     0x0c    /* FIFO level threshold mask */
 320 #define IT85_FIFOTL_DEFAULT 0x08        /* FIFO level threshold default
 321                                          * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
 322                                          * 0x0c -> 25 */
 323 #define IT85_ILE        0x10    /* internal loopback enable */
 324 #define IT85_ILSEL      0x20    /* internal loopback select */
 325
 326 /* C0IER bits */
 327 #define IT85_TLDLIE     0x01    /* TX low data level interrupt enable */
 328 #define IT85_RDAIE      0x02    /* RX data available interrupt enable */
 329 #define IT85_RFOIE      0x04    /* RX FIFO overrun interrupt enable */
 330 #define IT85_IEC        0x80    /* interrupt enable function control */
 331
 332 /* C0IIR bits */
 333 #define IT85_TLDLI      0x01    /* transmitter low data level interrupt */
 334 #define IT85_RDAI       0x02    /* receiver data available interrupt */
 335 #define IT85_RFOI       0x04    /* receiver FIFO overrun interrupt */
 336 #define IT85_NIP        0x80    /* no interrupt pending */
 337
 338 /* C0CFR bits */
 339 #define IT85_CFQ        0x1f    /* carrier frequency mask */
 340 #define IT85_HCFS       0x20    /* high speed carrier frequency select */
 341
 342 /* C0RCR bits */
 343 #define IT85_RXDCR      0x07    /* receiver demodulation carrier range mask */
 344 #define IT85_RXACT      0x08    /* receiver active */
 345 #define IT85_RXEND      0x10    /* receiver demodulation enable */
 346 #define IT85_RDWOS      0x20    /* receiver data without sync */
 347 #define IT85_RXEN       0x80    /* receiver enable */
 348
 349 /* C0TCR bits */
 350 #define IT85_TXMPW      0x07    /* transmitter modulation pulse width mask */
 351 #define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
 352 #define IT85_TXMPM      0x18    /* transmitter modulation pulse mode mask */
 353 #define IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
 354 #define IT85_TXENDF     0x20    /* transmitter deferral */
 355 #define IT85_TXRLE      0x40    /* transmitter run length enable */
 356
 357 /* C0SCK bits */
 358 #define IT85_SCKS       0x01    /* slow clock select */
 359 #define IT85_TXDCKG     0x02    /* TXD clock gating */
 360 #define IT85_DLL1P8E    0x04    /* DLL 1.8432M enable */
 361 #define IT85_DLLTE      0x08    /* DLL test enable */
 362 #define IT85_BRCM       0x70    /* baud rate count mode */
 363 #define IT85_DLLOCK     0x80    /* DLL lock */
 364
 365 /* C0TFSR bits */
 366 #define IT85_TXFBC      0x3f    /* transmitter FIFO count mask */
 367
 368 /* C0RFSR bits */
 369 #define IT85_RXFBC      0x3f    /* receiver FIFO count mask */
 370 #define IT85_RXFTO      0x80    /* receiver FIFO time-out */
 371
 372 /* C0WCL bits */
 373 #define IT85_WCL        0x3f    /* wakeup code length mask */
 374
 375 /* C0WPS bits */
 376 #define IT85_CIRPOSIE   0x01    /* power on/off status interrupt enable */
 377 #define IT85_CIRPOIS    0x02    /* power on/off interrupt status */
 378 #define IT85_CIRPOII    0x04    /* power on/off interrupt identification */
 379 #define IT85_RCRST      0x10    /* wakeup code reading counter reset bit */
 380 #define IT85_WCRST      0x20    /* wakeup code writing counter reset bit */
 381
 382 /*
 383  * ITE8708
 384  *
 385  * Hardware data obtained from hacked driver for IT8512 in this forum post:
 386  *
 387  *  http://ubuntuforums.org/showthread.php?t=1028640
 388  *
 389  * Although there's no official documentation for that driver, analysis would
 390  * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
 391  * selectable by a single bank-select bit that's mapped onto both banks. The
 392  * IT8512 registers are mapped in a different order, so that the first bank
 393  * maps the ones that are used more often, and two registers that share a
 394  * reserved high-order bit are placed at the same offset in both banks in
 395  * order to reuse the reserved bit as the bank select bit.
 396  */
 397
 398 /* register offsets */
 399
 400 /* mapped onto both banks */
 401 #define IT8708_BANKSEL  0x07    /* bank select register */
 402 #define IT8708_HRAE     0x80    /* high registers access enable */
 403
 404 /* mapped onto the low bank */
 405 #define IT8708_C0DR     0x00    /* data register */
 406 #define IT8708_C0MSTCR  0x01    /* master control register */
 407 #define IT8708_C0IER    0x02    /* interrupt enable register */
 408 #define IT8708_C0IIR    0x03    /* interrupt identification register */
 409 #define IT8708_C0RFSR   0x04    /* receiver FIFO status register */
 410 #define IT8708_C0RCR    0x05    /* receiver control register */
 411 #define IT8708_C0TFSR   0x06    /* transmitter FIFO status register */
 412 #define IT8708_C0TCR    0x07    /* transmitter control register */
 413
 414 /* mapped onto the high bank */
 415 #define IT8708_C0BDLR   0x01    /* baud rate divisor low byte register */
 416 #define IT8708_C0BDHR   0x02    /* baud rate divisor high byte register */
 417 #define IT8708_C0CFR    0x04    /* carrier frequency register */
 418
 419 /* registers whose bank mapping we don't know, since they weren't being used
 420  * in the hacked driver... most probably they belong to the high bank too,
 421  * since they fit in the holes the other registers leave */
 422 #define IT8708_C0SCK    0x03    /* slow clock control register */
 423 #define IT8708_C0WCL    0x05    /* wakeup code length register */
 424 #define IT8708_C0WCR    0x06    /* wakeup code read/write register */
 425 #define IT8708_C0WPS    0x07    /* wakeup power control/status register */
 426
 427 #define IT8708_IOREG_LENGTH 0x08        /* length of register file */
 428
 429 /* two more registers that are defined in the hacked driver, but can't be
 430  * found in the data sheets; no idea what they are or how they are accessed,
 431  * since the hacked driver doesn't seem to use them */
 432 #define IT8708_CSCRR    0x00
 433 #define IT8708_CGPINTR  0x01
 434
 435 /* CSCRR bits */
 436 #define IT8708_CSCRR_SCRB 0x3f
 437 #define IT8708_CSCRR_PM 0x80
 438
 439 /* CGPINTR bits */
 440 #define IT8708_CGPINT   0x01
 441
 442 /*
 443  * ITE8709
 444  *
 445  * Hardware interfacing data obtained from the original lirc_ite8709 driver.
 446  * Verbatim from its sources:
 447  *
 448  * The ITE8709 device seems to be the combination of IT8512 superIO chip and
 449  * a specific firmware running on the IT8512's embedded micro-controller.
 450  * In addition of the embedded micro-controller, the IT8512 chip contains a
 451  * CIR module and several other modules. A few modules are directly accessible
 452  * by the host CPU, but most of them are only accessible by the
 453  * micro-controller. The CIR module is only accessible by the
 454  * micro-controller.
 455  *
 456  * The battery-backed SRAM module is accessible by the host CPU and the
 457  * micro-controller. So one of the MC's firmware role is to act as a bridge
 458  * between the host CPU and the CIR module. The firmware implements a kind of
 459  * communication protocol using the SRAM module as a shared memory. The IT8512
 460  * specification is publicly available on ITE's web site, but the
 461  * communication protocol is not, so it was reverse-engineered.
 462  */
 463
 464 /* register offsets */
 465 #define IT8709_RAM_IDX  0x00    /* index into the SRAM module bytes */
 466 #define IT8709_RAM_VAL  0x01    /* read/write data to the indexed byte */
 467
 468 #define IT8709_IOREG_LENGTH 0x02        /* length of register file */
 469
 470 /* register offsets inside the SRAM module */
 471 #define IT8709_MODE     0x1a    /* request/ack byte */
 472 #define IT8709_REG_IDX  0x1b    /* index of the CIR register to access */
 473 #define IT8709_REG_VAL  0x1c    /* value read/to be written */
 474 #define IT8709_IIR      0x1e    /* interrupt identification register */
 475 #define IT8709_RFSR     0x1f    /* receiver FIFO status register */
 476 #define IT8709_FIFO     0x20    /* start of in RAM RX FIFO copy */
 477
 478 /* MODE values */
 479 #define IT8709_IDLE     0x00
 480 #define IT8709_WRITE    0x01
 481 #define IT8709_READ     0x02