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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / media / video / cx23885 / cx23885-cards.c
blobea88722cb4ab3250ce7719961610e3857057e41e
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <media/cx25840.h>
27 #include <linux/firmware.h>
28 #include <staging/altera.h>
29
30 #include "cx23885.h"
31 #include "tuner-xc2028.h"
32 #include "netup-init.h"
33 #include "altera-ci.h"
34 #include "xc5000.h"
35 #include "cx23888-ir.h"
36
37 static unsigned int enable_885_ir;
38 module_param(enable_885_ir, int, 0644);
39 MODULE_PARM_DESC(enable_885_ir,
40 "Enable integrated IR controller for supported\n"
41 "\t\t CX2388[57] boards that are wired for it:\n"
42 "\t\t\tHVR-1250 (reported safe)\n"
43 "\t\t\tTeVii S470 (reported unsafe)\n"
44 "\t\t This can cause an interrupt storm with some cards.\n"
45 "\t\t Default: 0 [Disabled]");
46
47 /* ------------------------------------------------------------------ */
48 /* board config info */
49
50 struct cx23885_board cx23885_boards[] = {
51 [CX23885_BOARD_UNKNOWN] = {
52 .name = "UNKNOWN/GENERIC",
53 /* Ensure safe default for unknown boards */
54 .clk_freq = 0,
55 .input = {{
56 .type = CX23885_VMUX_COMPOSITE1,
57 .vmux = 0,
58 }, {
59 .type = CX23885_VMUX_COMPOSITE2,
60 .vmux = 1,
61 }, {
62 .type = CX23885_VMUX_COMPOSITE3,
63 .vmux = 2,
64 }, {
65 .type = CX23885_VMUX_COMPOSITE4,
66 .vmux = 3,
67 } },
68 },
69 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
70 .name = "Hauppauge WinTV-HVR1800lp",
71 .portc = CX23885_MPEG_DVB,
72 .input = {{
73 .type = CX23885_VMUX_TELEVISION,
74 .vmux = 0,
75 .gpio0 = 0xff00,
76 }, {
77 .type = CX23885_VMUX_DEBUG,
78 .vmux = 0,
79 .gpio0 = 0xff01,
80 }, {
81 .type = CX23885_VMUX_COMPOSITE1,
82 .vmux = 1,
83 .gpio0 = 0xff02,
84 }, {
85 .type = CX23885_VMUX_SVIDEO,
86 .vmux = 2,
87 .gpio0 = 0xff02,
88 } },
89 },
90 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
91 .name = "Hauppauge WinTV-HVR1800",
92 .porta = CX23885_ANALOG_VIDEO,
93 .portb = CX23885_MPEG_ENCODER,
94 .portc = CX23885_MPEG_DVB,
95 .tuner_type = TUNER_PHILIPS_TDA8290,
96 .tuner_addr = 0x42, /* 0x84 >> 1 */
97 .tuner_bus = 1,
98 .input = {{
99 .type = CX23885_VMUX_TELEVISION,
100 .vmux = CX25840_VIN7_CH3 |
101 CX25840_VIN5_CH2 |
102 CX25840_VIN2_CH1,
103 .gpio0 = 0,
104 }, {
105 .type = CX23885_VMUX_COMPOSITE1,
106 .vmux = CX25840_VIN7_CH3 |
107 CX25840_VIN4_CH2 |
108 CX25840_VIN6_CH1,
109 .gpio0 = 0,
110 }, {
111 .type = CX23885_VMUX_SVIDEO,
112 .vmux = CX25840_VIN7_CH3 |
113 CX25840_VIN4_CH2 |
114 CX25840_VIN8_CH1 |
115 CX25840_SVIDEO_ON,
116 .gpio0 = 0,
117 } },
118 },
119 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
120 .name = "Hauppauge WinTV-HVR1250",
121 .portc = CX23885_MPEG_DVB,
122 .input = {{
123 .type = CX23885_VMUX_TELEVISION,
124 .vmux = 0,
125 .gpio0 = 0xff00,
126 }, {
127 .type = CX23885_VMUX_DEBUG,
128 .vmux = 0,
129 .gpio0 = 0xff01,
130 }, {
131 .type = CX23885_VMUX_COMPOSITE1,
132 .vmux = 1,
133 .gpio0 = 0xff02,
134 }, {
135 .type = CX23885_VMUX_SVIDEO,
136 .vmux = 2,
137 .gpio0 = 0xff02,
138 } },
139 },
140 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
141 .name = "DViCO FusionHDTV5 Express",
142 .portb = CX23885_MPEG_DVB,
143 },
144 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
145 .name = "Hauppauge WinTV-HVR1500Q",
146 .portc = CX23885_MPEG_DVB,
147 },
148 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
149 .name = "Hauppauge WinTV-HVR1500",
150 .portc = CX23885_MPEG_DVB,
151 },
152 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
153 .name = "Hauppauge WinTV-HVR1200",
154 .portc = CX23885_MPEG_DVB,
155 },
156 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
157 .name = "Hauppauge WinTV-HVR1700",
158 .portc = CX23885_MPEG_DVB,
159 },
160 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
161 .name = "Hauppauge WinTV-HVR1400",
162 .portc = CX23885_MPEG_DVB,
163 },
164 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
165 .name = "DViCO FusionHDTV7 Dual Express",
166 .portb = CX23885_MPEG_DVB,
167 .portc = CX23885_MPEG_DVB,
168 },
169 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
170 .name = "DViCO FusionHDTV DVB-T Dual Express",
171 .portb = CX23885_MPEG_DVB,
172 .portc = CX23885_MPEG_DVB,
173 },
174 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
175 .name = "Leadtek Winfast PxDVR3200 H",
176 .portc = CX23885_MPEG_DVB,
177 },
178 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
179 .name = "Compro VideoMate E650F",
180 .portc = CX23885_MPEG_DVB,
181 },
182 [CX23885_BOARD_TBS_6920] = {
183 .name = "TurboSight TBS 6920",
184 .portb = CX23885_MPEG_DVB,
185 },
186 [CX23885_BOARD_TEVII_S470] = {
187 .name = "TeVii S470",
188 .portb = CX23885_MPEG_DVB,
189 },
190 [CX23885_BOARD_DVBWORLD_2005] = {
191 .name = "DVBWorld DVB-S2 2005",
192 .portb = CX23885_MPEG_DVB,
193 },
194 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
195 .ci_type = 1,
196 .name = "NetUP Dual DVB-S2 CI",
197 .portb = CX23885_MPEG_DVB,
198 .portc = CX23885_MPEG_DVB,
199 },
200 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
201 .name = "Hauppauge WinTV-HVR1270",
202 .portc = CX23885_MPEG_DVB,
203 },
204 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
205 .name = "Hauppauge WinTV-HVR1275",
206 .portc = CX23885_MPEG_DVB,
207 },
208 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
209 .name = "Hauppauge WinTV-HVR1255",
210 .portc = CX23885_MPEG_DVB,
211 },
212 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
213 .name = "Hauppauge WinTV-HVR1210",
214 .portc = CX23885_MPEG_DVB,
215 },
216 [CX23885_BOARD_MYGICA_X8506] = {
217 .name = "Mygica X8506 DMB-TH",
218 .tuner_type = TUNER_XC5000,
219 .tuner_addr = 0x61,
220 .tuner_bus = 1,
221 .porta = CX23885_ANALOG_VIDEO,
222 .portb = CX23885_MPEG_DVB,
223 .input = {
224 {
225 .type = CX23885_VMUX_TELEVISION,
226 .vmux = CX25840_COMPOSITE2,
227 },
228 {
229 .type = CX23885_VMUX_COMPOSITE1,
230 .vmux = CX25840_COMPOSITE8,
231 },
232 {
233 .type = CX23885_VMUX_SVIDEO,
234 .vmux = CX25840_SVIDEO_LUMA3 |
235 CX25840_SVIDEO_CHROMA4,
236 },
237 {
238 .type = CX23885_VMUX_COMPONENT,
239 .vmux = CX25840_COMPONENT_ON |
240 CX25840_VIN1_CH1 |
241 CX25840_VIN6_CH2 |
242 CX25840_VIN7_CH3,
243 },
244 },
245 },
246 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
247 .name = "Magic-Pro ProHDTV Extreme 2",
248 .tuner_type = TUNER_XC5000,
249 .tuner_addr = 0x61,
250 .tuner_bus = 1,
251 .porta = CX23885_ANALOG_VIDEO,
252 .portb = CX23885_MPEG_DVB,
253 .input = {
254 {
255 .type = CX23885_VMUX_TELEVISION,
256 .vmux = CX25840_COMPOSITE2,
257 },
258 {
259 .type = CX23885_VMUX_COMPOSITE1,
260 .vmux = CX25840_COMPOSITE8,
261 },
262 {
263 .type = CX23885_VMUX_SVIDEO,
264 .vmux = CX25840_SVIDEO_LUMA3 |
265 CX25840_SVIDEO_CHROMA4,
266 },
267 {
268 .type = CX23885_VMUX_COMPONENT,
269 .vmux = CX25840_COMPONENT_ON |
270 CX25840_VIN1_CH1 |
271 CX25840_VIN6_CH2 |
272 CX25840_VIN7_CH3,
273 },
274 },
275 },
276 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
277 .name = "Hauppauge WinTV-HVR1850",
278 .portb = CX23885_MPEG_ENCODER,
279 .portc = CX23885_MPEG_DVB,
280 },
281 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
282 .name = "Compro VideoMate E800",
283 .portc = CX23885_MPEG_DVB,
284 },
285 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
286 .name = "Hauppauge WinTV-HVR1290",
287 .portc = CX23885_MPEG_DVB,
288 },
289 [CX23885_BOARD_MYGICA_X8558PRO] = {
290 .name = "Mygica X8558 PRO DMB-TH",
291 .portb = CX23885_MPEG_DVB,
292 .portc = CX23885_MPEG_DVB,
293 },
294 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
295 .name = "LEADTEK WinFast PxTV1200",
296 .porta = CX23885_ANALOG_VIDEO,
297 .tuner_type = TUNER_XC2028,
298 .tuner_addr = 0x61,
299 .tuner_bus = 1,
300 .input = {{
301 .type = CX23885_VMUX_TELEVISION,
302 .vmux = CX25840_VIN2_CH1 |
303 CX25840_VIN5_CH2 |
304 CX25840_NONE0_CH3,
305 }, {
306 .type = CX23885_VMUX_COMPOSITE1,
307 .vmux = CX25840_COMPOSITE1,
308 }, {
309 .type = CX23885_VMUX_SVIDEO,
310 .vmux = CX25840_SVIDEO_LUMA3 |
311 CX25840_SVIDEO_CHROMA4,
312 }, {
313 .type = CX23885_VMUX_COMPONENT,
314 .vmux = CX25840_VIN7_CH1 |
315 CX25840_VIN6_CH2 |
316 CX25840_VIN8_CH3 |
317 CX25840_COMPONENT_ON,
318 } },
319 },
320 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
321 .name = "GoTView X5 3D Hybrid",
322 .tuner_type = TUNER_XC5000,
323 .tuner_addr = 0x64,
324 .tuner_bus = 1,
325 .porta = CX23885_ANALOG_VIDEO,
326 .portb = CX23885_MPEG_DVB,
327 .input = {{
328 .type = CX23885_VMUX_TELEVISION,
329 .vmux = CX25840_VIN2_CH1 |
330 CX25840_VIN5_CH2,
331 .gpio0 = 0x02,
332 }, {
333 .type = CX23885_VMUX_COMPOSITE1,
334 .vmux = CX23885_VMUX_COMPOSITE1,
335 }, {
336 .type = CX23885_VMUX_SVIDEO,
337 .vmux = CX25840_SVIDEO_LUMA3 |
338 CX25840_SVIDEO_CHROMA4,
339 } },
340 },
341 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
342 .ci_type = 2,
343 .name = "NetUP Dual DVB-T/C-CI RF",
344 .porta = CX23885_ANALOG_VIDEO,
345 .portb = CX23885_MPEG_DVB,
346 .portc = CX23885_MPEG_DVB,
347 .num_fds_portb = 2,
348 .num_fds_portc = 2,
349 .tuner_type = TUNER_XC5000,
350 .tuner_addr = 0x64,
351 .input = { {
352 .type = CX23885_VMUX_TELEVISION,
353 .vmux = CX25840_COMPOSITE1,
354 } },
355 },
356 };
357 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
358
359 /* ------------------------------------------------------------------ */
360 /* PCI subsystem IDs */
361
362 struct cx23885_subid cx23885_subids[] = {
363 {
364 .subvendor = 0x0070,
365 .subdevice = 0x3400,
366 .card = CX23885_BOARD_UNKNOWN,
367 }, {
368 .subvendor = 0x0070,
369 .subdevice = 0x7600,
370 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
371 }, {
372 .subvendor = 0x0070,
373 .subdevice = 0x7800,
374 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
375 }, {
376 .subvendor = 0x0070,
377 .subdevice = 0x7801,
378 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
379 }, {
380 .subvendor = 0x0070,
381 .subdevice = 0x7809,
382 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
383 }, {
384 .subvendor = 0x0070,
385 .subdevice = 0x7911,
386 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
387 }, {
388 .subvendor = 0x18ac,
389 .subdevice = 0xd500,
390 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
391 }, {
392 .subvendor = 0x0070,
393 .subdevice = 0x7790,
394 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
395 }, {
396 .subvendor = 0x0070,
397 .subdevice = 0x7797,
398 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
399 }, {
400 .subvendor = 0x0070,
401 .subdevice = 0x7710,
402 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
403 }, {
404 .subvendor = 0x0070,
405 .subdevice = 0x7717,
406 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
407 }, {
408 .subvendor = 0x0070,
409 .subdevice = 0x71d1,
410 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
411 }, {
412 .subvendor = 0x0070,
413 .subdevice = 0x71d3,
414 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
415 }, {
416 .subvendor = 0x0070,
417 .subdevice = 0x8101,
418 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
419 }, {
420 .subvendor = 0x0070,
421 .subdevice = 0x8010,
422 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
423 }, {
424 .subvendor = 0x18ac,
425 .subdevice = 0xd618,
426 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
427 }, {
428 .subvendor = 0x18ac,
429 .subdevice = 0xdb78,
430 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
431 }, {
432 .subvendor = 0x107d,
433 .subdevice = 0x6681,
434 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
435 }, {
436 .subvendor = 0x185b,
437 .subdevice = 0xe800,
438 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
439 }, {
440 .subvendor = 0x6920,
441 .subdevice = 0x8888,
442 .card = CX23885_BOARD_TBS_6920,
443 }, {
444 .subvendor = 0xd470,
445 .subdevice = 0x9022,
446 .card = CX23885_BOARD_TEVII_S470,
447 }, {
448 .subvendor = 0x0001,
449 .subdevice = 0x2005,
450 .card = CX23885_BOARD_DVBWORLD_2005,
451 }, {
452 .subvendor = 0x1b55,
453 .subdevice = 0x2a2c,
454 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
455 }, {
456 .subvendor = 0x0070,
457 .subdevice = 0x2211,
458 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
459 }, {
460 .subvendor = 0x0070,
461 .subdevice = 0x2215,
462 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
463 }, {
464 .subvendor = 0x0070,
465 .subdevice = 0x221d,
466 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
467 }, {
468 .subvendor = 0x0070,
469 .subdevice = 0x2251,
470 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
471 }, {
472 .subvendor = 0x0070,
473 .subdevice = 0x2259,
474 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
475 }, {
476 .subvendor = 0x0070,
477 .subdevice = 0x2291,
478 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
479 }, {
480 .subvendor = 0x0070,
481 .subdevice = 0x2295,
482 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
483 }, {
484 .subvendor = 0x0070,
485 .subdevice = 0x2299,
486 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
487 }, {
488 .subvendor = 0x0070,
489 .subdevice = 0x229d,
490 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
491 }, {
492 .subvendor = 0x0070,
493 .subdevice = 0x22f0,
494 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
495 }, {
496 .subvendor = 0x0070,
497 .subdevice = 0x22f1,
498 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
499 }, {
500 .subvendor = 0x0070,
501 .subdevice = 0x22f2,
502 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
503 }, {
504 .subvendor = 0x0070,
505 .subdevice = 0x22f3,
506 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
507 }, {
508 .subvendor = 0x0070,
509 .subdevice = 0x22f4,
510 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
511 }, {
512 .subvendor = 0x0070,
513 .subdevice = 0x22f5,
514 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
515 }, {
516 .subvendor = 0x14f1,
517 .subdevice = 0x8651,
518 .card = CX23885_BOARD_MYGICA_X8506,
519 }, {
520 .subvendor = 0x14f1,
521 .subdevice = 0x8657,
522 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
523 }, {
524 .subvendor = 0x0070,
525 .subdevice = 0x8541,
526 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
527 }, {
528 .subvendor = 0x1858,
529 .subdevice = 0xe800,
530 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
531 }, {
532 .subvendor = 0x0070,
533 .subdevice = 0x8551,
534 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
535 }, {
536 .subvendor = 0x14f1,
537 .subdevice = 0x8578,
538 .card = CX23885_BOARD_MYGICA_X8558PRO,
539 }, {
540 .subvendor = 0x107d,
541 .subdevice = 0x6f22,
542 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
543 }, {
544 .subvendor = 0x5654,
545 .subdevice = 0x2390,
546 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
547 }, {
548 .subvendor = 0x1b55,
549 .subdevice = 0xe2e4,
550 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
551 },
552 };
553 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
554
555 void cx23885_card_list(struct cx23885_dev *dev)
556 {
557 int i;
558
559 if (0 == dev->pci->subsystem_vendor &&
560 0 == dev->pci->subsystem_device) {
561 printk(KERN_INFO
562 "%s: Board has no valid PCIe Subsystem ID and can't\n"
563 "%s: be autodetected. Pass card=<n> insmod option\n"
564 "%s: to workaround that. Redirect complaints to the\n"
565 "%s: vendor of the TV card. Best regards,\n"
566 "%s: -- tux\n",
567 dev->name, dev->name, dev->name, dev->name, dev->name);
568 } else {
569 printk(KERN_INFO
570 "%s: Your board isn't known (yet) to the driver.\n"
571 "%s: Try to pick one of the existing card configs via\n"
572 "%s: card=<n> insmod option. Updating to the latest\n"
573 "%s: version might help as well.\n",
574 dev->name, dev->name, dev->name, dev->name);
575 }
576 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
577 dev->name);
578 for (i = 0; i < cx23885_bcount; i++)
579 printk(KERN_INFO "%s: card=%d -> %s\n",
580 dev->name, i, cx23885_boards[i].name);
581 }
582
583 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
584 {
585 struct tveeprom tv;
586
587 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
588 eeprom_data);
589
590 /* Make sure we support the board model */
591 switch (tv.model) {
592 case 22001:
593 /* WinTV-HVR1270 (PCIe, Retail, half height)
594 * ATSC/QAM and basic analog, IR Blast */
595 case 22009:
596 /* WinTV-HVR1210 (PCIe, Retail, half height)
597 * DVB-T and basic analog, IR Blast */
598 case 22011:
599 /* WinTV-HVR1270 (PCIe, Retail, half height)
600 * ATSC/QAM and basic analog, IR Recv */
601 case 22019:
602 /* WinTV-HVR1210 (PCIe, Retail, half height)
603 * DVB-T and basic analog, IR Recv */
604 case 22021:
605 /* WinTV-HVR1275 (PCIe, Retail, half height)
606 * ATSC/QAM and basic analog, IR Recv */
607 case 22029:
608 /* WinTV-HVR1210 (PCIe, Retail, half height)
609 * DVB-T and basic analog, IR Recv */
610 case 22101:
611 /* WinTV-HVR1270 (PCIe, Retail, full height)
612 * ATSC/QAM and basic analog, IR Blast */
613 case 22109:
614 /* WinTV-HVR1210 (PCIe, Retail, full height)
615 * DVB-T and basic analog, IR Blast */
616 case 22111:
617 /* WinTV-HVR1270 (PCIe, Retail, full height)
618 * ATSC/QAM and basic analog, IR Recv */
619 case 22119:
620 /* WinTV-HVR1210 (PCIe, Retail, full height)
621 * DVB-T and basic analog, IR Recv */
622 case 22121:
623 /* WinTV-HVR1275 (PCIe, Retail, full height)
624 * ATSC/QAM and basic analog, IR Recv */
625 case 22129:
626 /* WinTV-HVR1210 (PCIe, Retail, full height)
627 * DVB-T and basic analog, IR Recv */
628 case 71009:
629 /* WinTV-HVR1200 (PCIe, Retail, full height)
630 * DVB-T and basic analog */
631 case 71359:
632 /* WinTV-HVR1200 (PCIe, OEM, half height)
633 * DVB-T and basic analog */
634 case 71439:
635 /* WinTV-HVR1200 (PCIe, OEM, half height)
636 * DVB-T and basic analog */
637 case 71449:
638 /* WinTV-HVR1200 (PCIe, OEM, full height)
639 * DVB-T and basic analog */
640 case 71939:
641 /* WinTV-HVR1200 (PCIe, OEM, half height)
642 * DVB-T and basic analog */
643 case 71949:
644 /* WinTV-HVR1200 (PCIe, OEM, full height)
645 * DVB-T and basic analog */
646 case 71959:
647 /* WinTV-HVR1200 (PCIe, OEM, full height)
648 * DVB-T and basic analog */
649 case 71979:
650 /* WinTV-HVR1200 (PCIe, OEM, half height)
651 * DVB-T and basic analog */
652 case 71999:
653 /* WinTV-HVR1200 (PCIe, OEM, full height)
654 * DVB-T and basic analog */
655 case 76601:
656 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
657 channel ATSC and MPEG2 HW Encoder */
658 case 77001:
659 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
660 and Basic analog */
661 case 77011:
662 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
663 and Basic analog */
664 case 77041:
665 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
666 and Basic analog */
667 case 77051:
668 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
669 and Basic analog */
670 case 78011:
671 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
672 Dual channel ATSC and MPEG2 HW Encoder */
673 case 78501:
674 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
675 Dual channel ATSC and MPEG2 HW Encoder */
676 case 78521:
677 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
678 Dual channel ATSC and MPEG2 HW Encoder */
679 case 78531:
680 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
681 Dual channel ATSC and MPEG2 HW Encoder */
682 case 78631:
683 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
684 Dual channel ATSC and MPEG2 HW Encoder */
685 case 79001:
686 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
687 ATSC and Basic analog */
688 case 79101:
689 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
690 ATSC and Basic analog */
691 case 79501:
692 /* WinTV-HVR1250 (PCIe, No IR, half height,
693 ATSC [at least] and Basic analog) */
694 case 79561:
695 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
696 ATSC and Basic analog */
697 case 79571:
698 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
699 ATSC and Basic analog */
700 case 79671:
701 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
702 ATSC and Basic analog */
703 case 80019:
704 /* WinTV-HVR1400 (Express Card, Retail, IR,
705 * DVB-T and Basic analog */
706 case 81509:
707 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
708 * DVB-T and MPEG2 HW Encoder */
709 case 81519:
710 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
711 * DVB-T and MPEG2 HW Encoder */
712 break;
713 case 85021:
714 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
715 Dual channel ATSC and MPEG2 HW Encoder */
716 break;
717 case 85721:
718 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
719 Dual channel ATSC and Basic analog */
720 break;
721 default:
722 printk(KERN_WARNING "%s: warning: "
723 "unknown hauppauge model #%d\n",
724 dev->name, tv.model);
725 break;
726 }
727
728 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
729 dev->name, tv.model);
730 }
731
732 int cx23885_tuner_callback(void *priv, int component, int command, int arg)
733 {
734 struct cx23885_tsport *port = priv;
735 struct cx23885_dev *dev = port->dev;
736 u32 bitmask = 0;
737
738 if (command == XC2028_RESET_CLK)
739 return 0;
740
741 if (command != 0) {
742 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
743 __func__, command);
744 return -EINVAL;
745 }
746
747 switch (dev->board) {
748 case CX23885_BOARD_HAUPPAUGE_HVR1400:
749 case CX23885_BOARD_HAUPPAUGE_HVR1500:
750 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
751 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
752 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
753 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
754 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
755 /* Tuner Reset Command */
756 bitmask = 0x04;
757 break;
758 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
759 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
760 /* Two identical tuners on two different i2c buses,
761 * we need to reset the correct gpio. */
762 if (port->nr == 1)
763 bitmask = 0x01;
764 else if (port->nr == 2)
765 bitmask = 0x04;
766 break;
767 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
768 /* Tuner Reset Command */
769 bitmask = 0x02;
770 break;
771 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
772 altera_ci_tuner_reset(dev, port->nr);
773 break;
774 }
775
776 if (bitmask) {
777 /* Drive the tuner into reset and back out */
778 cx_clear(GP0_IO, bitmask);
779 mdelay(200);
780 cx_set(GP0_IO, bitmask);
781 }
782
783 return 0;
784 }
785
786 void cx23885_gpio_setup(struct cx23885_dev *dev)
787 {
788 switch (dev->board) {
789 case CX23885_BOARD_HAUPPAUGE_HVR1250:
790 /* GPIO-0 cx24227 demodulator reset */
791 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
792 break;
793 case CX23885_BOARD_HAUPPAUGE_HVR1500:
794 /* GPIO-0 cx24227 demodulator */
795 /* GPIO-2 xc3028 tuner */
796
797 /* Put the parts into reset */
798 cx_set(GP0_IO, 0x00050000);
799 cx_clear(GP0_IO, 0x00000005);
800 msleep(5);
801
802 /* Bring the parts out of reset */
803 cx_set(GP0_IO, 0x00050005);
804 break;
805 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
806 /* GPIO-0 cx24227 demodulator reset */
807 /* GPIO-2 xc5000 tuner reset */
808 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
809 break;
810 case CX23885_BOARD_HAUPPAUGE_HVR1800:
811 /* GPIO-0 656_CLK */
812 /* GPIO-1 656_D0 */
813 /* GPIO-2 8295A Reset */
814 /* GPIO-3-10 cx23417 data0-7 */
815 /* GPIO-11-14 cx23417 addr0-3 */
816 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
817 /* GPIO-19 IR_RX */
818
819 /* CX23417 GPIO's */
820 /* EIO15 Zilog Reset */
821 /* EIO14 S5H1409/CX24227 Reset */
822 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
823
824 /* Put the demod into reset and protect the eeprom */
825 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
826 mdelay(100);
827
828 /* Bring the demod and blaster out of reset */
829 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
830 mdelay(100);
831
832 /* Force the TDA8295A into reset and back */
833 cx23885_gpio_enable(dev, GPIO_2, 1);
834 cx23885_gpio_set(dev, GPIO_2);
835 mdelay(20);
836 cx23885_gpio_clear(dev, GPIO_2);
837 mdelay(20);
838 cx23885_gpio_set(dev, GPIO_2);
839 mdelay(20);
840 break;
841 case CX23885_BOARD_HAUPPAUGE_HVR1200:
842 /* GPIO-0 tda10048 demodulator reset */
843 /* GPIO-2 tda18271 tuner reset */
844
845 /* Put the parts into reset and back */
846 cx_set(GP0_IO, 0x00050000);
847 mdelay(20);
848 cx_clear(GP0_IO, 0x00000005);
849 mdelay(20);
850 cx_set(GP0_IO, 0x00050005);
851 break;
852 case CX23885_BOARD_HAUPPAUGE_HVR1700:
853 /* GPIO-0 TDA10048 demodulator reset */
854 /* GPIO-2 TDA8295A Reset */
855 /* GPIO-3-10 cx23417 data0-7 */
856 /* GPIO-11-14 cx23417 addr0-3 */
857 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
858
859 /* The following GPIO's are on the interna AVCore (cx25840) */
860 /* GPIO-19 IR_RX */
861 /* GPIO-20 IR_TX 416/DVBT Select */
862 /* GPIO-21 IIS DAT */
863 /* GPIO-22 IIS WCLK */
864 /* GPIO-23 IIS BCLK */
865
866 /* Put the parts into reset and back */
867 cx_set(GP0_IO, 0x00050000);
868 mdelay(20);
869 cx_clear(GP0_IO, 0x00000005);
870 mdelay(20);
871 cx_set(GP0_IO, 0x00050005);
872 break;
873 case CX23885_BOARD_HAUPPAUGE_HVR1400:
874 /* GPIO-0 Dibcom7000p demodulator reset */
875 /* GPIO-2 xc3028L tuner reset */
876 /* GPIO-13 LED */
877
878 /* Put the parts into reset and back */
879 cx_set(GP0_IO, 0x00050000);
880 mdelay(20);
881 cx_clear(GP0_IO, 0x00000005);
882 mdelay(20);
883 cx_set(GP0_IO, 0x00050005);
884 break;
885 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
886 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
887 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
888 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
889 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
890
891 /* Put the parts into reset and back */
892 cx_set(GP0_IO, 0x000f0000);
893 mdelay(20);
894 cx_clear(GP0_IO, 0x0000000f);
895 mdelay(20);
896 cx_set(GP0_IO, 0x000f000f);
897 break;
898 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
899 /* GPIO-0 portb xc3028 reset */
900 /* GPIO-1 portb zl10353 reset */
901 /* GPIO-2 portc xc3028 reset */
902 /* GPIO-3 portc zl10353 reset */
903
904 /* Put the parts into reset and back */
905 cx_set(GP0_IO, 0x000f0000);
906 mdelay(20);
907 cx_clear(GP0_IO, 0x0000000f);
908 mdelay(20);
909 cx_set(GP0_IO, 0x000f000f);
910 break;
911 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
912 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
913 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
914 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
915 /* GPIO-2 xc3028 tuner reset */
916
917 /* The following GPIO's are on the internal AVCore (cx25840) */
918 /* GPIO-? zl10353 demod reset */
919
920 /* Put the parts into reset and back */
921 cx_set(GP0_IO, 0x00040000);
922 mdelay(20);
923 cx_clear(GP0_IO, 0x00000004);
924 mdelay(20);
925 cx_set(GP0_IO, 0x00040004);
926 break;
927 case CX23885_BOARD_TBS_6920:
928 cx_write(MC417_CTL, 0x00000036);
929 cx_write(MC417_OEN, 0x00001000);
930 cx_set(MC417_RWD, 0x00000002);
931 mdelay(200);
932 cx_clear(MC417_RWD, 0x00000800);
933 mdelay(200);
934 cx_set(MC417_RWD, 0x00000800);
935 mdelay(200);
936 break;
937 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
938 /* GPIO-0 INTA from CiMax1
939 GPIO-1 INTB from CiMax2
940 GPIO-2 reset chips
941 GPIO-3 to GPIO-10 data/addr for CA
942 GPIO-11 ~CS0 to CiMax1
943 GPIO-12 ~CS1 to CiMax2
944 GPIO-13 ADL0 load LSB addr
945 GPIO-14 ADL1 load MSB addr
946 GPIO-15 ~RDY from CiMax
947 GPIO-17 ~RD to CiMax
948 GPIO-18 ~WR to CiMax
949 */
950 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
951 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
952 cx_clear(GP0_IO, 0x00030004);
953 mdelay(100);/* reset delay */
954 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
955 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
956 /* GPIO-15 IN as ~ACK, rest as OUT */
957 cx_write(MC417_OEN, 0x00001000);
958 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
959 cx_write(MC417_RWD, 0x0000c300);
960 /* enable irq */
961 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
962 break;
963 case CX23885_BOARD_HAUPPAUGE_HVR1270:
964 case CX23885_BOARD_HAUPPAUGE_HVR1275:
965 case CX23885_BOARD_HAUPPAUGE_HVR1255:
966 case CX23885_BOARD_HAUPPAUGE_HVR1210:
967 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
968 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
969 /* GPIO-9 Demod reset */
970
971 /* Put the parts into reset and back */
972 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
973 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
974 cx23885_gpio_clear(dev, GPIO_9);
975 mdelay(20);
976 cx23885_gpio_set(dev, GPIO_9);
977 break;
978 case CX23885_BOARD_MYGICA_X8506:
979 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
980 /* GPIO-0 (0)Analog / (1)Digital TV */
981 /* GPIO-1 reset XC5000 */
982 /* GPIO-2 reset LGS8GL5 / LGS8G75 */
983 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
984 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
985 mdelay(100);
986 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
987 mdelay(100);
988 break;
989 case CX23885_BOARD_MYGICA_X8558PRO:
990 /* GPIO-0 reset first ATBM8830 */
991 /* GPIO-1 reset second ATBM8830 */
992 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
993 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
994 mdelay(100);
995 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
996 mdelay(100);
997 break;
998 case CX23885_BOARD_HAUPPAUGE_HVR1850:
999 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1000 /* GPIO-0 656_CLK */
1001 /* GPIO-1 656_D0 */
1002 /* GPIO-2 Wake# */
1003 /* GPIO-3-10 cx23417 data0-7 */
1004 /* GPIO-11-14 cx23417 addr0-3 */
1005 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1006 /* GPIO-19 IR_RX */
1007 /* GPIO-20 C_IR_TX */
1008 /* GPIO-21 I2S DAT */
1009 /* GPIO-22 I2S WCLK */
1010 /* GPIO-23 I2S BCLK */
1011 /* ALT GPIO: EXP GPIO LATCH */
1012
1013 /* CX23417 GPIO's */
1014 /* GPIO-14 S5H1411/CX24228 Reset */
1015 /* GPIO-13 EEPROM write protect */
1016 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1017
1018 /* Put the demod into reset and protect the eeprom */
1019 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1020 mdelay(100);
1021
1022 /* Bring the demod out of reset */
1023 mc417_gpio_set(dev, GPIO_14);
1024 mdelay(100);
1025
1026 /* CX24228 GPIO */
1027 /* Connected to IF / Mux */
1028 break;
1029 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1030 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1031 break;
1032 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1033 /* GPIO-0 ~INT in
1034 GPIO-1 TMS out
1035 GPIO-2 ~reset chips out
1036 GPIO-3 to GPIO-10 data/addr for CA in/out
1037 GPIO-11 ~CS out
1038 GPIO-12 ADDR out
1039 GPIO-13 ~WR out
1040 GPIO-14 ~RD out
1041 GPIO-15 ~RDY in
1042 GPIO-16 TCK out
1043 GPIO-17 TDO in
1044 GPIO-18 TDI out
1045 */
1046 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1047 /* GPIO-0 as INT, reset & TMS low */
1048 cx_clear(GP0_IO, 0x00010006);
1049 mdelay(100);/* reset delay */
1050 cx_set(GP0_IO, 0x00000004); /* reset high */
1051 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1052 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1053 cx_write(MC417_OEN, 0x00005000);
1054 /* ~RD, ~WR high; ADDR low; ~CS high */
1055 cx_write(MC417_RWD, 0x00000d00);
1056 /* enable irq */
1057 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1058 break;
1059 }
1060 }
1061
1062 int cx23885_ir_init(struct cx23885_dev *dev)
1063 {
1064 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1065 {
1066 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1067 .pin = CX23885_PIN_IR_RX_GPIO19,
1068 .function = CX23885_PAD_IR_RX,
1069 .value = 0,
1070 .strength = CX25840_PIN_DRIVE_MEDIUM,
1071 }, {
1072 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1073 .pin = CX23885_PIN_IR_TX_GPIO20,
1074 .function = CX23885_PAD_IR_TX,
1075 .value = 0,
1076 .strength = CX25840_PIN_DRIVE_MEDIUM,
1077 }
1078 };
1079 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1080
1081 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1082 {
1083 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1084 .pin = CX23885_PIN_IR_RX_GPIO19,
1085 .function = CX23885_PAD_IR_RX,
1086 .value = 0,
1087 .strength = CX25840_PIN_DRIVE_MEDIUM,
1088 }
1089 };
1090 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1091
1092 struct v4l2_subdev_ir_parameters params;
1093 int ret = 0;
1094 switch (dev->board) {
1095 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1096 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1097 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1098 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1099 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1100 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1101 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1102 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1103 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1104 /* FIXME: Implement me */
1105 break;
1106 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1107 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1108 ret = cx23888_ir_probe(dev);
1109 if (ret)
1110 break;
1111 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1112 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1113 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1114 /*
1115 * For these boards we need to invert the Tx output via the
1116 * IR controller to have the LED off while idle
1117 */
1118 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1119 params.enable = false;
1120 params.shutdown = false;
1121 params.invert_level = true;
1122 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1123 params.shutdown = true;
1124 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1125 break;
1126 case CX23885_BOARD_TEVII_S470:
1127 if (!enable_885_ir)
1128 break;
1129 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1130 if (dev->sd_ir == NULL) {
1131 ret = -ENODEV;
1132 break;
1133 }
1134 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1135 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1136 break;
1137 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1138 if (!enable_885_ir)
1139 break;
1140 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1141 if (dev->sd_ir == NULL) {
1142 ret = -ENODEV;
1143 break;
1144 }
1145 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1146 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1147 break;
1148 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1149 request_module("ir-kbd-i2c");
1150 break;
1151 }
1152
1153 return ret;
1154 }
1155
1156 void cx23885_ir_fini(struct cx23885_dev *dev)
1157 {
1158 switch (dev->board) {
1159 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1160 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1161 cx23885_irq_remove(dev, PCI_MSK_IR);
1162 cx23888_ir_remove(dev);
1163 dev->sd_ir = NULL;
1164 break;
1165 case CX23885_BOARD_TEVII_S470:
1166 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1167 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
1168 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1169 dev->sd_ir = NULL;
1170 break;
1171 }
1172 }
1173
1174 int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1175 {
1176 int data;
1177 int tdo = 0;
1178 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1179 /*TMS*/
1180 data = ((cx_read(GP0_IO)) & (~0x00000002));
1181 data |= (tms ? 0x00020002 : 0x00020000);
1182 cx_write(GP0_IO, data);
1183
1184 /*TDI*/
1185 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1186 data |= (tdi ? 0x00008000 : 0);
1187 cx_write(MC417_RWD, data);
1188 if (read_tdo)
1189 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1190
1191 cx_write(MC417_RWD, data | 0x00002000);
1192 udelay(1);
1193 /*TCK*/
1194 cx_write(MC417_RWD, data);
1195
1196 return tdo;
1197 }
1198
1199 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1200 {
1201 switch (dev->board) {
1202 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1203 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1204 if (dev->sd_ir)
1205 cx23885_irq_add_enable(dev, PCI_MSK_IR);
1206 break;
1207 case CX23885_BOARD_TEVII_S470:
1208 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1209 if (dev->sd_ir)
1210 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
1211 break;
1212 }
1213 }
1214
1215 void cx23885_card_setup(struct cx23885_dev *dev)
1216 {
1217 struct cx23885_tsport *ts1 = &dev->ts1;
1218 struct cx23885_tsport *ts2 = &dev->ts2;
1219
1220 static u8 eeprom[256];
1221
1222 if (dev->i2c_bus[0].i2c_rc == 0) {
1223 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1224 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1225 eeprom, sizeof(eeprom));
1226 }
1227
1228 switch (dev->board) {
1229 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1230 if (dev->i2c_bus[0].i2c_rc == 0) {
1231 if (eeprom[0x80] != 0x84)
1232 hauppauge_eeprom(dev, eeprom+0xc0);
1233 else
1234 hauppauge_eeprom(dev, eeprom+0x80);
1235 }
1236 break;
1237 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1238 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1239 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1240 if (dev->i2c_bus[0].i2c_rc == 0)
1241 hauppauge_eeprom(dev, eeprom+0x80);
1242 break;
1243 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1244 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1245 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1246 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1247 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1248 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1249 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1250 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1251 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1252 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1253 if (dev->i2c_bus[0].i2c_rc == 0)
1254 hauppauge_eeprom(dev, eeprom+0xc0);
1255 break;
1256 }
1257
1258 switch (dev->board) {
1259 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1260 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1261 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1262 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1263 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1264 /* break omitted intentionally */
1265 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1266 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1267 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1268 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1269 break;
1270 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1271 /* Defaults for VID B - Analog encoder */
1272 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1273 ts1->gen_ctrl_val = 0x10e;
1274 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1275 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1276
1277 /* APB_TSVALERR_POL (active low)*/
1278 ts1->vld_misc_val = 0x2000;
1279 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
1280
1281 /* Defaults for VID C */
1282 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1283 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1284 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1285 break;
1286 case CX23885_BOARD_TBS_6920:
1287 ts1->gen_ctrl_val = 0x4; /* Parallel */
1288 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1289 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1290 break;
1291 case CX23885_BOARD_TEVII_S470:
1292 case CX23885_BOARD_DVBWORLD_2005:
1293 ts1->gen_ctrl_val = 0x5; /* Parallel */
1294 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1295 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1296 break;
1297 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1298 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1299 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1300 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1301 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1302 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1303 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1304 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1305 break;
1306 case CX23885_BOARD_MYGICA_X8506:
1307 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1308 ts1->gen_ctrl_val = 0x5; /* Parallel */
1309 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1310 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1311 break;
1312 case CX23885_BOARD_MYGICA_X8558PRO:
1313 ts1->gen_ctrl_val = 0x5; /* Parallel */
1314 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1315 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1316 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1317 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1318 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1319 break;
1320 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1321 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1322 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1323 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1324 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1325 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1326 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1327 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1328 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1329 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1330 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1331 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1332 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1333 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1334 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1335 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1336 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1337 default:
1338 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1339 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1340 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1341 }
1342
1343 /* Certain boards support analog, or require the avcore to be
1344 * loaded, ensure this happens.
1345 */
1346 switch (dev->board) {
1347 case CX23885_BOARD_TEVII_S470:
1348 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1349 /* Currently only enabled for the integrated IR controller */
1350 if (!enable_885_ir)
1351 break;
1352 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1353 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1354 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1355 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1356 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1357 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1358 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1359 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1360 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1361 case CX23885_BOARD_MYGICA_X8506:
1362 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1363 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1364 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1365 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1366 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1367 &dev->i2c_bus[2].i2c_adap,
1368 "cx25840", 0x88 >> 1, NULL);
1369 if (dev->sd_cx25840) {
1370 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1371 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1372 }
1373 break;
1374 }
1375
1376 /* AUX-PLL 27MHz CLK */
1377 switch (dev->board) {
1378 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1379 netup_initialize(dev);
1380 break;
1381 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1382 int ret;
1383 const struct firmware *fw;
1384 const char *filename = "dvb-netup-altera-01.fw";
1385 char *action = "configure";
1386 struct altera_config netup_config = {
1387 .dev = dev,
1388 .action = action,
1389 .jtag_io = netup_jtag_io,
1390 };
1391
1392 netup_initialize(dev);
1393
1394 ret = request_firmware(&fw, filename, &dev->pci->dev);
1395 if (ret != 0)
1396 printk(KERN_ERR "did not find the firmware file. (%s) "
1397 "Please see linux/Documentation/dvb/ for more details "
1398 "on firmware-problems.", filename);
1399 else
1400 altera_init(&netup_config, fw);
1401
1402 break;
1403 }
1404 }
1405 }
1406
1407 /* ------------------------------------------------------------------ */