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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / media / video / mx2_camera.c
blob4eab1c620318ef49c22aed6e2a208646b27f513c
1 /*
2 * V4L2 Driver for i.MX27/i.MX25 camera host
3 *
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/slab.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/errno.h>
20 #include <linux/fs.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/mm.h>
24 #include <linux/moduleparam.h>
25 #include <linux/time.h>
26 #include <linux/version.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/mutex.h>
30 #include <linux/clk.h>
31
32 #include <media/v4l2-common.h>
33 #include <media/v4l2-dev.h>
34 #include <media/videobuf-core.h>
35 #include <media/videobuf-dma-contig.h>
36 #include <media/soc_camera.h>
37 #include <media/soc_mediabus.h>
38
39 #include <linux/videodev2.h>
40
41 #include <mach/mx2_cam.h>
42 #ifdef CONFIG_MACH_MX27
43 #include <mach/dma-mx1-mx2.h>
44 #endif
45 #include <mach/hardware.h>
46
47 #include <asm/dma.h>
48
49 #define MX2_CAM_DRV_NAME "mx2-camera"
50 #define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
51 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
52
53 /* reset values */
54 #define CSICR1_RESET_VAL 0x40000800
55 #define CSICR2_RESET_VAL 0x0
56 #define CSICR3_RESET_VAL 0x0
57
58 /* csi control reg 1 */
59 #define CSICR1_SWAP16_EN (1 << 31)
60 #define CSICR1_EXT_VSYNC (1 << 30)
61 #define CSICR1_EOF_INTEN (1 << 29)
62 #define CSICR1_PRP_IF_EN (1 << 28)
63 #define CSICR1_CCIR_MODE (1 << 27)
64 #define CSICR1_COF_INTEN (1 << 26)
65 #define CSICR1_SF_OR_INTEN (1 << 25)
66 #define CSICR1_RF_OR_INTEN (1 << 24)
67 #define CSICR1_STATFF_LEVEL (3 << 22)
68 #define CSICR1_STATFF_INTEN (1 << 21)
69 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
70 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
71 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
72 #define CSICR1_RXFF_INTEN (1 << 18)
73 #define CSICR1_SOF_POL (1 << 17)
74 #define CSICR1_SOF_INTEN (1 << 16)
75 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
76 #define CSICR1_HSYNC_POL (1 << 11)
77 #define CSICR1_CCIR_EN (1 << 10)
78 #define CSICR1_MCLKEN (1 << 9)
79 #define CSICR1_FCC (1 << 8)
80 #define CSICR1_PACK_DIR (1 << 7)
81 #define CSICR1_CLR_STATFIFO (1 << 6)
82 #define CSICR1_CLR_RXFIFO (1 << 5)
83 #define CSICR1_GCLK_MODE (1 << 4)
84 #define CSICR1_INV_DATA (1 << 3)
85 #define CSICR1_INV_PCLK (1 << 2)
86 #define CSICR1_REDGE (1 << 1)
87
88 #define SHIFT_STATFF_LEVEL 22
89 #define SHIFT_RXFF_LEVEL 19
90 #define SHIFT_MCLKDIV 12
91
92 /* control reg 3 */
93 #define CSICR3_FRMCNT (0xFFFF << 16)
94 #define CSICR3_FRMCNT_RST (1 << 15)
95 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
96 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
97 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
98 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
99 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
100 #define CSICR3_CSI_SUP (1 << 3)
101 #define CSICR3_ZERO_PACK_EN (1 << 2)
102 #define CSICR3_ECC_INT_EN (1 << 1)
103 #define CSICR3_ECC_AUTO_EN (1 << 0)
104
105 #define SHIFT_FRMCNT 16
106
107 /* csi status reg */
108 #define CSISR_SFF_OR_INT (1 << 25)
109 #define CSISR_RFF_OR_INT (1 << 24)
110 #define CSISR_STATFF_INT (1 << 21)
111 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
112 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
113 #define CSISR_RXFF_INT (1 << 18)
114 #define CSISR_EOF_INT (1 << 17)
115 #define CSISR_SOF_INT (1 << 16)
116 #define CSISR_F2_INT (1 << 15)
117 #define CSISR_F1_INT (1 << 14)
118 #define CSISR_COF_INT (1 << 13)
119 #define CSISR_ECC_INT (1 << 1)
120 #define CSISR_DRDY (1 << 0)
121
122 #define CSICR1 0x00
123 #define CSICR2 0x04
124 #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
125 #define CSISTATFIFO 0x0c
126 #define CSIRFIFO 0x10
127 #define CSIRXCNT 0x14
128 #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
129 #define CSIDMASA_STATFIFO 0x20
130 #define CSIDMATA_STATFIFO 0x24
131 #define CSIDMASA_FB1 0x28
132 #define CSIDMASA_FB2 0x2c
133 #define CSIFBUF_PARA 0x30
134 #define CSIIMAG_PARA 0x34
135
136 /* EMMA PrP */
137 #define PRP_CNTL 0x00
138 #define PRP_INTR_CNTL 0x04
139 #define PRP_INTRSTATUS 0x08
140 #define PRP_SOURCE_Y_PTR 0x0c
141 #define PRP_SOURCE_CB_PTR 0x10
142 #define PRP_SOURCE_CR_PTR 0x14
143 #define PRP_DEST_RGB1_PTR 0x18
144 #define PRP_DEST_RGB2_PTR 0x1c
145 #define PRP_DEST_Y_PTR 0x20
146 #define PRP_DEST_CB_PTR 0x24
147 #define PRP_DEST_CR_PTR 0x28
148 #define PRP_SRC_FRAME_SIZE 0x2c
149 #define PRP_DEST_CH1_LINE_STRIDE 0x30
150 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
151 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
152 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
153 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
154 #define PRP_SRC_LINE_STRIDE 0x44
155 #define PRP_CSC_COEF_012 0x48
156 #define PRP_CSC_COEF_345 0x4c
157 #define PRP_CSC_COEF_678 0x50
158 #define PRP_CH1_RZ_HORI_COEF1 0x54
159 #define PRP_CH1_RZ_HORI_COEF2 0x58
160 #define PRP_CH1_RZ_HORI_VALID 0x5c
161 #define PRP_CH1_RZ_VERT_COEF1 0x60
162 #define PRP_CH1_RZ_VERT_COEF2 0x64
163 #define PRP_CH1_RZ_VERT_VALID 0x68
164 #define PRP_CH2_RZ_HORI_COEF1 0x6c
165 #define PRP_CH2_RZ_HORI_COEF2 0x70
166 #define PRP_CH2_RZ_HORI_VALID 0x74
167 #define PRP_CH2_RZ_VERT_COEF1 0x78
168 #define PRP_CH2_RZ_VERT_COEF2 0x7c
169 #define PRP_CH2_RZ_VERT_VALID 0x80
170
171 #define PRP_CNTL_CH1EN (1 << 0)
172 #define PRP_CNTL_CH2EN (1 << 1)
173 #define PRP_CNTL_CSIEN (1 << 2)
174 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
175 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
176 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
177 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
178 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
179 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
180 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
181 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
182 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
183 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
184 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
185 #define PRP_CNTL_CH1_LEN (1 << 9)
186 #define PRP_CNTL_CH2_LEN (1 << 10)
187 #define PRP_CNTL_SKIP_FRAME (1 << 11)
188 #define PRP_CNTL_SWRST (1 << 12)
189 #define PRP_CNTL_CLKEN (1 << 13)
190 #define PRP_CNTL_WEN (1 << 14)
191 #define PRP_CNTL_CH1BYP (1 << 15)
192 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
193 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
194 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
195 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
196 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
197 #define PRP_CNTL_CH2B1EN (1 << 29)
198 #define PRP_CNTL_CH2B2EN (1 << 30)
199 #define PRP_CNTL_CH2FEN (1 << 31)
200
201 /* IRQ Enable and status register */
202 #define PRP_INTR_RDERR (1 << 0)
203 #define PRP_INTR_CH1WERR (1 << 1)
204 #define PRP_INTR_CH2WERR (1 << 2)
205 #define PRP_INTR_CH1FC (1 << 3)
206 #define PRP_INTR_CH2FC (1 << 5)
207 #define PRP_INTR_LBOVF (1 << 7)
208 #define PRP_INTR_CH2OVF (1 << 8)
209
210 #define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma)
211
212 #define MAX_VIDEO_MEM 16
213
214 struct mx2_camera_dev {
215 struct device *dev;
216 struct soc_camera_host soc_host;
217 struct soc_camera_device *icd;
218 struct clk *clk_csi, *clk_emma;
219
220 unsigned int irq_csi, irq_emma;
221 void __iomem *base_csi, *base_emma;
222 unsigned long base_dma;
223
224 struct mx2_camera_platform_data *pdata;
225 struct resource *res_csi, *res_emma;
226 unsigned long platform_flags;
227
228 struct list_head capture;
229 struct list_head active_bufs;
230
231 spinlock_t lock;
232
233 int dma;
234 struct mx2_buffer *active;
235 struct mx2_buffer *fb1_active;
236 struct mx2_buffer *fb2_active;
237
238 int use_emma;
239
240 u32 csicr1;
241
242 void *discard_buffer;
243 dma_addr_t discard_buffer_dma;
244 size_t discard_size;
245 };
246
247 /* buffer for one video frame */
248 struct mx2_buffer {
249 /* common v4l buffer stuff -- must be first */
250 struct videobuf_buffer vb;
251
252 enum v4l2_mbus_pixelcode code;
253
254 int bufnum;
255 };
256
257 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
258 {
259 unsigned long flags;
260
261 clk_disable(pcdev->clk_csi);
262 writel(0, pcdev->base_csi + CSICR1);
263 if (mx27_camera_emma(pcdev)) {
264 writel(0, pcdev->base_emma + PRP_CNTL);
265 } else if (cpu_is_mx25()) {
266 spin_lock_irqsave(&pcdev->lock, flags);
267 pcdev->fb1_active = NULL;
268 pcdev->fb2_active = NULL;
269 writel(0, pcdev->base_csi + CSIDMASA_FB1);
270 writel(0, pcdev->base_csi + CSIDMASA_FB2);
271 spin_unlock_irqrestore(&pcdev->lock, flags);
272 }
273 }
274
275 /*
276 * The following two functions absolutely depend on the fact, that
277 * there can be only one camera on mx2 camera sensor interface
278 */
279 static int mx2_camera_add_device(struct soc_camera_device *icd)
280 {
281 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
282 struct mx2_camera_dev *pcdev = ici->priv;
283 int ret;
284 u32 csicr1;
285
286 if (pcdev->icd)
287 return -EBUSY;
288
289 ret = clk_enable(pcdev->clk_csi);
290 if (ret < 0)
291 return ret;
292
293 csicr1 = CSICR1_MCLKEN;
294
295 if (mx27_camera_emma(pcdev)) {
296 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
297 CSICR1_RXFF_LEVEL(0);
298 } else if (cpu_is_mx27())
299 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
300
301 pcdev->csicr1 = csicr1;
302 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
303
304 pcdev->icd = icd;
305
306 dev_info(icd->dev.parent, "Camera driver attached to camera %d\n",
307 icd->devnum);
308
309 return 0;
310 }
311
312 static void mx2_camera_remove_device(struct soc_camera_device *icd)
313 {
314 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
315 struct mx2_camera_dev *pcdev = ici->priv;
316
317 BUG_ON(icd != pcdev->icd);
318
319 dev_info(icd->dev.parent, "Camera driver detached from camera %d\n",
320 icd->devnum);
321
322 mx2_camera_deactivate(pcdev);
323
324 if (pcdev->discard_buffer) {
325 dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size,
326 pcdev->discard_buffer,
327 pcdev->discard_buffer_dma);
328 pcdev->discard_buffer = NULL;
329 }
330
331 pcdev->icd = NULL;
332 }
333
334 #ifdef CONFIG_MACH_MX27
335 static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev)
336 {
337 u32 tmp;
338
339 imx_dma_enable(pcdev->dma);
340
341 tmp = readl(pcdev->base_csi + CSICR1);
342 tmp |= CSICR1_RF_OR_INTEN;
343 writel(tmp, pcdev->base_csi + CSICR1);
344 }
345
346 static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
347 {
348 struct mx2_camera_dev *pcdev = data;
349 u32 status = readl(pcdev->base_csi + CSISR);
350
351 if (status & CSISR_SOF_INT && pcdev->active) {
352 u32 tmp;
353
354 tmp = readl(pcdev->base_csi + CSICR1);
355 writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1);
356 mx27_camera_dma_enable(pcdev);
357 }
358
359 writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR);
360
361 return IRQ_HANDLED;
362 }
363 #else
364 static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
365 {
366 return IRQ_NONE;
367 }
368 #endif /* CONFIG_MACH_MX27 */
369
370 static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
371 int state)
372 {
373 struct videobuf_buffer *vb;
374 struct mx2_buffer *buf;
375 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
376 &pcdev->fb2_active;
377 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
378 unsigned long flags;
379
380 spin_lock_irqsave(&pcdev->lock, flags);
381
382 if (*fb_active == NULL)
383 goto out;
384
385 vb = &(*fb_active)->vb;
386 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
387 vb, vb->baddr, vb->bsize);
388
389 vb->state = state;
390 do_gettimeofday(&vb->ts);
391 vb->field_count++;
392
393 wake_up(&vb->done);
394
395 if (list_empty(&pcdev->capture)) {
396 buf = NULL;
397 writel(0, pcdev->base_csi + fb_reg);
398 } else {
399 buf = list_entry(pcdev->capture.next, struct mx2_buffer,
400 vb.queue);
401 vb = &buf->vb;
402 list_del(&vb->queue);
403 vb->state = VIDEOBUF_ACTIVE;
404 writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg);
405 }
406
407 *fb_active = buf;
408
409 out:
410 spin_unlock_irqrestore(&pcdev->lock, flags);
411 }
412
413 static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
414 {
415 struct mx2_camera_dev *pcdev = data;
416 u32 status = readl(pcdev->base_csi + CSISR);
417
418 if (status & CSISR_DMA_TSF_FB1_INT)
419 mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE);
420 else if (status & CSISR_DMA_TSF_FB2_INT)
421 mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE);
422
423 /* FIXME: handle CSISR_RFF_OR_INT */
424
425 writel(status, pcdev->base_csi + CSISR);
426
427 return IRQ_HANDLED;
428 }
429
430 /*
431 * Videobuf operations
432 */
433 static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
434 unsigned int *size)
435 {
436 struct soc_camera_device *icd = vq->priv_data;
437 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
438 icd->current_fmt->host_fmt);
439
440 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
441
442 if (bytes_per_line < 0)
443 return bytes_per_line;
444
445 *size = bytes_per_line * icd->user_height;
446
447 if (0 == *count)
448 *count = 32;
449 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
450 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size;
451
452 return 0;
453 }
454
455 static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf)
456 {
457 struct soc_camera_device *icd = vq->priv_data;
458 struct videobuf_buffer *vb = &buf->vb;
459
460 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
461 vb, vb->baddr, vb->bsize);
462
463 /*
464 * This waits until this buffer is out of danger, i.e., until it is no
465 * longer in state VIDEOBUF_QUEUED or VIDEOBUF_ACTIVE
466 */
467 videobuf_waiton(vq, vb, 0, 0);
468
469 videobuf_dma_contig_free(vq, vb);
470 dev_dbg(&icd->dev, "%s freed\n", __func__);
471
472 vb->state = VIDEOBUF_NEEDS_INIT;
473 }
474
475 static int mx2_videobuf_prepare(struct videobuf_queue *vq,
476 struct videobuf_buffer *vb, enum v4l2_field field)
477 {
478 struct soc_camera_device *icd = vq->priv_data;
479 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
480 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
481 icd->current_fmt->host_fmt);
482 int ret = 0;
483
484 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
485 vb, vb->baddr, vb->bsize);
486
487 if (bytes_per_line < 0)
488 return bytes_per_line;
489
490 #ifdef DEBUG
491 /*
492 * This can be useful if you want to see if we actually fill
493 * the buffer with something
494 */
495 memset((void *)vb->baddr, 0xaa, vb->bsize);
496 #endif
497
498 if (buf->code != icd->current_fmt->code ||
499 vb->width != icd->user_width ||
500 vb->height != icd->user_height ||
501 vb->field != field) {
502 buf->code = icd->current_fmt->code;
503 vb->width = icd->user_width;
504 vb->height = icd->user_height;
505 vb->field = field;
506 vb->state = VIDEOBUF_NEEDS_INIT;
507 }
508
509 vb->size = bytes_per_line * vb->height;
510 if (vb->baddr && vb->bsize < vb->size) {
511 ret = -EINVAL;
512 goto out;
513 }
514
515 if (vb->state == VIDEOBUF_NEEDS_INIT) {
516 ret = videobuf_iolock(vq, vb, NULL);
517 if (ret)
518 goto fail;
519
520 vb->state = VIDEOBUF_PREPARED;
521 }
522
523 return 0;
524
525 fail:
526 free_buffer(vq, buf);
527 out:
528 return ret;
529 }
530
531 static void mx2_videobuf_queue(struct videobuf_queue *vq,
532 struct videobuf_buffer *vb)
533 {
534 struct soc_camera_device *icd = vq->priv_data;
535 struct soc_camera_host *ici =
536 to_soc_camera_host(icd->dev.parent);
537 struct mx2_camera_dev *pcdev = ici->priv;
538 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
539 unsigned long flags;
540
541 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
542 vb, vb->baddr, vb->bsize);
543
544 spin_lock_irqsave(&pcdev->lock, flags);
545
546 vb->state = VIDEOBUF_QUEUED;
547 list_add_tail(&vb->queue, &pcdev->capture);
548
549 if (mx27_camera_emma(pcdev)) {
550 goto out;
551 #ifdef CONFIG_MACH_MX27
552 } else if (cpu_is_mx27()) {
553 int ret;
554
555 if (pcdev->active == NULL) {
556 ret = imx_dma_setup_single(pcdev->dma,
557 videobuf_to_dma_contig(vb), vb->size,
558 (u32)pcdev->base_dma + 0x10,
559 DMA_MODE_READ);
560 if (ret) {
561 vb->state = VIDEOBUF_ERROR;
562 wake_up(&vb->done);
563 goto out;
564 }
565
566 vb->state = VIDEOBUF_ACTIVE;
567 pcdev->active = buf;
568 }
569 #endif
570 } else { /* cpu_is_mx25() */
571 u32 csicr3, dma_inten = 0;
572
573 if (pcdev->fb1_active == NULL) {
574 writel(videobuf_to_dma_contig(vb),
575 pcdev->base_csi + CSIDMASA_FB1);
576 pcdev->fb1_active = buf;
577 dma_inten = CSICR1_FB1_DMA_INTEN;
578 } else if (pcdev->fb2_active == NULL) {
579 writel(videobuf_to_dma_contig(vb),
580 pcdev->base_csi + CSIDMASA_FB2);
581 pcdev->fb2_active = buf;
582 dma_inten = CSICR1_FB2_DMA_INTEN;
583 }
584
585 if (dma_inten) {
586 list_del(&vb->queue);
587 vb->state = VIDEOBUF_ACTIVE;
588
589 csicr3 = readl(pcdev->base_csi + CSICR3);
590
591 /* Reflash DMA */
592 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
593 pcdev->base_csi + CSICR3);
594
595 /* clear & enable interrupts */
596 writel(dma_inten, pcdev->base_csi + CSISR);
597 pcdev->csicr1 |= dma_inten;
598 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
599
600 /* enable DMA */
601 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
602 writel(csicr3, pcdev->base_csi + CSICR3);
603 }
604 }
605
606 out:
607 spin_unlock_irqrestore(&pcdev->lock, flags);
608 }
609
610 static void mx2_videobuf_release(struct videobuf_queue *vq,
611 struct videobuf_buffer *vb)
612 {
613 struct soc_camera_device *icd = vq->priv_data;
614 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
615 struct mx2_camera_dev *pcdev = ici->priv;
616 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
617 unsigned long flags;
618
619 #ifdef DEBUG
620 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
621 vb, vb->baddr, vb->bsize);
622
623 switch (vb->state) {
624 case VIDEOBUF_ACTIVE:
625 dev_info(&icd->dev, "%s (active)\n", __func__);
626 break;
627 case VIDEOBUF_QUEUED:
628 dev_info(&icd->dev, "%s (queued)\n", __func__);
629 break;
630 case VIDEOBUF_PREPARED:
631 dev_info(&icd->dev, "%s (prepared)\n", __func__);
632 break;
633 default:
634 dev_info(&icd->dev, "%s (unknown) %d\n", __func__,
635 vb->state);
636 break;
637 }
638 #endif
639
640 /*
641 * Terminate only queued but inactive buffers. Active buffers are
642 * released when they become inactive after videobuf_waiton().
643 *
644 * FIXME: implement forced termination of active buffers for mx27 and
645 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
646 * state. This requires a specific handling for each of the these DMA
647 * types.
648 */
649 spin_lock_irqsave(&pcdev->lock, flags);
650 if (vb->state == VIDEOBUF_QUEUED) {
651 list_del(&vb->queue);
652 vb->state = VIDEOBUF_ERROR;
653 } else if (cpu_is_mx25() && vb->state == VIDEOBUF_ACTIVE) {
654 if (pcdev->fb1_active == buf) {
655 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
656 writel(0, pcdev->base_csi + CSIDMASA_FB1);
657 pcdev->fb1_active = NULL;
658 } else if (pcdev->fb2_active == buf) {
659 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
660 writel(0, pcdev->base_csi + CSIDMASA_FB2);
661 pcdev->fb2_active = NULL;
662 }
663 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
664 vb->state = VIDEOBUF_ERROR;
665 }
666 spin_unlock_irqrestore(&pcdev->lock, flags);
667
668 free_buffer(vq, buf);
669 }
670
671 static struct videobuf_queue_ops mx2_videobuf_ops = {
672 .buf_setup = mx2_videobuf_setup,
673 .buf_prepare = mx2_videobuf_prepare,
674 .buf_queue = mx2_videobuf_queue,
675 .buf_release = mx2_videobuf_release,
676 };
677
678 static void mx2_camera_init_videobuf(struct videobuf_queue *q,
679 struct soc_camera_device *icd)
680 {
681 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
682 struct mx2_camera_dev *pcdev = ici->priv;
683
684 videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev,
685 &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE,
686 V4L2_FIELD_NONE, sizeof(struct mx2_buffer),
687 icd, &icd->video_lock);
688 }
689
690 #define MX2_BUS_FLAGS (SOCAM_DATAWIDTH_8 | \
691 SOCAM_MASTER | \
692 SOCAM_VSYNC_ACTIVE_HIGH | \
693 SOCAM_VSYNC_ACTIVE_LOW | \
694 SOCAM_HSYNC_ACTIVE_HIGH | \
695 SOCAM_HSYNC_ACTIVE_LOW | \
696 SOCAM_PCLK_SAMPLE_RISING | \
697 SOCAM_PCLK_SAMPLE_FALLING | \
698 SOCAM_DATA_ACTIVE_HIGH | \
699 SOCAM_DATA_ACTIVE_LOW)
700
701 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
702 {
703 u32 cntl;
704 int count = 0;
705
706 cntl = readl(pcdev->base_emma + PRP_CNTL);
707 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
708 while (count++ < 100) {
709 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
710 return 0;
711 barrier();
712 udelay(1);
713 }
714
715 return -ETIMEDOUT;
716 }
717
718 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
719 int bytesperline)
720 {
721 struct soc_camera_host *ici =
722 to_soc_camera_host(icd->dev.parent);
723 struct mx2_camera_dev *pcdev = ici->priv;
724
725 writel(pcdev->discard_buffer_dma,
726 pcdev->base_emma + PRP_DEST_RGB1_PTR);
727 writel(pcdev->discard_buffer_dma,
728 pcdev->base_emma + PRP_DEST_RGB2_PTR);
729
730 /*
731 * We only use the EMMA engine to get rid of the broken
732 * DMA Engine. No color space consversion at the moment.
733 * We set the incomming and outgoing pixelformat to an
734 * 16 Bit wide format and adjust the bytesperline
735 * accordingly. With this configuration the inputdata
736 * will not be changed by the emma and could be any type
737 * of 16 Bit Pixelformat.
738 */
739 writel(PRP_CNTL_CH1EN |
740 PRP_CNTL_CSIEN |
741 PRP_CNTL_DATA_IN_RGB16 |
742 PRP_CNTL_CH1_OUT_RGB16 |
743 PRP_CNTL_CH1_LEN |
744 PRP_CNTL_CH1BYP |
745 PRP_CNTL_CH1_TSKIP(0) |
746 PRP_CNTL_IN_TSKIP(0),
747 pcdev->base_emma + PRP_CNTL);
748
749 writel(((bytesperline >> 1) << 16) | icd->user_height,
750 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
751 writel(((bytesperline >> 1) << 16) | icd->user_height,
752 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
753 writel(bytesperline,
754 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
755 writel(0x2ca00565, /* RGB565 */
756 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
757 writel(0x2ca00565, /* RGB565 */
758 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
759
760 /* Enable interrupts */
761 writel(PRP_INTR_RDERR |
762 PRP_INTR_CH1WERR |
763 PRP_INTR_CH2WERR |
764 PRP_INTR_CH1FC |
765 PRP_INTR_CH2FC |
766 PRP_INTR_LBOVF |
767 PRP_INTR_CH2OVF,
768 pcdev->base_emma + PRP_INTR_CNTL);
769 }
770
771 static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
772 __u32 pixfmt)
773 {
774 struct soc_camera_host *ici =
775 to_soc_camera_host(icd->dev.parent);
776 struct mx2_camera_dev *pcdev = ici->priv;
777 unsigned long camera_flags, common_flags;
778 int ret = 0;
779 int bytesperline;
780 u32 csicr1 = pcdev->csicr1;
781
782 camera_flags = icd->ops->query_bus_param(icd);
783
784 common_flags = soc_camera_bus_param_compatible(camera_flags,
785 MX2_BUS_FLAGS);
786 if (!common_flags)
787 return -EINVAL;
788
789 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
790 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
791 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
792 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
793 else
794 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
795 }
796
797 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
798 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
799 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
800 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
801 else
802 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
803 }
804
805 ret = icd->ops->set_bus_param(icd, common_flags);
806 if (ret < 0)
807 return ret;
808
809 if (common_flags & SOCAM_PCLK_SAMPLE_RISING)
810 csicr1 |= CSICR1_REDGE;
811 if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH)
812 csicr1 |= CSICR1_SOF_POL;
813 if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH)
814 csicr1 |= CSICR1_HSYNC_POL;
815 if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
816 csicr1 |= CSICR1_SWAP16_EN;
817 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
818 csicr1 |= CSICR1_EXT_VSYNC;
819 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
820 csicr1 |= CSICR1_CCIR_EN;
821 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
822 csicr1 |= CSICR1_CCIR_MODE;
823 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
824 csicr1 |= CSICR1_GCLK_MODE;
825 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
826 csicr1 |= CSICR1_INV_DATA;
827 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
828 csicr1 |= CSICR1_PACK_DIR;
829
830 pcdev->csicr1 = csicr1;
831
832 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
833 icd->current_fmt->host_fmt);
834 if (bytesperline < 0)
835 return bytesperline;
836
837 if (mx27_camera_emma(pcdev)) {
838 ret = mx27_camera_emma_prp_reset(pcdev);
839 if (ret)
840 return ret;
841
842 if (pcdev->discard_buffer)
843 dma_free_coherent(ici->v4l2_dev.dev,
844 pcdev->discard_size, pcdev->discard_buffer,
845 pcdev->discard_buffer_dma);
846
847 /*
848 * I didn't manage to properly enable/disable the prp
849 * on a per frame basis during running transfers,
850 * thus we allocate a buffer here and use it to
851 * discard frames when no buffer is available.
852 * Feel free to work on this ;)
853 */
854 pcdev->discard_size = icd->user_height * bytesperline;
855 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
856 pcdev->discard_size, &pcdev->discard_buffer_dma,
857 GFP_KERNEL);
858 if (!pcdev->discard_buffer)
859 return -ENOMEM;
860
861 mx27_camera_emma_buf_init(icd, bytesperline);
862 } else if (cpu_is_mx25()) {
863 writel((bytesperline * icd->user_height) >> 2,
864 pcdev->base_csi + CSIRXCNT);
865 writel((bytesperline << 16) | icd->user_height,
866 pcdev->base_csi + CSIIMAG_PARA);
867 }
868
869 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
870
871 return 0;
872 }
873
874 static int mx2_camera_set_crop(struct soc_camera_device *icd,
875 struct v4l2_crop *a)
876 {
877 struct v4l2_rect *rect = &a->c;
878 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
879 struct v4l2_mbus_framefmt mf;
880 int ret;
881
882 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
883 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
884
885 ret = v4l2_subdev_call(sd, video, s_crop, a);
886 if (ret < 0)
887 return ret;
888
889 /* The capture device might have changed its output */
890 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
891 if (ret < 0)
892 return ret;
893
894 dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n",
895 mf.width, mf.height);
896
897 icd->user_width = mf.width;
898 icd->user_height = mf.height;
899
900 return ret;
901 }
902
903 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
904 struct v4l2_format *f)
905 {
906 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
907 const struct soc_camera_format_xlate *xlate;
908 struct v4l2_pix_format *pix = &f->fmt.pix;
909 struct v4l2_mbus_framefmt mf;
910 int ret;
911
912 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
913 if (!xlate) {
914 dev_warn(icd->dev.parent, "Format %x not found\n",
915 pix->pixelformat);
916 return -EINVAL;
917 }
918
919 mf.width = pix->width;
920 mf.height = pix->height;
921 mf.field = pix->field;
922 mf.colorspace = pix->colorspace;
923 mf.code = xlate->code;
924
925 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
926 if (ret < 0 && ret != -ENOIOCTLCMD)
927 return ret;
928
929 if (mf.code != xlate->code)
930 return -EINVAL;
931
932 pix->width = mf.width;
933 pix->height = mf.height;
934 pix->field = mf.field;
935 pix->colorspace = mf.colorspace;
936 icd->current_fmt = xlate;
937
938 return 0;
939 }
940
941 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
942 struct v4l2_format *f)
943 {
944 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
945 const struct soc_camera_format_xlate *xlate;
946 struct v4l2_pix_format *pix = &f->fmt.pix;
947 struct v4l2_mbus_framefmt mf;
948 __u32 pixfmt = pix->pixelformat;
949 unsigned int width_limit;
950 int ret;
951
952 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
953 if (pixfmt && !xlate) {
954 dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
955 return -EINVAL;
956 }
957
958 /* FIXME: implement MX27 limits */
959
960 /* limit to MX25 hardware capabilities */
961 if (cpu_is_mx25()) {
962 if (xlate->host_fmt->bits_per_sample <= 8)
963 width_limit = 0xffff * 4;
964 else
965 width_limit = 0xffff * 2;
966 /* CSIIMAG_PARA limit */
967 if (pix->width > width_limit)
968 pix->width = width_limit;
969 if (pix->height > 0xffff)
970 pix->height = 0xffff;
971
972 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
973 xlate->host_fmt);
974 if (pix->bytesperline < 0)
975 return pix->bytesperline;
976 pix->sizeimage = pix->height * pix->bytesperline;
977 if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */
978 dev_warn(icd->dev.parent,
979 "Image size (%u) above limit\n",
980 pix->sizeimage);
981 return -EINVAL;
982 }
983 }
984
985 /* limit to sensor capabilities */
986 mf.width = pix->width;
987 mf.height = pix->height;
988 mf.field = pix->field;
989 mf.colorspace = pix->colorspace;
990 mf.code = xlate->code;
991
992 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
993 if (ret < 0)
994 return ret;
995
996 if (mf.field == V4L2_FIELD_ANY)
997 mf.field = V4L2_FIELD_NONE;
998 if (mf.field != V4L2_FIELD_NONE) {
999 dev_err(icd->dev.parent, "Field type %d unsupported.\n",
1000 mf.field);
1001 return -EINVAL;
1002 }
1003
1004 pix->width = mf.width;
1005 pix->height = mf.height;
1006 pix->field = mf.field;
1007 pix->colorspace = mf.colorspace;
1008
1009 return 0;
1010 }
1011
1012 static int mx2_camera_querycap(struct soc_camera_host *ici,
1013 struct v4l2_capability *cap)
1014 {
1015 /* cap->name is set by the friendly caller:-> */
1016 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1017 cap->version = MX2_CAM_VERSION_CODE;
1018 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1019
1020 return 0;
1021 }
1022
1023 static int mx2_camera_reqbufs(struct soc_camera_device *icd,
1024 struct v4l2_requestbuffers *p)
1025 {
1026 int i;
1027
1028 for (i = 0; i < p->count; i++) {
1029 struct mx2_buffer *buf = container_of(icd->vb_vidq.bufs[i],
1030 struct mx2_buffer, vb);
1031 INIT_LIST_HEAD(&buf->vb.queue);
1032 }
1033
1034 return 0;
1035 }
1036
1037 #ifdef CONFIG_MACH_MX27
1038 static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state)
1039 {
1040 struct videobuf_buffer *vb;
1041 struct mx2_buffer *buf;
1042 unsigned long flags;
1043 int ret;
1044
1045 spin_lock_irqsave(&pcdev->lock, flags);
1046
1047 if (!pcdev->active) {
1048 dev_err(pcdev->dev, "%s called with no active buffer!\n",
1049 __func__);
1050 goto out;
1051 }
1052
1053 vb = &pcdev->active->vb;
1054 buf = container_of(vb, struct mx2_buffer, vb);
1055 WARN_ON(list_empty(&vb->queue));
1056 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
1057 vb, vb->baddr, vb->bsize);
1058
1059 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
1060 list_del_init(&vb->queue);
1061 vb->state = state;
1062 do_gettimeofday(&vb->ts);
1063 vb->field_count++;
1064
1065 wake_up(&vb->done);
1066
1067 if (list_empty(&pcdev->capture)) {
1068 pcdev->active = NULL;
1069 goto out;
1070 }
1071
1072 pcdev->active = list_entry(pcdev->capture.next,
1073 struct mx2_buffer, vb.queue);
1074
1075 vb = &pcdev->active->vb;
1076 vb->state = VIDEOBUF_ACTIVE;
1077
1078 ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb),
1079 vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ);
1080
1081 if (ret) {
1082 vb->state = VIDEOBUF_ERROR;
1083 pcdev->active = NULL;
1084 wake_up(&vb->done);
1085 }
1086
1087 out:
1088 spin_unlock_irqrestore(&pcdev->lock, flags);
1089 }
1090
1091 static void mx27_camera_dma_err_callback(int channel, void *data, int err)
1092 {
1093 struct mx2_camera_dev *pcdev = data;
1094
1095 mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR);
1096 }
1097
1098 static void mx27_camera_dma_callback(int channel, void *data)
1099 {
1100 struct mx2_camera_dev *pcdev = data;
1101
1102 mx27_camera_frame_done(pcdev, VIDEOBUF_DONE);
1103 }
1104
1105 #define DMA_REQ_CSI_RX 31 /* FIXME: Add this to a resource */
1106
1107 static int __devinit mx27_camera_dma_init(struct platform_device *pdev,
1108 struct mx2_camera_dev *pcdev)
1109 {
1110 int err;
1111
1112 pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH);
1113 if (pcdev->dma < 0) {
1114 dev_err(&pdev->dev, "%s failed to request DMA channel\n",
1115 __func__);
1116 return pcdev->dma;
1117 }
1118
1119 err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback,
1120 mx27_camera_dma_err_callback, pcdev);
1121 if (err) {
1122 dev_err(&pdev->dev, "%s failed to set DMA callback\n",
1123 __func__);
1124 goto err_out;
1125 }
1126
1127 err = imx_dma_config_channel(pcdev->dma,
1128 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
1129 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
1130 DMA_REQ_CSI_RX, 1);
1131 if (err) {
1132 dev_err(&pdev->dev, "%s failed to config DMA channel\n",
1133 __func__);
1134 goto err_out;
1135 }
1136
1137 imx_dma_config_burstlen(pcdev->dma, 64);
1138
1139 return 0;
1140
1141 err_out:
1142 imx_dma_free(pcdev->dma);
1143
1144 return err;
1145 }
1146 #endif /* CONFIG_MACH_MX27 */
1147
1148 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1149 {
1150 struct soc_camera_device *icd = file->private_data;
1151
1152 return videobuf_poll_stream(file, &icd->vb_vidq, pt);
1153 }
1154
1155 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1156 .owner = THIS_MODULE,
1157 .add = mx2_camera_add_device,
1158 .remove = mx2_camera_remove_device,
1159 .set_fmt = mx2_camera_set_fmt,
1160 .set_crop = mx2_camera_set_crop,
1161 .try_fmt = mx2_camera_try_fmt,
1162 .init_videobuf = mx2_camera_init_videobuf,
1163 .reqbufs = mx2_camera_reqbufs,
1164 .poll = mx2_camera_poll,
1165 .querycap = mx2_camera_querycap,
1166 .set_bus_param = mx2_camera_set_bus_param,
1167 };
1168
1169 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1170 int bufnum, int state)
1171 {
1172 struct mx2_buffer *buf;
1173 struct videobuf_buffer *vb;
1174 unsigned long phys;
1175
1176 if (!list_empty(&pcdev->active_bufs)) {
1177 buf = list_entry(pcdev->active_bufs.next,
1178 struct mx2_buffer, vb.queue);
1179
1180 BUG_ON(buf->bufnum != bufnum);
1181
1182 vb = &buf->vb;
1183 #ifdef DEBUG
1184 phys = videobuf_to_dma_contig(vb);
1185 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum)
1186 != phys) {
1187 dev_err(pcdev->dev, "%p != %p\n", phys,
1188 readl(pcdev->base_emma +
1189 PRP_DEST_RGB1_PTR +
1190 4 * bufnum));
1191 }
1192 #endif
1193 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb,
1194 vb->baddr, vb->bsize);
1195
1196 list_del(&vb->queue);
1197 vb->state = state;
1198 do_gettimeofday(&vb->ts);
1199 vb->field_count++;
1200
1201 wake_up(&vb->done);
1202 }
1203
1204 if (list_empty(&pcdev->capture)) {
1205 writel(pcdev->discard_buffer_dma, pcdev->base_emma +
1206 PRP_DEST_RGB1_PTR + 4 * bufnum);
1207 return;
1208 }
1209
1210 buf = list_entry(pcdev->capture.next,
1211 struct mx2_buffer, vb.queue);
1212
1213 buf->bufnum = !bufnum;
1214
1215 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1216
1217 vb = &buf->vb;
1218 vb->state = VIDEOBUF_ACTIVE;
1219
1220 phys = videobuf_to_dma_contig(vb);
1221 writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum);
1222 }
1223
1224 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1225 {
1226 struct mx2_camera_dev *pcdev = data;
1227 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1228 struct mx2_buffer *buf;
1229
1230 if (status & (1 << 7)) { /* overflow */
1231 u32 cntl;
1232 /*
1233 * We only disable channel 1 here since this is the only
1234 * enabled channel
1235 *
1236 * FIXME: the correct DMA overflow handling should be resetting
1237 * the buffer, returning an error frame, and continuing with
1238 * the next one.
1239 */
1240 cntl = readl(pcdev->base_emma + PRP_CNTL);
1241 writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL);
1242 writel(cntl, pcdev->base_emma + PRP_CNTL);
1243 }
1244 if ((status & (3 << 5)) == (3 << 5)
1245 && !list_empty(&pcdev->active_bufs)) {
1246 /*
1247 * Both buffers have triggered, process the one we're expecting
1248 * to first
1249 */
1250 buf = list_entry(pcdev->active_bufs.next,
1251 struct mx2_buffer, vb.queue);
1252 mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE);
1253 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */
1254 }
1255 if (status & (1 << 6))
1256 mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
1257 if (status & (1 << 5))
1258 mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);
1259
1260 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1261
1262 return IRQ_HANDLED;
1263 }
1264
1265 static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
1266 {
1267 struct resource *res_emma = pcdev->res_emma;
1268 int err = 0;
1269
1270 if (!request_mem_region(res_emma->start, resource_size(res_emma),
1271 MX2_CAM_DRV_NAME)) {
1272 err = -EBUSY;
1273 goto out;
1274 }
1275
1276 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
1277 if (!pcdev->base_emma) {
1278 err = -ENOMEM;
1279 goto exit_release;
1280 }
1281
1282 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
1283 MX2_CAM_DRV_NAME, pcdev);
1284 if (err) {
1285 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1286 goto exit_iounmap;
1287 }
1288
1289 pcdev->clk_emma = clk_get(NULL, "emma");
1290 if (IS_ERR(pcdev->clk_emma)) {
1291 err = PTR_ERR(pcdev->clk_emma);
1292 goto exit_free_irq;
1293 }
1294
1295 clk_enable(pcdev->clk_emma);
1296
1297 err = mx27_camera_emma_prp_reset(pcdev);
1298 if (err)
1299 goto exit_clk_emma_put;
1300
1301 return err;
1302
1303 exit_clk_emma_put:
1304 clk_disable(pcdev->clk_emma);
1305 clk_put(pcdev->clk_emma);
1306 exit_free_irq:
1307 free_irq(pcdev->irq_emma, pcdev);
1308 exit_iounmap:
1309 iounmap(pcdev->base_emma);
1310 exit_release:
1311 release_mem_region(res_emma->start, resource_size(res_emma));
1312 out:
1313 return err;
1314 }
1315
1316 static int __devinit mx2_camera_probe(struct platform_device *pdev)
1317 {
1318 struct mx2_camera_dev *pcdev;
1319 struct resource *res_csi, *res_emma;
1320 void __iomem *base_csi;
1321 int irq_csi, irq_emma;
1322 irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq
1323 : mx27_camera_irq;
1324 int err = 0;
1325
1326 dev_dbg(&pdev->dev, "initialising\n");
1327
1328 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1329 irq_csi = platform_get_irq(pdev, 0);
1330 if (res_csi == NULL || irq_csi < 0) {
1331 dev_err(&pdev->dev, "Missing platform resources data\n");
1332 err = -ENODEV;
1333 goto exit;
1334 }
1335
1336 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1337 if (!pcdev) {
1338 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1339 err = -ENOMEM;
1340 goto exit;
1341 }
1342
1343 pcdev->clk_csi = clk_get(&pdev->dev, NULL);
1344 if (IS_ERR(pcdev->clk_csi)) {
1345 err = PTR_ERR(pcdev->clk_csi);
1346 goto exit_kfree;
1347 }
1348
1349 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n",
1350 clk_get_rate(pcdev->clk_csi));
1351
1352 /* Initialize DMA */
1353 #ifdef CONFIG_MACH_MX27
1354 if (cpu_is_mx27()) {
1355 err = mx27_camera_dma_init(pdev, pcdev);
1356 if (err)
1357 goto exit_clk_put;
1358 }
1359 #endif /* CONFIG_MACH_MX27 */
1360
1361 pcdev->res_csi = res_csi;
1362 pcdev->pdata = pdev->dev.platform_data;
1363 if (pcdev->pdata) {
1364 long rate;
1365
1366 pcdev->platform_flags = pcdev->pdata->flags;
1367
1368 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
1369 if (rate <= 0) {
1370 err = -ENODEV;
1371 goto exit_dma_free;
1372 }
1373 err = clk_set_rate(pcdev->clk_csi, rate);
1374 if (err < 0)
1375 goto exit_dma_free;
1376 }
1377
1378 INIT_LIST_HEAD(&pcdev->capture);
1379 INIT_LIST_HEAD(&pcdev->active_bufs);
1380 spin_lock_init(&pcdev->lock);
1381
1382 /*
1383 * Request the regions.
1384 */
1385 if (!request_mem_region(res_csi->start, resource_size(res_csi),
1386 MX2_CAM_DRV_NAME)) {
1387 err = -EBUSY;
1388 goto exit_dma_free;
1389 }
1390
1391 base_csi = ioremap(res_csi->start, resource_size(res_csi));
1392 if (!base_csi) {
1393 err = -ENOMEM;
1394 goto exit_release;
1395 }
1396 pcdev->irq_csi = irq_csi;
1397 pcdev->base_csi = base_csi;
1398 pcdev->base_dma = res_csi->start;
1399 pcdev->dev = &pdev->dev;
1400
1401 err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0,
1402 MX2_CAM_DRV_NAME, pcdev);
1403 if (err) {
1404 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1405 goto exit_iounmap;
1406 }
1407
1408 if (cpu_is_mx27()) {
1409 /* EMMA support */
1410 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1411 irq_emma = platform_get_irq(pdev, 1);
1412
1413 if (res_emma && irq_emma >= 0) {
1414 dev_info(&pdev->dev, "Using EMMA\n");
1415 pcdev->use_emma = 1;
1416 pcdev->res_emma = res_emma;
1417 pcdev->irq_emma = irq_emma;
1418 if (mx27_camera_emma_init(pcdev))
1419 goto exit_free_irq;
1420 }
1421 }
1422
1423 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1424 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1425 pcdev->soc_host.priv = pcdev;
1426 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1427 pcdev->soc_host.nr = pdev->id;
1428 err = soc_camera_host_register(&pcdev->soc_host);
1429 if (err)
1430 goto exit_free_emma;
1431
1432 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1433 clk_get_rate(pcdev->clk_csi));
1434
1435 return 0;
1436
1437 exit_free_emma:
1438 if (mx27_camera_emma(pcdev)) {
1439 free_irq(pcdev->irq_emma, pcdev);
1440 clk_disable(pcdev->clk_emma);
1441 clk_put(pcdev->clk_emma);
1442 iounmap(pcdev->base_emma);
1443 release_mem_region(res_emma->start, resource_size(res_emma));
1444 }
1445 exit_free_irq:
1446 free_irq(pcdev->irq_csi, pcdev);
1447 exit_iounmap:
1448 iounmap(base_csi);
1449 exit_release:
1450 release_mem_region(res_csi->start, resource_size(res_csi));
1451 exit_dma_free:
1452 #ifdef CONFIG_MACH_MX27
1453 if (cpu_is_mx27())
1454 imx_dma_free(pcdev->dma);
1455 exit_clk_put:
1456 clk_put(pcdev->clk_csi);
1457 #endif /* CONFIG_MACH_MX27 */
1458 exit_kfree:
1459 kfree(pcdev);
1460 exit:
1461 return err;
1462 }
1463
1464 static int __devexit mx2_camera_remove(struct platform_device *pdev)
1465 {
1466 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1467 struct mx2_camera_dev *pcdev = container_of(soc_host,
1468 struct mx2_camera_dev, soc_host);
1469 struct resource *res;
1470
1471 clk_put(pcdev->clk_csi);
1472 #ifdef CONFIG_MACH_MX27
1473 if (cpu_is_mx27())
1474 imx_dma_free(pcdev->dma);
1475 #endif /* CONFIG_MACH_MX27 */
1476 free_irq(pcdev->irq_csi, pcdev);
1477 if (mx27_camera_emma(pcdev))
1478 free_irq(pcdev->irq_emma, pcdev);
1479
1480 soc_camera_host_unregister(&pcdev->soc_host);
1481
1482 iounmap(pcdev->base_csi);
1483
1484 if (mx27_camera_emma(pcdev)) {
1485 clk_disable(pcdev->clk_emma);
1486 clk_put(pcdev->clk_emma);
1487 iounmap(pcdev->base_emma);
1488 res = pcdev->res_emma;
1489 release_mem_region(res->start, resource_size(res));
1490 }
1491
1492 res = pcdev->res_csi;
1493 release_mem_region(res->start, resource_size(res));
1494
1495 kfree(pcdev);
1496
1497 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1498
1499 return 0;
1500 }
1501
1502 static struct platform_driver mx2_camera_driver = {
1503 .driver = {
1504 .name = MX2_CAM_DRV_NAME,
1505 },
1506 .remove = __devexit_p(mx2_camera_remove),
1507 };
1508
1509
1510 static int __init mx2_camera_init(void)
1511 {
1512 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1513 }
1514
1515 static void __exit mx2_camera_exit(void)
1516 {
1517 return platform_driver_unregister(&mx2_camera_driver);
1518 }
1519
1520 module_init(mx2_camera_init);
1521 module_exit(mx2_camera_exit);
1522
1523 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1524 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1525 MODULE_LICENSE("GPL");