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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / media / video / ov7670.c
blobd4e7c11553c3b427ee12e99631f2a65a224c9bfc
1 /*
2 * A V4L2 driver for OmniVision OV7670 cameras.
3 *
4 * Copyright 2006 One Laptop Per Child Association, Inc. Written
5 * by Jonathan Corbet with substantial inspiration from Mark
6 * McClelland's ovcamchip code.
7 *
8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
9 *
10 * This file may be distributed under the terms of the GNU General
11 * Public License, version 2.
12 */
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17 #include <linux/delay.h>
18 #include <linux/videodev2.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-chip-ident.h>
21 #include <media/v4l2-mediabus.h>
22
23 #include "ov7670.h"
24
25 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
26 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
27 MODULE_LICENSE("GPL");
28
29 static int debug;
30 module_param(debug, bool, 0644);
31 MODULE_PARM_DESC(debug, "Debug level (0-1)");
32
33 /*
34 * Basic window sizes. These probably belong somewhere more globally
35 * useful.
36 */
37 #define VGA_WIDTH 640
38 #define VGA_HEIGHT 480
39 #define QVGA_WIDTH 320
40 #define QVGA_HEIGHT 240
41 #define CIF_WIDTH 352
42 #define CIF_HEIGHT 288
43 #define QCIF_WIDTH 176
44 #define QCIF_HEIGHT 144
45
46 /*
47 * The 7670 sits on i2c with ID 0x42
48 */
49 #define OV7670_I2C_ADDR 0x42
50
51 /* Registers */
52 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
53 #define REG_BLUE 0x01 /* blue gain */
54 #define REG_RED 0x02 /* red gain */
55 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
56 #define REG_COM1 0x04 /* Control 1 */
57 #define COM1_CCIR656 0x40 /* CCIR656 enable */
58 #define REG_BAVE 0x05 /* U/B Average level */
59 #define REG_GbAVE 0x06 /* Y/Gb Average level */
60 #define REG_AECHH 0x07 /* AEC MS 5 bits */
61 #define REG_RAVE 0x08 /* V/R Average level */
62 #define REG_COM2 0x09 /* Control 2 */
63 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
64 #define REG_PID 0x0a /* Product ID MSB */
65 #define REG_VER 0x0b /* Product ID LSB */
66 #define REG_COM3 0x0c /* Control 3 */
67 #define COM3_SWAP 0x40 /* Byte swap */
68 #define COM3_SCALEEN 0x08 /* Enable scaling */
69 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
70 #define REG_COM4 0x0d /* Control 4 */
71 #define REG_COM5 0x0e /* All "reserved" */
72 #define REG_COM6 0x0f /* Control 6 */
73 #define REG_AECH 0x10 /* More bits of AEC value */
74 #define REG_CLKRC 0x11 /* Clocl control */
75 #define CLK_EXT 0x40 /* Use external clock directly */
76 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
77 #define REG_COM7 0x12 /* Control 7 */
78 #define COM7_RESET 0x80 /* Register reset */
79 #define COM7_FMT_MASK 0x38
80 #define COM7_FMT_VGA 0x00
81 #define COM7_FMT_CIF 0x20 /* CIF format */
82 #define COM7_FMT_QVGA 0x10 /* QVGA format */
83 #define COM7_FMT_QCIF 0x08 /* QCIF format */
84 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
85 #define COM7_YUV 0x00 /* YUV */
86 #define COM7_BAYER 0x01 /* Bayer format */
87 #define COM7_PBAYER 0x05 /* "Processed bayer" */
88 #define REG_COM8 0x13 /* Control 8 */
89 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
90 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
91 #define COM8_BFILT 0x20 /* Band filter enable */
92 #define COM8_AGC 0x04 /* Auto gain enable */
93 #define COM8_AWB 0x02 /* White balance enable */
94 #define COM8_AEC 0x01 /* Auto exposure enable */
95 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
96 #define REG_COM10 0x15 /* Control 10 */
97 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
98 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
99 #define COM10_HREF_REV 0x08 /* Reverse HREF */
100 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
101 #define COM10_VS_NEG 0x02 /* VSYNC negative */
102 #define COM10_HS_NEG 0x01 /* HSYNC negative */
103 #define REG_HSTART 0x17 /* Horiz start high bits */
104 #define REG_HSTOP 0x18 /* Horiz stop high bits */
105 #define REG_VSTART 0x19 /* Vert start high bits */
106 #define REG_VSTOP 0x1a /* Vert stop high bits */
107 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
108 #define REG_MIDH 0x1c /* Manuf. ID high */
109 #define REG_MIDL 0x1d /* Manuf. ID low */
110 #define REG_MVFP 0x1e /* Mirror / vflip */
111 #define MVFP_MIRROR 0x20 /* Mirror image */
112 #define MVFP_FLIP 0x10 /* Vertical flip */
113
114 #define REG_AEW 0x24 /* AGC upper limit */
115 #define REG_AEB 0x25 /* AGC lower limit */
116 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
117 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
118 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
119 #define REG_HREF 0x32 /* HREF pieces */
120 #define REG_TSLB 0x3a /* lots of stuff */
121 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
122 #define REG_COM11 0x3b /* Control 11 */
123 #define COM11_NIGHT 0x80 /* NIght mode enable */
124 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
125 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
126 #define COM11_50HZ 0x08 /* Manual 50Hz select */
127 #define COM11_EXP 0x02
128 #define REG_COM12 0x3c /* Control 12 */
129 #define COM12_HREF 0x80 /* HREF always */
130 #define REG_COM13 0x3d /* Control 13 */
131 #define COM13_GAMMA 0x80 /* Gamma enable */
132 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
133 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
134 #define REG_COM14 0x3e /* Control 14 */
135 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
136 #define REG_EDGE 0x3f /* Edge enhancement factor */
137 #define REG_COM15 0x40 /* Control 15 */
138 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
139 #define COM15_R01FE 0x80 /* 01 to FE */
140 #define COM15_R00FF 0xc0 /* 00 to FF */
141 #define COM15_RGB565 0x10 /* RGB565 output */
142 #define COM15_RGB555 0x30 /* RGB555 output */
143 #define REG_COM16 0x41 /* Control 16 */
144 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
145 #define REG_COM17 0x42 /* Control 17 */
146 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
147 #define COM17_CBAR 0x08 /* DSP Color bar */
148
149 /*
150 * This matrix defines how the colors are generated, must be
151 * tweaked to adjust hue and saturation.
152 *
153 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
154 *
155 * They are nine-bit signed quantities, with the sign bit
156 * stored in 0x58. Sign for v-red is bit 0, and up from there.
157 */
158 #define REG_CMATRIX_BASE 0x4f
159 #define CMATRIX_LEN 6
160 #define REG_CMATRIX_SIGN 0x58
161
162
163 #define REG_BRIGHT 0x55 /* Brightness */
164 #define REG_CONTRAS 0x56 /* Contrast control */
165
166 #define REG_GFIX 0x69 /* Fix gain control */
167
168 #define REG_REG76 0x76 /* OV's name */
169 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
170 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
171
172 #define REG_RGB444 0x8c /* RGB 444 control */
173 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
174 #define R444_RGBX 0x01 /* Empty nibble at end */
175
176 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
177 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
178
179 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
180 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
181 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
182 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
183 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
184 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
185 #define REG_BD60MAX 0xab /* 60hz banding step limit */
186
187
188 /*
189 * Information we maintain about a known sensor.
190 */
191 struct ov7670_format_struct; /* coming later */
192 struct ov7670_info {
193 struct v4l2_subdev sd;
194 struct ov7670_format_struct *fmt; /* Current format */
195 unsigned char sat; /* Saturation value */
196 int hue; /* Hue value */
197 int min_width; /* Filter out smaller sizes */
198 int min_height; /* Filter out smaller sizes */
199 int clock_speed; /* External clock speed (MHz) */
200 u8 clkrc; /* Clock divider value */
201 bool use_smbus; /* Use smbus I/O instead of I2C */
202 };
203
204 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
205 {
206 return container_of(sd, struct ov7670_info, sd);
207 }
208
209
210
211 /*
212 * The default register settings, as obtained from OmniVision. There
213 * is really no making sense of most of these - lots of "reserved" values
214 * and such.
215 *
216 * These settings give VGA YUYV.
217 */
218
219 struct regval_list {
220 unsigned char reg_num;
221 unsigned char value;
222 };
223
224 static struct regval_list ov7670_default_regs[] = {
225 { REG_COM7, COM7_RESET },
226 /*
227 * Clock scale: 3 = 15fps
228 * 2 = 20fps
229 * 1 = 30fps
230 */
231 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
232 { REG_TSLB, 0x04 }, /* OV */
233 { REG_COM7, 0 }, /* VGA */
234 /*
235 * Set the hardware window. These values from OV don't entirely
236 * make sense - hstop is less than hstart. But they work...
237 */
238 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
239 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
240 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
241
242 { REG_COM3, 0 }, { REG_COM14, 0 },
243 /* Mystery scaling numbers */
244 { 0x70, 0x3a }, { 0x71, 0x35 },
245 { 0x72, 0x11 }, { 0x73, 0xf0 },
246 { 0xa2, 0x02 }, { REG_COM10, 0x0 },
247
248 /* Gamma curve values */
249 { 0x7a, 0x20 }, { 0x7b, 0x10 },
250 { 0x7c, 0x1e }, { 0x7d, 0x35 },
251 { 0x7e, 0x5a }, { 0x7f, 0x69 },
252 { 0x80, 0x76 }, { 0x81, 0x80 },
253 { 0x82, 0x88 }, { 0x83, 0x8f },
254 { 0x84, 0x96 }, { 0x85, 0xa3 },
255 { 0x86, 0xaf }, { 0x87, 0xc4 },
256 { 0x88, 0xd7 }, { 0x89, 0xe8 },
257
258 /* AGC and AEC parameters. Note we start by disabling those features,
259 then turn them only after tweaking the values. */
260 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
261 { REG_GAIN, 0 }, { REG_AECH, 0 },
262 { REG_COM4, 0x40 }, /* magic reserved bit */
263 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
264 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
265 { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
266 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
267 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
268 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
269 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
270 { REG_HAECC7, 0x94 },
271 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
272
273 /* Almost all of these are magic "reserved" values. */
274 { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
275 { 0x16, 0x02 }, { REG_MVFP, 0x07 },
276 { 0x21, 0x02 }, { 0x22, 0x91 },
277 { 0x29, 0x07 }, { 0x33, 0x0b },
278 { 0x35, 0x0b }, { 0x37, 0x1d },
279 { 0x38, 0x71 }, { 0x39, 0x2a },
280 { REG_COM12, 0x78 }, { 0x4d, 0x40 },
281 { 0x4e, 0x20 }, { REG_GFIX, 0 },
282 { 0x6b, 0x4a }, { 0x74, 0x10 },
283 { 0x8d, 0x4f }, { 0x8e, 0 },
284 { 0x8f, 0 }, { 0x90, 0 },
285 { 0x91, 0 }, { 0x96, 0 },
286 { 0x9a, 0 }, { 0xb0, 0x84 },
287 { 0xb1, 0x0c }, { 0xb2, 0x0e },
288 { 0xb3, 0x82 }, { 0xb8, 0x0a },
289
290 /* More reserved magic, some of which tweaks white balance */
291 { 0x43, 0x0a }, { 0x44, 0xf0 },
292 { 0x45, 0x34 }, { 0x46, 0x58 },
293 { 0x47, 0x28 }, { 0x48, 0x3a },
294 { 0x59, 0x88 }, { 0x5a, 0x88 },
295 { 0x5b, 0x44 }, { 0x5c, 0x67 },
296 { 0x5d, 0x49 }, { 0x5e, 0x0e },
297 { 0x6c, 0x0a }, { 0x6d, 0x55 },
298 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
299 { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
300 { REG_RED, 0x60 },
301 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
302
303 /* Matrix coefficients */
304 { 0x4f, 0x80 }, { 0x50, 0x80 },
305 { 0x51, 0 }, { 0x52, 0x22 },
306 { 0x53, 0x5e }, { 0x54, 0x80 },
307 { 0x58, 0x9e },
308
309 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
310 { 0x75, 0x05 }, { 0x76, 0xe1 },
311 { 0x4c, 0 }, { 0x77, 0x01 },
312 { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
313 { 0xc9, 0x60 }, { REG_COM16, 0x38 },
314 { 0x56, 0x40 },
315
316 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
317 { 0xa4, 0x88 }, { 0x96, 0 },
318 { 0x97, 0x30 }, { 0x98, 0x20 },
319 { 0x99, 0x30 }, { 0x9a, 0x84 },
320 { 0x9b, 0x29 }, { 0x9c, 0x03 },
321 { 0x9d, 0x4c }, { 0x9e, 0x3f },
322 { 0x78, 0x04 },
323
324 /* Extra-weird stuff. Some sort of multiplexor register */
325 { 0x79, 0x01 }, { 0xc8, 0xf0 },
326 { 0x79, 0x0f }, { 0xc8, 0x00 },
327 { 0x79, 0x10 }, { 0xc8, 0x7e },
328 { 0x79, 0x0a }, { 0xc8, 0x80 },
329 { 0x79, 0x0b }, { 0xc8, 0x01 },
330 { 0x79, 0x0c }, { 0xc8, 0x0f },
331 { 0x79, 0x0d }, { 0xc8, 0x20 },
332 { 0x79, 0x09 }, { 0xc8, 0x80 },
333 { 0x79, 0x02 }, { 0xc8, 0xc0 },
334 { 0x79, 0x03 }, { 0xc8, 0x40 },
335 { 0x79, 0x05 }, { 0xc8, 0x30 },
336 { 0x79, 0x26 },
337
338 { 0xff, 0xff }, /* END MARKER */
339 };
340
341
342 /*
343 * Here we'll try to encapsulate the changes for just the output
344 * video format.
345 *
346 * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
347 *
348 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
349 */
350
351
352 static struct regval_list ov7670_fmt_yuv422[] = {
353 { REG_COM7, 0x0 }, /* Selects YUV mode */
354 { REG_RGB444, 0 }, /* No RGB444 please */
355 { REG_COM1, 0 }, /* CCIR601 */
356 { REG_COM15, COM15_R00FF },
357 { REG_COM9, 0x18 }, /* 4x gain ceiling; 0x8 is reserved bit */
358 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
359 { 0x50, 0x80 }, /* "matrix coefficient 2" */
360 { 0x51, 0 }, /* vb */
361 { 0x52, 0x22 }, /* "matrix coefficient 4" */
362 { 0x53, 0x5e }, /* "matrix coefficient 5" */
363 { 0x54, 0x80 }, /* "matrix coefficient 6" */
364 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
365 { 0xff, 0xff },
366 };
367
368 static struct regval_list ov7670_fmt_rgb565[] = {
369 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
370 { REG_RGB444, 0 }, /* No RGB444 please */
371 { REG_COM1, 0x0 }, /* CCIR601 */
372 { REG_COM15, COM15_RGB565 },
373 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
374 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
375 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
376 { 0x51, 0 }, /* vb */
377 { 0x52, 0x3d }, /* "matrix coefficient 4" */
378 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
379 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
380 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
381 { 0xff, 0xff },
382 };
383
384 static struct regval_list ov7670_fmt_rgb444[] = {
385 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
386 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
387 { REG_COM1, 0x0 }, /* CCIR601 */
388 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
389 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
390 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
391 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
392 { 0x51, 0 }, /* vb */
393 { 0x52, 0x3d }, /* "matrix coefficient 4" */
394 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
395 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
396 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
397 { 0xff, 0xff },
398 };
399
400 static struct regval_list ov7670_fmt_raw[] = {
401 { REG_COM7, COM7_BAYER },
402 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
403 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
404 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
405 { 0xff, 0xff },
406 };
407
408
409
410 /*
411 * Low-level register I/O.
412 *
413 * Note that there are two versions of these. On the XO 1, the
414 * i2c controller only does SMBUS, so that's what we use. The
415 * ov7670 is not really an SMBUS device, though, so the communication
416 * is not always entirely reliable.
417 */
418 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
419 unsigned char *value)
420 {
421 struct i2c_client *client = v4l2_get_subdevdata(sd);
422 int ret;
423
424 ret = i2c_smbus_read_byte_data(client, reg);
425 if (ret >= 0) {
426 *value = (unsigned char)ret;
427 ret = 0;
428 }
429 return ret;
430 }
431
432
433 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
434 unsigned char value)
435 {
436 struct i2c_client *client = v4l2_get_subdevdata(sd);
437 int ret = i2c_smbus_write_byte_data(client, reg, value);
438
439 if (reg == REG_COM7 && (value & COM7_RESET))
440 msleep(5); /* Wait for reset to run */
441 return ret;
442 }
443
444 /*
445 * On most platforms, we'd rather do straight i2c I/O.
446 */
447 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
448 unsigned char *value)
449 {
450 struct i2c_client *client = v4l2_get_subdevdata(sd);
451 u8 data = reg;
452 struct i2c_msg msg;
453 int ret;
454
455 /*
456 * Send out the register address...
457 */
458 msg.addr = client->addr;
459 msg.flags = 0;
460 msg.len = 1;
461 msg.buf = &data;
462 ret = i2c_transfer(client->adapter, &msg, 1);
463 if (ret < 0) {
464 printk(KERN_ERR "Error %d on register write\n", ret);
465 return ret;
466 }
467 /*
468 * ...then read back the result.
469 */
470 msg.flags = I2C_M_RD;
471 ret = i2c_transfer(client->adapter, &msg, 1);
472 if (ret >= 0) {
473 *value = data;
474 ret = 0;
475 }
476 return ret;
477 }
478
479
480 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
481 unsigned char value)
482 {
483 struct i2c_client *client = v4l2_get_subdevdata(sd);
484 struct i2c_msg msg;
485 unsigned char data[2] = { reg, value };
486 int ret;
487
488 msg.addr = client->addr;
489 msg.flags = 0;
490 msg.len = 2;
491 msg.buf = data;
492 ret = i2c_transfer(client->adapter, &msg, 1);
493 if (ret > 0)
494 ret = 0;
495 if (reg == REG_COM7 && (value & COM7_RESET))
496 msleep(5); /* Wait for reset to run */
497 return ret;
498 }
499
500 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
501 unsigned char *value)
502 {
503 struct ov7670_info *info = to_state(sd);
504 if (info->use_smbus)
505 return ov7670_read_smbus(sd, reg, value);
506 else
507 return ov7670_read_i2c(sd, reg, value);
508 }
509
510 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
511 unsigned char value)
512 {
513 struct ov7670_info *info = to_state(sd);
514 if (info->use_smbus)
515 return ov7670_write_smbus(sd, reg, value);
516 else
517 return ov7670_write_i2c(sd, reg, value);
518 }
519
520 /*
521 * Write a list of register settings; ff/ff stops the process.
522 */
523 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
524 {
525 while (vals->reg_num != 0xff || vals->value != 0xff) {
526 int ret = ov7670_write(sd, vals->reg_num, vals->value);
527 if (ret < 0)
528 return ret;
529 vals++;
530 }
531 return 0;
532 }
533
534
535 /*
536 * Stuff that knows about the sensor.
537 */
538 static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
539 {
540 ov7670_write(sd, REG_COM7, COM7_RESET);
541 msleep(1);
542 return 0;
543 }
544
545
546 static int ov7670_init(struct v4l2_subdev *sd, u32 val)
547 {
548 return ov7670_write_array(sd, ov7670_default_regs);
549 }
550
551
552
553 static int ov7670_detect(struct v4l2_subdev *sd)
554 {
555 unsigned char v;
556 int ret;
557
558 ret = ov7670_init(sd, 0);
559 if (ret < 0)
560 return ret;
561 ret = ov7670_read(sd, REG_MIDH, &v);
562 if (ret < 0)
563 return ret;
564 if (v != 0x7f) /* OV manuf. id. */
565 return -ENODEV;
566 ret = ov7670_read(sd, REG_MIDL, &v);
567 if (ret < 0)
568 return ret;
569 if (v != 0xa2)
570 return -ENODEV;
571 /*
572 * OK, we know we have an OmniVision chip...but which one?
573 */
574 ret = ov7670_read(sd, REG_PID, &v);
575 if (ret < 0)
576 return ret;
577 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
578 return -ENODEV;
579 ret = ov7670_read(sd, REG_VER, &v);
580 if (ret < 0)
581 return ret;
582 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
583 return -ENODEV;
584 return 0;
585 }
586
587
588 /*
589 * Store information about the video data format. The color matrix
590 * is deeply tied into the format, so keep the relevant values here.
591 * The magic matrix numbers come from OmniVision.
592 */
593 static struct ov7670_format_struct {
594 enum v4l2_mbus_pixelcode mbus_code;
595 enum v4l2_colorspace colorspace;
596 struct regval_list *regs;
597 int cmatrix[CMATRIX_LEN];
598 } ov7670_formats[] = {
599 {
600 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
601 .colorspace = V4L2_COLORSPACE_JPEG,
602 .regs = ov7670_fmt_yuv422,
603 .cmatrix = { 128, -128, 0, -34, -94, 128 },
604 },
605 {
606 .mbus_code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE,
607 .colorspace = V4L2_COLORSPACE_SRGB,
608 .regs = ov7670_fmt_rgb444,
609 .cmatrix = { 179, -179, 0, -61, -176, 228 },
610 },
611 {
612 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_LE,
613 .colorspace = V4L2_COLORSPACE_SRGB,
614 .regs = ov7670_fmt_rgb565,
615 .cmatrix = { 179, -179, 0, -61, -176, 228 },
616 },
617 {
618 .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8,
619 .colorspace = V4L2_COLORSPACE_SRGB,
620 .regs = ov7670_fmt_raw,
621 .cmatrix = { 0, 0, 0, 0, 0, 0 },
622 },
623 };
624 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
625
626
627 /*
628 * Then there is the issue of window sizes. Try to capture the info here.
629 */
630
631 /*
632 * QCIF mode is done (by OV) in a very strange way - it actually looks like
633 * VGA with weird scaling options - they do *not* use the canned QCIF mode
634 * which is allegedly provided by the sensor. So here's the weird register
635 * settings.
636 */
637 static struct regval_list ov7670_qcif_regs[] = {
638 { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
639 { REG_COM3, COM3_DCWEN },
640 { REG_COM14, COM14_DCWEN | 0x01},
641 { 0x73, 0xf1 },
642 { 0xa2, 0x52 },
643 { 0x7b, 0x1c },
644 { 0x7c, 0x28 },
645 { 0x7d, 0x3c },
646 { 0x7f, 0x69 },
647 { REG_COM9, 0x38 },
648 { 0xa1, 0x0b },
649 { 0x74, 0x19 },
650 { 0x9a, 0x80 },
651 { 0x43, 0x14 },
652 { REG_COM13, 0xc0 },
653 { 0xff, 0xff },
654 };
655
656 static struct ov7670_win_size {
657 int width;
658 int height;
659 unsigned char com7_bit;
660 int hstart; /* Start/stop values for the camera. Note */
661 int hstop; /* that they do not always make complete */
662 int vstart; /* sense to humans, but evidently the sensor */
663 int vstop; /* will do the right thing... */
664 struct regval_list *regs; /* Regs to tweak */
665 /* h/vref stuff */
666 } ov7670_win_sizes[] = {
667 /* VGA */
668 {
669 .width = VGA_WIDTH,
670 .height = VGA_HEIGHT,
671 .com7_bit = COM7_FMT_VGA,
672 .hstart = 158, /* These values from */
673 .hstop = 14, /* Omnivision */
674 .vstart = 10,
675 .vstop = 490,
676 .regs = NULL,
677 },
678 /* CIF */
679 {
680 .width = CIF_WIDTH,
681 .height = CIF_HEIGHT,
682 .com7_bit = COM7_FMT_CIF,
683 .hstart = 170, /* Empirically determined */
684 .hstop = 90,
685 .vstart = 14,
686 .vstop = 494,
687 .regs = NULL,
688 },
689 /* QVGA */
690 {
691 .width = QVGA_WIDTH,
692 .height = QVGA_HEIGHT,
693 .com7_bit = COM7_FMT_QVGA,
694 .hstart = 168, /* Empirically determined */
695 .hstop = 24,
696 .vstart = 12,
697 .vstop = 492,
698 .regs = NULL,
699 },
700 /* QCIF */
701 {
702 .width = QCIF_WIDTH,
703 .height = QCIF_HEIGHT,
704 .com7_bit = COM7_FMT_VGA, /* see comment above */
705 .hstart = 456, /* Empirically determined */
706 .hstop = 24,
707 .vstart = 14,
708 .vstop = 494,
709 .regs = ov7670_qcif_regs,
710 },
711 };
712
713 #define N_WIN_SIZES (ARRAY_SIZE(ov7670_win_sizes))
714
715
716 /*
717 * Store a set of start/stop values into the camera.
718 */
719 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
720 int vstart, int vstop)
721 {
722 int ret;
723 unsigned char v;
724 /*
725 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
726 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
727 * a mystery "edge offset" value in the top two bits of href.
728 */
729 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
730 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
731 ret += ov7670_read(sd, REG_HREF, &v);
732 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
733 msleep(10);
734 ret += ov7670_write(sd, REG_HREF, v);
735 /*
736 * Vertical: similar arrangement, but only 10 bits.
737 */
738 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
739 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
740 ret += ov7670_read(sd, REG_VREF, &v);
741 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
742 msleep(10);
743 ret += ov7670_write(sd, REG_VREF, v);
744 return ret;
745 }
746
747
748 static int ov7670_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
749 enum v4l2_mbus_pixelcode *code)
750 {
751 if (index >= N_OV7670_FMTS)
752 return -EINVAL;
753
754 *code = ov7670_formats[index].mbus_code;
755 return 0;
756 }
757
758 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
759 struct v4l2_mbus_framefmt *fmt,
760 struct ov7670_format_struct **ret_fmt,
761 struct ov7670_win_size **ret_wsize)
762 {
763 int index;
764 struct ov7670_win_size *wsize;
765
766 for (index = 0; index < N_OV7670_FMTS; index++)
767 if (ov7670_formats[index].mbus_code == fmt->code)
768 break;
769 if (index >= N_OV7670_FMTS) {
770 /* default to first format */
771 index = 0;
772 fmt->code = ov7670_formats[0].mbus_code;
773 }
774 if (ret_fmt != NULL)
775 *ret_fmt = ov7670_formats + index;
776 /*
777 * Fields: the OV devices claim to be progressive.
778 */
779 fmt->field = V4L2_FIELD_NONE;
780 /*
781 * Round requested image size down to the nearest
782 * we support, but not below the smallest.
783 */
784 for (wsize = ov7670_win_sizes; wsize < ov7670_win_sizes + N_WIN_SIZES;
785 wsize++)
786 if (fmt->width >= wsize->width && fmt->height >= wsize->height)
787 break;
788 if (wsize >= ov7670_win_sizes + N_WIN_SIZES)
789 wsize--; /* Take the smallest one */
790 if (ret_wsize != NULL)
791 *ret_wsize = wsize;
792 /*
793 * Note the size we'll actually handle.
794 */
795 fmt->width = wsize->width;
796 fmt->height = wsize->height;
797 fmt->colorspace = ov7670_formats[index].colorspace;
798 return 0;
799 }
800
801 static int ov7670_try_mbus_fmt(struct v4l2_subdev *sd,
802 struct v4l2_mbus_framefmt *fmt)
803 {
804 return ov7670_try_fmt_internal(sd, fmt, NULL, NULL);
805 }
806
807 /*
808 * Set a format.
809 */
810 static int ov7670_s_mbus_fmt(struct v4l2_subdev *sd,
811 struct v4l2_mbus_framefmt *fmt)
812 {
813 struct ov7670_format_struct *ovfmt;
814 struct ov7670_win_size *wsize;
815 struct ov7670_info *info = to_state(sd);
816 unsigned char com7;
817 int ret;
818
819 ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize);
820
821 if (ret)
822 return ret;
823 /*
824 * COM7 is a pain in the ass, it doesn't like to be read then
825 * quickly written afterward. But we have everything we need
826 * to set it absolutely here, as long as the format-specific
827 * register sets list it first.
828 */
829 com7 = ovfmt->regs[0].value;
830 com7 |= wsize->com7_bit;
831 ov7670_write(sd, REG_COM7, com7);
832 /*
833 * Now write the rest of the array. Also store start/stops
834 */
835 ov7670_write_array(sd, ovfmt->regs + 1);
836 ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
837 wsize->vstop);
838 ret = 0;
839 if (wsize->regs)
840 ret = ov7670_write_array(sd, wsize->regs);
841 info->fmt = ovfmt;
842
843 /*
844 * If we're running RGB565, we must rewrite clkrc after setting
845 * the other parameters or the image looks poor. If we're *not*
846 * doing RGB565, we must not rewrite clkrc or the image looks
847 * *really* poor.
848 *
849 * (Update) Now that we retain clkrc state, we should be able
850 * to write it unconditionally, and that will make the frame
851 * rate persistent too.
852 */
853 if (ret == 0)
854 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
855 return 0;
856 }
857
858 /*
859 * Implement G/S_PARM. There is a "high quality" mode we could try
860 * to do someday; for now, we just do the frame rate tweak.
861 */
862 static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
863 {
864 struct v4l2_captureparm *cp = &parms->parm.capture;
865 struct ov7670_info *info = to_state(sd);
866
867 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
868 return -EINVAL;
869
870 memset(cp, 0, sizeof(struct v4l2_captureparm));
871 cp->capability = V4L2_CAP_TIMEPERFRAME;
872 cp->timeperframe.numerator = 1;
873 cp->timeperframe.denominator = info->clock_speed;
874 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
875 cp->timeperframe.denominator /= (info->clkrc & CLK_SCALE);
876 return 0;
877 }
878
879 static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
880 {
881 struct v4l2_captureparm *cp = &parms->parm.capture;
882 struct v4l2_fract *tpf = &cp->timeperframe;
883 struct ov7670_info *info = to_state(sd);
884 int div;
885
886 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
887 return -EINVAL;
888 if (cp->extendedmode != 0)
889 return -EINVAL;
890
891 if (tpf->numerator == 0 || tpf->denominator == 0)
892 div = 1; /* Reset to full rate */
893 else
894 div = (tpf->numerator * info->clock_speed) / tpf->denominator;
895 if (div == 0)
896 div = 1;
897 else if (div > CLK_SCALE)
898 div = CLK_SCALE;
899 info->clkrc = (info->clkrc & 0x80) | div;
900 tpf->numerator = 1;
901 tpf->denominator = info->clock_speed / div;
902 return ov7670_write(sd, REG_CLKRC, info->clkrc);
903 }
904
905
906 /*
907 * Frame intervals. Since frame rates are controlled with the clock
908 * divider, we can only do 30/n for integer n values. So no continuous
909 * or stepwise options. Here we just pick a handful of logical values.
910 */
911
912 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
913
914 static int ov7670_enum_frameintervals(struct v4l2_subdev *sd,
915 struct v4l2_frmivalenum *interval)
916 {
917 if (interval->index >= ARRAY_SIZE(ov7670_frame_rates))
918 return -EINVAL;
919 interval->type = V4L2_FRMIVAL_TYPE_DISCRETE;
920 interval->discrete.numerator = 1;
921 interval->discrete.denominator = ov7670_frame_rates[interval->index];
922 return 0;
923 }
924
925 /*
926 * Frame size enumeration
927 */
928 static int ov7670_enum_framesizes(struct v4l2_subdev *sd,
929 struct v4l2_frmsizeenum *fsize)
930 {
931 struct ov7670_info *info = to_state(sd);
932 int i;
933 int num_valid = -1;
934 __u32 index = fsize->index;
935
936 /*
937 * If a minimum width/height was requested, filter out the capture
938 * windows that fall outside that.
939 */
940 for (i = 0; i < N_WIN_SIZES; i++) {
941 struct ov7670_win_size *win = &ov7670_win_sizes[index];
942 if (info->min_width && win->width < info->min_width)
943 continue;
944 if (info->min_height && win->height < info->min_height)
945 continue;
946 if (index == ++num_valid) {
947 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
948 fsize->discrete.width = win->width;
949 fsize->discrete.height = win->height;
950 return 0;
951 }
952 }
953
954 return -EINVAL;
955 }
956
957 /*
958 * Code for dealing with controls.
959 */
960
961 static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
962 int matrix[CMATRIX_LEN])
963 {
964 int i, ret;
965 unsigned char signbits = 0;
966
967 /*
968 * Weird crap seems to exist in the upper part of
969 * the sign bits register, so let's preserve it.
970 */
971 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
972 signbits &= 0xc0;
973
974 for (i = 0; i < CMATRIX_LEN; i++) {
975 unsigned char raw;
976
977 if (matrix[i] < 0) {
978 signbits |= (1 << i);
979 if (matrix[i] < -255)
980 raw = 0xff;
981 else
982 raw = (-1 * matrix[i]) & 0xff;
983 }
984 else {
985 if (matrix[i] > 255)
986 raw = 0xff;
987 else
988 raw = matrix[i] & 0xff;
989 }
990 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
991 }
992 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
993 return ret;
994 }
995
996
997 /*
998 * Hue also requires messing with the color matrix. It also requires
999 * trig functions, which tend not to be well supported in the kernel.
1000 * So here is a simple table of sine values, 0-90 degrees, in steps
1001 * of five degrees. Values are multiplied by 1000.
1002 *
1003 * The following naive approximate trig functions require an argument
1004 * carefully limited to -180 <= theta <= 180.
1005 */
1006 #define SIN_STEP 5
1007 static const int ov7670_sin_table[] = {
1008 0, 87, 173, 258, 342, 422,
1009 499, 573, 642, 707, 766, 819,
1010 866, 906, 939, 965, 984, 996,
1011 1000
1012 };
1013
1014 static int ov7670_sine(int theta)
1015 {
1016 int chs = 1;
1017 int sine;
1018
1019 if (theta < 0) {
1020 theta = -theta;
1021 chs = -1;
1022 }
1023 if (theta <= 90)
1024 sine = ov7670_sin_table[theta/SIN_STEP];
1025 else {
1026 theta -= 90;
1027 sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
1028 }
1029 return sine*chs;
1030 }
1031
1032 static int ov7670_cosine(int theta)
1033 {
1034 theta = 90 - theta;
1035 if (theta > 180)
1036 theta -= 360;
1037 else if (theta < -180)
1038 theta += 360;
1039 return ov7670_sine(theta);
1040 }
1041
1042
1043
1044
1045 static void ov7670_calc_cmatrix(struct ov7670_info *info,
1046 int matrix[CMATRIX_LEN])
1047 {
1048 int i;
1049 /*
1050 * Apply the current saturation setting first.
1051 */
1052 for (i = 0; i < CMATRIX_LEN; i++)
1053 matrix[i] = (info->fmt->cmatrix[i]*info->sat) >> 7;
1054 /*
1055 * Then, if need be, rotate the hue value.
1056 */
1057 if (info->hue != 0) {
1058 int sinth, costh, tmpmatrix[CMATRIX_LEN];
1059
1060 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
1061 sinth = ov7670_sine(info->hue);
1062 costh = ov7670_cosine(info->hue);
1063
1064 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
1065 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
1066 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
1067 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
1068 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
1069 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
1070 }
1071 }
1072
1073
1074
1075 static int ov7670_s_sat(struct v4l2_subdev *sd, int value)
1076 {
1077 struct ov7670_info *info = to_state(sd);
1078 int matrix[CMATRIX_LEN];
1079 int ret;
1080
1081 info->sat = value;
1082 ov7670_calc_cmatrix(info, matrix);
1083 ret = ov7670_store_cmatrix(sd, matrix);
1084 return ret;
1085 }
1086
1087 static int ov7670_g_sat(struct v4l2_subdev *sd, __s32 *value)
1088 {
1089 struct ov7670_info *info = to_state(sd);
1090
1091 *value = info->sat;
1092 return 0;
1093 }
1094
1095 static int ov7670_s_hue(struct v4l2_subdev *sd, int value)
1096 {
1097 struct ov7670_info *info = to_state(sd);
1098 int matrix[CMATRIX_LEN];
1099 int ret;
1100
1101 if (value < -180 || value > 180)
1102 return -EINVAL;
1103 info->hue = value;
1104 ov7670_calc_cmatrix(info, matrix);
1105 ret = ov7670_store_cmatrix(sd, matrix);
1106 return ret;
1107 }
1108
1109
1110 static int ov7670_g_hue(struct v4l2_subdev *sd, __s32 *value)
1111 {
1112 struct ov7670_info *info = to_state(sd);
1113
1114 *value = info->hue;
1115 return 0;
1116 }
1117
1118
1119 /*
1120 * Some weird registers seem to store values in a sign/magnitude format!
1121 */
1122 static unsigned char ov7670_sm_to_abs(unsigned char v)
1123 {
1124 if ((v & 0x80) == 0)
1125 return v + 128;
1126 return 128 - (v & 0x7f);
1127 }
1128
1129
1130 static unsigned char ov7670_abs_to_sm(unsigned char v)
1131 {
1132 if (v > 127)
1133 return v & 0x7f;
1134 return (128 - v) | 0x80;
1135 }
1136
1137 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
1138 {
1139 unsigned char com8 = 0, v;
1140 int ret;
1141
1142 ov7670_read(sd, REG_COM8, &com8);
1143 com8 &= ~COM8_AEC;
1144 ov7670_write(sd, REG_COM8, com8);
1145 v = ov7670_abs_to_sm(value);
1146 ret = ov7670_write(sd, REG_BRIGHT, v);
1147 return ret;
1148 }
1149
1150 static int ov7670_g_brightness(struct v4l2_subdev *sd, __s32 *value)
1151 {
1152 unsigned char v = 0;
1153 int ret = ov7670_read(sd, REG_BRIGHT, &v);
1154
1155 *value = ov7670_sm_to_abs(v);
1156 return ret;
1157 }
1158
1159 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
1160 {
1161 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
1162 }
1163
1164 static int ov7670_g_contrast(struct v4l2_subdev *sd, __s32 *value)
1165 {
1166 unsigned char v = 0;
1167 int ret = ov7670_read(sd, REG_CONTRAS, &v);
1168
1169 *value = v;
1170 return ret;
1171 }
1172
1173 static int ov7670_g_hflip(struct v4l2_subdev *sd, __s32 *value)
1174 {
1175 int ret;
1176 unsigned char v = 0;
1177
1178 ret = ov7670_read(sd, REG_MVFP, &v);
1179 *value = (v & MVFP_MIRROR) == MVFP_MIRROR;
1180 return ret;
1181 }
1182
1183
1184 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
1185 {
1186 unsigned char v = 0;
1187 int ret;
1188
1189 ret = ov7670_read(sd, REG_MVFP, &v);
1190 if (value)
1191 v |= MVFP_MIRROR;
1192 else
1193 v &= ~MVFP_MIRROR;
1194 msleep(10); /* FIXME */
1195 ret += ov7670_write(sd, REG_MVFP, v);
1196 return ret;
1197 }
1198
1199
1200
1201 static int ov7670_g_vflip(struct v4l2_subdev *sd, __s32 *value)
1202 {
1203 int ret;
1204 unsigned char v = 0;
1205
1206 ret = ov7670_read(sd, REG_MVFP, &v);
1207 *value = (v & MVFP_FLIP) == MVFP_FLIP;
1208 return ret;
1209 }
1210
1211
1212 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
1213 {
1214 unsigned char v = 0;
1215 int ret;
1216
1217 ret = ov7670_read(sd, REG_MVFP, &v);
1218 if (value)
1219 v |= MVFP_FLIP;
1220 else
1221 v &= ~MVFP_FLIP;
1222 msleep(10); /* FIXME */
1223 ret += ov7670_write(sd, REG_MVFP, v);
1224 return ret;
1225 }
1226
1227 /*
1228 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes
1229 * the data sheet, the VREF parts should be the most significant, but
1230 * experience shows otherwise. There seems to be little value in
1231 * messing with the VREF bits, so we leave them alone.
1232 */
1233 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
1234 {
1235 int ret;
1236 unsigned char gain;
1237
1238 ret = ov7670_read(sd, REG_GAIN, &gain);
1239 *value = gain;
1240 return ret;
1241 }
1242
1243 static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
1244 {
1245 int ret;
1246 unsigned char com8;
1247
1248 ret = ov7670_write(sd, REG_GAIN, value & 0xff);
1249 /* Have to turn off AGC as well */
1250 if (ret == 0) {
1251 ret = ov7670_read(sd, REG_COM8, &com8);
1252 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
1253 }
1254 return ret;
1255 }
1256
1257 /*
1258 * Tweak autogain.
1259 */
1260 static int ov7670_g_autogain(struct v4l2_subdev *sd, __s32 *value)
1261 {
1262 int ret;
1263 unsigned char com8;
1264
1265 ret = ov7670_read(sd, REG_COM8, &com8);
1266 *value = (com8 & COM8_AGC) != 0;
1267 return ret;
1268 }
1269
1270 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
1271 {
1272 int ret;
1273 unsigned char com8;
1274
1275 ret = ov7670_read(sd, REG_COM8, &com8);
1276 if (ret == 0) {
1277 if (value)
1278 com8 |= COM8_AGC;
1279 else
1280 com8 &= ~COM8_AGC;
1281 ret = ov7670_write(sd, REG_COM8, com8);
1282 }
1283 return ret;
1284 }
1285
1286 /*
1287 * Exposure is spread all over the place: top 6 bits in AECHH, middle
1288 * 8 in AECH, and two stashed in COM1 just for the hell of it.
1289 */
1290 static int ov7670_g_exp(struct v4l2_subdev *sd, __s32 *value)
1291 {
1292 int ret;
1293 unsigned char com1, aech, aechh;
1294
1295 ret = ov7670_read(sd, REG_COM1, &com1) +
1296 ov7670_read(sd, REG_AECH, &aech) +
1297 ov7670_read(sd, REG_AECHH, &aechh);
1298 *value = ((aechh & 0x3f) << 10) | (aech << 2) | (com1 & 0x03);
1299 return ret;
1300 }
1301
1302 static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
1303 {
1304 int ret;
1305 unsigned char com1, com8, aech, aechh;
1306
1307 ret = ov7670_read(sd, REG_COM1, &com1) +
1308 ov7670_read(sd, REG_COM8, &com8);
1309 ov7670_read(sd, REG_AECHH, &aechh);
1310 if (ret)
1311 return ret;
1312
1313 com1 = (com1 & 0xfc) | (value & 0x03);
1314 aech = (value >> 2) & 0xff;
1315 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
1316 ret = ov7670_write(sd, REG_COM1, com1) +
1317 ov7670_write(sd, REG_AECH, aech) +
1318 ov7670_write(sd, REG_AECHH, aechh);
1319 /* Have to turn off AEC as well */
1320 if (ret == 0)
1321 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
1322 return ret;
1323 }
1324
1325 /*
1326 * Tweak autoexposure.
1327 */
1328 static int ov7670_g_autoexp(struct v4l2_subdev *sd, __s32 *value)
1329 {
1330 int ret;
1331 unsigned char com8;
1332 enum v4l2_exposure_auto_type *atype = (enum v4l2_exposure_auto_type *) value;
1333
1334 ret = ov7670_read(sd, REG_COM8, &com8);
1335 if (com8 & COM8_AEC)
1336 *atype = V4L2_EXPOSURE_AUTO;
1337 else
1338 *atype = V4L2_EXPOSURE_MANUAL;
1339 return ret;
1340 }
1341
1342 static int ov7670_s_autoexp(struct v4l2_subdev *sd,
1343 enum v4l2_exposure_auto_type value)
1344 {
1345 int ret;
1346 unsigned char com8;
1347
1348 ret = ov7670_read(sd, REG_COM8, &com8);
1349 if (ret == 0) {
1350 if (value == V4L2_EXPOSURE_AUTO)
1351 com8 |= COM8_AEC;
1352 else
1353 com8 &= ~COM8_AEC;
1354 ret = ov7670_write(sd, REG_COM8, com8);
1355 }
1356 return ret;
1357 }
1358
1359
1360
1361 static int ov7670_queryctrl(struct v4l2_subdev *sd,
1362 struct v4l2_queryctrl *qc)
1363 {
1364 /* Fill in min, max, step and default value for these controls. */
1365 switch (qc->id) {
1366 case V4L2_CID_BRIGHTNESS:
1367 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
1368 case V4L2_CID_CONTRAST:
1369 return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64);
1370 case V4L2_CID_VFLIP:
1371 case V4L2_CID_HFLIP:
1372 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
1373 case V4L2_CID_SATURATION:
1374 return v4l2_ctrl_query_fill(qc, 0, 256, 1, 128);
1375 case V4L2_CID_HUE:
1376 return v4l2_ctrl_query_fill(qc, -180, 180, 5, 0);
1377 case V4L2_CID_GAIN:
1378 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
1379 case V4L2_CID_AUTOGAIN:
1380 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1);
1381 case V4L2_CID_EXPOSURE:
1382 return v4l2_ctrl_query_fill(qc, 0, 65535, 1, 500);
1383 case V4L2_CID_EXPOSURE_AUTO:
1384 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
1385 }
1386 return -EINVAL;
1387 }
1388
1389 static int ov7670_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
1390 {
1391 switch (ctrl->id) {
1392 case V4L2_CID_BRIGHTNESS:
1393 return ov7670_g_brightness(sd, &ctrl->value);
1394 case V4L2_CID_CONTRAST:
1395 return ov7670_g_contrast(sd, &ctrl->value);
1396 case V4L2_CID_SATURATION:
1397 return ov7670_g_sat(sd, &ctrl->value);
1398 case V4L2_CID_HUE:
1399 return ov7670_g_hue(sd, &ctrl->value);
1400 case V4L2_CID_VFLIP:
1401 return ov7670_g_vflip(sd, &ctrl->value);
1402 case V4L2_CID_HFLIP:
1403 return ov7670_g_hflip(sd, &ctrl->value);
1404 case V4L2_CID_GAIN:
1405 return ov7670_g_gain(sd, &ctrl->value);
1406 case V4L2_CID_AUTOGAIN:
1407 return ov7670_g_autogain(sd, &ctrl->value);
1408 case V4L2_CID_EXPOSURE:
1409 return ov7670_g_exp(sd, &ctrl->value);
1410 case V4L2_CID_EXPOSURE_AUTO:
1411 return ov7670_g_autoexp(sd, &ctrl->value);
1412 }
1413 return -EINVAL;
1414 }
1415
1416 static int ov7670_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
1417 {
1418 switch (ctrl->id) {
1419 case V4L2_CID_BRIGHTNESS:
1420 return ov7670_s_brightness(sd, ctrl->value);
1421 case V4L2_CID_CONTRAST:
1422 return ov7670_s_contrast(sd, ctrl->value);
1423 case V4L2_CID_SATURATION:
1424 return ov7670_s_sat(sd, ctrl->value);
1425 case V4L2_CID_HUE:
1426 return ov7670_s_hue(sd, ctrl->value);
1427 case V4L2_CID_VFLIP:
1428 return ov7670_s_vflip(sd, ctrl->value);
1429 case V4L2_CID_HFLIP:
1430 return ov7670_s_hflip(sd, ctrl->value);
1431 case V4L2_CID_GAIN:
1432 return ov7670_s_gain(sd, ctrl->value);
1433 case V4L2_CID_AUTOGAIN:
1434 return ov7670_s_autogain(sd, ctrl->value);
1435 case V4L2_CID_EXPOSURE:
1436 return ov7670_s_exp(sd, ctrl->value);
1437 case V4L2_CID_EXPOSURE_AUTO:
1438 return ov7670_s_autoexp(sd,
1439 (enum v4l2_exposure_auto_type) ctrl->value);
1440 }
1441 return -EINVAL;
1442 }
1443
1444 static int ov7670_g_chip_ident(struct v4l2_subdev *sd,
1445 struct v4l2_dbg_chip_ident *chip)
1446 {
1447 struct i2c_client *client = v4l2_get_subdevdata(sd);
1448
1449 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_OV7670, 0);
1450 }
1451
1452 #ifdef CONFIG_VIDEO_ADV_DEBUG
1453 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1454 {
1455 struct i2c_client *client = v4l2_get_subdevdata(sd);
1456 unsigned char val = 0;
1457 int ret;
1458
1459 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1460 return -EINVAL;
1461 if (!capable(CAP_SYS_ADMIN))
1462 return -EPERM;
1463 ret = ov7670_read(sd, reg->reg & 0xff, &val);
1464 reg->val = val;
1465 reg->size = 1;
1466 return ret;
1467 }
1468
1469 static int ov7670_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1470 {
1471 struct i2c_client *client = v4l2_get_subdevdata(sd);
1472
1473 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1474 return -EINVAL;
1475 if (!capable(CAP_SYS_ADMIN))
1476 return -EPERM;
1477 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1478 return 0;
1479 }
1480 #endif
1481
1482 /* ----------------------------------------------------------------------- */
1483
1484 static const struct v4l2_subdev_core_ops ov7670_core_ops = {
1485 .g_chip_ident = ov7670_g_chip_ident,
1486 .g_ctrl = ov7670_g_ctrl,
1487 .s_ctrl = ov7670_s_ctrl,
1488 .queryctrl = ov7670_queryctrl,
1489 .reset = ov7670_reset,
1490 .init = ov7670_init,
1491 #ifdef CONFIG_VIDEO_ADV_DEBUG
1492 .g_register = ov7670_g_register,
1493 .s_register = ov7670_s_register,
1494 #endif
1495 };
1496
1497 static const struct v4l2_subdev_video_ops ov7670_video_ops = {
1498 .enum_mbus_fmt = ov7670_enum_mbus_fmt,
1499 .try_mbus_fmt = ov7670_try_mbus_fmt,
1500 .s_mbus_fmt = ov7670_s_mbus_fmt,
1501 .s_parm = ov7670_s_parm,
1502 .g_parm = ov7670_g_parm,
1503 .enum_frameintervals = ov7670_enum_frameintervals,
1504 .enum_framesizes = ov7670_enum_framesizes,
1505 };
1506
1507 static const struct v4l2_subdev_ops ov7670_ops = {
1508 .core = &ov7670_core_ops,
1509 .video = &ov7670_video_ops,
1510 };
1511
1512 /* ----------------------------------------------------------------------- */
1513
1514 static int ov7670_probe(struct i2c_client *client,
1515 const struct i2c_device_id *id)
1516 {
1517 struct v4l2_subdev *sd;
1518 struct ov7670_info *info;
1519 int ret;
1520
1521 info = kzalloc(sizeof(struct ov7670_info), GFP_KERNEL);
1522 if (info == NULL)
1523 return -ENOMEM;
1524 sd = &info->sd;
1525 v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1526
1527 info->clock_speed = 30; /* default: a guess */
1528 if (client->dev.platform_data) {
1529 struct ov7670_config *config = client->dev.platform_data;
1530
1531 /*
1532 * Must apply configuration before initializing device, because it
1533 * selects I/O method.
1534 */
1535 info->min_width = config->min_width;
1536 info->min_height = config->min_height;
1537 info->use_smbus = config->use_smbus;
1538
1539 if (config->clock_speed)
1540 info->clock_speed = config->clock_speed;
1541 }
1542
1543 /* Make sure it's an ov7670 */
1544 ret = ov7670_detect(sd);
1545 if (ret) {
1546 v4l_dbg(1, debug, client,
1547 "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1548 client->addr << 1, client->adapter->name);
1549 kfree(info);
1550 return ret;
1551 }
1552 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1553 client->addr << 1, client->adapter->name);
1554
1555 info->fmt = &ov7670_formats[0];
1556 info->sat = 128; /* Review this */
1557 info->clkrc = info->clock_speed / 30;
1558 return 0;
1559 }
1560
1561
1562 static int ov7670_remove(struct i2c_client *client)
1563 {
1564 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1565
1566 v4l2_device_unregister_subdev(sd);
1567 kfree(to_state(sd));
1568 return 0;
1569 }
1570
1571 static const struct i2c_device_id ov7670_id[] = {
1572 { "ov7670", 0 },
1573 { }
1574 };
1575 MODULE_DEVICE_TABLE(i2c, ov7670_id);
1576
1577 static struct i2c_driver ov7670_driver = {
1578 .driver = {
1579 .owner = THIS_MODULE,
1580 .name = "ov7670",
1581 },
1582 .probe = ov7670_probe,
1583 .remove = ov7670_remove,
1584 .id_table = ov7670_id,
1585 };
1586
1587 static __init int init_ov7670(void)
1588 {
1589 return i2c_add_driver(&ov7670_driver);
1590 }
1591
1592 static __exit void exit_ov7670(void)
1593 {
1594 i2c_del_driver(&ov7670_driver);
1595 }
1596
1597 module_init(init_ov7670);
1598 module_exit(exit_ov7670);