drivers/mtd/nand/mpc5121_nfc.c

   1 /*
   2  * Copyright 2004-2008 Freescale Semiconductor, Inc.
   3  * Copyright 2009 Semihalf.
   4  *
   5  * Approved as OSADL project by a majority of OSADL members and funded
   6  * by OSADL membership fees in 2009;  for details see www.osadl.org.
   7  *
   8  * Based on original driver from Freescale Semiconductor
   9  * written by John Rigby <jrigby@freescale.com> on basis
  10  * of drivers/mtd/nand/mxc_nand.c. Reworked and extended
  11  * Piotr Ziecik <kosmo@semihalf.com>.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  25  * MA 02110-1301, USA.
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/clk.h>
  30 #include <linux/gfp.h>
  31 #include <linux/delay.h>
  32 #include <linux/err.h>
  33 #include <linux/init.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/io.h>
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38 #include <linux/mtd/partitions.h>
  39 #include <linux/of_device.h>
  40 #include <linux/of_platform.h>
  41
  42 #include <asm/mpc5121.h>
  43
  44 /* Addresses for NFC MAIN RAM BUFFER areas */
  45 #define NFC_MAIN_AREA(n)        ((n) *  0x200)
  46
  47 /* Addresses for NFC SPARE BUFFER areas */
  48 #define NFC_SPARE_BUFFERS       8
  49 #define NFC_SPARE_LEN           0x40
  50 #define NFC_SPARE_AREA(n)       (0x1000 + ((n) * NFC_SPARE_LEN))
  51
  52 /* MPC5121 NFC registers */
  53 #define NFC_BUF_ADDR            0x1E04
  54 #define NFC_FLASH_ADDR          0x1E06
  55 #define NFC_FLASH_CMD           0x1E08
  56 #define NFC_CONFIG              0x1E0A
  57 #define NFC_ECC_STATUS1         0x1E0C
  58 #define NFC_ECC_STATUS2         0x1E0E
  59 #define NFC_SPAS                0x1E10
  60 #define NFC_WRPROT              0x1E12
  61 #define NFC_NF_WRPRST           0x1E18
  62 #define NFC_CONFIG1             0x1E1A
  63 #define NFC_CONFIG2             0x1E1C
  64 #define NFC_UNLOCKSTART_BLK0    0x1E20
  65 #define NFC_UNLOCKEND_BLK0      0x1E22
  66 #define NFC_UNLOCKSTART_BLK1    0x1E24
  67 #define NFC_UNLOCKEND_BLK1      0x1E26
  68 #define NFC_UNLOCKSTART_BLK2    0x1E28
  69 #define NFC_UNLOCKEND_BLK2      0x1E2A
  70 #define NFC_UNLOCKSTART_BLK3    0x1E2C
  71 #define NFC_UNLOCKEND_BLK3      0x1E2E
  72
  73 /* Bit Definitions: NFC_BUF_ADDR */
  74 #define NFC_RBA_MASK            (7 << 0)
  75 #define NFC_ACTIVE_CS_SHIFT     5
  76 #define NFC_ACTIVE_CS_MASK      (3 << NFC_ACTIVE_CS_SHIFT)
  77
  78 /* Bit Definitions: NFC_CONFIG */
  79 #define NFC_BLS_UNLOCKED        (1 << 1)
  80
  81 /* Bit Definitions: NFC_CONFIG1 */
  82 #define NFC_ECC_4BIT            (1 << 0)
  83 #define NFC_FULL_PAGE_DMA       (1 << 1)
  84 #define NFC_SPARE_ONLY          (1 << 2)
  85 #define NFC_ECC_ENABLE          (1 << 3)
  86 #define NFC_INT_MASK            (1 << 4)
  87 #define NFC_BIG_ENDIAN          (1 << 5)
  88 #define NFC_RESET               (1 << 6)
  89 #define NFC_CE                  (1 << 7)
  90 #define NFC_ONE_CYCLE           (1 << 8)
  91 #define NFC_PPB_32              (0 << 9)
  92 #define NFC_PPB_64              (1 << 9)
  93 #define NFC_PPB_128             (2 << 9)
  94 #define NFC_PPB_256             (3 << 9)
  95 #define NFC_PPB_MASK            (3 << 9)
  96 #define NFC_FULL_PAGE_INT       (1 << 11)
  97
  98 /* Bit Definitions: NFC_CONFIG2 */
  99 #define NFC_COMMAND             (1 << 0)
 100 #define NFC_ADDRESS             (1 << 1)
 101 #define NFC_INPUT               (1 << 2)
 102 #define NFC_OUTPUT              (1 << 3)
 103 #define NFC_ID                  (1 << 4)
 104 #define NFC_STATUS              (1 << 5)
 105 #define NFC_CMD_FAIL            (1 << 15)
 106 #define NFC_INT                 (1 << 15)
 107
 108 /* Bit Definitions: NFC_WRPROT */
 109 #define NFC_WPC_LOCK_TIGHT      (1 << 0)
 110 #define NFC_WPC_LOCK            (1 << 1)
 111 #define NFC_WPC_UNLOCK          (1 << 2)
 112
 113 #define DRV_NAME                "mpc5121_nfc"
 114
 115 /* Timeouts */
 116 #define NFC_RESET_TIMEOUT       1000            /* 1 ms */
 117 #define NFC_TIMEOUT             (HZ / 10)       /* 1/10 s */
 118
 119 struct mpc5121_nfc_prv {
 120         struct mtd_info         mtd;
 121         struct nand_chip        chip;
 122         int                     irq;
 123         void __iomem            *regs;
 124         struct clk              *clk;
 125         wait_queue_head_t       irq_waitq;
 126         uint                    column;
 127         int                     spareonly;
 128         void __iomem            *csreg;
 129         struct device           *dev;
 130 };
 131
 132 static void mpc5121_nfc_done(struct mtd_info *mtd);
 133
 134 #ifdef CONFIG_MTD_PARTITIONS
 135 static const char *mpc5121_nfc_pprobes[] = { "cmdlinepart", NULL };
 136 #endif
 137
 138 /* Read NFC register */
 139 static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
 140 {
 141         struct nand_chip *chip = mtd->priv;
 142         struct mpc5121_nfc_prv *prv = chip->priv;
 143
 144         return in_be16(prv->regs + reg);
 145 }
 146
 147 /* Write NFC register */
 148 static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
 149 {
 150         struct nand_chip *chip = mtd->priv;
 151         struct mpc5121_nfc_prv *prv = chip->priv;
 152
 153         out_be16(prv->regs + reg, val);
 154 }
 155
 156 /* Set bits in NFC register */
 157 static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
 158 {
 159         nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
 160 }
 161
 162 /* Clear bits in NFC register */
 163 static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
 164 {
 165         nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
 166 }
 167
 168 /* Invoke address cycle */
 169 static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
 170 {
 171         nfc_write(mtd, NFC_FLASH_ADDR, addr);
 172         nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
 173         mpc5121_nfc_done(mtd);
 174 }
 175
 176 /* Invoke command cycle */
 177 static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
 178 {
 179         nfc_write(mtd, NFC_FLASH_CMD, cmd);
 180         nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
 181         mpc5121_nfc_done(mtd);
 182 }
 183
 184 /* Send data from NFC buffers to NAND flash */
 185 static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
 186 {
 187         nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
 188         nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
 189         mpc5121_nfc_done(mtd);
 190 }
 191
 192 /* Receive data from NAND flash */
 193 static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
 194 {
 195         nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
 196         nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
 197         mpc5121_nfc_done(mtd);
 198 }
 199
 200 /* Receive ID from NAND flash */
 201 static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
 202 {
 203         nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
 204         nfc_write(mtd, NFC_CONFIG2, NFC_ID);
 205         mpc5121_nfc_done(mtd);
 206 }
 207
 208 /* Receive status from NAND flash */
 209 static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
 210 {
 211         nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
 212         nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
 213         mpc5121_nfc_done(mtd);
 214 }
 215
 216 /* NFC interrupt handler */
 217 static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
 218 {
 219         struct mtd_info *mtd = data;
 220         struct nand_chip *chip = mtd->priv;
 221         struct mpc5121_nfc_prv *prv = chip->priv;
 222
 223         nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
 224         wake_up(&prv->irq_waitq);
 225
 226         return IRQ_HANDLED;
 227 }
 228
 229 /* Wait for operation complete */
 230 static void mpc5121_nfc_done(struct mtd_info *mtd)
 231 {
 232         struct nand_chip *chip = mtd->priv;
 233         struct mpc5121_nfc_prv *prv = chip->priv;
 234         int rv;
 235
 236         if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
 237                 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
 238                 rv = wait_event_timeout(prv->irq_waitq,
 239                         (nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
 240
 241                 if (!rv)
 242                         dev_warn(prv->dev,
 243                                 "Timeout while waiting for interrupt.\n");
 244         }
 245
 246         nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
 247 }
 248
 249 /* Do address cycle(s) */
 250 static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
 251 {
 252         struct nand_chip *chip = mtd->priv;
 253         u32 pagemask = chip->pagemask;
 254
 255         if (column != -1) {
 256                 mpc5121_nfc_send_addr(mtd, column);
 257                 if (mtd->writesize > 512)
 258                         mpc5121_nfc_send_addr(mtd, column >> 8);
 259         }
 260
 261         if (page != -1) {
 262                 do {
 263                         mpc5121_nfc_send_addr(mtd, page & 0xFF);
 264                         page >>= 8;
 265                         pagemask >>= 8;
 266                 } while (pagemask);
 267         }
 268 }
 269
 270 /* Control chip select signals */
 271 static void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
 272 {
 273         if (chip < 0) {
 274                 nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
 275                 return;
 276         }
 277
 278         nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
 279         nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
 280                                                         NFC_ACTIVE_CS_MASK);
 281         nfc_set(mtd, NFC_CONFIG1, NFC_CE);
 282 }
 283
 284 /* Init external chip select logic on ADS5121 board */
 285 static int ads5121_chipselect_init(struct mtd_info *mtd)
 286 {
 287         struct nand_chip *chip = mtd->priv;
 288         struct mpc5121_nfc_prv *prv = chip->priv;
 289         struct device_node *dn;
 290
 291         dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
 292         if (dn) {
 293                 prv->csreg = of_iomap(dn, 0);
 294                 of_node_put(dn);
 295                 if (!prv->csreg)
 296                         return -ENOMEM;
 297
 298                 /* CPLD Register 9 controls NAND /CE Lines */
 299                 prv->csreg += 9;
 300                 return 0;
 301         }
 302
 303         return -EINVAL;
 304 }
 305
 306 /* Control chips select signal on ADS5121 board */
 307 static void ads5121_select_chip(struct mtd_info *mtd, int chip)
 308 {
 309         struct nand_chip *nand = mtd->priv;
 310         struct mpc5121_nfc_prv *prv = nand->priv;
 311         u8 v;
 312
 313         v = in_8(prv->csreg);
 314         v |= 0x0F;
 315
 316         if (chip >= 0) {
 317                 mpc5121_nfc_select_chip(mtd, 0);
 318                 v &= ~(1 << chip);
 319         } else
 320                 mpc5121_nfc_select_chip(mtd, -1);
 321
 322         out_8(prv->csreg, v);
 323 }
 324
 325 /* Read NAND Ready/Busy signal */
 326 static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
 327 {
 328         /*
 329          * NFC handles ready/busy signal internally. Therefore, this function
 330          * always returns status as ready.
 331          */
 332         return 1;
 333 }
 334
 335 /* Write command to NAND flash */
 336 static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
 337                                                         int column, int page)
 338 {
 339         struct nand_chip *chip = mtd->priv;
 340         struct mpc5121_nfc_prv *prv = chip->priv;
 341
 342         prv->column = (column >= 0) ? column : 0;
 343         prv->spareonly = 0;
 344
 345         switch (command) {
 346         case NAND_CMD_PAGEPROG:
 347                 mpc5121_nfc_send_prog_page(mtd);
 348                 break;
 349         /*
 350          * NFC does not support sub-page reads and writes,
 351          * so emulate them using full page transfers.
 352          */
 353         case NAND_CMD_READ0:
 354                 column = 0;
 355                 break;
 356
 357         case NAND_CMD_READ1:
 358                 prv->column += 256;
 359                 command = NAND_CMD_READ0;
 360                 column = 0;
 361                 break;
 362
 363         case NAND_CMD_READOOB:
 364                 prv->spareonly = 1;
 365                 command = NAND_CMD_READ0;
 366                 column = 0;
 367                 break;
 368
 369         case NAND_CMD_SEQIN:
 370                 mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page);
 371                 column = 0;
 372                 break;
 373
 374         case NAND_CMD_ERASE1:
 375         case NAND_CMD_ERASE2:
 376         case NAND_CMD_READID:
 377         case NAND_CMD_STATUS:
 378                 break;
 379
 380         default:
 381                 return;
 382         }
 383
 384         mpc5121_nfc_send_cmd(mtd, command);
 385         mpc5121_nfc_addr_cycle(mtd, column, page);
 386
 387         switch (command) {
 388         case NAND_CMD_READ0:
 389                 if (mtd->writesize > 512)
 390                         mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
 391                 mpc5121_nfc_send_read_page(mtd);
 392                 break;
 393
 394         case NAND_CMD_READID:
 395                 mpc5121_nfc_send_read_id(mtd);
 396                 break;
 397
 398         case NAND_CMD_STATUS:
 399                 mpc5121_nfc_send_read_status(mtd);
 400                 if (chip->options & NAND_BUSWIDTH_16)
 401                         prv->column = 1;
 402                 else
 403                         prv->column = 0;
 404                 break;
 405         }
 406 }
 407
 408 /* Copy data from/to NFC spare buffers. */
 409 static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
 410                                                 u8 *buffer, uint size, int wr)
 411 {
 412         struct nand_chip *nand = mtd->priv;
 413         struct mpc5121_nfc_prv *prv = nand->priv;
 414         uint o, s, sbsize, blksize;
 415
 416         /*
 417          * NAND spare area is available through NFC spare buffers.
 418          * The NFC divides spare area into (page_size / 512) chunks.
 419          * Each chunk is placed into separate spare memory area, using
 420          * first (spare_size / num_of_chunks) bytes of the buffer.
 421          *
 422          * For NAND device in which the spare area is not divided fully
 423          * by the number of chunks, number of used bytes in each spare
 424          * buffer is rounded down to the nearest even number of bytes,
 425          * and all remaining bytes are added to the last used spare area.
 426          *
 427          * For more information read section 26.6.10 of MPC5121e
 428          * Microcontroller Reference Manual, Rev. 3.
 429          */
 430
 431         /* Calculate number of valid bytes in each spare buffer */
 432         sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
 433
 434         while (size) {
 435                 /* Calculate spare buffer number */
 436                 s = offset / sbsize;
 437                 if (s > NFC_SPARE_BUFFERS - 1)
 438                         s = NFC_SPARE_BUFFERS - 1;
 439
 440                 /*
 441                  * Calculate offset to requested data block in selected spare
 442                  * buffer and its size.
 443                  */
 444                 o = offset - (s * sbsize);
 445                 blksize = min(sbsize - o, size);
 446
 447                 if (wr)
 448                         memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
 449                                                         buffer, blksize);
 450                 else
 451                         memcpy_fromio(buffer,
 452                                 prv->regs + NFC_SPARE_AREA(s) + o, blksize);
 453
 454                 buffer += blksize;
 455                 offset += blksize;
 456                 size -= blksize;
 457         };
 458 }
 459
 460 /* Copy data from/to NFC main and spare buffers */
 461 static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
 462                                                                         int wr)
 463 {
 464         struct nand_chip *chip = mtd->priv;
 465         struct mpc5121_nfc_prv *prv = chip->priv;
 466         uint c = prv->column;
 467         uint l;
 468
 469         /* Handle spare area access */
 470         if (prv->spareonly || c >= mtd->writesize) {
 471                 /* Calculate offset from beginning of spare area */
 472                 if (c >= mtd->writesize)
 473                         c -= mtd->writesize;
 474
 475                 prv->column += len;
 476                 mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
 477                 return;
 478         }
 479
 480         /*
 481          * Handle main area access - limit copy length to prevent
 482          * crossing main/spare boundary.
 483          */
 484         l = min((uint)len, mtd->writesize - c);
 485         prv->column += l;
 486
 487         if (wr)
 488                 memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
 489         else
 490                 memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
 491
 492         /* Handle crossing main/spare boundary */
 493         if (l != len) {
 494                 buf += l;
 495                 len -= l;
 496                 mpc5121_nfc_buf_copy(mtd, buf, len, wr);
 497         }
 498 }
 499
 500 /* Read data from NFC buffers */
 501 static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 502 {
 503         mpc5121_nfc_buf_copy(mtd, buf, len, 0);
 504 }
 505
 506 /* Write data to NFC buffers */
 507 static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
 508                                                 const u_char *buf, int len)
 509 {
 510         mpc5121_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
 511 }
 512
 513 /* Compare buffer with NAND flash */
 514 static int mpc5121_nfc_verify_buf(struct mtd_info *mtd,
 515                                                 const u_char *buf, int len)
 516 {
 517         u_char tmp[256];
 518         uint bsize;
 519
 520         while (len) {
 521                 bsize = min(len, 256);
 522                 mpc5121_nfc_read_buf(mtd, tmp, bsize);
 523
 524                 if (memcmp(buf, tmp, bsize))
 525                         return 1;
 526
 527                 buf += bsize;
 528                 len -= bsize;
 529         }
 530
 531         return 0;
 532 }
 533
 534 /* Read byte from NFC buffers */
 535 static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
 536 {
 537         u8 tmp;
 538
 539         mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp));
 540
 541         return tmp;
 542 }
 543
 544 /* Read word from NFC buffers */
 545 static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
 546 {
 547         u16 tmp;
 548
 549         mpc5121_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
 550
 551         return tmp;
 552 }
 553
 554 /*
 555  * Read NFC configuration from Reset Config Word
 556  *
 557  * NFC is configured during reset in basis of information stored
 558  * in Reset Config Word. There is no other way to set NAND block
 559  * size, spare size and bus width.
 560  */
 561 static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
 562 {
 563         struct nand_chip *chip = mtd->priv;
 564         struct mpc5121_nfc_prv *prv = chip->priv;
 565         struct mpc512x_reset_module *rm;
 566         struct device_node *rmnode;
 567         uint rcw_pagesize = 0;
 568         uint rcw_sparesize = 0;
 569         uint rcw_width;
 570         uint rcwh;
 571         uint romloc, ps;
 572         int ret = 0;
 573
 574         rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
 575         if (!rmnode) {
 576                 dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' "
 577                                         "node in device tree!\n");
 578                 return -ENODEV;
 579         }
 580
 581         rm = of_iomap(rmnode, 0);
 582         if (!rm) {
 583                 dev_err(prv->dev, "Error mapping reset module node!\n");
 584                 ret = -EBUSY;
 585                 goto out;
 586         }
 587
 588         rcwh = in_be32(&rm->rcwhr);
 589
 590         /* Bit 6: NFC bus width */
 591         rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
 592
 593         /* Bit 7: NFC Page/Spare size */
 594         ps = (rcwh >> 7) & 0x1;
 595
 596         /* Bits [22:21]: ROM Location */
 597         romloc = (rcwh >> 21) & 0x3;
 598
 599         /* Decode RCW bits */
 600         switch ((ps << 2) | romloc) {
 601         case 0x00:
 602         case 0x01:
 603                 rcw_pagesize = 512;
 604                 rcw_sparesize = 16;
 605                 break;
 606         case 0x02:
 607         case 0x03:
 608                 rcw_pagesize = 4096;
 609                 rcw_sparesize = 128;
 610                 break;
 611         case 0x04:
 612         case 0x05:
 613                 rcw_pagesize = 2048;
 614                 rcw_sparesize = 64;
 615                 break;
 616         case 0x06:
 617         case 0x07:
 618                 rcw_pagesize = 4096;
 619                 rcw_sparesize = 218;
 620                 break;
 621         }
 622
 623         mtd->writesize = rcw_pagesize;
 624         mtd->oobsize = rcw_sparesize;
 625         if (rcw_width == 2)
 626                 chip->options |= NAND_BUSWIDTH_16;
 627
 628         dev_notice(prv->dev, "Configured for "
 629                                 "%u-bit NAND, page size %u "
 630                                 "with %u spare.\n",
 631                                 rcw_width * 8, rcw_pagesize,
 632                                 rcw_sparesize);
 633         iounmap(rm);
 634 out:
 635         of_node_put(rmnode);
 636         return ret;
 637 }
 638
 639 /* Free driver resources */
 640 static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
 641 {
 642         struct nand_chip *chip = mtd->priv;
 643         struct mpc5121_nfc_prv *prv = chip->priv;
 644
 645         if (prv->clk) {
 646                 clk_disable(prv->clk);
 647                 clk_put(prv->clk);
 648         }
 649
 650         if (prv->csreg)
 651                 iounmap(prv->csreg);
 652 }
 653
 654 static int __devinit mpc5121_nfc_probe(struct platform_device *op)
 655 {
 656         struct device_node *rootnode, *dn = op->dev.of_node;
 657         struct device *dev = &op->dev;
 658         struct mpc5121_nfc_prv *prv;
 659         struct resource res;
 660         struct mtd_info *mtd;
 661 #ifdef CONFIG_MTD_PARTITIONS
 662         struct mtd_partition *parts;
 663 #endif
 664         struct nand_chip *chip;
 665         unsigned long regs_paddr, regs_size;
 666         const __be32 *chips_no;
 667         int resettime = 0;
 668         int retval = 0;
 669         int rev, len;
 670
 671         /*
 672          * Check SoC revision. This driver supports only NFC
 673          * in MPC5121 revision 2 and MPC5123 revision 3.
 674          */
 675         rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
 676         if ((rev != 2) && (rev != 3)) {
 677                 dev_err(dev, "SoC revision %u is not supported!\n", rev);
 678                 return -ENXIO;
 679         }
 680
 681         prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
 682         if (!prv) {
 683                 dev_err(dev, "Memory exhausted!\n");
 684                 return -ENOMEM;
 685         }
 686
 687         mtd = &prv->mtd;
 688         chip = &prv->chip;
 689
 690         mtd->priv = chip;
 691         chip->priv = prv;
 692         prv->dev = dev;
 693
 694         /* Read NFC configuration from Reset Config Word */
 695         retval = mpc5121_nfc_read_hw_config(mtd);
 696         if (retval) {
 697                 dev_err(dev, "Unable to read NFC config!\n");
 698                 return retval;
 699         }
 700
 701         prv->irq = irq_of_parse_and_map(dn, 0);
 702         if (prv->irq == NO_IRQ) {
 703                 dev_err(dev, "Error mapping IRQ!\n");
 704                 return -EINVAL;
 705         }
 706
 707         retval = of_address_to_resource(dn, 0, &res);
 708         if (retval) {
 709                 dev_err(dev, "Error parsing memory region!\n");
 710                 return retval;
 711         }
 712
 713         chips_no = of_get_property(dn, "chips", &len);
 714         if (!chips_no || len != sizeof(*chips_no)) {
 715                 dev_err(dev, "Invalid/missing 'chips' property!\n");
 716                 return -EINVAL;
 717         }
 718
 719         regs_paddr = res.start;
 720         regs_size = res.end - res.start + 1;
 721
 722         if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
 723                 dev_err(dev, "Error requesting memory region!\n");
 724                 return -EBUSY;
 725         }
 726
 727         prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
 728         if (!prv->regs) {
 729                 dev_err(dev, "Error mapping memory region!\n");
 730                 return -ENOMEM;
 731         }
 732
 733         mtd->name = "MPC5121 NAND";
 734         chip->dev_ready = mpc5121_nfc_dev_ready;
 735         chip->cmdfunc = mpc5121_nfc_command;
 736         chip->read_byte = mpc5121_nfc_read_byte;
 737         chip->read_word = mpc5121_nfc_read_word;
 738         chip->read_buf = mpc5121_nfc_read_buf;
 739         chip->write_buf = mpc5121_nfc_write_buf;
 740         chip->verify_buf = mpc5121_nfc_verify_buf;
 741         chip->select_chip = mpc5121_nfc_select_chip;
 742         chip->options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT;
 743         chip->ecc.mode = NAND_ECC_SOFT;
 744
 745         /* Support external chip-select logic on ADS5121 board */
 746         rootnode = of_find_node_by_path("/");
 747         if (of_device_is_compatible(rootnode, "fsl,mpc5121ads")) {
 748                 retval = ads5121_chipselect_init(mtd);
 749                 if (retval) {
 750                         dev_err(dev, "Chipselect init error!\n");
 751                         of_node_put(rootnode);
 752                         return retval;
 753                 }
 754
 755                 chip->select_chip = ads5121_select_chip;
 756         }
 757         of_node_put(rootnode);
 758
 759         /* Enable NFC clock */
 760         prv->clk = clk_get(dev, "nfc_clk");
 761         if (IS_ERR(prv->clk)) {
 762                 dev_err(dev, "Unable to acquire NFC clock!\n");
 763                 retval = PTR_ERR(prv->clk);
 764                 goto error;
 765         }
 766
 767         clk_enable(prv->clk);
 768
 769         /* Reset NAND Flash controller */
 770         nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
 771         while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
 772                 if (resettime++ >= NFC_RESET_TIMEOUT) {
 773                         dev_err(dev, "Timeout while resetting NFC!\n");
 774                         retval = -EINVAL;
 775                         goto error;
 776                 }
 777
 778                 udelay(1);
 779         }
 780
 781         /* Enable write to NFC memory */
 782         nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
 783
 784         /* Enable write to all NAND pages */
 785         nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
 786         nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
 787         nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
 788
 789         /*
 790          * Setup NFC:
 791          *      - Big Endian transfers,
 792          *      - Interrupt after full page read/write.
 793          */
 794         nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
 795                                                         NFC_FULL_PAGE_INT);
 796
 797         /* Set spare area size */
 798         nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
 799
 800         init_waitqueue_head(&prv->irq_waitq);
 801         retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
 802                                                                         mtd);
 803         if (retval) {
 804                 dev_err(dev, "Error requesting IRQ!\n");
 805                 goto error;
 806         }
 807
 808         /* Detect NAND chips */
 809         if (nand_scan(mtd, be32_to_cpup(chips_no))) {
 810                 dev_err(dev, "NAND Flash not found !\n");
 811                 devm_free_irq(dev, prv->irq, mtd);
 812                 retval = -ENXIO;
 813                 goto error;
 814         }
 815
 816         /* Set erase block size */
 817         switch (mtd->erasesize / mtd->writesize) {
 818         case 32:
 819                 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
 820                 break;
 821
 822         case 64:
 823                 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
 824                 break;
 825
 826         case 128:
 827                 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
 828                 break;
 829
 830         case 256:
 831                 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
 832                 break;
 833
 834         default:
 835                 dev_err(dev, "Unsupported NAND flash!\n");
 836                 devm_free_irq(dev, prv->irq, mtd);
 837                 retval = -ENXIO;
 838                 goto error;
 839         }
 840
 841         dev_set_drvdata(dev, mtd);
 842
 843         /* Register device in MTD */
 844 #ifdef CONFIG_MTD_PARTITIONS
 845         retval = parse_mtd_partitions(mtd, mpc5121_nfc_pprobes, &parts, 0);
 846 #ifdef CONFIG_MTD_OF_PARTS
 847         if (retval == 0)
 848                 retval = of_mtd_parse_partitions(dev, dn, &parts);
 849 #endif
 850         if (retval < 0) {
 851                 dev_err(dev, "Error parsing MTD partitions!\n");
 852                 devm_free_irq(dev, prv->irq, mtd);
 853                 retval = -EINVAL;
 854                 goto error;
 855         }
 856
 857         if (retval > 0)
 858                 retval = add_mtd_partitions(mtd, parts, retval);
 859         else
 860 #endif
 861                 retval = add_mtd_device(mtd);
 862
 863         if (retval) {
 864                 dev_err(dev, "Error adding MTD device!\n");
 865                 devm_free_irq(dev, prv->irq, mtd);
 866                 goto error;
 867         }
 868
 869         return 0;
 870 error:
 871         mpc5121_nfc_free(dev, mtd);
 872         return retval;
 873 }
 874
 875 static int __devexit mpc5121_nfc_remove(struct platform_device *op)
 876 {
 877         struct device *dev = &op->dev;
 878         struct mtd_info *mtd = dev_get_drvdata(dev);
 879         struct nand_chip *chip = mtd->priv;
 880         struct mpc5121_nfc_prv *prv = chip->priv;
 881
 882         nand_release(mtd);
 883         devm_free_irq(dev, prv->irq, mtd);
 884         mpc5121_nfc_free(dev, mtd);
 885
 886         return 0;
 887 }
 888
 889 static struct of_device_id mpc5121_nfc_match[] __devinitdata = {
 890         { .compatible = "fsl,mpc5121-nfc", },
 891         {},
 892 };
 893
 894 static struct platform_driver mpc5121_nfc_driver = {
 895         .probe          = mpc5121_nfc_probe,
 896         .remove         = __devexit_p(mpc5121_nfc_remove),
 897         .driver         = {
 898                 .name = DRV_NAME,
 899                 .owner = THIS_MODULE,
 900                 .of_match_table = mpc5121_nfc_match,
 901         },
 902 };
 903
 904 static int __init mpc5121_nfc_init(void)
 905 {
 906         return platform_driver_register(&mpc5121_nfc_driver);
 907 }
 908
 909 module_init(mpc5121_nfc_init);
 910
 911 static void __exit mpc5121_nfc_cleanup(void)
 912 {
 913         platform_driver_unregister(&mpc5121_nfc_driver);
 914 }
 915
 916 module_exit(mpc5121_nfc_cleanup);
 917
 918 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 919 MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
 920 MODULE_LICENSE("GPL");