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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / net / 8139too.c
blob98517a373473e18b1a9f6982407831580079263a
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
93
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.28"
96
97
98 #include <linux/module.h>
99 #include <linux/kernel.h>
100 #include <linux/compiler.h>
101 #include <linux/pci.h>
102 #include <linux/init.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
111 #include <linux/io.h>
112 #include <linux/uaccess.h>
113 #include <linux/gfp.h>
114 #include <asm/irq.h>
115
116 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
117
118 /* Default Message level */
119 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
120 NETIF_MSG_PROBE | \
121 NETIF_MSG_LINK)
122
123
124 /* define to 1, 2 or 3 to enable copious debugging info */
125 #define RTL8139_DEBUG 0
126
127 /* define to 1 to disable lightweight runtime debugging checks */
128 #undef RTL8139_NDEBUG
129
130
131 #ifdef RTL8139_NDEBUG
132 # define assert(expr) do {} while (0)
133 #else
134 # define assert(expr) \
135 if (unlikely(!(expr))) { \
136 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
137 #expr, __FILE__, __func__, __LINE__); \
138 }
139 #endif
140
141
142 /* A few user-configurable values. */
143 /* media options */
144 #define MAX_UNITS 8
145 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
146 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
147
148 /* Whether to use MMIO or PIO. Default to MMIO. */
149 #ifdef CONFIG_8139TOO_PIO
150 static int use_io = 1;
151 #else
152 static int use_io = 0;
153 #endif
154
155 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
156 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
157 static int multicast_filter_limit = 32;
158
159 /* bitmapped message enable number */
160 static int debug = -1;
161
162 /*
163 * Receive ring size
164 * Warning: 64K ring has hardware issues and may lock up.
165 */
166 #if defined(CONFIG_SH_DREAMCAST)
167 #define RX_BUF_IDX 0 /* 8K ring */
168 #else
169 #define RX_BUF_IDX 2 /* 32K ring */
170 #endif
171 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
172 #define RX_BUF_PAD 16
173 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
174
175 #if RX_BUF_LEN == 65536
176 #define RX_BUF_TOT_LEN RX_BUF_LEN
177 #else
178 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
179 #endif
180
181 /* Number of Tx descriptor registers. */
182 #define NUM_TX_DESC 4
183
184 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
185 #define MAX_ETH_FRAME_SIZE 1536
186
187 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
188 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
189 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
190
191 /* PCI Tuning Parameters
192 Threshold is bytes transferred to chip before transmission starts. */
193 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
194
195 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
196 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
197 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
198 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
199 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
200
201 /* Operational parameters that usually are not changed. */
202 /* Time in jiffies before concluding the transmitter is hung. */
203 #define TX_TIMEOUT (6*HZ)
204
205
206 enum {
207 HAS_MII_XCVR = 0x010000,
208 HAS_CHIP_XCVR = 0x020000,
209 HAS_LNK_CHNG = 0x040000,
210 };
211
212 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
213 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
214 #define RTL_MIN_IO_SIZE 0x80
215 #define RTL8139B_IO_SIZE 256
216
217 #define RTL8129_CAPS HAS_MII_XCVR
218 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
219
220 typedef enum {
221 RTL8139 = 0,
222 RTL8129,
223 } board_t;
224
225
226 /* indexed by board_t, above */
227 static const struct {
228 const char *name;
229 u32 hw_flags;
230 } board_info[] __devinitdata = {
231 { "RealTek RTL8139", RTL8139_CAPS },
232 { "RealTek RTL8129", RTL8129_CAPS },
233 };
234
235
236 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {
237 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
238 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
239 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
240 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
241 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256
257 #ifdef CONFIG_SH_SECUREEDGE5410
258 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
259 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 #endif
261 #ifdef CONFIG_8139TOO_8129
262 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
263 #endif
264
265 /* some crazy cards report invalid vendor ids like
266 * 0x0001 here. The other ids are valid and constant,
267 * so we simply don't match on the main vendor id.
268 */
269 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
270 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
271 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
272
273 {0,}
274 };
275 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
276
277 static struct {
278 const char str[ETH_GSTRING_LEN];
279 } ethtool_stats_keys[] = {
280 { "early_rx" },
281 { "tx_buf_mapped" },
282 { "tx_timeouts" },
283 { "rx_lost_in_ring" },
284 };
285
286 /* The rest of these values should never change. */
287
288 /* Symbolic offsets to registers. */
289 enum RTL8139_registers {
290 MAC0 = 0, /* Ethernet hardware address. */
291 MAR0 = 8, /* Multicast filter. */
292 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
293 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
294 RxBuf = 0x30,
295 ChipCmd = 0x37,
296 RxBufPtr = 0x38,
297 RxBufAddr = 0x3A,
298 IntrMask = 0x3C,
299 IntrStatus = 0x3E,
300 TxConfig = 0x40,
301 RxConfig = 0x44,
302 Timer = 0x48, /* A general-purpose counter. */
303 RxMissed = 0x4C, /* 24 bits valid, write clears. */
304 Cfg9346 = 0x50,
305 Config0 = 0x51,
306 Config1 = 0x52,
307 TimerInt = 0x54,
308 MediaStatus = 0x58,
309 Config3 = 0x59,
310 Config4 = 0x5A, /* absent on RTL-8139A */
311 HltClk = 0x5B,
312 MultiIntr = 0x5C,
313 TxSummary = 0x60,
314 BasicModeCtrl = 0x62,
315 BasicModeStatus = 0x64,
316 NWayAdvert = 0x66,
317 NWayLPAR = 0x68,
318 NWayExpansion = 0x6A,
319 /* Undocumented registers, but required for proper operation. */
320 FIFOTMS = 0x70, /* FIFO Control and test. */
321 CSCR = 0x74, /* Chip Status and Configuration Register. */
322 PARA78 = 0x78,
323 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
324 PARA7c = 0x7c, /* Magic transceiver parameter register. */
325 Config5 = 0xD8, /* absent on RTL-8139A */
326 };
327
328 enum ClearBitMasks {
329 MultiIntrClear = 0xF000,
330 ChipCmdClear = 0xE2,
331 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
332 };
333
334 enum ChipCmdBits {
335 CmdReset = 0x10,
336 CmdRxEnb = 0x08,
337 CmdTxEnb = 0x04,
338 RxBufEmpty = 0x01,
339 };
340
341 /* Interrupt register bits, using my own meaningful names. */
342 enum IntrStatusBits {
343 PCIErr = 0x8000,
344 PCSTimeout = 0x4000,
345 RxFIFOOver = 0x40,
346 RxUnderrun = 0x20,
347 RxOverflow = 0x10,
348 TxErr = 0x08,
349 TxOK = 0x04,
350 RxErr = 0x02,
351 RxOK = 0x01,
352
353 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
354 };
355
356 enum TxStatusBits {
357 TxHostOwns = 0x2000,
358 TxUnderrun = 0x4000,
359 TxStatOK = 0x8000,
360 TxOutOfWindow = 0x20000000,
361 TxAborted = 0x40000000,
362 TxCarrierLost = 0x80000000,
363 };
364 enum RxStatusBits {
365 RxMulticast = 0x8000,
366 RxPhysical = 0x4000,
367 RxBroadcast = 0x2000,
368 RxBadSymbol = 0x0020,
369 RxRunt = 0x0010,
370 RxTooLong = 0x0008,
371 RxCRCErr = 0x0004,
372 RxBadAlign = 0x0002,
373 RxStatusOK = 0x0001,
374 };
375
376 /* Bits in RxConfig. */
377 enum rx_mode_bits {
378 AcceptErr = 0x20,
379 AcceptRunt = 0x10,
380 AcceptBroadcast = 0x08,
381 AcceptMulticast = 0x04,
382 AcceptMyPhys = 0x02,
383 AcceptAllPhys = 0x01,
384 };
385
386 /* Bits in TxConfig. */
387 enum tx_config_bits {
388 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
389 TxIFGShift = 24,
390 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
391 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
392 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
393 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
394
395 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
396 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
397 TxClearAbt = (1 << 0), /* Clear abort (WO) */
398 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
399 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
400
401 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
402 };
403
404 /* Bits in Config1 */
405 enum Config1Bits {
406 Cfg1_PM_Enable = 0x01,
407 Cfg1_VPD_Enable = 0x02,
408 Cfg1_PIO = 0x04,
409 Cfg1_MMIO = 0x08,
410 LWAKE = 0x10, /* not on 8139, 8139A */
411 Cfg1_Driver_Load = 0x20,
412 Cfg1_LED0 = 0x40,
413 Cfg1_LED1 = 0x80,
414 SLEEP = (1 << 1), /* only on 8139, 8139A */
415 PWRDN = (1 << 0), /* only on 8139, 8139A */
416 };
417
418 /* Bits in Config3 */
419 enum Config3Bits {
420 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
421 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
422 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
423 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
424 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
425 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
426 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
427 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
428 };
429
430 /* Bits in Config4 */
431 enum Config4Bits {
432 LWPTN = (1 << 2), /* not on 8139, 8139A */
433 };
434
435 /* Bits in Config5 */
436 enum Config5Bits {
437 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
438 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
439 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
440 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
441 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
442 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
443 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
444 };
445
446 enum RxConfigBits {
447 /* rx fifo threshold */
448 RxCfgFIFOShift = 13,
449 RxCfgFIFONone = (7 << RxCfgFIFOShift),
450
451 /* Max DMA burst */
452 RxCfgDMAShift = 8,
453 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
454
455 /* rx ring buffer length */
456 RxCfgRcv8K = 0,
457 RxCfgRcv16K = (1 << 11),
458 RxCfgRcv32K = (1 << 12),
459 RxCfgRcv64K = (1 << 11) | (1 << 12),
460
461 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
462 RxNoWrap = (1 << 7),
463 };
464
465 /* Twister tuning parameters from RealTek.
466 Completely undocumented, but required to tune bad links on some boards. */
467 enum CSCRBits {
468 CSCR_LinkOKBit = 0x0400,
469 CSCR_LinkChangeBit = 0x0800,
470 CSCR_LinkStatusBits = 0x0f000,
471 CSCR_LinkDownOffCmd = 0x003c0,
472 CSCR_LinkDownCmd = 0x0f3c0,
473 };
474
475 enum Cfg9346Bits {
476 Cfg9346_Lock = 0x00,
477 Cfg9346_Unlock = 0xC0,
478 };
479
480 typedef enum {
481 CH_8139 = 0,
482 CH_8139_K,
483 CH_8139A,
484 CH_8139A_G,
485 CH_8139B,
486 CH_8130,
487 CH_8139C,
488 CH_8100,
489 CH_8100B_8139D,
490 CH_8101,
491 } chip_t;
492
493 enum chip_flags {
494 HasHltClk = (1 << 0),
495 HasLWake = (1 << 1),
496 };
497
498 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
499 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
500 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
501
502 /* directly indexed by chip_t, above */
503 static const struct {
504 const char *name;
505 u32 version; /* from RTL8139C/RTL8139D docs */
506 u32 flags;
507 } rtl_chip_info[] = {
508 { "RTL-8139",
509 HW_REVID(1, 0, 0, 0, 0, 0, 0),
510 HasHltClk,
511 },
512
513 { "RTL-8139 rev K",
514 HW_REVID(1, 1, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139A",
519 HW_REVID(1, 1, 1, 0, 0, 0, 0),
520 HasHltClk, /* XXX undocumented? */
521 },
522
523 { "RTL-8139A rev G",
524 HW_REVID(1, 1, 1, 0, 0, 1, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139B",
529 HW_REVID(1, 1, 1, 1, 0, 0, 0),
530 HasLWake,
531 },
532
533 { "RTL-8130",
534 HW_REVID(1, 1, 1, 1, 1, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8139C",
539 HW_REVID(1, 1, 1, 0, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8100",
544 HW_REVID(1, 1, 1, 1, 0, 1, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100B/8139D",
549 HW_REVID(1, 1, 1, 0, 1, 0, 1),
550 HasHltClk /* XXX undocumented? */
551 | HasLWake,
552 },
553
554 { "RTL-8101",
555 HW_REVID(1, 1, 1, 0, 1, 1, 1),
556 HasLWake,
557 },
558 };
559
560 struct rtl_extra_stats {
561 unsigned long early_rx;
562 unsigned long tx_buf_mapped;
563 unsigned long tx_timeouts;
564 unsigned long rx_lost_in_ring;
565 };
566
567 struct rtl8139_private {
568 void __iomem *mmio_addr;
569 int drv_flags;
570 struct pci_dev *pci_dev;
571 u32 msg_enable;
572 struct napi_struct napi;
573 struct net_device *dev;
574
575 unsigned char *rx_ring;
576 unsigned int cur_rx; /* RX buf index of next pkt */
577 dma_addr_t rx_ring_dma;
578
579 unsigned int tx_flag;
580 unsigned long cur_tx;
581 unsigned long dirty_tx;
582 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
583 unsigned char *tx_bufs; /* Tx bounce buffer region. */
584 dma_addr_t tx_bufs_dma;
585
586 signed char phys[4]; /* MII device addresses. */
587
588 /* Twister tune state. */
589 char twistie, twist_row, twist_col;
590
591 unsigned int watchdog_fired : 1;
592 unsigned int default_port : 4; /* Last dev->if_port value. */
593 unsigned int have_thread : 1;
594
595 spinlock_t lock;
596 spinlock_t rx_lock;
597
598 chip_t chipset;
599 u32 rx_config;
600 struct rtl_extra_stats xstats;
601
602 struct delayed_work thread;
603
604 struct mii_if_info mii;
605 unsigned int regs_len;
606 unsigned long fifo_copy_timeout;
607 };
608
609 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
610 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
611 MODULE_LICENSE("GPL");
612 MODULE_VERSION(DRV_VERSION);
613
614 module_param(use_io, int, 0);
615 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
616 module_param(multicast_filter_limit, int, 0);
617 module_param_array(media, int, NULL, 0);
618 module_param_array(full_duplex, int, NULL, 0);
619 module_param(debug, int, 0);
620 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
621 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
622 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
623 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
624
625 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
626 static int rtl8139_open (struct net_device *dev);
627 static int mdio_read (struct net_device *dev, int phy_id, int location);
628 static void mdio_write (struct net_device *dev, int phy_id, int location,
629 int val);
630 static void rtl8139_start_thread(struct rtl8139_private *tp);
631 static void rtl8139_tx_timeout (struct net_device *dev);
632 static void rtl8139_init_ring (struct net_device *dev);
633 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
634 struct net_device *dev);
635 #ifdef CONFIG_NET_POLL_CONTROLLER
636 static void rtl8139_poll_controller(struct net_device *dev);
637 #endif
638 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
639 static int rtl8139_poll(struct napi_struct *napi, int budget);
640 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
641 static int rtl8139_close (struct net_device *dev);
642 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
643 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
644 static void rtl8139_set_rx_mode (struct net_device *dev);
645 static void __set_rx_mode (struct net_device *dev);
646 static void rtl8139_hw_start (struct net_device *dev);
647 static void rtl8139_thread (struct work_struct *work);
648 static void rtl8139_tx_timeout_task(struct work_struct *work);
649 static const struct ethtool_ops rtl8139_ethtool_ops;
650
651 /* write MMIO register, with flush */
652 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
653 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
654 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
655 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
656
657 /* write MMIO register */
658 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
659 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
660 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
661
662 /* read MMIO register */
663 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
664 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
665 #define RTL_R32(reg) ioread32 (ioaddr + (reg))
666
667
668 static const u16 rtl8139_intr_mask =
669 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
670 TxErr | TxOK | RxErr | RxOK;
671
672 static const u16 rtl8139_norx_intr_mask =
673 PCIErr | PCSTimeout | RxUnderrun |
674 TxErr | TxOK | RxErr ;
675
676 #if RX_BUF_IDX == 0
677 static const unsigned int rtl8139_rx_config =
678 RxCfgRcv8K | RxNoWrap |
679 (RX_FIFO_THRESH << RxCfgFIFOShift) |
680 (RX_DMA_BURST << RxCfgDMAShift);
681 #elif RX_BUF_IDX == 1
682 static const unsigned int rtl8139_rx_config =
683 RxCfgRcv16K | RxNoWrap |
684 (RX_FIFO_THRESH << RxCfgFIFOShift) |
685 (RX_DMA_BURST << RxCfgDMAShift);
686 #elif RX_BUF_IDX == 2
687 static const unsigned int rtl8139_rx_config =
688 RxCfgRcv32K | RxNoWrap |
689 (RX_FIFO_THRESH << RxCfgFIFOShift) |
690 (RX_DMA_BURST << RxCfgDMAShift);
691 #elif RX_BUF_IDX == 3
692 static const unsigned int rtl8139_rx_config =
693 RxCfgRcv64K |
694 (RX_FIFO_THRESH << RxCfgFIFOShift) |
695 (RX_DMA_BURST << RxCfgDMAShift);
696 #else
697 #error "Invalid configuration for 8139_RXBUF_IDX"
698 #endif
699
700 static const unsigned int rtl8139_tx_config =
701 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
702
703 static void __rtl8139_cleanup_dev (struct net_device *dev)
704 {
705 struct rtl8139_private *tp = netdev_priv(dev);
706 struct pci_dev *pdev;
707
708 assert (dev != NULL);
709 assert (tp->pci_dev != NULL);
710 pdev = tp->pci_dev;
711
712 if (tp->mmio_addr)
713 pci_iounmap (pdev, tp->mmio_addr);
714
715 /* it's ok to call this even if we have no regions to free */
716 pci_release_regions (pdev);
717
718 free_netdev(dev);
719 pci_set_drvdata (pdev, NULL);
720 }
721
722
723 static void rtl8139_chip_reset (void __iomem *ioaddr)
724 {
725 int i;
726
727 /* Soft reset the chip. */
728 RTL_W8 (ChipCmd, CmdReset);
729
730 /* Check that the chip has finished the reset. */
731 for (i = 1000; i > 0; i--) {
732 barrier();
733 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
734 break;
735 udelay (10);
736 }
737 }
738
739
740 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)
741 {
742 void __iomem *ioaddr;
743 struct net_device *dev;
744 struct rtl8139_private *tp;
745 u8 tmp8;
746 int rc, disable_dev_on_err = 0;
747 unsigned int i;
748 unsigned long pio_start, pio_end, pio_flags, pio_len;
749 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
750 u32 version;
751
752 assert (pdev != NULL);
753
754 /* dev and priv zeroed in alloc_etherdev */
755 dev = alloc_etherdev (sizeof (*tp));
756 if (dev == NULL) {
757 dev_err(&pdev->dev, "Unable to alloc new net device\n");
758 return ERR_PTR(-ENOMEM);
759 }
760 SET_NETDEV_DEV(dev, &pdev->dev);
761
762 tp = netdev_priv(dev);
763 tp->pci_dev = pdev;
764
765 /* enable device (incl. PCI PM wakeup and hotplug setup) */
766 rc = pci_enable_device (pdev);
767 if (rc)
768 goto err_out;
769
770 pio_start = pci_resource_start (pdev, 0);
771 pio_end = pci_resource_end (pdev, 0);
772 pio_flags = pci_resource_flags (pdev, 0);
773 pio_len = pci_resource_len (pdev, 0);
774
775 mmio_start = pci_resource_start (pdev, 1);
776 mmio_end = pci_resource_end (pdev, 1);
777 mmio_flags = pci_resource_flags (pdev, 1);
778 mmio_len = pci_resource_len (pdev, 1);
779
780 /* set this immediately, we need to know before
781 * we talk to the chip directly */
782 pr_debug("PIO region size == 0x%02lX\n", pio_len);
783 pr_debug("MMIO region size == 0x%02lX\n", mmio_len);
784
785 retry:
786 if (use_io) {
787 /* make sure PCI base addr 0 is PIO */
788 if (!(pio_flags & IORESOURCE_IO)) {
789 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
790 rc = -ENODEV;
791 goto err_out;
792 }
793 /* check for weird/broken PCI region reporting */
794 if (pio_len < RTL_MIN_IO_SIZE) {
795 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
796 rc = -ENODEV;
797 goto err_out;
798 }
799 } else {
800 /* make sure PCI base addr 1 is MMIO */
801 if (!(mmio_flags & IORESOURCE_MEM)) {
802 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
803 rc = -ENODEV;
804 goto err_out;
805 }
806 if (mmio_len < RTL_MIN_IO_SIZE) {
807 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
808 rc = -ENODEV;
809 goto err_out;
810 }
811 }
812
813 rc = pci_request_regions (pdev, DRV_NAME);
814 if (rc)
815 goto err_out;
816 disable_dev_on_err = 1;
817
818 /* enable PCI bus-mastering */
819 pci_set_master (pdev);
820
821 if (use_io) {
822 ioaddr = pci_iomap(pdev, 0, 0);
823 if (!ioaddr) {
824 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
825 rc = -EIO;
826 goto err_out;
827 }
828 dev->base_addr = pio_start;
829 tp->regs_len = pio_len;
830 } else {
831 /* ioremap MMIO region */
832 ioaddr = pci_iomap(pdev, 1, 0);
833 if (ioaddr == NULL) {
834 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
835 pci_release_regions(pdev);
836 use_io = 1;
837 goto retry;
838 }
839 dev->base_addr = (long) ioaddr;
840 tp->regs_len = mmio_len;
841 }
842 tp->mmio_addr = ioaddr;
843
844 /* Bring old chips out of low-power mode. */
845 RTL_W8 (HltClk, 'R');
846
847 /* check for missing/broken hardware */
848 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
849 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
850 rc = -EIO;
851 goto err_out;
852 }
853
854 /* identify chip attached to board */
855 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
856 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
857 if (version == rtl_chip_info[i].version) {
858 tp->chipset = i;
859 goto match;
860 }
861
862 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
863 i = 0;
864 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
865 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));
866 tp->chipset = 0;
867
868 match:
869 pr_debug("chipset id (%d) == index %d, '%s'\n",
870 version, i, rtl_chip_info[i].name);
871
872 if (tp->chipset >= CH_8139B) {
873 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
874 pr_debug("PCI PM wakeup\n");
875 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
876 (tmp8 & LWAKE))
877 new_tmp8 &= ~LWAKE;
878 new_tmp8 |= Cfg1_PM_Enable;
879 if (new_tmp8 != tmp8) {
880 RTL_W8 (Cfg9346, Cfg9346_Unlock);
881 RTL_W8 (Config1, tmp8);
882 RTL_W8 (Cfg9346, Cfg9346_Lock);
883 }
884 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
885 tmp8 = RTL_R8 (Config4);
886 if (tmp8 & LWPTN) {
887 RTL_W8 (Cfg9346, Cfg9346_Unlock);
888 RTL_W8 (Config4, tmp8 & ~LWPTN);
889 RTL_W8 (Cfg9346, Cfg9346_Lock);
890 }
891 }
892 } else {
893 pr_debug("Old chip wakeup\n");
894 tmp8 = RTL_R8 (Config1);
895 tmp8 &= ~(SLEEP | PWRDN);
896 RTL_W8 (Config1, tmp8);
897 }
898
899 rtl8139_chip_reset (ioaddr);
900
901 return dev;
902
903 err_out:
904 __rtl8139_cleanup_dev (dev);
905 if (disable_dev_on_err)
906 pci_disable_device (pdev);
907 return ERR_PTR(rc);
908 }
909
910 static const struct net_device_ops rtl8139_netdev_ops = {
911 .ndo_open = rtl8139_open,
912 .ndo_stop = rtl8139_close,
913 .ndo_get_stats = rtl8139_get_stats,
914 .ndo_change_mtu = eth_change_mtu,
915 .ndo_validate_addr = eth_validate_addr,
916 .ndo_set_mac_address = rtl8139_set_mac_address,
917 .ndo_start_xmit = rtl8139_start_xmit,
918 .ndo_set_multicast_list = rtl8139_set_rx_mode,
919 .ndo_do_ioctl = netdev_ioctl,
920 .ndo_tx_timeout = rtl8139_tx_timeout,
921 #ifdef CONFIG_NET_POLL_CONTROLLER
922 .ndo_poll_controller = rtl8139_poll_controller,
923 #endif
924 };
925
926 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
927 const struct pci_device_id *ent)
928 {
929 struct net_device *dev = NULL;
930 struct rtl8139_private *tp;
931 int i, addr_len, option;
932 void __iomem *ioaddr;
933 static int board_idx = -1;
934
935 assert (pdev != NULL);
936 assert (ent != NULL);
937
938 board_idx++;
939
940 /* when we're built into the kernel, the driver version message
941 * is only printed if at least one 8139 board has been found
942 */
943 #ifndef MODULE
944 {
945 static int printed_version;
946 if (!printed_version++)
947 pr_info(RTL8139_DRIVER_NAME "\n");
948 }
949 #endif
950
951 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
952 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
953 dev_info(&pdev->dev,
954 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
955 pdev->vendor, pdev->device, pdev->revision);
956 return -ENODEV;
957 }
958
959 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
960 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
961 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
962 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
963 pr_info("OQO Model 2 detected. Forcing PIO\n");
964 use_io = 1;
965 }
966
967 dev = rtl8139_init_board (pdev);
968 if (IS_ERR(dev))
969 return PTR_ERR(dev);
970
971 assert (dev != NULL);
972 tp = netdev_priv(dev);
973 tp->dev = dev;
974
975 ioaddr = tp->mmio_addr;
976 assert (ioaddr != NULL);
977
978 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
979 for (i = 0; i < 3; i++)
980 ((__le16 *) (dev->dev_addr))[i] =
981 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
982 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
983
984 /* The Rtl8139-specific entries in the device structure. */
985 dev->netdev_ops = &rtl8139_netdev_ops;
986 dev->ethtool_ops = &rtl8139_ethtool_ops;
987 dev->watchdog_timeo = TX_TIMEOUT;
988 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
989
990 /* note: the hardware is not capable of sg/csum/highdma, however
991 * through the use of skb_copy_and_csum_dev we enable these
992 * features
993 */
994 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
995
996 dev->irq = pdev->irq;
997
998 /* tp zeroed and aligned in alloc_etherdev */
999 tp = netdev_priv(dev);
1000
1001 /* note: tp->chipset set in rtl8139_init_board */
1002 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1003 tp->mmio_addr = ioaddr;
1004 tp->msg_enable =
1005 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1006 spin_lock_init (&tp->lock);
1007 spin_lock_init (&tp->rx_lock);
1008 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1009 tp->mii.dev = dev;
1010 tp->mii.mdio_read = mdio_read;
1011 tp->mii.mdio_write = mdio_write;
1012 tp->mii.phy_id_mask = 0x3f;
1013 tp->mii.reg_num_mask = 0x1f;
1014
1015 /* dev is fully set up and ready to use now */
1016 pr_debug("about to register device named %s (%p)...\n",
1017 dev->name, dev);
1018 i = register_netdev (dev);
1019 if (i) goto err_out;
1020
1021 pci_set_drvdata (pdev, dev);
1022
1023 netdev_info(dev, "%s at 0x%lx, %pM, IRQ %d\n",
1024 board_info[ent->driver_data].name,
1025 dev->base_addr, dev->dev_addr, dev->irq);
1026
1027 netdev_dbg(dev, "Identified 8139 chip type '%s'\n",
1028 rtl_chip_info[tp->chipset].name);
1029
1030 /* Find the connected MII xcvrs.
1031 Doing this in open() would allow detecting external xcvrs later, but
1032 takes too much time. */
1033 #ifdef CONFIG_8139TOO_8129
1034 if (tp->drv_flags & HAS_MII_XCVR) {
1035 int phy, phy_idx = 0;
1036 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1037 int mii_status = mdio_read(dev, phy, 1);
1038 if (mii_status != 0xffff && mii_status != 0x0000) {
1039 u16 advertising = mdio_read(dev, phy, 4);
1040 tp->phys[phy_idx++] = phy;
1041 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n",
1042 phy, mii_status, advertising);
1043 }
1044 }
1045 if (phy_idx == 0) {
1046 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n");
1047 tp->phys[0] = 32;
1048 }
1049 } else
1050 #endif
1051 tp->phys[0] = 32;
1052 tp->mii.phy_id = tp->phys[0];
1053
1054 /* The lower four bits are the media type. */
1055 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1056 if (option > 0) {
1057 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1058 tp->default_port = option & 0xFF;
1059 if (tp->default_port)
1060 tp->mii.force_media = 1;
1061 }
1062 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1063 tp->mii.full_duplex = full_duplex[board_idx];
1064 if (tp->mii.full_duplex) {
1065 netdev_info(dev, "Media type forced to Full Duplex\n");
1066 /* Changing the MII-advertised media because might prevent
1067 re-connection. */
1068 tp->mii.force_media = 1;
1069 }
1070 if (tp->default_port) {
1071 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n",
1072 (option & 0x20 ? 100 : 10),
1073 (option & 0x10 ? "full" : "half"));
1074 mdio_write(dev, tp->phys[0], 0,
1075 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1076 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1077 }
1078
1079 /* Put the chip into low-power mode. */
1080 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1081 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1082
1083 return 0;
1084
1085 err_out:
1086 __rtl8139_cleanup_dev (dev);
1087 pci_disable_device (pdev);
1088 return i;
1089 }
1090
1091
1092 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1093 {
1094 struct net_device *dev = pci_get_drvdata (pdev);
1095 struct rtl8139_private *tp = netdev_priv(dev);
1096
1097 assert (dev != NULL);
1098
1099 cancel_delayed_work_sync(&tp->thread);
1100
1101 unregister_netdev (dev);
1102
1103 __rtl8139_cleanup_dev (dev);
1104 pci_disable_device (pdev);
1105 }
1106
1107
1108 /* Serial EEPROM section. */
1109
1110 /* EEPROM_Ctrl bits. */
1111 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1112 #define EE_CS 0x08 /* EEPROM chip select. */
1113 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1114 #define EE_WRITE_0 0x00
1115 #define EE_WRITE_1 0x02
1116 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1117 #define EE_ENB (0x80 | EE_CS)
1118
1119 /* Delay between EEPROM clock transitions.
1120 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1121 */
1122
1123 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1124
1125 /* The EEPROM commands include the alway-set leading bit. */
1126 #define EE_WRITE_CMD (5)
1127 #define EE_READ_CMD (6)
1128 #define EE_ERASE_CMD (7)
1129
1130 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1131 {
1132 int i;
1133 unsigned retval = 0;
1134 int read_cmd = location | (EE_READ_CMD << addr_len);
1135
1136 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1137 RTL_W8 (Cfg9346, EE_ENB);
1138 eeprom_delay ();
1139
1140 /* Shift the read command bits out. */
1141 for (i = 4 + addr_len; i >= 0; i--) {
1142 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1143 RTL_W8 (Cfg9346, EE_ENB | dataval);
1144 eeprom_delay ();
1145 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1146 eeprom_delay ();
1147 }
1148 RTL_W8 (Cfg9346, EE_ENB);
1149 eeprom_delay ();
1150
1151 for (i = 16; i > 0; i--) {
1152 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1153 eeprom_delay ();
1154 retval =
1155 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1156 0);
1157 RTL_W8 (Cfg9346, EE_ENB);
1158 eeprom_delay ();
1159 }
1160
1161 /* Terminate the EEPROM access. */
1162 RTL_W8 (Cfg9346, ~EE_CS);
1163 eeprom_delay ();
1164
1165 return retval;
1166 }
1167
1168 /* MII serial management: mostly bogus for now. */
1169 /* Read and write the MII management registers using software-generated
1170 serial MDIO protocol.
1171 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1172 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1173 "overclocking" issues. */
1174 #define MDIO_DIR 0x80
1175 #define MDIO_DATA_OUT 0x04
1176 #define MDIO_DATA_IN 0x02
1177 #define MDIO_CLK 0x01
1178 #define MDIO_WRITE0 (MDIO_DIR)
1179 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1180
1181 #define mdio_delay() RTL_R8(Config4)
1182
1183
1184 static const char mii_2_8139_map[8] = {
1185 BasicModeCtrl,
1186 BasicModeStatus,
1187 0,
1188 0,
1189 NWayAdvert,
1190 NWayLPAR,
1191 NWayExpansion,
1192 0
1193 };
1194
1195
1196 #ifdef CONFIG_8139TOO_8129
1197 /* Syncronize the MII management interface by shifting 32 one bits out. */
1198 static void mdio_sync (void __iomem *ioaddr)
1199 {
1200 int i;
1201
1202 for (i = 32; i >= 0; i--) {
1203 RTL_W8 (Config4, MDIO_WRITE1);
1204 mdio_delay ();
1205 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1206 mdio_delay ();
1207 }
1208 }
1209 #endif
1210
1211 static int mdio_read (struct net_device *dev, int phy_id, int location)
1212 {
1213 struct rtl8139_private *tp = netdev_priv(dev);
1214 int retval = 0;
1215 #ifdef CONFIG_8139TOO_8129
1216 void __iomem *ioaddr = tp->mmio_addr;
1217 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1218 int i;
1219 #endif
1220
1221 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1222 void __iomem *ioaddr = tp->mmio_addr;
1223 return location < 8 && mii_2_8139_map[location] ?
1224 RTL_R16 (mii_2_8139_map[location]) : 0;
1225 }
1226
1227 #ifdef CONFIG_8139TOO_8129
1228 mdio_sync (ioaddr);
1229 /* Shift the read command bits out. */
1230 for (i = 15; i >= 0; i--) {
1231 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1232
1233 RTL_W8 (Config4, MDIO_DIR | dataval);
1234 mdio_delay ();
1235 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1236 mdio_delay ();
1237 }
1238
1239 /* Read the two transition, 16 data, and wire-idle bits. */
1240 for (i = 19; i > 0; i--) {
1241 RTL_W8 (Config4, 0);
1242 mdio_delay ();
1243 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1244 RTL_W8 (Config4, MDIO_CLK);
1245 mdio_delay ();
1246 }
1247 #endif
1248
1249 return (retval >> 1) & 0xffff;
1250 }
1251
1252
1253 static void mdio_write (struct net_device *dev, int phy_id, int location,
1254 int value)
1255 {
1256 struct rtl8139_private *tp = netdev_priv(dev);
1257 #ifdef CONFIG_8139TOO_8129
1258 void __iomem *ioaddr = tp->mmio_addr;
1259 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1260 int i;
1261 #endif
1262
1263 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1264 void __iomem *ioaddr = tp->mmio_addr;
1265 if (location == 0) {
1266 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1267 RTL_W16 (BasicModeCtrl, value);
1268 RTL_W8 (Cfg9346, Cfg9346_Lock);
1269 } else if (location < 8 && mii_2_8139_map[location])
1270 RTL_W16 (mii_2_8139_map[location], value);
1271 return;
1272 }
1273
1274 #ifdef CONFIG_8139TOO_8129
1275 mdio_sync (ioaddr);
1276
1277 /* Shift the command bits out. */
1278 for (i = 31; i >= 0; i--) {
1279 int dataval =
1280 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1281 RTL_W8 (Config4, dataval);
1282 mdio_delay ();
1283 RTL_W8 (Config4, dataval | MDIO_CLK);
1284 mdio_delay ();
1285 }
1286 /* Clear out extra bits. */
1287 for (i = 2; i > 0; i--) {
1288 RTL_W8 (Config4, 0);
1289 mdio_delay ();
1290 RTL_W8 (Config4, MDIO_CLK);
1291 mdio_delay ();
1292 }
1293 #endif
1294 }
1295
1296
1297 static int rtl8139_open (struct net_device *dev)
1298 {
1299 struct rtl8139_private *tp = netdev_priv(dev);
1300 int retval;
1301 void __iomem *ioaddr = tp->mmio_addr;
1302
1303 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1304 if (retval)
1305 return retval;
1306
1307 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1308 &tp->tx_bufs_dma, GFP_KERNEL);
1309 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1310 &tp->rx_ring_dma, GFP_KERNEL);
1311 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1312 free_irq(dev->irq, dev);
1313
1314 if (tp->tx_bufs)
1315 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1316 tp->tx_bufs, tp->tx_bufs_dma);
1317 if (tp->rx_ring)
1318 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1319 tp->rx_ring, tp->rx_ring_dma);
1320
1321 return -ENOMEM;
1322
1323 }
1324
1325 napi_enable(&tp->napi);
1326
1327 tp->mii.full_duplex = tp->mii.force_media;
1328 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1329
1330 rtl8139_init_ring (dev);
1331 rtl8139_hw_start (dev);
1332 netif_start_queue (dev);
1333
1334 netif_dbg(tp, ifup, dev,
1335 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1336 __func__,
1337 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1338 dev->irq, RTL_R8 (MediaStatus),
1339 tp->mii.full_duplex ? "full" : "half");
1340
1341 rtl8139_start_thread(tp);
1342
1343 return 0;
1344 }
1345
1346
1347 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1348 {
1349 struct rtl8139_private *tp = netdev_priv(dev);
1350
1351 if (tp->phys[0] >= 0) {
1352 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1353 }
1354 }
1355
1356 /* Start the hardware at open or resume. */
1357 static void rtl8139_hw_start (struct net_device *dev)
1358 {
1359 struct rtl8139_private *tp = netdev_priv(dev);
1360 void __iomem *ioaddr = tp->mmio_addr;
1361 u32 i;
1362 u8 tmp;
1363
1364 /* Bring old chips out of low-power mode. */
1365 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1366 RTL_W8 (HltClk, 'R');
1367
1368 rtl8139_chip_reset (ioaddr);
1369
1370 /* unlock Config[01234] and BMCR register writes */
1371 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1372 /* Restore our idea of the MAC address. */
1373 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1374 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1375
1376 tp->cur_rx = 0;
1377
1378 /* init Rx ring buffer DMA address */
1379 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1380
1381 /* Must enable Tx/Rx before setting transfer thresholds! */
1382 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1383
1384 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1385 RTL_W32 (RxConfig, tp->rx_config);
1386 RTL_W32 (TxConfig, rtl8139_tx_config);
1387
1388 rtl_check_media (dev, 1);
1389
1390 if (tp->chipset >= CH_8139B) {
1391 /* Disable magic packet scanning, which is enabled
1392 * when PM is enabled in Config1. It can be reenabled
1393 * via ETHTOOL_SWOL if desired. */
1394 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1395 }
1396
1397 netdev_dbg(dev, "init buffer addresses\n");
1398
1399 /* Lock Config[01234] and BMCR register writes */
1400 RTL_W8 (Cfg9346, Cfg9346_Lock);
1401
1402 /* init Tx buffer DMA addresses */
1403 for (i = 0; i < NUM_TX_DESC; i++)
1404 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1405
1406 RTL_W32 (RxMissed, 0);
1407
1408 rtl8139_set_rx_mode (dev);
1409
1410 /* no early-rx interrupts */
1411 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1412
1413 /* make sure RxTx has started */
1414 tmp = RTL_R8 (ChipCmd);
1415 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1416 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1417
1418 /* Enable all known interrupts by setting the interrupt mask. */
1419 RTL_W16 (IntrMask, rtl8139_intr_mask);
1420 }
1421
1422
1423 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1424 static void rtl8139_init_ring (struct net_device *dev)
1425 {
1426 struct rtl8139_private *tp = netdev_priv(dev);
1427 int i;
1428
1429 tp->cur_rx = 0;
1430 tp->cur_tx = 0;
1431 tp->dirty_tx = 0;
1432
1433 for (i = 0; i < NUM_TX_DESC; i++)
1434 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1435 }
1436
1437
1438 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1439 static int next_tick = 3 * HZ;
1440
1441 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1442 static inline void rtl8139_tune_twister (struct net_device *dev,
1443 struct rtl8139_private *tp) {}
1444 #else
1445 enum TwisterParamVals {
1446 PARA78_default = 0x78fa8388,
1447 PARA7c_default = 0xcb38de43, /* param[0][3] */
1448 PARA7c_xxx = 0xcb38de43,
1449 };
1450
1451 static const unsigned long param[4][4] = {
1452 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1453 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1454 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1455 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1456 };
1457
1458 static void rtl8139_tune_twister (struct net_device *dev,
1459 struct rtl8139_private *tp)
1460 {
1461 int linkcase;
1462 void __iomem *ioaddr = tp->mmio_addr;
1463
1464 /* This is a complicated state machine to configure the "twister" for
1465 impedance/echos based on the cable length.
1466 All of this is magic and undocumented.
1467 */
1468 switch (tp->twistie) {
1469 case 1:
1470 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1471 /* We have link beat, let us tune the twister. */
1472 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1473 tp->twistie = 2; /* Change to state 2. */
1474 next_tick = HZ / 10;
1475 } else {
1476 /* Just put in some reasonable defaults for when beat returns. */
1477 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1478 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1479 RTL_W32 (PARA78, PARA78_default);
1480 RTL_W32 (PARA7c, PARA7c_default);
1481 tp->twistie = 0; /* Bail from future actions. */
1482 }
1483 break;
1484 case 2:
1485 /* Read how long it took to hear the echo. */
1486 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1487 if (linkcase == 0x7000)
1488 tp->twist_row = 3;
1489 else if (linkcase == 0x3000)
1490 tp->twist_row = 2;
1491 else if (linkcase == 0x1000)
1492 tp->twist_row = 1;
1493 else
1494 tp->twist_row = 0;
1495 tp->twist_col = 0;
1496 tp->twistie = 3; /* Change to state 2. */
1497 next_tick = HZ / 10;
1498 break;
1499 case 3:
1500 /* Put out four tuning parameters, one per 100msec. */
1501 if (tp->twist_col == 0)
1502 RTL_W16 (FIFOTMS, 0);
1503 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1504 [(int) tp->twist_col]);
1505 next_tick = HZ / 10;
1506 if (++tp->twist_col >= 4) {
1507 /* For short cables we are done.
1508 For long cables (row == 3) check for mistune. */
1509 tp->twistie =
1510 (tp->twist_row == 3) ? 4 : 0;
1511 }
1512 break;
1513 case 4:
1514 /* Special case for long cables: check for mistune. */
1515 if ((RTL_R16 (CSCR) &
1516 CSCR_LinkStatusBits) == 0x7000) {
1517 tp->twistie = 0;
1518 break;
1519 } else {
1520 RTL_W32 (PARA7c, 0xfb38de03);
1521 tp->twistie = 5;
1522 next_tick = HZ / 10;
1523 }
1524 break;
1525 case 5:
1526 /* Retune for shorter cable (column 2). */
1527 RTL_W32 (FIFOTMS, 0x20);
1528 RTL_W32 (PARA78, PARA78_default);
1529 RTL_W32 (PARA7c, PARA7c_default);
1530 RTL_W32 (FIFOTMS, 0x00);
1531 tp->twist_row = 2;
1532 tp->twist_col = 0;
1533 tp->twistie = 3;
1534 next_tick = HZ / 10;
1535 break;
1536
1537 default:
1538 /* do nothing */
1539 break;
1540 }
1541 }
1542 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1543
1544 static inline void rtl8139_thread_iter (struct net_device *dev,
1545 struct rtl8139_private *tp,
1546 void __iomem *ioaddr)
1547 {
1548 int mii_lpa;
1549
1550 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1551
1552 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1553 int duplex = ((mii_lpa & LPA_100FULL) ||
1554 (mii_lpa & 0x01C0) == 0x0040);
1555 if (tp->mii.full_duplex != duplex) {
1556 tp->mii.full_duplex = duplex;
1557
1558 if (mii_lpa) {
1559 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1560 tp->mii.full_duplex ? "full" : "half",
1561 tp->phys[0], mii_lpa);
1562 } else {
1563 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
1564 }
1565 #if 0
1566 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1567 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1568 RTL_W8 (Cfg9346, Cfg9346_Lock);
1569 #endif
1570 }
1571 }
1572
1573 next_tick = HZ * 60;
1574
1575 rtl8139_tune_twister (dev, tp);
1576
1577 netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1578 RTL_R16(NWayLPAR));
1579 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
1580 RTL_R16(IntrMask), RTL_R16(IntrStatus));
1581 netdev_dbg(dev, "Chip config %02x %02x\n",
1582 RTL_R8(Config0), RTL_R8(Config1));
1583 }
1584
1585 static void rtl8139_thread (struct work_struct *work)
1586 {
1587 struct rtl8139_private *tp =
1588 container_of(work, struct rtl8139_private, thread.work);
1589 struct net_device *dev = tp->mii.dev;
1590 unsigned long thr_delay = next_tick;
1591
1592 rtnl_lock();
1593
1594 if (!netif_running(dev))
1595 goto out_unlock;
1596
1597 if (tp->watchdog_fired) {
1598 tp->watchdog_fired = 0;
1599 rtl8139_tx_timeout_task(work);
1600 } else
1601 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1602
1603 if (tp->have_thread)
1604 schedule_delayed_work(&tp->thread, thr_delay);
1605 out_unlock:
1606 rtnl_unlock ();
1607 }
1608
1609 static void rtl8139_start_thread(struct rtl8139_private *tp)
1610 {
1611 tp->twistie = 0;
1612 if (tp->chipset == CH_8139_K)
1613 tp->twistie = 1;
1614 else if (tp->drv_flags & HAS_LNK_CHNG)
1615 return;
1616
1617 tp->have_thread = 1;
1618 tp->watchdog_fired = 0;
1619
1620 schedule_delayed_work(&tp->thread, next_tick);
1621 }
1622
1623 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1624 {
1625 tp->cur_tx = 0;
1626 tp->dirty_tx = 0;
1627
1628 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1629 }
1630
1631 static void rtl8139_tx_timeout_task (struct work_struct *work)
1632 {
1633 struct rtl8139_private *tp =
1634 container_of(work, struct rtl8139_private, thread.work);
1635 struct net_device *dev = tp->mii.dev;
1636 void __iomem *ioaddr = tp->mmio_addr;
1637 int i;
1638 u8 tmp8;
1639
1640 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
1641 RTL_R8(ChipCmd), RTL_R16(IntrStatus),
1642 RTL_R16(IntrMask), RTL_R8(MediaStatus));
1643 /* Emit info to figure out what went wrong. */
1644 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n",
1645 tp->cur_tx, tp->dirty_tx);
1646 for (i = 0; i < NUM_TX_DESC; i++)
1647 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n",
1648 i, RTL_R32(TxStatus0 + (i * 4)),
1649 i == tp->dirty_tx % NUM_TX_DESC ?
1650 " (queue head)" : "");
1651
1652 tp->xstats.tx_timeouts++;
1653
1654 /* disable Tx ASAP, if not already */
1655 tmp8 = RTL_R8 (ChipCmd);
1656 if (tmp8 & CmdTxEnb)
1657 RTL_W8 (ChipCmd, CmdRxEnb);
1658
1659 spin_lock_bh(&tp->rx_lock);
1660 /* Disable interrupts by clearing the interrupt mask. */
1661 RTL_W16 (IntrMask, 0x0000);
1662
1663 /* Stop a shared interrupt from scavenging while we are. */
1664 spin_lock_irq(&tp->lock);
1665 rtl8139_tx_clear (tp);
1666 spin_unlock_irq(&tp->lock);
1667
1668 /* ...and finally, reset everything */
1669 if (netif_running(dev)) {
1670 rtl8139_hw_start (dev);
1671 netif_wake_queue (dev);
1672 }
1673 spin_unlock_bh(&tp->rx_lock);
1674 }
1675
1676 static void rtl8139_tx_timeout (struct net_device *dev)
1677 {
1678 struct rtl8139_private *tp = netdev_priv(dev);
1679
1680 tp->watchdog_fired = 1;
1681 if (!tp->have_thread) {
1682 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1683 schedule_delayed_work(&tp->thread, next_tick);
1684 }
1685 }
1686
1687 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1688 struct net_device *dev)
1689 {
1690 struct rtl8139_private *tp = netdev_priv(dev);
1691 void __iomem *ioaddr = tp->mmio_addr;
1692 unsigned int entry;
1693 unsigned int len = skb->len;
1694 unsigned long flags;
1695
1696 /* Calculate the next Tx descriptor entry. */
1697 entry = tp->cur_tx % NUM_TX_DESC;
1698
1699 /* Note: the chip doesn't have auto-pad! */
1700 if (likely(len < TX_BUF_SIZE)) {
1701 if (len < ETH_ZLEN)
1702 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1703 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1704 dev_kfree_skb(skb);
1705 } else {
1706 dev_kfree_skb(skb);
1707 dev->stats.tx_dropped++;
1708 return NETDEV_TX_OK;
1709 }
1710
1711 spin_lock_irqsave(&tp->lock, flags);
1712 /*
1713 * Writing to TxStatus triggers a DMA transfer of the data
1714 * copied to tp->tx_buf[entry] above. Use a memory barrier
1715 * to make sure that the device sees the updated data.
1716 */
1717 wmb();
1718 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1719 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1720
1721 tp->cur_tx++;
1722
1723 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1724 netif_stop_queue (dev);
1725 spin_unlock_irqrestore(&tp->lock, flags);
1726
1727 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
1728 len, entry);
1729
1730 return NETDEV_TX_OK;
1731 }
1732
1733
1734 static void rtl8139_tx_interrupt (struct net_device *dev,
1735 struct rtl8139_private *tp,
1736 void __iomem *ioaddr)
1737 {
1738 unsigned long dirty_tx, tx_left;
1739
1740 assert (dev != NULL);
1741 assert (ioaddr != NULL);
1742
1743 dirty_tx = tp->dirty_tx;
1744 tx_left = tp->cur_tx - dirty_tx;
1745 while (tx_left > 0) {
1746 int entry = dirty_tx % NUM_TX_DESC;
1747 int txstatus;
1748
1749 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1750
1751 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1752 break; /* It still hasn't been Txed */
1753
1754 /* Note: TxCarrierLost is always asserted at 100mbps. */
1755 if (txstatus & (TxOutOfWindow | TxAborted)) {
1756 /* There was an major error, log it. */
1757 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
1758 txstatus);
1759 dev->stats.tx_errors++;
1760 if (txstatus & TxAborted) {
1761 dev->stats.tx_aborted_errors++;
1762 RTL_W32 (TxConfig, TxClearAbt);
1763 RTL_W16 (IntrStatus, TxErr);
1764 wmb();
1765 }
1766 if (txstatus & TxCarrierLost)
1767 dev->stats.tx_carrier_errors++;
1768 if (txstatus & TxOutOfWindow)
1769 dev->stats.tx_window_errors++;
1770 } else {
1771 if (txstatus & TxUnderrun) {
1772 /* Add 64 to the Tx FIFO threshold. */
1773 if (tp->tx_flag < 0x00300000)
1774 tp->tx_flag += 0x00020000;
1775 dev->stats.tx_fifo_errors++;
1776 }
1777 dev->stats.collisions += (txstatus >> 24) & 15;
1778 dev->stats.tx_bytes += txstatus & 0x7ff;
1779 dev->stats.tx_packets++;
1780 }
1781
1782 dirty_tx++;
1783 tx_left--;
1784 }
1785
1786 #ifndef RTL8139_NDEBUG
1787 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1788 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n",
1789 dirty_tx, tp->cur_tx);
1790 dirty_tx += NUM_TX_DESC;
1791 }
1792 #endif /* RTL8139_NDEBUG */
1793
1794 /* only wake the queue if we did work, and the queue is stopped */
1795 if (tp->dirty_tx != dirty_tx) {
1796 tp->dirty_tx = dirty_tx;
1797 mb();
1798 netif_wake_queue (dev);
1799 }
1800 }
1801
1802
1803 /* TODO: clean this up! Rx reset need not be this intensive */
1804 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1805 struct rtl8139_private *tp, void __iomem *ioaddr)
1806 {
1807 u8 tmp8;
1808 #ifdef CONFIG_8139_OLD_RX_RESET
1809 int tmp_work;
1810 #endif
1811
1812 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n",
1813 rx_status);
1814 dev->stats.rx_errors++;
1815 if (!(rx_status & RxStatusOK)) {
1816 if (rx_status & RxTooLong) {
1817 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1818 rx_status);
1819 /* A.C.: The chip hangs here. */
1820 }
1821 if (rx_status & (RxBadSymbol | RxBadAlign))
1822 dev->stats.rx_frame_errors++;
1823 if (rx_status & (RxRunt | RxTooLong))
1824 dev->stats.rx_length_errors++;
1825 if (rx_status & RxCRCErr)
1826 dev->stats.rx_crc_errors++;
1827 } else {
1828 tp->xstats.rx_lost_in_ring++;
1829 }
1830
1831 #ifndef CONFIG_8139_OLD_RX_RESET
1832 tmp8 = RTL_R8 (ChipCmd);
1833 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1834 RTL_W8 (ChipCmd, tmp8);
1835 RTL_W32 (RxConfig, tp->rx_config);
1836 tp->cur_rx = 0;
1837 #else
1838 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1839
1840 /* disable receive */
1841 RTL_W8_F (ChipCmd, CmdTxEnb);
1842 tmp_work = 200;
1843 while (--tmp_work > 0) {
1844 udelay(1);
1845 tmp8 = RTL_R8 (ChipCmd);
1846 if (!(tmp8 & CmdRxEnb))
1847 break;
1848 }
1849 if (tmp_work <= 0)
1850 netdev_warn(dev, "rx stop wait too long\n");
1851 /* restart receive */
1852 tmp_work = 200;
1853 while (--tmp_work > 0) {
1854 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1855 udelay(1);
1856 tmp8 = RTL_R8 (ChipCmd);
1857 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1858 break;
1859 }
1860 if (tmp_work <= 0)
1861 netdev_warn(dev, "tx/rx enable wait too long\n");
1862
1863 /* and reinitialize all rx related registers */
1864 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1865 /* Must enable Tx/Rx before setting transfer thresholds! */
1866 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1867
1868 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1869 RTL_W32 (RxConfig, tp->rx_config);
1870 tp->cur_rx = 0;
1871
1872 netdev_dbg(dev, "init buffer addresses\n");
1873
1874 /* Lock Config[01234] and BMCR register writes */
1875 RTL_W8 (Cfg9346, Cfg9346_Lock);
1876
1877 /* init Rx ring buffer DMA address */
1878 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1879
1880 /* A.C.: Reset the multicast list. */
1881 __set_rx_mode (dev);
1882 #endif
1883 }
1884
1885 #if RX_BUF_IDX == 3
1886 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1887 u32 offset, unsigned int size)
1888 {
1889 u32 left = RX_BUF_LEN - offset;
1890
1891 if (size > left) {
1892 skb_copy_to_linear_data(skb, ring + offset, left);
1893 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1894 } else
1895 skb_copy_to_linear_data(skb, ring + offset, size);
1896 }
1897 #endif
1898
1899 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1900 {
1901 void __iomem *ioaddr = tp->mmio_addr;
1902 u16 status;
1903
1904 status = RTL_R16 (IntrStatus) & RxAckBits;
1905
1906 /* Clear out errors and receive interrupts */
1907 if (likely(status != 0)) {
1908 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1909 tp->dev->stats.rx_errors++;
1910 if (status & RxFIFOOver)
1911 tp->dev->stats.rx_fifo_errors++;
1912 }
1913 RTL_W16_F (IntrStatus, RxAckBits);
1914 }
1915 }
1916
1917 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1918 int budget)
1919 {
1920 void __iomem *ioaddr = tp->mmio_addr;
1921 int received = 0;
1922 unsigned char *rx_ring = tp->rx_ring;
1923 unsigned int cur_rx = tp->cur_rx;
1924 unsigned int rx_size = 0;
1925
1926 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1927 __func__, (u16)cur_rx,
1928 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
1929
1930 while (netif_running(dev) && received < budget &&
1931 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1932 u32 ring_offset = cur_rx % RX_BUF_LEN;
1933 u32 rx_status;
1934 unsigned int pkt_size;
1935 struct sk_buff *skb;
1936
1937 rmb();
1938
1939 /* read size+status of next frame from DMA ring buffer */
1940 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1941 rx_size = rx_status >> 16;
1942 pkt_size = rx_size - 4;
1943
1944 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n",
1945 __func__, rx_status, rx_size, cur_rx);
1946 #if RTL8139_DEBUG > 2
1947 print_hex_dump(KERN_DEBUG, "Frame contents: ",
1948 DUMP_PREFIX_OFFSET, 16, 1,
1949 &rx_ring[ring_offset], 70, true);
1950 #endif
1951
1952 /* Packet copy from FIFO still in progress.
1953 * Theoretically, this should never happen
1954 * since EarlyRx is disabled.
1955 */
1956 if (unlikely(rx_size == 0xfff0)) {
1957 if (!tp->fifo_copy_timeout)
1958 tp->fifo_copy_timeout = jiffies + 2;
1959 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1960 netdev_dbg(dev, "hung FIFO. Reset\n");
1961 rx_size = 0;
1962 goto no_early_rx;
1963 }
1964 netif_dbg(tp, intr, dev, "fifo copy in progress\n");
1965 tp->xstats.early_rx++;
1966 break;
1967 }
1968
1969 no_early_rx:
1970 tp->fifo_copy_timeout = 0;
1971
1972 /* If Rx err or invalid rx_size/rx_status received
1973 * (which happens if we get lost in the ring),
1974 * Rx process gets reset, so we abort any further
1975 * Rx processing.
1976 */
1977 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1978 (rx_size < 8) ||
1979 (!(rx_status & RxStatusOK)))) {
1980 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1981 received = -1;
1982 goto out;
1983 }
1984
1985 /* Malloc up new buffer, compatible with net-2e. */
1986 /* Omit the four octet CRC from the length. */
1987
1988 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
1989 if (likely(skb)) {
1990 #if RX_BUF_IDX == 3
1991 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
1992 #else
1993 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
1994 #endif
1995 skb_put (skb, pkt_size);
1996
1997 skb->protocol = eth_type_trans (skb, dev);
1998
1999 dev->stats.rx_bytes += pkt_size;
2000 dev->stats.rx_packets++;
2001
2002 netif_receive_skb (skb);
2003 } else {
2004 if (net_ratelimit())
2005 netdev_warn(dev, "Memory squeeze, dropping packet\n");
2006 dev->stats.rx_dropped++;
2007 }
2008 received++;
2009
2010 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2011 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2012
2013 rtl8139_isr_ack(tp);
2014 }
2015
2016 if (unlikely(!received || rx_size == 0xfff0))
2017 rtl8139_isr_ack(tp);
2018
2019 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
2020 __func__, cur_rx,
2021 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
2022
2023 tp->cur_rx = cur_rx;
2024
2025 /*
2026 * The receive buffer should be mostly empty.
2027 * Tell NAPI to reenable the Rx irq.
2028 */
2029 if (tp->fifo_copy_timeout)
2030 received = budget;
2031
2032 out:
2033 return received;
2034 }
2035
2036
2037 static void rtl8139_weird_interrupt (struct net_device *dev,
2038 struct rtl8139_private *tp,
2039 void __iomem *ioaddr,
2040 int status, int link_changed)
2041 {
2042 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status);
2043
2044 assert (dev != NULL);
2045 assert (tp != NULL);
2046 assert (ioaddr != NULL);
2047
2048 /* Update the error count. */
2049 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2050 RTL_W32 (RxMissed, 0);
2051
2052 if ((status & RxUnderrun) && link_changed &&
2053 (tp->drv_flags & HAS_LNK_CHNG)) {
2054 rtl_check_media(dev, 0);
2055 status &= ~RxUnderrun;
2056 }
2057
2058 if (status & (RxUnderrun | RxErr))
2059 dev->stats.rx_errors++;
2060
2061 if (status & PCSTimeout)
2062 dev->stats.rx_length_errors++;
2063 if (status & RxUnderrun)
2064 dev->stats.rx_fifo_errors++;
2065 if (status & PCIErr) {
2066 u16 pci_cmd_status;
2067 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2068 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2069
2070 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
2071 }
2072 }
2073
2074 static int rtl8139_poll(struct napi_struct *napi, int budget)
2075 {
2076 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2077 struct net_device *dev = tp->dev;
2078 void __iomem *ioaddr = tp->mmio_addr;
2079 int work_done;
2080
2081 spin_lock(&tp->rx_lock);
2082 work_done = 0;
2083 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2084 work_done += rtl8139_rx(dev, tp, budget);
2085
2086 if (work_done < budget) {
2087 unsigned long flags;
2088 /*
2089 * Order is important since data can get interrupted
2090 * again when we think we are done.
2091 */
2092 spin_lock_irqsave(&tp->lock, flags);
2093 __napi_complete(napi);
2094 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2095 spin_unlock_irqrestore(&tp->lock, flags);
2096 }
2097 spin_unlock(&tp->rx_lock);
2098
2099 return work_done;
2100 }
2101
2102 /* The interrupt handler does all of the Rx thread work and cleans up
2103 after the Tx thread. */
2104 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2105 {
2106 struct net_device *dev = (struct net_device *) dev_instance;
2107 struct rtl8139_private *tp = netdev_priv(dev);
2108 void __iomem *ioaddr = tp->mmio_addr;
2109 u16 status, ackstat;
2110 int link_changed = 0; /* avoid bogus "uninit" warning */
2111 int handled = 0;
2112
2113 spin_lock (&tp->lock);
2114 status = RTL_R16 (IntrStatus);
2115
2116 /* shared irq? */
2117 if (unlikely((status & rtl8139_intr_mask) == 0))
2118 goto out;
2119
2120 handled = 1;
2121
2122 /* h/w no longer present (hotplug?) or major error, bail */
2123 if (unlikely(status == 0xFFFF))
2124 goto out;
2125
2126 /* close possible race's with dev_close */
2127 if (unlikely(!netif_running(dev))) {
2128 RTL_W16 (IntrMask, 0);
2129 goto out;
2130 }
2131
2132 /* Acknowledge all of the current interrupt sources ASAP, but
2133 an first get an additional status bit from CSCR. */
2134 if (unlikely(status & RxUnderrun))
2135 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2136
2137 ackstat = status & ~(RxAckBits | TxErr);
2138 if (ackstat)
2139 RTL_W16 (IntrStatus, ackstat);
2140
2141 /* Receive packets are processed by poll routine.
2142 If not running start it now. */
2143 if (status & RxAckBits){
2144 if (napi_schedule_prep(&tp->napi)) {
2145 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2146 __napi_schedule(&tp->napi);
2147 }
2148 }
2149
2150 /* Check uncommon events with one test. */
2151 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2152 rtl8139_weird_interrupt (dev, tp, ioaddr,
2153 status, link_changed);
2154
2155 if (status & (TxOK | TxErr)) {
2156 rtl8139_tx_interrupt (dev, tp, ioaddr);
2157 if (status & TxErr)
2158 RTL_W16 (IntrStatus, TxErr);
2159 }
2160 out:
2161 spin_unlock (&tp->lock);
2162
2163 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n",
2164 RTL_R16(IntrStatus));
2165 return IRQ_RETVAL(handled);
2166 }
2167
2168 #ifdef CONFIG_NET_POLL_CONTROLLER
2169 /*
2170 * Polling receive - used by netconsole and other diagnostic tools
2171 * to allow network i/o with interrupts disabled.
2172 */
2173 static void rtl8139_poll_controller(struct net_device *dev)
2174 {
2175 disable_irq(dev->irq);
2176 rtl8139_interrupt(dev->irq, dev);
2177 enable_irq(dev->irq);
2178 }
2179 #endif
2180
2181 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2182 {
2183 struct rtl8139_private *tp = netdev_priv(dev);
2184 void __iomem *ioaddr = tp->mmio_addr;
2185 struct sockaddr *addr = p;
2186
2187 if (!is_valid_ether_addr(addr->sa_data))
2188 return -EADDRNOTAVAIL;
2189
2190 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2191
2192 spin_lock_irq(&tp->lock);
2193
2194 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2195 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2196 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2197 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2198
2199 spin_unlock_irq(&tp->lock);
2200
2201 return 0;
2202 }
2203
2204 static int rtl8139_close (struct net_device *dev)
2205 {
2206 struct rtl8139_private *tp = netdev_priv(dev);
2207 void __iomem *ioaddr = tp->mmio_addr;
2208 unsigned long flags;
2209
2210 netif_stop_queue(dev);
2211 napi_disable(&tp->napi);
2212
2213 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n",
2214 RTL_R16(IntrStatus));
2215
2216 spin_lock_irqsave (&tp->lock, flags);
2217
2218 /* Stop the chip's Tx and Rx DMA processes. */
2219 RTL_W8 (ChipCmd, 0);
2220
2221 /* Disable interrupts by clearing the interrupt mask. */
2222 RTL_W16 (IntrMask, 0);
2223
2224 /* Update the error counts. */
2225 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2226 RTL_W32 (RxMissed, 0);
2227
2228 spin_unlock_irqrestore (&tp->lock, flags);
2229
2230 free_irq (dev->irq, dev);
2231
2232 rtl8139_tx_clear (tp);
2233
2234 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2235 tp->rx_ring, tp->rx_ring_dma);
2236 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2237 tp->tx_bufs, tp->tx_bufs_dma);
2238 tp->rx_ring = NULL;
2239 tp->tx_bufs = NULL;
2240
2241 /* Green! Put the chip in low-power mode. */
2242 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2243
2244 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2245 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2246
2247 return 0;
2248 }
2249
2250
2251 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2252 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2253 other threads or interrupts aren't messing with the 8139. */
2254 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2255 {
2256 struct rtl8139_private *tp = netdev_priv(dev);
2257 void __iomem *ioaddr = tp->mmio_addr;
2258
2259 spin_lock_irq(&tp->lock);
2260 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2261 u8 cfg3 = RTL_R8 (Config3);
2262 u8 cfg5 = RTL_R8 (Config5);
2263
2264 wol->supported = WAKE_PHY | WAKE_MAGIC
2265 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2266
2267 wol->wolopts = 0;
2268 if (cfg3 & Cfg3_LinkUp)
2269 wol->wolopts |= WAKE_PHY;
2270 if (cfg3 & Cfg3_Magic)
2271 wol->wolopts |= WAKE_MAGIC;
2272 /* (KON)FIXME: See how netdev_set_wol() handles the
2273 following constants. */
2274 if (cfg5 & Cfg5_UWF)
2275 wol->wolopts |= WAKE_UCAST;
2276 if (cfg5 & Cfg5_MWF)
2277 wol->wolopts |= WAKE_MCAST;
2278 if (cfg5 & Cfg5_BWF)
2279 wol->wolopts |= WAKE_BCAST;
2280 }
2281 spin_unlock_irq(&tp->lock);
2282 }
2283
2284
2285 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2286 that wol points to kernel memory and other threads or interrupts
2287 aren't messing with the 8139. */
2288 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2289 {
2290 struct rtl8139_private *tp = netdev_priv(dev);
2291 void __iomem *ioaddr = tp->mmio_addr;
2292 u32 support;
2293 u8 cfg3, cfg5;
2294
2295 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2296 ? (WAKE_PHY | WAKE_MAGIC
2297 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2298 : 0);
2299 if (wol->wolopts & ~support)
2300 return -EINVAL;
2301
2302 spin_lock_irq(&tp->lock);
2303 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2304 if (wol->wolopts & WAKE_PHY)
2305 cfg3 |= Cfg3_LinkUp;
2306 if (wol->wolopts & WAKE_MAGIC)
2307 cfg3 |= Cfg3_Magic;
2308 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2309 RTL_W8 (Config3, cfg3);
2310 RTL_W8 (Cfg9346, Cfg9346_Lock);
2311
2312 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2313 /* (KON)FIXME: These are untested. We may have to set the
2314 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2315 documentation. */
2316 if (wol->wolopts & WAKE_UCAST)
2317 cfg5 |= Cfg5_UWF;
2318 if (wol->wolopts & WAKE_MCAST)
2319 cfg5 |= Cfg5_MWF;
2320 if (wol->wolopts & WAKE_BCAST)
2321 cfg5 |= Cfg5_BWF;
2322 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2323 spin_unlock_irq(&tp->lock);
2324
2325 return 0;
2326 }
2327
2328 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2329 {
2330 struct rtl8139_private *tp = netdev_priv(dev);
2331 strcpy(info->driver, DRV_NAME);
2332 strcpy(info->version, DRV_VERSION);
2333 strcpy(info->bus_info, pci_name(tp->pci_dev));
2334 info->regdump_len = tp->regs_len;
2335 }
2336
2337 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2338 {
2339 struct rtl8139_private *tp = netdev_priv(dev);
2340 spin_lock_irq(&tp->lock);
2341 mii_ethtool_gset(&tp->mii, cmd);
2342 spin_unlock_irq(&tp->lock);
2343 return 0;
2344 }
2345
2346 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2347 {
2348 struct rtl8139_private *tp = netdev_priv(dev);
2349 int rc;
2350 spin_lock_irq(&tp->lock);
2351 rc = mii_ethtool_sset(&tp->mii, cmd);
2352 spin_unlock_irq(&tp->lock);
2353 return rc;
2354 }
2355
2356 static int rtl8139_nway_reset(struct net_device *dev)
2357 {
2358 struct rtl8139_private *tp = netdev_priv(dev);
2359 return mii_nway_restart(&tp->mii);
2360 }
2361
2362 static u32 rtl8139_get_link(struct net_device *dev)
2363 {
2364 struct rtl8139_private *tp = netdev_priv(dev);
2365 return mii_link_ok(&tp->mii);
2366 }
2367
2368 static u32 rtl8139_get_msglevel(struct net_device *dev)
2369 {
2370 struct rtl8139_private *tp = netdev_priv(dev);
2371 return tp->msg_enable;
2372 }
2373
2374 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2375 {
2376 struct rtl8139_private *tp = netdev_priv(dev);
2377 tp->msg_enable = datum;
2378 }
2379
2380 static int rtl8139_get_regs_len(struct net_device *dev)
2381 {
2382 struct rtl8139_private *tp;
2383 /* TODO: we are too slack to do reg dumping for pio, for now */
2384 if (use_io)
2385 return 0;
2386 tp = netdev_priv(dev);
2387 return tp->regs_len;
2388 }
2389
2390 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2391 {
2392 struct rtl8139_private *tp;
2393
2394 /* TODO: we are too slack to do reg dumping for pio, for now */
2395 if (use_io)
2396 return;
2397 tp = netdev_priv(dev);
2398
2399 regs->version = RTL_REGS_VER;
2400
2401 spin_lock_irq(&tp->lock);
2402 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2403 spin_unlock_irq(&tp->lock);
2404 }
2405
2406 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2407 {
2408 switch (sset) {
2409 case ETH_SS_STATS:
2410 return RTL_NUM_STATS;
2411 default:
2412 return -EOPNOTSUPP;
2413 }
2414 }
2415
2416 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2417 {
2418 struct rtl8139_private *tp = netdev_priv(dev);
2419
2420 data[0] = tp->xstats.early_rx;
2421 data[1] = tp->xstats.tx_buf_mapped;
2422 data[2] = tp->xstats.tx_timeouts;
2423 data[3] = tp->xstats.rx_lost_in_ring;
2424 }
2425
2426 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2427 {
2428 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2429 }
2430
2431 static const struct ethtool_ops rtl8139_ethtool_ops = {
2432 .get_drvinfo = rtl8139_get_drvinfo,
2433 .get_settings = rtl8139_get_settings,
2434 .set_settings = rtl8139_set_settings,
2435 .get_regs_len = rtl8139_get_regs_len,
2436 .get_regs = rtl8139_get_regs,
2437 .nway_reset = rtl8139_nway_reset,
2438 .get_link = rtl8139_get_link,
2439 .get_msglevel = rtl8139_get_msglevel,
2440 .set_msglevel = rtl8139_set_msglevel,
2441 .get_wol = rtl8139_get_wol,
2442 .set_wol = rtl8139_set_wol,
2443 .get_strings = rtl8139_get_strings,
2444 .get_sset_count = rtl8139_get_sset_count,
2445 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2446 };
2447
2448 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2449 {
2450 struct rtl8139_private *tp = netdev_priv(dev);
2451 int rc;
2452
2453 if (!netif_running(dev))
2454 return -EINVAL;
2455
2456 spin_lock_irq(&tp->lock);
2457 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2458 spin_unlock_irq(&tp->lock);
2459
2460 return rc;
2461 }
2462
2463
2464 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2465 {
2466 struct rtl8139_private *tp = netdev_priv(dev);
2467 void __iomem *ioaddr = tp->mmio_addr;
2468 unsigned long flags;
2469
2470 if (netif_running(dev)) {
2471 spin_lock_irqsave (&tp->lock, flags);
2472 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2473 RTL_W32 (RxMissed, 0);
2474 spin_unlock_irqrestore (&tp->lock, flags);
2475 }
2476
2477 return &dev->stats;
2478 }
2479
2480 /* Set or clear the multicast filter for this adaptor.
2481 This routine is not state sensitive and need not be SMP locked. */
2482
2483 static void __set_rx_mode (struct net_device *dev)
2484 {
2485 struct rtl8139_private *tp = netdev_priv(dev);
2486 void __iomem *ioaddr = tp->mmio_addr;
2487 u32 mc_filter[2]; /* Multicast hash filter */
2488 int rx_mode;
2489 u32 tmp;
2490
2491 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n",
2492 dev->flags, RTL_R32(RxConfig));
2493
2494 /* Note: do not reorder, GCC is clever about common statements. */
2495 if (dev->flags & IFF_PROMISC) {
2496 rx_mode =
2497 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2498 AcceptAllPhys;
2499 mc_filter[1] = mc_filter[0] = 0xffffffff;
2500 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2501 (dev->flags & IFF_ALLMULTI)) {
2502 /* Too many to filter perfectly -- accept all multicasts. */
2503 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2504 mc_filter[1] = mc_filter[0] = 0xffffffff;
2505 } else {
2506 struct netdev_hw_addr *ha;
2507 rx_mode = AcceptBroadcast | AcceptMyPhys;
2508 mc_filter[1] = mc_filter[0] = 0;
2509 netdev_for_each_mc_addr(ha, dev) {
2510 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2511
2512 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2513 rx_mode |= AcceptMulticast;
2514 }
2515 }
2516
2517 /* We can safely update without stopping the chip. */
2518 tmp = rtl8139_rx_config | rx_mode;
2519 if (tp->rx_config != tmp) {
2520 RTL_W32_F (RxConfig, tmp);
2521 tp->rx_config = tmp;
2522 }
2523 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2524 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2525 }
2526
2527 static void rtl8139_set_rx_mode (struct net_device *dev)
2528 {
2529 unsigned long flags;
2530 struct rtl8139_private *tp = netdev_priv(dev);
2531
2532 spin_lock_irqsave (&tp->lock, flags);
2533 __set_rx_mode(dev);
2534 spin_unlock_irqrestore (&tp->lock, flags);
2535 }
2536
2537 #ifdef CONFIG_PM
2538
2539 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2540 {
2541 struct net_device *dev = pci_get_drvdata (pdev);
2542 struct rtl8139_private *tp = netdev_priv(dev);
2543 void __iomem *ioaddr = tp->mmio_addr;
2544 unsigned long flags;
2545
2546 pci_save_state (pdev);
2547
2548 if (!netif_running (dev))
2549 return 0;
2550
2551 netif_device_detach (dev);
2552
2553 spin_lock_irqsave (&tp->lock, flags);
2554
2555 /* Disable interrupts, stop Tx and Rx. */
2556 RTL_W16 (IntrMask, 0);
2557 RTL_W8 (ChipCmd, 0);
2558
2559 /* Update the error counts. */
2560 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2561 RTL_W32 (RxMissed, 0);
2562
2563 spin_unlock_irqrestore (&tp->lock, flags);
2564
2565 pci_set_power_state (pdev, PCI_D3hot);
2566
2567 return 0;
2568 }
2569
2570
2571 static int rtl8139_resume (struct pci_dev *pdev)
2572 {
2573 struct net_device *dev = pci_get_drvdata (pdev);
2574
2575 pci_restore_state (pdev);
2576 if (!netif_running (dev))
2577 return 0;
2578 pci_set_power_state (pdev, PCI_D0);
2579 rtl8139_init_ring (dev);
2580 rtl8139_hw_start (dev);
2581 netif_device_attach (dev);
2582 return 0;
2583 }
2584
2585 #endif /* CONFIG_PM */
2586
2587
2588 static struct pci_driver rtl8139_pci_driver = {
2589 .name = DRV_NAME,
2590 .id_table = rtl8139_pci_tbl,
2591 .probe = rtl8139_init_one,
2592 .remove = __devexit_p(rtl8139_remove_one),
2593 #ifdef CONFIG_PM
2594 .suspend = rtl8139_suspend,
2595 .resume = rtl8139_resume,
2596 #endif /* CONFIG_PM */
2597 };
2598
2599
2600 static int __init rtl8139_init_module (void)
2601 {
2602 /* when we're a module, we always print a version message,
2603 * even if no 8139 board is found.
2604 */
2605 #ifdef MODULE
2606 pr_info(RTL8139_DRIVER_NAME "\n");
2607 #endif
2608
2609 return pci_register_driver(&rtl8139_pci_driver);
2610 }
2611
2612
2613 static void __exit rtl8139_cleanup_module (void)
2614 {
2615 pci_unregister_driver (&rtl8139_pci_driver);
2616 }
2617
2618
2619 module_init(rtl8139_init_module);
2620 module_exit(rtl8139_cleanup_module);