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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / net / cxgb4 / cxgb4.h
blobbc9982a4c1f4e3e44f6b01f4bf90f095b4176ab4
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef __CXGB4_H__
36 #define __CXGB4_H__
37
38 #include <linux/bitops.h>
39 #include <linux/cache.h>
40 #include <linux/interrupt.h>
41 #include <linux/list.h>
42 #include <linux/netdevice.h>
43 #include <linux/pci.h>
44 #include <linux/spinlock.h>
45 #include <linux/timer.h>
46 #include <asm/io.h>
47 #include "cxgb4_uld.h"
48 #include "t4_hw.h"
49
50 #define FW_VERSION_MAJOR 1
51 #define FW_VERSION_MINOR 1
52 #define FW_VERSION_MICRO 0
53
54 enum {
55 MAX_NPORTS = 4, /* max # of ports */
56 SERNUM_LEN = 24, /* Serial # length */
57 EC_LEN = 16, /* E/C length */
58 ID_LEN = 16, /* ID length */
59 };
60
61 enum {
62 MEM_EDC0,
63 MEM_EDC1,
64 MEM_MC
65 };
66
67 enum dev_master {
68 MASTER_CANT,
69 MASTER_MAY,
70 MASTER_MUST
71 };
72
73 enum dev_state {
74 DEV_STATE_UNINIT,
75 DEV_STATE_INIT,
76 DEV_STATE_ERR
77 };
78
79 enum {
80 PAUSE_RX = 1 << 0,
81 PAUSE_TX = 1 << 1,
82 PAUSE_AUTONEG = 1 << 2
83 };
84
85 struct port_stats {
86 u64 tx_octets; /* total # of octets in good frames */
87 u64 tx_frames; /* all good frames */
88 u64 tx_bcast_frames; /* all broadcast frames */
89 u64 tx_mcast_frames; /* all multicast frames */
90 u64 tx_ucast_frames; /* all unicast frames */
91 u64 tx_error_frames; /* all error frames */
92
93 u64 tx_frames_64; /* # of Tx frames in a particular range */
94 u64 tx_frames_65_127;
95 u64 tx_frames_128_255;
96 u64 tx_frames_256_511;
97 u64 tx_frames_512_1023;
98 u64 tx_frames_1024_1518;
99 u64 tx_frames_1519_max;
100
101 u64 tx_drop; /* # of dropped Tx frames */
102 u64 tx_pause; /* # of transmitted pause frames */
103 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
104 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
105 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
106 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
107 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
108 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
109 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
110 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
111
112 u64 rx_octets; /* total # of octets in good frames */
113 u64 rx_frames; /* all good frames */
114 u64 rx_bcast_frames; /* all broadcast frames */
115 u64 rx_mcast_frames; /* all multicast frames */
116 u64 rx_ucast_frames; /* all unicast frames */
117 u64 rx_too_long; /* # of frames exceeding MTU */
118 u64 rx_jabber; /* # of jabber frames */
119 u64 rx_fcs_err; /* # of received frames with bad FCS */
120 u64 rx_len_err; /* # of received frames with length error */
121 u64 rx_symbol_err; /* symbol errors */
122 u64 rx_runt; /* # of short frames */
123
124 u64 rx_frames_64; /* # of Rx frames in a particular range */
125 u64 rx_frames_65_127;
126 u64 rx_frames_128_255;
127 u64 rx_frames_256_511;
128 u64 rx_frames_512_1023;
129 u64 rx_frames_1024_1518;
130 u64 rx_frames_1519_max;
131
132 u64 rx_pause; /* # of received pause frames */
133 u64 rx_ppp0; /* # of received PPP prio 0 frames */
134 u64 rx_ppp1; /* # of received PPP prio 1 frames */
135 u64 rx_ppp2; /* # of received PPP prio 2 frames */
136 u64 rx_ppp3; /* # of received PPP prio 3 frames */
137 u64 rx_ppp4; /* # of received PPP prio 4 frames */
138 u64 rx_ppp5; /* # of received PPP prio 5 frames */
139 u64 rx_ppp6; /* # of received PPP prio 6 frames */
140 u64 rx_ppp7; /* # of received PPP prio 7 frames */
141
142 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
143 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
144 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
145 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
146 u64 rx_trunc0; /* buffer-group 0 truncated packets */
147 u64 rx_trunc1; /* buffer-group 1 truncated packets */
148 u64 rx_trunc2; /* buffer-group 2 truncated packets */
149 u64 rx_trunc3; /* buffer-group 3 truncated packets */
150 };
151
152 struct lb_port_stats {
153 u64 octets;
154 u64 frames;
155 u64 bcast_frames;
156 u64 mcast_frames;
157 u64 ucast_frames;
158 u64 error_frames;
159
160 u64 frames_64;
161 u64 frames_65_127;
162 u64 frames_128_255;
163 u64 frames_256_511;
164 u64 frames_512_1023;
165 u64 frames_1024_1518;
166 u64 frames_1519_max;
167
168 u64 drop;
169
170 u64 ovflow0;
171 u64 ovflow1;
172 u64 ovflow2;
173 u64 ovflow3;
174 u64 trunc0;
175 u64 trunc1;
176 u64 trunc2;
177 u64 trunc3;
178 };
179
180 struct tp_tcp_stats {
181 u32 tcpOutRsts;
182 u64 tcpInSegs;
183 u64 tcpOutSegs;
184 u64 tcpRetransSegs;
185 };
186
187 struct tp_err_stats {
188 u32 macInErrs[4];
189 u32 hdrInErrs[4];
190 u32 tcpInErrs[4];
191 u32 tnlCongDrops[4];
192 u32 ofldChanDrops[4];
193 u32 tnlTxDrops[4];
194 u32 ofldVlanDrops[4];
195 u32 tcp6InErrs[4];
196 u32 ofldNoNeigh;
197 u32 ofldCongDefer;
198 };
199
200 struct tp_params {
201 unsigned int ntxchan; /* # of Tx channels */
202 unsigned int tre; /* log2 of core clocks per TP tick */
203 };
204
205 struct vpd_params {
206 unsigned int cclk;
207 u8 ec[EC_LEN + 1];
208 u8 sn[SERNUM_LEN + 1];
209 u8 id[ID_LEN + 1];
210 };
211
212 struct pci_params {
213 unsigned char speed;
214 unsigned char width;
215 };
216
217 struct adapter_params {
218 struct tp_params tp;
219 struct vpd_params vpd;
220 struct pci_params pci;
221
222 unsigned int sf_size; /* serial flash size in bytes */
223 unsigned int sf_nsec; /* # of flash sectors */
224 unsigned int sf_fw_start; /* start of FW image in flash */
225
226 unsigned int fw_vers;
227 unsigned int tp_vers;
228 u8 api_vers[7];
229
230 unsigned short mtus[NMTUS];
231 unsigned short a_wnd[NCCTRL_WIN];
232 unsigned short b_wnd[NCCTRL_WIN];
233
234 unsigned char nports; /* # of ethernet ports */
235 unsigned char portvec;
236 unsigned char rev; /* chip revision */
237 unsigned char offload;
238
239 unsigned int ofldq_wr_cred;
240 };
241
242 struct trace_params {
243 u32 data[TRACE_LEN / 4];
244 u32 mask[TRACE_LEN / 4];
245 unsigned short snap_len;
246 unsigned short min_len;
247 unsigned char skip_ofst;
248 unsigned char skip_len;
249 unsigned char invert;
250 unsigned char port;
251 };
252
253 struct link_config {
254 unsigned short supported; /* link capabilities */
255 unsigned short advertising; /* advertised capabilities */
256 unsigned short requested_speed; /* speed user has requested */
257 unsigned short speed; /* actual link speed */
258 unsigned char requested_fc; /* flow control user has requested */
259 unsigned char fc; /* actual link flow control */
260 unsigned char autoneg; /* autonegotiating? */
261 unsigned char link_ok; /* link up? */
262 };
263
264 #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
265
266 enum {
267 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
268 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
269 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
270 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
271 };
272
273 enum {
274 MAX_EGRQ = 128, /* max # of egress queues, including FLs */
275 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
276 };
277
278 struct adapter;
279 struct vlan_group;
280 struct sge_rspq;
281
282 struct port_info {
283 struct adapter *adapter;
284 u16 viid;
285 s16 xact_addr_filt; /* index of exact MAC address filter */
286 u16 rss_size; /* size of VI's RSS table slice */
287 s8 mdio_addr;
288 u8 port_type;
289 u8 mod_type;
290 u8 port_id;
291 u8 tx_chan;
292 u8 lport; /* associated offload logical port */
293 u8 nqsets; /* # of qsets */
294 u8 first_qset; /* index of first qset */
295 u8 rss_mode;
296 struct link_config link_cfg;
297 u16 *rss;
298 };
299
300 struct dentry;
301 struct work_struct;
302
303 enum { /* adapter flags */
304 FULL_INIT_DONE = (1 << 0),
305 USING_MSI = (1 << 1),
306 USING_MSIX = (1 << 2),
307 FW_OK = (1 << 4),
308 };
309
310 struct rx_sw_desc;
311
312 struct sge_fl { /* SGE free-buffer queue state */
313 unsigned int avail; /* # of available Rx buffers */
314 unsigned int pend_cred; /* new buffers since last FL DB ring */
315 unsigned int cidx; /* consumer index */
316 unsigned int pidx; /* producer index */
317 unsigned long alloc_failed; /* # of times buffer allocation failed */
318 unsigned long large_alloc_failed;
319 unsigned long starving;
320 /* RO fields */
321 unsigned int cntxt_id; /* SGE context id for the free list */
322 unsigned int size; /* capacity of free list */
323 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
324 __be64 *desc; /* address of HW Rx descriptor ring */
325 dma_addr_t addr; /* bus address of HW ring start */
326 };
327
328 /* A packet gather list */
329 struct pkt_gl {
330 skb_frag_t frags[MAX_SKB_FRAGS];
331 void *va; /* virtual address of first byte */
332 unsigned int nfrags; /* # of fragments */
333 unsigned int tot_len; /* total length of fragments */
334 };
335
336 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
337 const struct pkt_gl *gl);
338
339 struct sge_rspq { /* state for an SGE response queue */
340 struct napi_struct napi;
341 const __be64 *cur_desc; /* current descriptor in queue */
342 unsigned int cidx; /* consumer index */
343 u8 gen; /* current generation bit */
344 u8 intr_params; /* interrupt holdoff parameters */
345 u8 next_intr_params; /* holdoff params for next interrupt */
346 u8 pktcnt_idx; /* interrupt packet threshold */
347 u8 uld; /* ULD handling this queue */
348 u8 idx; /* queue index within its group */
349 int offset; /* offset into current Rx buffer */
350 u16 cntxt_id; /* SGE context id for the response q */
351 u16 abs_id; /* absolute SGE id for the response q */
352 __be64 *desc; /* address of HW response ring */
353 dma_addr_t phys_addr; /* physical address of the ring */
354 unsigned int iqe_len; /* entry size */
355 unsigned int size; /* capacity of response queue */
356 struct adapter *adap;
357 struct net_device *netdev; /* associated net device */
358 rspq_handler_t handler;
359 };
360
361 struct sge_eth_stats { /* Ethernet queue statistics */
362 unsigned long pkts; /* # of ethernet packets */
363 unsigned long lro_pkts; /* # of LRO super packets */
364 unsigned long lro_merged; /* # of wire packets merged by LRO */
365 unsigned long rx_cso; /* # of Rx checksum offloads */
366 unsigned long vlan_ex; /* # of Rx VLAN extractions */
367 unsigned long rx_drops; /* # of packets dropped due to no mem */
368 };
369
370 struct sge_eth_rxq { /* SW Ethernet Rx queue */
371 struct sge_rspq rspq;
372 struct sge_fl fl;
373 struct sge_eth_stats stats;
374 } ____cacheline_aligned_in_smp;
375
376 struct sge_ofld_stats { /* offload queue statistics */
377 unsigned long pkts; /* # of packets */
378 unsigned long imm; /* # of immediate-data packets */
379 unsigned long an; /* # of asynchronous notifications */
380 unsigned long nomem; /* # of responses deferred due to no mem */
381 };
382
383 struct sge_ofld_rxq { /* SW offload Rx queue */
384 struct sge_rspq rspq;
385 struct sge_fl fl;
386 struct sge_ofld_stats stats;
387 } ____cacheline_aligned_in_smp;
388
389 struct tx_desc {
390 __be64 flit[8];
391 };
392
393 struct tx_sw_desc;
394
395 struct sge_txq {
396 unsigned int in_use; /* # of in-use Tx descriptors */
397 unsigned int size; /* # of descriptors */
398 unsigned int cidx; /* SW consumer index */
399 unsigned int pidx; /* producer index */
400 unsigned long stops; /* # of times q has been stopped */
401 unsigned long restarts; /* # of queue restarts */
402 unsigned int cntxt_id; /* SGE context id for the Tx q */
403 struct tx_desc *desc; /* address of HW Tx descriptor ring */
404 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
405 struct sge_qstat *stat; /* queue status entry */
406 dma_addr_t phys_addr; /* physical address of the ring */
407 };
408
409 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
410 struct sge_txq q;
411 struct netdev_queue *txq; /* associated netdev TX queue */
412 unsigned long tso; /* # of TSO requests */
413 unsigned long tx_cso; /* # of Tx checksum offloads */
414 unsigned long vlan_ins; /* # of Tx VLAN insertions */
415 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
416 } ____cacheline_aligned_in_smp;
417
418 struct sge_ofld_txq { /* state for an SGE offload Tx queue */
419 struct sge_txq q;
420 struct adapter *adap;
421 struct sk_buff_head sendq; /* list of backpressured packets */
422 struct tasklet_struct qresume_tsk; /* restarts the queue */
423 u8 full; /* the Tx ring is full */
424 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
425 } ____cacheline_aligned_in_smp;
426
427 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
428 struct sge_txq q;
429 struct adapter *adap;
430 struct sk_buff_head sendq; /* list of backpressured packets */
431 struct tasklet_struct qresume_tsk; /* restarts the queue */
432 u8 full; /* the Tx ring is full */
433 } ____cacheline_aligned_in_smp;
434
435 struct sge {
436 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
437 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
438 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
439
440 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
441 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
442 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
443 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
444
445 struct sge_rspq intrq ____cacheline_aligned_in_smp;
446 spinlock_t intrq_lock;
447
448 u16 max_ethqsets; /* # of available Ethernet queue sets */
449 u16 ethqsets; /* # of active Ethernet queue sets */
450 u16 ethtxq_rover; /* Tx queue to clean up next */
451 u16 ofldqsets; /* # of active offload queue sets */
452 u16 rdmaqs; /* # of available RDMA Rx queues */
453 u16 ofld_rxq[MAX_OFLD_QSETS];
454 u16 rdma_rxq[NCHAN];
455 u16 timer_val[SGE_NTIMERS];
456 u8 counter_val[SGE_NCOUNTERS];
457 unsigned int starve_thres;
458 u8 idma_state[2];
459 unsigned int egr_start;
460 unsigned int ingr_start;
461 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
462 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
463 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
464 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
465 struct timer_list rx_timer; /* refills starving FLs */
466 struct timer_list tx_timer; /* checks Tx queues */
467 };
468
469 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
470 #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
471 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
472
473 struct l2t_data;
474
475 struct adapter {
476 void __iomem *regs;
477 struct pci_dev *pdev;
478 struct device *pdev_dev;
479 unsigned int fn;
480 unsigned int flags;
481
482 int msg_enable;
483
484 struct adapter_params params;
485 struct cxgb4_virt_res vres;
486 unsigned int swintr;
487
488 unsigned int wol;
489
490 struct {
491 unsigned short vec;
492 char desc[IFNAMSIZ + 10];
493 } msix_info[MAX_INGQ + 1];
494
495 struct sge sge;
496
497 struct net_device *port[MAX_NPORTS];
498 u8 chan_map[NCHAN]; /* channel -> port map */
499
500 struct l2t_data *l2t;
501 void *uld_handle[CXGB4_ULD_MAX];
502 struct list_head list_node;
503
504 struct tid_info tids;
505 void **tid_release_head;
506 spinlock_t tid_release_lock;
507 struct work_struct tid_release_task;
508 bool tid_release_task_busy;
509
510 struct dentry *debugfs_root;
511
512 spinlock_t stats_lock;
513 };
514
515 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
516 {
517 return readl(adap->regs + reg_addr);
518 }
519
520 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
521 {
522 writel(val, adap->regs + reg_addr);
523 }
524
525 #ifndef readq
526 static inline u64 readq(const volatile void __iomem *addr)
527 {
528 return readl(addr) + ((u64)readl(addr + 4) << 32);
529 }
530
531 static inline void writeq(u64 val, volatile void __iomem *addr)
532 {
533 writel(val, addr);
534 writel(val >> 32, addr + 4);
535 }
536 #endif
537
538 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
539 {
540 return readq(adap->regs + reg_addr);
541 }
542
543 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
544 {
545 writeq(val, adap->regs + reg_addr);
546 }
547
548 /**
549 * netdev2pinfo - return the port_info structure associated with a net_device
550 * @dev: the netdev
551 *
552 * Return the struct port_info associated with a net_device
553 */
554 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
555 {
556 return netdev_priv(dev);
557 }
558
559 /**
560 * adap2pinfo - return the port_info of a port
561 * @adap: the adapter
562 * @idx: the port index
563 *
564 * Return the port_info structure for the port of the given index.
565 */
566 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
567 {
568 return netdev_priv(adap->port[idx]);
569 }
570
571 /**
572 * netdev2adap - return the adapter structure associated with a net_device
573 * @dev: the netdev
574 *
575 * Return the struct adapter associated with a net_device
576 */
577 static inline struct adapter *netdev2adap(const struct net_device *dev)
578 {
579 return netdev2pinfo(dev)->adapter;
580 }
581
582 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
583 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
584
585 void *t4_alloc_mem(size_t size);
586
587 void t4_free_sge_resources(struct adapter *adap);
588 irq_handler_t t4_intr_handler(struct adapter *adap);
589 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
590 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
591 const struct pkt_gl *gl);
592 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
593 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
594 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
595 struct net_device *dev, int intr_idx,
596 struct sge_fl *fl, rspq_handler_t hnd);
597 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
598 struct net_device *dev, struct netdev_queue *netdevq,
599 unsigned int iqid);
600 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
601 struct net_device *dev, unsigned int iqid,
602 unsigned int cmplqid);
603 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
604 struct net_device *dev, unsigned int iqid);
605 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
606 void t4_sge_init(struct adapter *adap);
607 void t4_sge_start(struct adapter *adap);
608 void t4_sge_stop(struct adapter *adap);
609
610 #define for_each_port(adapter, iter) \
611 for (iter = 0; iter < (adapter)->params.nports; ++iter)
612
613 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
614 {
615 return adap->params.vpd.cclk / 1000;
616 }
617
618 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
619 unsigned int us)
620 {
621 return (us * adap->params.vpd.cclk) / 1000;
622 }
623
624 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
625 u32 val);
626
627 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
628 void *rpl, bool sleep_ok);
629
630 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
631 int size, void *rpl)
632 {
633 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
634 }
635
636 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
637 int size, void *rpl)
638 {
639 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
640 }
641
642 void t4_intr_enable(struct adapter *adapter);
643 void t4_intr_disable(struct adapter *adapter);
644 int t4_slow_intr_handler(struct adapter *adapter);
645
646 int t4_wait_dev_ready(struct adapter *adap);
647 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
648 struct link_config *lc);
649 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
650 int t4_seeprom_wp(struct adapter *adapter, bool enable);
651 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
652 int t4_check_fw_version(struct adapter *adapter);
653 int t4_prep_adapter(struct adapter *adapter);
654 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
655 void t4_fatal_err(struct adapter *adapter);
656 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
657 int start, int n, const u16 *rspq, unsigned int nrspq);
658 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
659 unsigned int flags);
660 int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity);
661 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
662 u64 *parity);
663
664 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
665 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
666 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
667 struct tp_tcp_stats *v6);
668 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
669 const unsigned short *alpha, const unsigned short *beta);
670
671 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
672 const u8 *addr);
673 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
674 u64 mask0, u64 mask1, unsigned int crc, bool enable);
675
676 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
677 enum dev_master master, enum dev_state *state);
678 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
679 int t4_early_init(struct adapter *adap, unsigned int mbox);
680 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
681 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
682 unsigned int vf, unsigned int nparams, const u32 *params,
683 u32 *val);
684 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
685 unsigned int vf, unsigned int nparams, const u32 *params,
686 const u32 *val);
687 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
688 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
689 unsigned int rxqi, unsigned int rxq, unsigned int tc,
690 unsigned int vi, unsigned int cmask, unsigned int pmask,
691 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
692 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
693 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
694 unsigned int *rss_size);
695 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
696 int mtu, int promisc, int all_multi, int bcast, int vlanex,
697 bool sleep_ok);
698 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
699 unsigned int viid, bool free, unsigned int naddr,
700 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
701 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
702 int idx, const u8 *addr, bool persist, bool add_smt);
703 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
704 bool ucast, u64 vec, bool sleep_ok);
705 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
706 bool rx_en, bool tx_en);
707 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
708 unsigned int nblinks);
709 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
710 unsigned int mmd, unsigned int reg, u16 *valp);
711 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
712 unsigned int mmd, unsigned int reg, u16 val);
713 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
714 unsigned int vf, unsigned int iqtype, unsigned int iqid,
715 unsigned int fl0id, unsigned int fl1id);
716 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
717 unsigned int vf, unsigned int eqid);
718 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
719 unsigned int vf, unsigned int eqid);
720 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
721 unsigned int vf, unsigned int eqid);
722 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
723 #endif /* __CXGB4_H__ */