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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / net / ixgbe / ixgbe_82599.c
blob8ee661245af39a055bad37177961807fdfe822ad
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
42
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg,
49 bool autoneg_wait_to_complete);
50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
52 bool autoneg,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
58 bool autoneg,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
62 bool autoneg,
63 bool autoneg_wait_to_complete);
64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
66
67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
68 {
69 struct ixgbe_mac_info *mac = &hw->mac;
70
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
73 mac->ops.disable_tx_laser =
74 &ixgbe_disable_tx_laser_multispeed_fiber;
75 mac->ops.enable_tx_laser =
76 &ixgbe_enable_tx_laser_multispeed_fiber;
77 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
78 } else {
79 mac->ops.disable_tx_laser = NULL;
80 mac->ops.enable_tx_laser = NULL;
81 mac->ops.flap_tx_laser = NULL;
82 }
83
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
87 } else {
88 if ((mac->ops.get_media_type(hw) ==
89 ixgbe_media_type_backplane) &&
90 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
91 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw))
93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
94 else
95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
96 }
97 }
98
99 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
100 {
101 s32 ret_val = 0;
102 u32 reg_anlp1 = 0;
103 u32 i = 0;
104 u16 list_offset, data_offset, data_value;
105
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
107 ixgbe_init_mac_link_ops_82599(hw);
108
109 hw->phy.ops.reset = NULL;
110
111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
112 &data_offset);
113 if (ret_val != 0)
114 goto setup_sfp_out;
115
116 /* PHY config will finish before releasing the semaphore */
117 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
118 IXGBE_GSSR_MAC_CSR_SM);
119 if (ret_val != 0) {
120 ret_val = IXGBE_ERR_SWFW_SYNC;
121 goto setup_sfp_out;
122 }
123
124 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
125 while (data_value != 0xffff) {
126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
127 IXGBE_WRITE_FLUSH(hw);
128 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
129 }
130
131 /* Release the semaphore */
132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
133 /*
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
136 */
137 usleep_range(hw->eeprom.semaphore_delay * 1000,
138 hw->eeprom.semaphore_delay * 2000);
139
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
142 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
143 IXGBE_AUTOC_AN_RESTART));
144
145 /* Wait for AN to leave state 0 */
146 for (i = 0; i < 10; i++) {
147 usleep_range(4000, 8000);
148 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
149 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
150 break;
151 }
152 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
153 hw_dbg(hw, "sfp module setup not complete\n");
154 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
155 goto setup_sfp_out;
156 }
157
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
160 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
161 IXGBE_AUTOC_AN_RESTART));
162 }
163
164 setup_sfp_out:
165 return ret_val;
166 }
167
168 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
169 {
170 struct ixgbe_mac_info *mac = &hw->mac;
171
172 ixgbe_init_mac_link_ops_82599(hw);
173
174 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
175 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
176 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
177 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
178 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
180
181 return 0;
182 }
183
184 /**
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
187 *
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
191 *
192 **/
193 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
194 {
195 struct ixgbe_mac_info *mac = &hw->mac;
196 struct ixgbe_phy_info *phy = &hw->phy;
197 s32 ret_val = 0;
198
199 /* Identify the PHY or SFP module */
200 ret_val = phy->ops.identify(hw);
201
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw);
204
205 /* If copper media, overwrite with copper function pointers */
206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
207 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
208 mac->ops.get_link_capabilities =
209 &ixgbe_get_copper_link_capabilities_generic;
210 }
211
212 /* Set necessary function pointers based on phy type */
213 switch (hw->phy.type) {
214 case ixgbe_phy_tn:
215 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
216 phy->ops.get_firmware_version =
217 &ixgbe_get_phy_firmware_version_tnx;
218 break;
219 case ixgbe_phy_aq:
220 phy->ops.get_firmware_version =
221 &ixgbe_get_phy_firmware_version_generic;
222 break;
223 default:
224 break;
225 }
226
227 return ret_val;
228 }
229
230 /**
231 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
232 * @hw: pointer to hardware structure
233 * @speed: pointer to link speed
234 * @negotiation: true when autoneg or autotry is enabled
235 *
236 * Determines the link capabilities by reading the AUTOC register.
237 **/
238 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
239 ixgbe_link_speed *speed,
240 bool *negotiation)
241 {
242 s32 status = 0;
243 u32 autoc = 0;
244
245 /* Determine 1G link capabilities off of SFP+ type */
246 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
247 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
248 *speed = IXGBE_LINK_SPEED_1GB_FULL;
249 *negotiation = true;
250 goto out;
251 }
252
253 /*
254 * Determine link capabilities based on the stored value of AUTOC,
255 * which represents EEPROM defaults. If AUTOC value has not been
256 * stored, use the current register value.
257 */
258 if (hw->mac.orig_link_settings_stored)
259 autoc = hw->mac.orig_autoc;
260 else
261 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
262
263 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
264 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
265 *speed = IXGBE_LINK_SPEED_1GB_FULL;
266 *negotiation = false;
267 break;
268
269 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
270 *speed = IXGBE_LINK_SPEED_10GB_FULL;
271 *negotiation = false;
272 break;
273
274 case IXGBE_AUTOC_LMS_1G_AN:
275 *speed = IXGBE_LINK_SPEED_1GB_FULL;
276 *negotiation = true;
277 break;
278
279 case IXGBE_AUTOC_LMS_10G_SERIAL:
280 *speed = IXGBE_LINK_SPEED_10GB_FULL;
281 *negotiation = false;
282 break;
283
284 case IXGBE_AUTOC_LMS_KX4_KX_KR:
285 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
286 *speed = IXGBE_LINK_SPEED_UNKNOWN;
287 if (autoc & IXGBE_AUTOC_KR_SUPP)
288 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
289 if (autoc & IXGBE_AUTOC_KX4_SUPP)
290 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
291 if (autoc & IXGBE_AUTOC_KX_SUPP)
292 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
293 *negotiation = true;
294 break;
295
296 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
297 *speed = IXGBE_LINK_SPEED_100_FULL;
298 if (autoc & IXGBE_AUTOC_KR_SUPP)
299 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
300 if (autoc & IXGBE_AUTOC_KX4_SUPP)
301 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
302 if (autoc & IXGBE_AUTOC_KX_SUPP)
303 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
304 *negotiation = true;
305 break;
306
307 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
308 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
309 *negotiation = false;
310 break;
311
312 default:
313 status = IXGBE_ERR_LINK_SETUP;
314 goto out;
315 break;
316 }
317
318 if (hw->phy.multispeed_fiber) {
319 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
320 IXGBE_LINK_SPEED_1GB_FULL;
321 *negotiation = true;
322 }
323
324 out:
325 return status;
326 }
327
328 /**
329 * ixgbe_get_media_type_82599 - Get media type
330 * @hw: pointer to hardware structure
331 *
332 * Returns the media type (fiber, copper, backplane)
333 **/
334 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
335 {
336 enum ixgbe_media_type media_type;
337
338 /* Detect if there is a copper PHY attached. */
339 switch (hw->phy.type) {
340 case ixgbe_phy_cu_unknown:
341 case ixgbe_phy_tn:
342 case ixgbe_phy_aq:
343 media_type = ixgbe_media_type_copper;
344 goto out;
345 default:
346 break;
347 }
348
349 switch (hw->device_id) {
350 case IXGBE_DEV_ID_82599_KX4:
351 case IXGBE_DEV_ID_82599_KX4_MEZZ:
352 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
353 case IXGBE_DEV_ID_82599_KR:
354 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
355 case IXGBE_DEV_ID_82599_XAUI_LOM:
356 /* Default device ID is mezzanine card KX/KX4 */
357 media_type = ixgbe_media_type_backplane;
358 break;
359 case IXGBE_DEV_ID_82599_SFP:
360 case IXGBE_DEV_ID_82599_SFP_FCOE:
361 case IXGBE_DEV_ID_82599_SFP_EM:
362 case IXGBE_DEV_ID_82599_SFP_SF2:
363 media_type = ixgbe_media_type_fiber;
364 break;
365 case IXGBE_DEV_ID_82599_CX4:
366 media_type = ixgbe_media_type_cx4;
367 break;
368 case IXGBE_DEV_ID_82599_T3_LOM:
369 media_type = ixgbe_media_type_copper;
370 break;
371 case IXGBE_DEV_ID_82599_LS:
372 media_type = ixgbe_media_type_fiber_lco;
373 break;
374 default:
375 media_type = ixgbe_media_type_unknown;
376 break;
377 }
378 out:
379 return media_type;
380 }
381
382 /**
383 * ixgbe_start_mac_link_82599 - Setup MAC link settings
384 * @hw: pointer to hardware structure
385 * @autoneg_wait_to_complete: true when waiting for completion is needed
386 *
387 * Configures link settings based on values in the ixgbe_hw struct.
388 * Restarts the link. Performs autonegotiation if needed.
389 **/
390 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
391 bool autoneg_wait_to_complete)
392 {
393 u32 autoc_reg;
394 u32 links_reg;
395 u32 i;
396 s32 status = 0;
397
398 /* Restart link */
399 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
400 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
401 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
402
403 /* Only poll for autoneg to complete if specified to do so */
404 if (autoneg_wait_to_complete) {
405 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
406 IXGBE_AUTOC_LMS_KX4_KX_KR ||
407 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
408 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
409 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
410 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
411 links_reg = 0; /* Just in case Autoneg time = 0 */
412 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
413 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
414 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
415 break;
416 msleep(100);
417 }
418 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
419 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
420 hw_dbg(hw, "Autoneg did not complete.\n");
421 }
422 }
423 }
424
425 /* Add delay to filter out noises during initial link setup */
426 msleep(50);
427
428 return status;
429 }
430
431 /**
432 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
433 * @hw: pointer to hardware structure
434 *
435 * The base drivers may require better control over SFP+ module
436 * PHY states. This includes selectively shutting down the Tx
437 * laser on the PHY, effectively halting physical link.
438 **/
439 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
440 {
441 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
442
443 /* Disable tx laser; allow 100us to go dark per spec */
444 esdp_reg |= IXGBE_ESDP_SDP3;
445 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
446 IXGBE_WRITE_FLUSH(hw);
447 udelay(100);
448 }
449
450 /**
451 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
452 * @hw: pointer to hardware structure
453 *
454 * The base drivers may require better control over SFP+ module
455 * PHY states. This includes selectively turning on the Tx
456 * laser on the PHY, effectively starting physical link.
457 **/
458 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
459 {
460 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
461
462 /* Enable tx laser; allow 100ms to light up */
463 esdp_reg &= ~IXGBE_ESDP_SDP3;
464 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
465 IXGBE_WRITE_FLUSH(hw);
466 msleep(100);
467 }
468
469 /**
470 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
471 * @hw: pointer to hardware structure
472 *
473 * When the driver changes the link speeds that it can support,
474 * it sets autotry_restart to true to indicate that we need to
475 * initiate a new autotry session with the link partner. To do
476 * so, we set the speed then disable and re-enable the tx laser, to
477 * alert the link partner that it also needs to restart autotry on its
478 * end. This is consistent with true clause 37 autoneg, which also
479 * involves a loss of signal.
480 **/
481 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
482 {
483 if (hw->mac.autotry_restart) {
484 ixgbe_disable_tx_laser_multispeed_fiber(hw);
485 ixgbe_enable_tx_laser_multispeed_fiber(hw);
486 hw->mac.autotry_restart = false;
487 }
488 }
489
490 /**
491 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
492 * @hw: pointer to hardware structure
493 * @speed: new link speed
494 * @autoneg: true if autonegotiation enabled
495 * @autoneg_wait_to_complete: true when waiting for completion is needed
496 *
497 * Set the link speed in the AUTOC register and restarts link.
498 **/
499 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
500 ixgbe_link_speed speed,
501 bool autoneg,
502 bool autoneg_wait_to_complete)
503 {
504 s32 status = 0;
505 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
506 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
507 u32 speedcnt = 0;
508 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
509 u32 i = 0;
510 bool link_up = false;
511 bool negotiation;
512
513 /* Mask off requested but non-supported speeds */
514 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
515 &negotiation);
516 if (status != 0)
517 return status;
518
519 speed &= link_speed;
520
521 /*
522 * Try each speed one by one, highest priority first. We do this in
523 * software because 10gb fiber doesn't support speed autonegotiation.
524 */
525 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
526 speedcnt++;
527 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
528
529 /* If we already have link at this speed, just jump out */
530 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
531 false);
532 if (status != 0)
533 return status;
534
535 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
536 goto out;
537
538 /* Set the module link speed */
539 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
540 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
541 IXGBE_WRITE_FLUSH(hw);
542
543 /* Allow module to change analog characteristics (1G->10G) */
544 msleep(40);
545
546 status = ixgbe_setup_mac_link_82599(hw,
547 IXGBE_LINK_SPEED_10GB_FULL,
548 autoneg,
549 autoneg_wait_to_complete);
550 if (status != 0)
551 return status;
552
553 /* Flap the tx laser if it has not already been done */
554 hw->mac.ops.flap_tx_laser(hw);
555
556 /*
557 * Wait for the controller to acquire link. Per IEEE 802.3ap,
558 * Section 73.10.2, we may have to wait up to 500ms if KR is
559 * attempted. 82599 uses the same timing for 10g SFI.
560 */
561 for (i = 0; i < 5; i++) {
562 /* Wait for the link partner to also set speed */
563 msleep(100);
564
565 /* If we have link, just jump out */
566 status = hw->mac.ops.check_link(hw, &link_speed,
567 &link_up, false);
568 if (status != 0)
569 return status;
570
571 if (link_up)
572 goto out;
573 }
574 }
575
576 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
577 speedcnt++;
578 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
579 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
580
581 /* If we already have link at this speed, just jump out */
582 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
583 false);
584 if (status != 0)
585 return status;
586
587 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
588 goto out;
589
590 /* Set the module link speed */
591 esdp_reg &= ~IXGBE_ESDP_SDP5;
592 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
593 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
594 IXGBE_WRITE_FLUSH(hw);
595
596 /* Allow module to change analog characteristics (10G->1G) */
597 msleep(40);
598
599 status = ixgbe_setup_mac_link_82599(hw,
600 IXGBE_LINK_SPEED_1GB_FULL,
601 autoneg,
602 autoneg_wait_to_complete);
603 if (status != 0)
604 return status;
605
606 /* Flap the tx laser if it has not already been done */
607 hw->mac.ops.flap_tx_laser(hw);
608
609 /* Wait for the link partner to also set speed */
610 msleep(100);
611
612 /* If we have link, just jump out */
613 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
614 false);
615 if (status != 0)
616 return status;
617
618 if (link_up)
619 goto out;
620 }
621
622 /*
623 * We didn't get link. Configure back to the highest speed we tried,
624 * (if there was more than one). We call ourselves back with just the
625 * single highest speed that the user requested.
626 */
627 if (speedcnt > 1)
628 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
629 highest_link_speed,
630 autoneg,
631 autoneg_wait_to_complete);
632
633 out:
634 /* Set autoneg_advertised value based on input link speed */
635 hw->phy.autoneg_advertised = 0;
636
637 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
638 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
639
640 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
641 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
642
643 return status;
644 }
645
646 /**
647 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
648 * @hw: pointer to hardware structure
649 * @speed: new link speed
650 * @autoneg: true if autonegotiation enabled
651 * @autoneg_wait_to_complete: true when waiting for completion is needed
652 *
653 * Implements the Intel SmartSpeed algorithm.
654 **/
655 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
656 ixgbe_link_speed speed, bool autoneg,
657 bool autoneg_wait_to_complete)
658 {
659 s32 status = 0;
660 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
661 s32 i, j;
662 bool link_up = false;
663 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
664
665 /* Set autoneg_advertised value based on input link speed */
666 hw->phy.autoneg_advertised = 0;
667
668 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
669 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
670
671 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
672 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
673
674 if (speed & IXGBE_LINK_SPEED_100_FULL)
675 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
676
677 /*
678 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
679 * autoneg advertisement if link is unable to be established at the
680 * highest negotiated rate. This can sometimes happen due to integrity
681 * issues with the physical media connection.
682 */
683
684 /* First, try to get link with full advertisement */
685 hw->phy.smart_speed_active = false;
686 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
687 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
688 autoneg_wait_to_complete);
689 if (status != 0)
690 goto out;
691
692 /*
693 * Wait for the controller to acquire link. Per IEEE 802.3ap,
694 * Section 73.10.2, we may have to wait up to 500ms if KR is
695 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
696 * Table 9 in the AN MAS.
697 */
698 for (i = 0; i < 5; i++) {
699 mdelay(100);
700
701 /* If we have link, just jump out */
702 status = hw->mac.ops.check_link(hw, &link_speed,
703 &link_up, false);
704 if (status != 0)
705 goto out;
706
707 if (link_up)
708 goto out;
709 }
710 }
711
712 /*
713 * We didn't get link. If we advertised KR plus one of KX4/KX
714 * (or BX4/BX), then disable KR and try again.
715 */
716 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
717 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
718 goto out;
719
720 /* Turn SmartSpeed on to disable KR support */
721 hw->phy.smart_speed_active = true;
722 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
723 autoneg_wait_to_complete);
724 if (status != 0)
725 goto out;
726
727 /*
728 * Wait for the controller to acquire link. 600ms will allow for
729 * the AN link_fail_inhibit_timer as well for multiple cycles of
730 * parallel detect, both 10g and 1g. This allows for the maximum
731 * connect attempts as defined in the AN MAS table 73-7.
732 */
733 for (i = 0; i < 6; i++) {
734 mdelay(100);
735
736 /* If we have link, just jump out */
737 status = hw->mac.ops.check_link(hw, &link_speed,
738 &link_up, false);
739 if (status != 0)
740 goto out;
741
742 if (link_up)
743 goto out;
744 }
745
746 /* We didn't get link. Turn SmartSpeed back off. */
747 hw->phy.smart_speed_active = false;
748 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
749 autoneg_wait_to_complete);
750
751 out:
752 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
753 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
754 "the maximum advertised\n");
755 return status;
756 }
757
758 /**
759 * ixgbe_setup_mac_link_82599 - Set MAC link speed
760 * @hw: pointer to hardware structure
761 * @speed: new link speed
762 * @autoneg: true if autonegotiation enabled
763 * @autoneg_wait_to_complete: true when waiting for completion is needed
764 *
765 * Set the link speed in the AUTOC register and restarts link.
766 **/
767 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
768 ixgbe_link_speed speed, bool autoneg,
769 bool autoneg_wait_to_complete)
770 {
771 s32 status = 0;
772 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
773 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
774 u32 start_autoc = autoc;
775 u32 orig_autoc = 0;
776 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
777 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
778 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
779 u32 links_reg;
780 u32 i;
781 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
782
783 /* Check to see if speed passed in is supported. */
784 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
785 if (status != 0)
786 goto out;
787
788 speed &= link_capabilities;
789
790 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
791 status = IXGBE_ERR_LINK_SETUP;
792 goto out;
793 }
794
795 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
796 if (hw->mac.orig_link_settings_stored)
797 orig_autoc = hw->mac.orig_autoc;
798 else
799 orig_autoc = autoc;
800
801 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
802 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
803 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
804 /* Set KX4/KX/KR support according to speed requested */
805 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
806 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
807 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
808 autoc |= IXGBE_AUTOC_KX4_SUPP;
809 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
810 (hw->phy.smart_speed_active == false))
811 autoc |= IXGBE_AUTOC_KR_SUPP;
812 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
813 autoc |= IXGBE_AUTOC_KX_SUPP;
814 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
815 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
816 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
817 /* Switch from 1G SFI to 10G SFI if requested */
818 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
819 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
820 autoc &= ~IXGBE_AUTOC_LMS_MASK;
821 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
822 }
823 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
824 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
825 /* Switch from 10G SFI to 1G SFI if requested */
826 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
827 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
828 autoc &= ~IXGBE_AUTOC_LMS_MASK;
829 if (autoneg)
830 autoc |= IXGBE_AUTOC_LMS_1G_AN;
831 else
832 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
833 }
834 }
835
836 if (autoc != start_autoc) {
837 /* Restart link */
838 autoc |= IXGBE_AUTOC_AN_RESTART;
839 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
840
841 /* Only poll for autoneg to complete if specified to do so */
842 if (autoneg_wait_to_complete) {
843 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
844 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
845 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
846 links_reg = 0; /*Just in case Autoneg time=0*/
847 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
848 links_reg =
849 IXGBE_READ_REG(hw, IXGBE_LINKS);
850 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
851 break;
852 msleep(100);
853 }
854 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
855 status =
856 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
857 hw_dbg(hw, "Autoneg did not "
858 "complete.\n");
859 }
860 }
861 }
862
863 /* Add delay to filter out noises during initial link setup */
864 msleep(50);
865 }
866
867 out:
868 return status;
869 }
870
871 /**
872 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
873 * @hw: pointer to hardware structure
874 * @speed: new link speed
875 * @autoneg: true if autonegotiation enabled
876 * @autoneg_wait_to_complete: true if waiting is needed to complete
877 *
878 * Restarts link on PHY and MAC based on settings passed in.
879 **/
880 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
881 ixgbe_link_speed speed,
882 bool autoneg,
883 bool autoneg_wait_to_complete)
884 {
885 s32 status;
886
887 /* Setup the PHY according to input speed */
888 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
889 autoneg_wait_to_complete);
890 /* Set up MAC */
891 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
892
893 return status;
894 }
895
896 /**
897 * ixgbe_reset_hw_82599 - Perform hardware reset
898 * @hw: pointer to hardware structure
899 *
900 * Resets the hardware by resetting the transmit and receive units, masks
901 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
902 * reset.
903 **/
904 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
905 {
906 s32 status = 0;
907 u32 ctrl;
908 u32 i;
909 u32 autoc;
910 u32 autoc2;
911
912 /* Call adapter stop to disable tx/rx and clear interrupts */
913 hw->mac.ops.stop_adapter(hw);
914
915 /* PHY ops must be identified and initialized prior to reset */
916
917 /* Identify PHY and related function pointers */
918 status = hw->phy.ops.init(hw);
919
920 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
921 goto reset_hw_out;
922
923 /* Setup SFP module if there is one present. */
924 if (hw->phy.sfp_setup_needed) {
925 status = hw->mac.ops.setup_sfp(hw);
926 hw->phy.sfp_setup_needed = false;
927 }
928
929 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
930 goto reset_hw_out;
931
932 /* Reset PHY */
933 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
934 hw->phy.ops.reset(hw);
935
936 /*
937 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
938 * access and verify no pending requests before reset
939 */
940 ixgbe_disable_pcie_master(hw);
941
942 mac_reset_top:
943 /*
944 * Issue global reset to the MAC. This needs to be a SW reset.
945 * If link reset is used, it might reset the MAC when mng is using it
946 */
947 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
948 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
949 IXGBE_WRITE_FLUSH(hw);
950
951 /* Poll for reset bit to self-clear indicating reset is complete */
952 for (i = 0; i < 10; i++) {
953 udelay(1);
954 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
955 if (!(ctrl & IXGBE_CTRL_RST))
956 break;
957 }
958 if (ctrl & IXGBE_CTRL_RST) {
959 status = IXGBE_ERR_RESET_FAILED;
960 hw_dbg(hw, "Reset polling failed to complete.\n");
961 }
962
963 /*
964 * Double resets are required for recovery from certain error
965 * conditions. Between resets, it is necessary to stall to allow time
966 * for any pending HW events to complete. We use 1usec since that is
967 * what is needed for ixgbe_disable_pcie_master(). The second reset
968 * then clears out any effects of those events.
969 */
970 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
971 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
972 udelay(1);
973 goto mac_reset_top;
974 }
975
976 msleep(50);
977
978 /*
979 * Store the original AUTOC/AUTOC2 values if they have not been
980 * stored off yet. Otherwise restore the stored original
981 * values since the reset operation sets back to defaults.
982 */
983 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
984 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
985 if (hw->mac.orig_link_settings_stored == false) {
986 hw->mac.orig_autoc = autoc;
987 hw->mac.orig_autoc2 = autoc2;
988 hw->mac.orig_link_settings_stored = true;
989 } else {
990 if (autoc != hw->mac.orig_autoc)
991 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
992 IXGBE_AUTOC_AN_RESTART));
993
994 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
995 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
996 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
997 autoc2 |= (hw->mac.orig_autoc2 &
998 IXGBE_AUTOC2_UPPER_MASK);
999 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1000 }
1001 }
1002
1003 /* Store the permanent mac address */
1004 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1005
1006 /*
1007 * Store MAC address from RAR0, clear receive address registers, and
1008 * clear the multicast table. Also reset num_rar_entries to 128,
1009 * since we modify this value when programming the SAN MAC address.
1010 */
1011 hw->mac.num_rar_entries = 128;
1012 hw->mac.ops.init_rx_addrs(hw);
1013
1014 /* Store the permanent SAN mac address */
1015 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1016
1017 /* Add the SAN MAC address to the RAR only if it's a valid address */
1018 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1019 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1020 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1021
1022 /* Reserve the last RAR for the SAN MAC address */
1023 hw->mac.num_rar_entries--;
1024 }
1025
1026 /* Store the alternative WWNN/WWPN prefix */
1027 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1028 &hw->mac.wwpn_prefix);
1029
1030 reset_hw_out:
1031 return status;
1032 }
1033
1034 /**
1035 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1036 * @hw: pointer to hardware structure
1037 **/
1038 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1039 {
1040 int i;
1041 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1042 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1043
1044 /*
1045 * Before starting reinitialization process,
1046 * FDIRCMD.CMD must be zero.
1047 */
1048 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1049 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1050 IXGBE_FDIRCMD_CMD_MASK))
1051 break;
1052 udelay(10);
1053 }
1054 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1055 hw_dbg(hw, "Flow Director previous command isn't complete, "
1056 "aborting table re-initialization.\n");
1057 return IXGBE_ERR_FDIR_REINIT_FAILED;
1058 }
1059
1060 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1061 IXGBE_WRITE_FLUSH(hw);
1062 /*
1063 * 82599 adapters flow director init flow cannot be restarted,
1064 * Workaround 82599 silicon errata by performing the following steps
1065 * before re-writing the FDIRCTRL control register with the same value.
1066 * - write 1 to bit 8 of FDIRCMD register &
1067 * - write 0 to bit 8 of FDIRCMD register
1068 */
1069 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1070 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1071 IXGBE_FDIRCMD_CLEARHT));
1072 IXGBE_WRITE_FLUSH(hw);
1073 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1074 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1075 ~IXGBE_FDIRCMD_CLEARHT));
1076 IXGBE_WRITE_FLUSH(hw);
1077 /*
1078 * Clear FDIR Hash register to clear any leftover hashes
1079 * waiting to be programmed.
1080 */
1081 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1082 IXGBE_WRITE_FLUSH(hw);
1083
1084 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1085 IXGBE_WRITE_FLUSH(hw);
1086
1087 /* Poll init-done after we write FDIRCTRL register */
1088 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1089 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1090 IXGBE_FDIRCTRL_INIT_DONE)
1091 break;
1092 udelay(10);
1093 }
1094 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1095 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1096 return IXGBE_ERR_FDIR_REINIT_FAILED;
1097 }
1098
1099 /* Clear FDIR statistics registers (read to clear) */
1100 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1101 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1102 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1103 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1104 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1105
1106 return 0;
1107 }
1108
1109 /**
1110 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1111 * @hw: pointer to hardware structure
1112 * @pballoc: which mode to allocate filters with
1113 **/
1114 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1115 {
1116 u32 fdirctrl = 0;
1117 u32 pbsize;
1118 int i;
1119
1120 /*
1121 * Before enabling Flow Director, the Rx Packet Buffer size
1122 * must be reduced. The new value is the current size minus
1123 * flow director memory usage size.
1124 */
1125 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1126 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1127 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1128
1129 /*
1130 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1131 * initialized to zero for non DCB mode otherwise actual total RX PB
1132 * would be bigger than programmed and filter space would run into
1133 * the PB 0 region.
1134 */
1135 for (i = 1; i < 8; i++)
1136 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1137
1138 /* Send interrupt when 64 filters are left */
1139 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1140
1141 /* Set the maximum length per hash bucket to 0xA filters */
1142 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1143
1144 switch (pballoc) {
1145 case IXGBE_FDIR_PBALLOC_64K:
1146 /* 8k - 1 signature filters */
1147 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1148 break;
1149 case IXGBE_FDIR_PBALLOC_128K:
1150 /* 16k - 1 signature filters */
1151 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1152 break;
1153 case IXGBE_FDIR_PBALLOC_256K:
1154 /* 32k - 1 signature filters */
1155 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1156 break;
1157 default:
1158 /* bad value */
1159 return IXGBE_ERR_CONFIG;
1160 };
1161
1162 /* Move the flexible bytes to use the ethertype - shift 6 words */
1163 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1164
1165
1166 /* Prime the keys for hashing */
1167 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1168 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1169
1170 /*
1171 * Poll init-done after we write the register. Estimated times:
1172 * 10G: PBALLOC = 11b, timing is 60us
1173 * 1G: PBALLOC = 11b, timing is 600us
1174 * 100M: PBALLOC = 11b, timing is 6ms
1175 *
1176 * Multiple these timings by 4 if under full Rx load
1177 *
1178 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1179 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1180 * this might not finish in our poll time, but we can live with that
1181 * for now.
1182 */
1183 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1184 IXGBE_WRITE_FLUSH(hw);
1185 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1186 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1187 IXGBE_FDIRCTRL_INIT_DONE)
1188 break;
1189 usleep_range(1000, 2000);
1190 }
1191 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1192 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1193
1194 return 0;
1195 }
1196
1197 /**
1198 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1199 * @hw: pointer to hardware structure
1200 * @pballoc: which mode to allocate filters with
1201 **/
1202 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1203 {
1204 u32 fdirctrl = 0;
1205 u32 pbsize;
1206 int i;
1207
1208 /*
1209 * Before enabling Flow Director, the Rx Packet Buffer size
1210 * must be reduced. The new value is the current size minus
1211 * flow director memory usage size.
1212 */
1213 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1214 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1215 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1216
1217 /*
1218 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1219 * initialized to zero for non DCB mode otherwise actual total RX PB
1220 * would be bigger than programmed and filter space would run into
1221 * the PB 0 region.
1222 */
1223 for (i = 1; i < 8; i++)
1224 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1225
1226 /* Send interrupt when 64 filters are left */
1227 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1228
1229 /* Initialize the drop queue to Rx queue 127 */
1230 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1231
1232 switch (pballoc) {
1233 case IXGBE_FDIR_PBALLOC_64K:
1234 /* 2k - 1 perfect filters */
1235 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1236 break;
1237 case IXGBE_FDIR_PBALLOC_128K:
1238 /* 4k - 1 perfect filters */
1239 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1240 break;
1241 case IXGBE_FDIR_PBALLOC_256K:
1242 /* 8k - 1 perfect filters */
1243 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1244 break;
1245 default:
1246 /* bad value */
1247 return IXGBE_ERR_CONFIG;
1248 };
1249
1250 /* Turn perfect match filtering on */
1251 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1252 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1253
1254 /* Move the flexible bytes to use the ethertype - shift 6 words */
1255 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1256
1257 /* Prime the keys for hashing */
1258 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1259 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1260
1261 /*
1262 * Poll init-done after we write the register. Estimated times:
1263 * 10G: PBALLOC = 11b, timing is 60us
1264 * 1G: PBALLOC = 11b, timing is 600us
1265 * 100M: PBALLOC = 11b, timing is 6ms
1266 *
1267 * Multiple these timings by 4 if under full Rx load
1268 *
1269 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1270 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1271 * this might not finish in our poll time, but we can live with that
1272 * for now.
1273 */
1274
1275 /* Set the maximum length per hash bucket to 0xA filters */
1276 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1277
1278 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1279 IXGBE_WRITE_FLUSH(hw);
1280 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1281 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1282 IXGBE_FDIRCTRL_INIT_DONE)
1283 break;
1284 usleep_range(1000, 2000);
1285 }
1286 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1287 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1288
1289 return 0;
1290 }
1291
1292
1293 /**
1294 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1295 * @stream: input bitstream to compute the hash on
1296 * @key: 32-bit hash key
1297 **/
1298 static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
1299 u32 key)
1300 {
1301 /*
1302 * The algorithm is as follows:
1303 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1304 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1305 * and A[n] x B[n] is bitwise AND between same length strings
1306 *
1307 * K[n] is 16 bits, defined as:
1308 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1309 * for n modulo 32 < 15, K[n] =
1310 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1311 *
1312 * S[n] is 16 bits, defined as:
1313 * for n >= 15, S[n] = S[n:n - 15]
1314 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1315 *
1316 * To simplify for programming, the algorithm is implemented
1317 * in software this way:
1318 *
1319 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1320 *
1321 * for (i = 0; i < 352; i+=32)
1322 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1323 *
1324 * lo_hash_dword[15:0] ^= Stream[15:0];
1325 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1326 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
1327 *
1328 * hi_hash_dword[31:0] ^= Stream[351:320];
1329 *
1330 * if(key[0])
1331 * hash[15:0] ^= Stream[15:0];
1332 *
1333 * for (i = 0; i < 16; i++) {
1334 * if (key[i])
1335 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1336 * if (key[i + 16])
1337 * hash[15:0] ^= hi_hash_dword[(i+15):i];
1338 * }
1339 *
1340 */
1341 __be32 common_hash_dword = 0;
1342 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1343 u32 hash_result = 0;
1344 u8 i;
1345
1346 /* record the flow_vm_vlan bits as they are a key part to the hash */
1347 flow_vm_vlan = ntohl(atr_input->dword_stream[0]);
1348
1349 /* generate common hash dword */
1350 for (i = 10; i; i -= 2)
1351 common_hash_dword ^= atr_input->dword_stream[i] ^
1352 atr_input->dword_stream[i - 1];
1353
1354 hi_hash_dword = ntohl(common_hash_dword);
1355
1356 /* low dword is word swapped version of common */
1357 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1358
1359 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1360 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1361
1362 /* Process bits 0 and 16 */
1363 if (key & 0x0001) hash_result ^= lo_hash_dword;
1364 if (key & 0x00010000) hash_result ^= hi_hash_dword;
1365
1366 /*
1367 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1368 * delay this because bit 0 of the stream should not be processed
1369 * so we do not add the vlan until after bit 0 was processed
1370 */
1371 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1372
1373
1374 /* process the remaining 30 bits in the key 2 bits at a time */
1375 for (i = 15; i; i-- ) {
1376 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
1377 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
1378 }
1379
1380 return hash_result & IXGBE_ATR_HASH_MASK;
1381 }
1382
1383 /*
1384 * These defines allow us to quickly generate all of the necessary instructions
1385 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1386 * for values 0 through 15
1387 */
1388 #define IXGBE_ATR_COMMON_HASH_KEY \
1389 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1390 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1391 do { \
1392 u32 n = (_n); \
1393 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1394 common_hash ^= lo_hash_dword >> n; \
1395 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1396 bucket_hash ^= lo_hash_dword >> n; \
1397 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1398 sig_hash ^= lo_hash_dword << (16 - n); \
1399 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1400 common_hash ^= hi_hash_dword >> n; \
1401 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1402 bucket_hash ^= hi_hash_dword >> n; \
1403 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1404 sig_hash ^= hi_hash_dword << (16 - n); \
1405 } while (0);
1406
1407 /**
1408 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1409 * @stream: input bitstream to compute the hash on
1410 *
1411 * This function is almost identical to the function above but contains
1412 * several optomizations such as unwinding all of the loops, letting the
1413 * compiler work out all of the conditional ifs since the keys are static
1414 * defines, and computing two keys at once since the hashed dword stream
1415 * will be the same for both keys.
1416 **/
1417 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1418 union ixgbe_atr_hash_dword common)
1419 {
1420 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1421 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1422
1423 /* record the flow_vm_vlan bits as they are a key part to the hash */
1424 flow_vm_vlan = ntohl(input.dword);
1425
1426 /* generate common hash dword */
1427 hi_hash_dword = ntohl(common.dword);
1428
1429 /* low dword is word swapped version of common */
1430 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1431
1432 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1433 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1434
1435 /* Process bits 0 and 16 */
1436 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1437
1438 /*
1439 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1440 * delay this because bit 0 of the stream should not be processed
1441 * so we do not add the vlan until after bit 0 was processed
1442 */
1443 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1444
1445 /* Process remaining 30 bit of the key */
1446 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1447 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1448 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1449 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1450 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1451 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1452 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1453 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1454 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1455 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1456 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1457 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1458 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1459 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1460 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1461
1462 /* combine common_hash result with signature and bucket hashes */
1463 bucket_hash ^= common_hash;
1464 bucket_hash &= IXGBE_ATR_HASH_MASK;
1465
1466 sig_hash ^= common_hash << 16;
1467 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1468
1469 /* return completed signature hash */
1470 return sig_hash ^ bucket_hash;
1471 }
1472
1473 /**
1474 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1475 * @hw: pointer to hardware structure
1476 * @input: unique input dword
1477 * @common: compressed common input dword
1478 * @queue: queue index to direct traffic to
1479 **/
1480 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1481 union ixgbe_atr_hash_dword input,
1482 union ixgbe_atr_hash_dword common,
1483 u8 queue)
1484 {
1485 u64 fdirhashcmd;
1486 u32 fdircmd;
1487
1488 /*
1489 * Get the flow_type in order to program FDIRCMD properly
1490 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1491 */
1492 switch (input.formatted.flow_type) {
1493 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1494 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1495 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1496 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1497 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1498 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1499 break;
1500 default:
1501 hw_dbg(hw, " Error on flow type input\n");
1502 return IXGBE_ERR_CONFIG;
1503 }
1504
1505 /* configure FDIRCMD register */
1506 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1507 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1508 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1509 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1510
1511 /*
1512 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1513 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1514 */
1515 fdirhashcmd = (u64)fdircmd << 32;
1516 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1517
1518 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1519
1520 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1521
1522 return 0;
1523 }
1524
1525 /**
1526 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1527 * @input_mask: mask to be bit swapped
1528 *
1529 * The source and destination port masks for flow director are bit swapped
1530 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1531 * generate a correctly swapped value we need to bit swap the mask and that
1532 * is what is accomplished by this function.
1533 **/
1534 static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
1535 {
1536 u32 mask = ntohs(input_masks->dst_port_mask);
1537 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1538 mask |= ntohs(input_masks->src_port_mask);
1539 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1540 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1541 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1542 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1543 }
1544
1545 /*
1546 * These two macros are meant to address the fact that we have registers
1547 * that are either all or in part big-endian. As a result on big-endian
1548 * systems we will end up byte swapping the value to little-endian before
1549 * it is byte swapped again and written to the hardware in the original
1550 * big-endian format.
1551 */
1552 #define IXGBE_STORE_AS_BE32(_value) \
1553 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1554 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1555
1556 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1557 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1558
1559 #define IXGBE_STORE_AS_BE16(_value) \
1560 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1561
1562 /**
1563 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1564 * @hw: pointer to hardware structure
1565 * @input: input bitstream
1566 * @input_masks: bitwise masks for relevant fields
1567 * @soft_id: software index into the silicon hash tables for filter storage
1568 * @queue: queue index to direct traffic to
1569 *
1570 * Note that the caller to this function must lock before calling, since the
1571 * hardware writes must be protected from one another.
1572 **/
1573 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1574 union ixgbe_atr_input *input,
1575 struct ixgbe_atr_input_masks *input_masks,
1576 u16 soft_id, u8 queue)
1577 {
1578 u32 fdirhash;
1579 u32 fdircmd;
1580 u32 fdirport, fdirtcpm;
1581 u32 fdirvlan;
1582 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1583 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
1584 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
1585
1586 /*
1587 * Check flow_type formatting, and bail out before we touch the hardware
1588 * if there's a configuration issue
1589 */
1590 switch (input->formatted.flow_type) {
1591 case IXGBE_ATR_FLOW_TYPE_IPV4:
1592 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1593 fdirm |= IXGBE_FDIRM_L4P;
1594 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1595 if (input_masks->dst_port_mask || input_masks->src_port_mask) {
1596 hw_dbg(hw, " Error on src/dst port mask\n");
1597 return IXGBE_ERR_CONFIG;
1598 }
1599 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1600 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1601 break;
1602 default:
1603 hw_dbg(hw, " Error on flow type input\n");
1604 return IXGBE_ERR_CONFIG;
1605 }
1606
1607 /*
1608 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1609 * are zero, then assume a full mask for that field. Also assume that
1610 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1611 * cannot be masked out in this implementation.
1612 *
1613 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1614 * point in time.
1615 */
1616
1617 /* Program FDIRM */
1618 switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) {
1619 case 0xEFFF:
1620 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1621 fdirm &= ~IXGBE_FDIRM_VLANID;
1622 case 0xE000:
1623 /* Unmask VLAN prio - bit 1 */
1624 fdirm &= ~IXGBE_FDIRM_VLANP;
1625 break;
1626 case 0x0FFF:
1627 /* Unmask VLAN ID - bit 0 */
1628 fdirm &= ~IXGBE_FDIRM_VLANID;
1629 break;
1630 case 0x0000:
1631 /* do nothing, vlans already masked */
1632 break;
1633 default:
1634 hw_dbg(hw, " Error on VLAN mask\n");
1635 return IXGBE_ERR_CONFIG;
1636 }
1637
1638 if (input_masks->flex_mask & 0xFFFF) {
1639 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
1640 hw_dbg(hw, " Error on flexible byte mask\n");
1641 return IXGBE_ERR_CONFIG;
1642 }
1643 /* Unmask Flex Bytes - bit 4 */
1644 fdirm &= ~IXGBE_FDIRM_FLEX;
1645 }
1646
1647 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1648 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1649
1650 /* store the TCP/UDP port masks, bit reversed from port layout */
1651 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
1652
1653 /* write both the same so that UDP and TCP use the same mask */
1654 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1655 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1656
1657 /* store source and destination IP masks (big-enian) */
1658 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1659 ~input_masks->src_ip_mask[0]);
1660 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1661 ~input_masks->dst_ip_mask[0]);
1662
1663 /* Apply masks to input data */
1664 input->formatted.vlan_id &= input_masks->vlan_id_mask;
1665 input->formatted.flex_bytes &= input_masks->flex_mask;
1666 input->formatted.src_port &= input_masks->src_port_mask;
1667 input->formatted.dst_port &= input_masks->dst_port_mask;
1668 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
1669 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
1670
1671 /* record vlan (little-endian) and flex_bytes(big-endian) */
1672 fdirvlan =
1673 IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes));
1674 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1675 fdirvlan |= ntohs(input->formatted.vlan_id);
1676 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1677
1678 /* record source and destination port (little-endian)*/
1679 fdirport = ntohs(input->formatted.dst_port);
1680 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1681 fdirport |= ntohs(input->formatted.src_port);
1682 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1683
1684 /* record the first 32 bits of the destination address (big-endian) */
1685 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1686
1687 /* record the source address (big-endian) */
1688 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1689
1690 /* configure FDIRCMD register */
1691 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1692 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1693 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1694 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1695
1696 /* we only want the bucket hash so drop the upper 16 bits */
1697 fdirhash = ixgbe_atr_compute_hash_82599(input,
1698 IXGBE_ATR_BUCKET_HASH_KEY);
1699 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1700
1701 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1702 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1703
1704 return 0;
1705 }
1706
1707 /**
1708 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1709 * @hw: pointer to hardware structure
1710 * @reg: analog register to read
1711 * @val: read value
1712 *
1713 * Performs read operation to Omer analog register specified.
1714 **/
1715 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1716 {
1717 u32 core_ctl;
1718
1719 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1720 (reg << 8));
1721 IXGBE_WRITE_FLUSH(hw);
1722 udelay(10);
1723 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1724 *val = (u8)core_ctl;
1725
1726 return 0;
1727 }
1728
1729 /**
1730 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1731 * @hw: pointer to hardware structure
1732 * @reg: atlas register to write
1733 * @val: value to write
1734 *
1735 * Performs write operation to Omer analog register specified.
1736 **/
1737 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1738 {
1739 u32 core_ctl;
1740
1741 core_ctl = (reg << 8) | val;
1742 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1743 IXGBE_WRITE_FLUSH(hw);
1744 udelay(10);
1745
1746 return 0;
1747 }
1748
1749 /**
1750 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1751 * @hw: pointer to hardware structure
1752 *
1753 * Starts the hardware using the generic start_hw function
1754 * and the generation start_hw function.
1755 * Then performs revision-specific operations, if any.
1756 **/
1757 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1758 {
1759 s32 ret_val = 0;
1760
1761 ret_val = ixgbe_start_hw_generic(hw);
1762 if (ret_val != 0)
1763 goto out;
1764
1765 ret_val = ixgbe_start_hw_gen2(hw);
1766 if (ret_val != 0)
1767 goto out;
1768
1769 /* We need to run link autotry after the driver loads */
1770 hw->mac.autotry_restart = true;
1771 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1772
1773 if (ret_val == 0)
1774 ret_val = ixgbe_verify_fw_version_82599(hw);
1775 out:
1776 return ret_val;
1777 }
1778
1779 /**
1780 * ixgbe_identify_phy_82599 - Get physical layer module
1781 * @hw: pointer to hardware structure
1782 *
1783 * Determines the physical layer module found on the current adapter.
1784 * If PHY already detected, maintains current PHY type in hw struct,
1785 * otherwise executes the PHY detection routine.
1786 **/
1787 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1788 {
1789 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1790
1791 /* Detect PHY if not unknown - returns success if already detected. */
1792 status = ixgbe_identify_phy_generic(hw);
1793 if (status != 0) {
1794 /* 82599 10GBASE-T requires an external PHY */
1795 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1796 goto out;
1797 else
1798 status = ixgbe_identify_sfp_module_generic(hw);
1799 }
1800
1801 /* Set PHY type none if no PHY detected */
1802 if (hw->phy.type == ixgbe_phy_unknown) {
1803 hw->phy.type = ixgbe_phy_none;
1804 status = 0;
1805 }
1806
1807 /* Return error if SFP module has been detected but is not supported */
1808 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1809 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1810
1811 out:
1812 return status;
1813 }
1814
1815 /**
1816 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1817 * @hw: pointer to hardware structure
1818 *
1819 * Determines physical layer capabilities of the current configuration.
1820 **/
1821 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1822 {
1823 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1824 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1825 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1826 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1827 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1828 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1829 u16 ext_ability = 0;
1830 u8 comp_codes_10g = 0;
1831 u8 comp_codes_1g = 0;
1832
1833 hw->phy.ops.identify(hw);
1834
1835 switch (hw->phy.type) {
1836 case ixgbe_phy_tn:
1837 case ixgbe_phy_aq:
1838 case ixgbe_phy_cu_unknown:
1839 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1840 &ext_ability);
1841 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1842 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1843 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1844 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1845 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1846 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1847 goto out;
1848 default:
1849 break;
1850 }
1851
1852 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1853 case IXGBE_AUTOC_LMS_1G_AN:
1854 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1855 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1856 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1857 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1858 goto out;
1859 } else
1860 /* SFI mode so read SFP module */
1861 goto sfp_check;
1862 break;
1863 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1864 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1865 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1866 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1867 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1868 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1869 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1870 goto out;
1871 break;
1872 case IXGBE_AUTOC_LMS_10G_SERIAL:
1873 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1874 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1875 goto out;
1876 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1877 goto sfp_check;
1878 break;
1879 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1880 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1881 if (autoc & IXGBE_AUTOC_KX_SUPP)
1882 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1883 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1884 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1885 if (autoc & IXGBE_AUTOC_KR_SUPP)
1886 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1887 goto out;
1888 break;
1889 default:
1890 goto out;
1891 break;
1892 }
1893
1894 sfp_check:
1895 /* SFP check must be done last since DA modules are sometimes used to
1896 * test KR mode - we need to id KR mode correctly before SFP module.
1897 * Call identify_sfp because the pluggable module may have changed */
1898 hw->phy.ops.identify_sfp(hw);
1899 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1900 goto out;
1901
1902 switch (hw->phy.type) {
1903 case ixgbe_phy_sfp_passive_tyco:
1904 case ixgbe_phy_sfp_passive_unknown:
1905 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1906 break;
1907 case ixgbe_phy_sfp_ftl_active:
1908 case ixgbe_phy_sfp_active_unknown:
1909 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1910 break;
1911 case ixgbe_phy_sfp_avago:
1912 case ixgbe_phy_sfp_ftl:
1913 case ixgbe_phy_sfp_intel:
1914 case ixgbe_phy_sfp_unknown:
1915 hw->phy.ops.read_i2c_eeprom(hw,
1916 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1917 hw->phy.ops.read_i2c_eeprom(hw,
1918 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1919 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1920 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1921 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1922 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1923 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1924 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1925 break;
1926 default:
1927 break;
1928 }
1929
1930 out:
1931 return physical_layer;
1932 }
1933
1934 /**
1935 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1936 * @hw: pointer to hardware structure
1937 * @regval: register value to write to RXCTRL
1938 *
1939 * Enables the Rx DMA unit for 82599
1940 **/
1941 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1942 {
1943 #define IXGBE_MAX_SECRX_POLL 30
1944 int i;
1945 int secrxreg;
1946
1947 /*
1948 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1949 * If traffic is incoming before we enable the Rx unit, it could hang
1950 * the Rx DMA unit. Therefore, make sure the security engine is
1951 * completely disabled prior to enabling the Rx unit.
1952 */
1953 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1954 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1955 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1956 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1957 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1958 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1959 break;
1960 else
1961 /* Use interrupt-safe sleep just in case */
1962 udelay(10);
1963 }
1964
1965 /* For informational purposes only */
1966 if (i >= IXGBE_MAX_SECRX_POLL)
1967 hw_dbg(hw, "Rx unit being enabled before security "
1968 "path fully disabled. Continuing with init.\n");
1969
1970 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1971 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1972 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1973 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1974 IXGBE_WRITE_FLUSH(hw);
1975
1976 return 0;
1977 }
1978
1979 /**
1980 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1981 * @hw: pointer to hardware structure
1982 *
1983 * Verifies that installed the firmware version is 0.6 or higher
1984 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1985 *
1986 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1987 * if the FW version is not supported.
1988 **/
1989 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1990 {
1991 s32 status = IXGBE_ERR_EEPROM_VERSION;
1992 u16 fw_offset, fw_ptp_cfg_offset;
1993 u16 fw_version = 0;
1994
1995 /* firmware check is only necessary for SFI devices */
1996 if (hw->phy.media_type != ixgbe_media_type_fiber) {
1997 status = 0;
1998 goto fw_version_out;
1999 }
2000
2001 /* get the offset to the Firmware Module block */
2002 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2003
2004 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2005 goto fw_version_out;
2006
2007 /* get the offset to the Pass Through Patch Configuration block */
2008 hw->eeprom.ops.read(hw, (fw_offset +
2009 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2010 &fw_ptp_cfg_offset);
2011
2012 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2013 goto fw_version_out;
2014
2015 /* get the firmware version */
2016 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2017 IXGBE_FW_PATCH_VERSION_4),
2018 &fw_version);
2019
2020 if (fw_version > 0x5)
2021 status = 0;
2022
2023 fw_version_out:
2024 return status;
2025 }
2026
2027 /**
2028 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2029 * @hw: pointer to hardware structure
2030 *
2031 * Returns true if the LESM FW module is present and enabled. Otherwise
2032 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2033 **/
2034 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2035 {
2036 bool lesm_enabled = false;
2037 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2038 s32 status;
2039
2040 /* get the offset to the Firmware Module block */
2041 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2042
2043 if ((status != 0) ||
2044 (fw_offset == 0) || (fw_offset == 0xFFFF))
2045 goto out;
2046
2047 /* get the offset to the LESM Parameters block */
2048 status = hw->eeprom.ops.read(hw, (fw_offset +
2049 IXGBE_FW_LESM_PARAMETERS_PTR),
2050 &fw_lesm_param_offset);
2051
2052 if ((status != 0) ||
2053 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2054 goto out;
2055
2056 /* get the lesm state word */
2057 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2058 IXGBE_FW_LESM_STATE_1),
2059 &fw_lesm_state);
2060
2061 if ((status == 0) &&
2062 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2063 lesm_enabled = true;
2064
2065 out:
2066 return lesm_enabled;
2067 }
2068
2069 /**
2070 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2071 * fastest available method
2072 *
2073 * @hw: pointer to hardware structure
2074 * @offset: offset of word in EEPROM to read
2075 * @words: number of words
2076 * @data: word(s) read from the EEPROM
2077 *
2078 * Retrieves 16 bit word(s) read from EEPROM
2079 **/
2080 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2081 u16 words, u16 *data)
2082 {
2083 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2084 s32 ret_val = IXGBE_ERR_CONFIG;
2085
2086 /*
2087 * If EEPROM is detected and can be addressed using 14 bits,
2088 * use EERD otherwise use bit bang
2089 */
2090 if ((eeprom->type == ixgbe_eeprom_spi) &&
2091 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2092 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2093 data);
2094 else
2095 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2096 words,
2097 data);
2098
2099 return ret_val;
2100 }
2101
2102 /**
2103 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2104 * fastest available method
2105 *
2106 * @hw: pointer to hardware structure
2107 * @offset: offset of word in the EEPROM to read
2108 * @data: word read from the EEPROM
2109 *
2110 * Reads a 16 bit word from the EEPROM
2111 **/
2112 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2113 u16 offset, u16 *data)
2114 {
2115 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2116 s32 ret_val = IXGBE_ERR_CONFIG;
2117
2118 /*
2119 * If EEPROM is detected and can be addressed using 14 bits,
2120 * use EERD otherwise use bit bang
2121 */
2122 if ((eeprom->type == ixgbe_eeprom_spi) &&
2123 (offset <= IXGBE_EERD_MAX_ADDR))
2124 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2125 else
2126 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2127
2128 return ret_val;
2129 }
2130
2131 static struct ixgbe_mac_operations mac_ops_82599 = {
2132 .init_hw = &ixgbe_init_hw_generic,
2133 .reset_hw = &ixgbe_reset_hw_82599,
2134 .start_hw = &ixgbe_start_hw_82599,
2135 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2136 .get_media_type = &ixgbe_get_media_type_82599,
2137 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2138 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2139 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2140 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2141 .get_device_caps = &ixgbe_get_device_caps_generic,
2142 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2143 .stop_adapter = &ixgbe_stop_adapter_generic,
2144 .get_bus_info = &ixgbe_get_bus_info_generic,
2145 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2146 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2147 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2148 .setup_link = &ixgbe_setup_mac_link_82599,
2149 .check_link = &ixgbe_check_mac_link_generic,
2150 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2151 .led_on = &ixgbe_led_on_generic,
2152 .led_off = &ixgbe_led_off_generic,
2153 .blink_led_start = &ixgbe_blink_led_start_generic,
2154 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2155 .set_rar = &ixgbe_set_rar_generic,
2156 .clear_rar = &ixgbe_clear_rar_generic,
2157 .set_vmdq = &ixgbe_set_vmdq_generic,
2158 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2159 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2160 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2161 .enable_mc = &ixgbe_enable_mc_generic,
2162 .disable_mc = &ixgbe_disable_mc_generic,
2163 .clear_vfta = &ixgbe_clear_vfta_generic,
2164 .set_vfta = &ixgbe_set_vfta_generic,
2165 .fc_enable = &ixgbe_fc_enable_generic,
2166 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2167 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2168 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2169 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2170 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2171 .release_swfw_sync = &ixgbe_release_swfw_sync,
2172
2173 };
2174
2175 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2176 .init_params = &ixgbe_init_eeprom_params_generic,
2177 .read = &ixgbe_read_eeprom_82599,
2178 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2179 .write = &ixgbe_write_eeprom_generic,
2180 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2181 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2182 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2183 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2184 };
2185
2186 static struct ixgbe_phy_operations phy_ops_82599 = {
2187 .identify = &ixgbe_identify_phy_82599,
2188 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2189 .init = &ixgbe_init_phy_ops_82599,
2190 .reset = &ixgbe_reset_phy_generic,
2191 .read_reg = &ixgbe_read_phy_reg_generic,
2192 .write_reg = &ixgbe_write_phy_reg_generic,
2193 .setup_link = &ixgbe_setup_phy_link_generic,
2194 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2195 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2196 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2197 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2198 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2199 .check_overtemp = &ixgbe_tn_check_overtemp,
2200 };
2201
2202 struct ixgbe_info ixgbe_82599_info = {
2203 .mac = ixgbe_mac_82599EB,
2204 .get_invariants = &ixgbe_get_invariants_82599,
2205 .mac_ops = &mac_ops_82599,
2206 .eeprom_ops = &eeprom_ops_82599,
2207 .phy_ops = &phy_ops_82599,
2208 .mbx_ops = &mbx_ops_generic,
2209 };