sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / net / ixgbe / ixgbe_fcoe.h
blob5a650a4ace66ef2e8575872ee5814b521fb58d5a
1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #ifndef _IXGBE_FCOE_H
29 #define _IXGBE_FCOE_H
31 #include <scsi/fc/fc_fs.h>
32 #include <scsi/fc/fc_fcoe.h>
34 /* shift bits within STAT fo FCSTAT */
35 #define IXGBE_RXDADV_FCSTAT_SHIFT 4
37 /* ddp user buffer */
38 #define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */
39 #define IXGBE_FCPTR_ALIGN 16
40 #define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t))
41 #define IXGBE_FCBUFF_4KB 0x0
42 #define IXGBE_FCBUFF_8KB 0x1
43 #define IXGBE_FCBUFF_16KB 0x2
44 #define IXGBE_FCBUFF_64KB 0x3
45 #define IXGBE_FCBUFF_MAX 65536 /* 64KB max */
46 #define IXGBE_FCBUFF_MIN 4096 /* 4KB min */
47 #define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */
49 /* Default traffic class to use for FCoE */
50 #define IXGBE_FCOE_DEFTC 3
52 /* fcerr */
53 #define IXGBE_FCERR_BADCRC 0x00100000
55 /* FCoE DDP for target mode */
56 #define __IXGBE_FCOE_TARGET 1
58 struct ixgbe_fcoe_ddp {
59 int len;
60 u32 err;
61 unsigned int sgc;
62 struct scatterlist *sgl;
63 dma_addr_t udp;
64 u64 *udl;
67 struct ixgbe_fcoe {
68 #ifdef CONFIG_IXGBE_DCB
69 u8 tc;
70 u8 up;
71 #endif
72 unsigned long mode;
73 atomic_t refcnt;
74 spinlock_t lock;
75 struct pci_pool *pool;
76 struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX];
77 unsigned char *extra_ddp_buffer;
78 dma_addr_t extra_ddp_buffer_dma;
81 #endif /* _IXGBE_FCOE_H */