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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / net / ixgbe / ixgbe_main.c
blob2dce3d0381881887d3adafed71c50bdb8e34bdc6
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54 #define MAJ 3
55 #define MIN 3
56 #define BUILD 8
57 #define KFIX 2
58 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
59 __stringify(BUILD) "-k" __stringify(KFIX)
60 const char ixgbe_driver_version[] = DRV_VERSION;
61 static const char ixgbe_copyright[] =
62 "Copyright (c) 1999-2011 Intel Corporation.";
63
64 static const struct ixgbe_info *ixgbe_info_tbl[] = {
65 [board_82598] = &ixgbe_82598_info,
66 [board_82599] = &ixgbe_82599_info,
67 [board_X540] = &ixgbe_X540_info,
68 };
69
70 /* ixgbe_pci_tbl - PCI Device ID Table
71 *
72 * Wildcard entries (PCI_ANY_ID) should come last
73 * Last entry must be all 0s
74 *
75 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
76 * Class, Class Mask, private data (not used) }
77 */
78 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
98 board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
100 board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
102 board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
104 board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
114 board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
116 board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
118 board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
120 board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
122 board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
124 board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
126 board_X540 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
128 board_82599 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
130 board_82599 },
131
132 /* required last entry */
133 {0, }
134 };
135 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
136
137 #ifdef CONFIG_IXGBE_DCA
138 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
139 void *p);
140 static struct notifier_block dca_notifier = {
141 .notifier_call = ixgbe_notify_dca,
142 .next = NULL,
143 .priority = 0
144 };
145 #endif
146
147 #ifdef CONFIG_PCI_IOV
148 static unsigned int max_vfs;
149 module_param(max_vfs, uint, 0);
150 MODULE_PARM_DESC(max_vfs,
151 "Maximum number of virtual functions to allocate per physical function");
152 #endif /* CONFIG_PCI_IOV */
153
154 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
155 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
156 MODULE_LICENSE("GPL");
157 MODULE_VERSION(DRV_VERSION);
158
159 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
160
161 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
162 {
163 struct ixgbe_hw *hw = &adapter->hw;
164 u32 gcr;
165 u32 gpie;
166 u32 vmdctl;
167
168 #ifdef CONFIG_PCI_IOV
169 /* disable iov and allow time for transactions to clear */
170 pci_disable_sriov(adapter->pdev);
171 #endif
172
173 /* turn off device IOV mode */
174 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
175 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
176 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
177 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
178 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
179 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
180
181 /* set default pool back to 0 */
182 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
183 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
184 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
185
186 /* take a breather then clean up driver data */
187 msleep(100);
188
189 kfree(adapter->vfinfo);
190 adapter->vfinfo = NULL;
191
192 adapter->num_vfs = 0;
193 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
194 }
195
196 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
197 {
198 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
199 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
200 schedule_work(&adapter->service_task);
201 }
202
203 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
204 {
205 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
206
207 /* flush memory to make sure state is correct before next watchog */
208 smp_mb__before_clear_bit();
209 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
210 }
211
212 struct ixgbe_reg_info {
213 u32 ofs;
214 char *name;
215 };
216
217 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
218
219 /* General Registers */
220 {IXGBE_CTRL, "CTRL"},
221 {IXGBE_STATUS, "STATUS"},
222 {IXGBE_CTRL_EXT, "CTRL_EXT"},
223
224 /* Interrupt Registers */
225 {IXGBE_EICR, "EICR"},
226
227 /* RX Registers */
228 {IXGBE_SRRCTL(0), "SRRCTL"},
229 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
230 {IXGBE_RDLEN(0), "RDLEN"},
231 {IXGBE_RDH(0), "RDH"},
232 {IXGBE_RDT(0), "RDT"},
233 {IXGBE_RXDCTL(0), "RXDCTL"},
234 {IXGBE_RDBAL(0), "RDBAL"},
235 {IXGBE_RDBAH(0), "RDBAH"},
236
237 /* TX Registers */
238 {IXGBE_TDBAL(0), "TDBAL"},
239 {IXGBE_TDBAH(0), "TDBAH"},
240 {IXGBE_TDLEN(0), "TDLEN"},
241 {IXGBE_TDH(0), "TDH"},
242 {IXGBE_TDT(0), "TDT"},
243 {IXGBE_TXDCTL(0), "TXDCTL"},
244
245 /* List Terminator */
246 {}
247 };
248
249
250 /*
251 * ixgbe_regdump - register printout routine
252 */
253 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
254 {
255 int i = 0, j = 0;
256 char rname[16];
257 u32 regs[64];
258
259 switch (reginfo->ofs) {
260 case IXGBE_SRRCTL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
263 break;
264 case IXGBE_DCA_RXCTRL(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
267 break;
268 case IXGBE_RDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
271 break;
272 case IXGBE_RDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
275 break;
276 case IXGBE_RDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
279 break;
280 case IXGBE_RXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
283 break;
284 case IXGBE_RDBAL(0):
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
287 break;
288 case IXGBE_RDBAH(0):
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
291 break;
292 case IXGBE_TDBAL(0):
293 for (i = 0; i < 64; i++)
294 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
295 break;
296 case IXGBE_TDBAH(0):
297 for (i = 0; i < 64; i++)
298 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
299 break;
300 case IXGBE_TDLEN(0):
301 for (i = 0; i < 64; i++)
302 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
303 break;
304 case IXGBE_TDH(0):
305 for (i = 0; i < 64; i++)
306 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
307 break;
308 case IXGBE_TDT(0):
309 for (i = 0; i < 64; i++)
310 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
311 break;
312 case IXGBE_TXDCTL(0):
313 for (i = 0; i < 64; i++)
314 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
315 break;
316 default:
317 pr_info("%-15s %08x\n", reginfo->name,
318 IXGBE_READ_REG(hw, reginfo->ofs));
319 return;
320 }
321
322 for (i = 0; i < 8; i++) {
323 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
324 pr_err("%-15s", rname);
325 for (j = 0; j < 8; j++)
326 pr_cont(" %08x", regs[i*8+j]);
327 pr_cont("\n");
328 }
329
330 }
331
332 /*
333 * ixgbe_dump - Print registers, tx-rings and rx-rings
334 */
335 static void ixgbe_dump(struct ixgbe_adapter *adapter)
336 {
337 struct net_device *netdev = adapter->netdev;
338 struct ixgbe_hw *hw = &adapter->hw;
339 struct ixgbe_reg_info *reginfo;
340 int n = 0;
341 struct ixgbe_ring *tx_ring;
342 struct ixgbe_tx_buffer *tx_buffer_info;
343 union ixgbe_adv_tx_desc *tx_desc;
344 struct my_u0 { u64 a; u64 b; } *u0;
345 struct ixgbe_ring *rx_ring;
346 union ixgbe_adv_rx_desc *rx_desc;
347 struct ixgbe_rx_buffer *rx_buffer_info;
348 u32 staterr;
349 int i = 0;
350
351 if (!netif_msg_hw(adapter))
352 return;
353
354 /* Print netdevice Info */
355 if (netdev) {
356 dev_info(&adapter->pdev->dev, "Net device Info\n");
357 pr_info("Device Name state "
358 "trans_start last_rx\n");
359 pr_info("%-15s %016lX %016lX %016lX\n",
360 netdev->name,
361 netdev->state,
362 netdev->trans_start,
363 netdev->last_rx);
364 }
365
366 /* Print Registers */
367 dev_info(&adapter->pdev->dev, "Register Dump\n");
368 pr_info(" Register Name Value\n");
369 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
370 reginfo->name; reginfo++) {
371 ixgbe_regdump(hw, reginfo);
372 }
373
374 /* Print TX Ring Summary */
375 if (!netdev || !netif_running(netdev))
376 goto exit;
377
378 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
379 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
380 for (n = 0; n < adapter->num_tx_queues; n++) {
381 tx_ring = adapter->tx_ring[n];
382 tx_buffer_info =
383 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
384 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
385 n, tx_ring->next_to_use, tx_ring->next_to_clean,
386 (u64)tx_buffer_info->dma,
387 tx_buffer_info->length,
388 tx_buffer_info->next_to_watch,
389 (u64)tx_buffer_info->time_stamp);
390 }
391
392 /* Print TX Rings */
393 if (!netif_msg_tx_done(adapter))
394 goto rx_ring_summary;
395
396 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
397
398 /* Transmit Descriptor Formats
399 *
400 * Advanced Transmit Descriptor
401 * +--------------------------------------------------------------+
402 * 0 | Buffer Address [63:0] |
403 * +--------------------------------------------------------------+
404 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
405 * +--------------------------------------------------------------+
406 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
407 */
408
409 for (n = 0; n < adapter->num_tx_queues; n++) {
410 tx_ring = adapter->tx_ring[n];
411 pr_info("------------------------------------\n");
412 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
413 pr_info("------------------------------------\n");
414 pr_info("T [desc] [address 63:0 ] "
415 "[PlPOIdStDDt Ln] [bi->dma ] "
416 "leng ntw timestamp bi->skb\n");
417
418 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
419 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
420 tx_buffer_info = &tx_ring->tx_buffer_info[i];
421 u0 = (struct my_u0 *)tx_desc;
422 pr_info("T [0x%03X] %016llX %016llX %016llX"
423 " %04X %3X %016llX %p", i,
424 le64_to_cpu(u0->a),
425 le64_to_cpu(u0->b),
426 (u64)tx_buffer_info->dma,
427 tx_buffer_info->length,
428 tx_buffer_info->next_to_watch,
429 (u64)tx_buffer_info->time_stamp,
430 tx_buffer_info->skb);
431 if (i == tx_ring->next_to_use &&
432 i == tx_ring->next_to_clean)
433 pr_cont(" NTC/U\n");
434 else if (i == tx_ring->next_to_use)
435 pr_cont(" NTU\n");
436 else if (i == tx_ring->next_to_clean)
437 pr_cont(" NTC\n");
438 else
439 pr_cont("\n");
440
441 if (netif_msg_pktdata(adapter) &&
442 tx_buffer_info->dma != 0)
443 print_hex_dump(KERN_INFO, "",
444 DUMP_PREFIX_ADDRESS, 16, 1,
445 phys_to_virt(tx_buffer_info->dma),
446 tx_buffer_info->length, true);
447 }
448 }
449
450 /* Print RX Rings Summary */
451 rx_ring_summary:
452 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
453 pr_info("Queue [NTU] [NTC]\n");
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
456 pr_info("%5d %5X %5X\n",
457 n, rx_ring->next_to_use, rx_ring->next_to_clean);
458 }
459
460 /* Print RX Rings */
461 if (!netif_msg_rx_status(adapter))
462 goto exit;
463
464 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
465
466 /* Advanced Receive Descriptor (Read) Format
467 * 63 1 0
468 * +-----------------------------------------------------+
469 * 0 | Packet Buffer Address [63:1] |A0/NSE|
470 * +----------------------------------------------+------+
471 * 8 | Header Buffer Address [63:1] | DD |
472 * +-----------------------------------------------------+
473 *
474 *
475 * Advanced Receive Descriptor (Write-Back) Format
476 *
477 * 63 48 47 32 31 30 21 20 16 15 4 3 0
478 * +------------------------------------------------------+
479 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
480 * | Checksum Ident | | | | Type | Type |
481 * +------------------------------------------------------+
482 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
483 * +------------------------------------------------------+
484 * 63 48 47 32 31 20 19 0
485 */
486 for (n = 0; n < adapter->num_rx_queues; n++) {
487 rx_ring = adapter->rx_ring[n];
488 pr_info("------------------------------------\n");
489 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
490 pr_info("------------------------------------\n");
491 pr_info("R [desc] [ PktBuf A0] "
492 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
493 "<-- Adv Rx Read format\n");
494 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
495 "[vl er S cks ln] ---------------- [bi->skb] "
496 "<-- Adv Rx Write-Back format\n");
497
498 for (i = 0; i < rx_ring->count; i++) {
499 rx_buffer_info = &rx_ring->rx_buffer_info[i];
500 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
501 u0 = (struct my_u0 *)rx_desc;
502 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
503 if (staterr & IXGBE_RXD_STAT_DD) {
504 /* Descriptor Done */
505 pr_info("RWB[0x%03X] %016llX "
506 "%016llX ---------------- %p", i,
507 le64_to_cpu(u0->a),
508 le64_to_cpu(u0->b),
509 rx_buffer_info->skb);
510 } else {
511 pr_info("R [0x%03X] %016llX "
512 "%016llX %016llX %p", i,
513 le64_to_cpu(u0->a),
514 le64_to_cpu(u0->b),
515 (u64)rx_buffer_info->dma,
516 rx_buffer_info->skb);
517
518 if (netif_msg_pktdata(adapter)) {
519 print_hex_dump(KERN_INFO, "",
520 DUMP_PREFIX_ADDRESS, 16, 1,
521 phys_to_virt(rx_buffer_info->dma),
522 rx_ring->rx_buf_len, true);
523
524 if (rx_ring->rx_buf_len
525 < IXGBE_RXBUFFER_2048)
526 print_hex_dump(KERN_INFO, "",
527 DUMP_PREFIX_ADDRESS, 16, 1,
528 phys_to_virt(
529 rx_buffer_info->page_dma +
530 rx_buffer_info->page_offset
531 ),
532 PAGE_SIZE/2, true);
533 }
534 }
535
536 if (i == rx_ring->next_to_use)
537 pr_cont(" NTU\n");
538 else if (i == rx_ring->next_to_clean)
539 pr_cont(" NTC\n");
540 else
541 pr_cont("\n");
542
543 }
544 }
545
546 exit:
547 return;
548 }
549
550 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
551 {
552 u32 ctrl_ext;
553
554 /* Let firmware take over control of h/w */
555 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
557 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
558 }
559
560 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
561 {
562 u32 ctrl_ext;
563
564 /* Let firmware know the driver has taken over */
565 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
566 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
567 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
568 }
569
570 /*
571 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
572 * @adapter: pointer to adapter struct
573 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
574 * @queue: queue to map the corresponding interrupt to
575 * @msix_vector: the vector to map to the corresponding queue
576 *
577 */
578 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
579 u8 queue, u8 msix_vector)
580 {
581 u32 ivar, index;
582 struct ixgbe_hw *hw = &adapter->hw;
583 switch (hw->mac.type) {
584 case ixgbe_mac_82598EB:
585 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
586 if (direction == -1)
587 direction = 0;
588 index = (((direction * 64) + queue) >> 2) & 0x1F;
589 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
590 ivar &= ~(0xFF << (8 * (queue & 0x3)));
591 ivar |= (msix_vector << (8 * (queue & 0x3)));
592 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
593 break;
594 case ixgbe_mac_82599EB:
595 case ixgbe_mac_X540:
596 if (direction == -1) {
597 /* other causes */
598 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
599 index = ((queue & 1) * 8);
600 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
601 ivar &= ~(0xFF << index);
602 ivar |= (msix_vector << index);
603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
604 break;
605 } else {
606 /* tx or rx causes */
607 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
608 index = ((16 * (queue & 1)) + (8 * direction));
609 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
610 ivar &= ~(0xFF << index);
611 ivar |= (msix_vector << index);
612 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
613 break;
614 }
615 default:
616 break;
617 }
618 }
619
620 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
621 u64 qmask)
622 {
623 u32 mask;
624
625 switch (adapter->hw.mac.type) {
626 case ixgbe_mac_82598EB:
627 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
628 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
629 break;
630 case ixgbe_mac_82599EB:
631 case ixgbe_mac_X540:
632 mask = (qmask & 0xFFFFFFFF);
633 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
634 mask = (qmask >> 32);
635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
636 break;
637 default:
638 break;
639 }
640 }
641
642 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
643 struct ixgbe_tx_buffer *tx_buffer_info)
644 {
645 if (tx_buffer_info->dma) {
646 if (tx_buffer_info->mapped_as_page)
647 dma_unmap_page(tx_ring->dev,
648 tx_buffer_info->dma,
649 tx_buffer_info->length,
650 DMA_TO_DEVICE);
651 else
652 dma_unmap_single(tx_ring->dev,
653 tx_buffer_info->dma,
654 tx_buffer_info->length,
655 DMA_TO_DEVICE);
656 tx_buffer_info->dma = 0;
657 }
658 if (tx_buffer_info->skb) {
659 dev_kfree_skb_any(tx_buffer_info->skb);
660 tx_buffer_info->skb = NULL;
661 }
662 tx_buffer_info->time_stamp = 0;
663 /* tx_buffer_info must be completely set up in the transmit path */
664 }
665
666 /**
667 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
668 * @adapter: driver private struct
669 * @index: reg idx of queue to query (0-127)
670 *
671 * Helper function to determine the traffic index for a particular
672 * register index.
673 *
674 * Returns : a tc index for use in range 0-7, or 0-3
675 */
676 static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
677 {
678 int tc = -1;
679 int dcb_i = netdev_get_num_tc(adapter->netdev);
680
681 /* if DCB is not enabled the queues have no TC */
682 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
683 return tc;
684
685 /* check valid range */
686 if (reg_idx >= adapter->hw.mac.max_tx_queues)
687 return tc;
688
689 switch (adapter->hw.mac.type) {
690 case ixgbe_mac_82598EB:
691 tc = reg_idx >> 2;
692 break;
693 default:
694 if (dcb_i != 4 && dcb_i != 8)
695 break;
696
697 /* if VMDq is enabled the lowest order bits determine TC */
698 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
699 IXGBE_FLAG_VMDQ_ENABLED)) {
700 tc = reg_idx & (dcb_i - 1);
701 break;
702 }
703
704 /*
705 * Convert the reg_idx into the correct TC. This bitmask
706 * targets the last full 32 ring traffic class and assigns
707 * it a value of 1. From there the rest of the rings are
708 * based on shifting the mask further up to include the
709 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
710 * will only ever be 8 or 4 and that reg_idx will never
711 * be greater then 128. The code without the power of 2
712 * optimizations would be:
713 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
714 */
715 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
716 tc >>= 9 - (reg_idx >> 5);
717 }
718
719 return tc;
720 }
721
722 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
723 {
724 struct ixgbe_hw *hw = &adapter->hw;
725 struct ixgbe_hw_stats *hwstats = &adapter->stats;
726 u32 data = 0;
727 u32 xoff[8] = {0};
728 int i;
729
730 if ((hw->fc.current_mode == ixgbe_fc_full) ||
731 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
732 switch (hw->mac.type) {
733 case ixgbe_mac_82598EB:
734 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
735 break;
736 default:
737 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
738 }
739 hwstats->lxoffrxc += data;
740
741 /* refill credits (no tx hang) if we received xoff */
742 if (!data)
743 return;
744
745 for (i = 0; i < adapter->num_tx_queues; i++)
746 clear_bit(__IXGBE_HANG_CHECK_ARMED,
747 &adapter->tx_ring[i]->state);
748 return;
749 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
750 return;
751
752 /* update stats for each tc, only valid with PFC enabled */
753 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
754 switch (hw->mac.type) {
755 case ixgbe_mac_82598EB:
756 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
757 break;
758 default:
759 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
760 }
761 hwstats->pxoffrxc[i] += xoff[i];
762 }
763
764 /* disarm tx queues that have received xoff frames */
765 for (i = 0; i < adapter->num_tx_queues; i++) {
766 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
767 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
768
769 if (xoff[tc])
770 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
771 }
772 }
773
774 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
775 {
776 return ring->tx_stats.completed;
777 }
778
779 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
780 {
781 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
782 struct ixgbe_hw *hw = &adapter->hw;
783
784 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
785 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
786
787 if (head != tail)
788 return (head < tail) ?
789 tail - head : (tail + ring->count - head);
790
791 return 0;
792 }
793
794 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
795 {
796 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
797 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
798 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
799 bool ret = false;
800
801 clear_check_for_tx_hang(tx_ring);
802
803 /*
804 * Check for a hung queue, but be thorough. This verifies
805 * that a transmit has been completed since the previous
806 * check AND there is at least one packet pending. The
807 * ARMED bit is set to indicate a potential hang. The
808 * bit is cleared if a pause frame is received to remove
809 * false hang detection due to PFC or 802.3x frames. By
810 * requiring this to fail twice we avoid races with
811 * pfc clearing the ARMED bit and conditions where we
812 * run the check_tx_hang logic with a transmit completion
813 * pending but without time to complete it yet.
814 */
815 if ((tx_done_old == tx_done) && tx_pending) {
816 /* make sure it is true for two checks in a row */
817 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
818 &tx_ring->state);
819 } else {
820 /* update completed stats and continue */
821 tx_ring->tx_stats.tx_done_old = tx_done;
822 /* reset the countdown */
823 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
824 }
825
826 return ret;
827 }
828
829 #define IXGBE_MAX_TXD_PWR 14
830 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
831
832 /* Tx Descriptors needed, worst case */
833 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
834 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
835 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
836 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
837
838 /**
839 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
840 * @adapter: driver private struct
841 **/
842 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
843 {
844
845 /* Do the reset outside of interrupt context */
846 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
847 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
848 ixgbe_service_event_schedule(adapter);
849 }
850 }
851
852 /**
853 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
854 * @q_vector: structure containing interrupt and ring information
855 * @tx_ring: tx ring to clean
856 **/
857 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
858 struct ixgbe_ring *tx_ring)
859 {
860 struct ixgbe_adapter *adapter = q_vector->adapter;
861 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
862 struct ixgbe_tx_buffer *tx_buffer_info;
863 unsigned int total_bytes = 0, total_packets = 0;
864 u16 i, eop, count = 0;
865
866 i = tx_ring->next_to_clean;
867 eop = tx_ring->tx_buffer_info[i].next_to_watch;
868 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
869
870 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
871 (count < tx_ring->work_limit)) {
872 bool cleaned = false;
873 rmb(); /* read buffer_info after eop_desc */
874 for ( ; !cleaned; count++) {
875 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
876 tx_buffer_info = &tx_ring->tx_buffer_info[i];
877
878 tx_desc->wb.status = 0;
879 cleaned = (i == eop);
880
881 i++;
882 if (i == tx_ring->count)
883 i = 0;
884
885 if (cleaned && tx_buffer_info->skb) {
886 total_bytes += tx_buffer_info->bytecount;
887 total_packets += tx_buffer_info->gso_segs;
888 }
889
890 ixgbe_unmap_and_free_tx_resource(tx_ring,
891 tx_buffer_info);
892 }
893
894 tx_ring->tx_stats.completed++;
895 eop = tx_ring->tx_buffer_info[i].next_to_watch;
896 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
897 }
898
899 tx_ring->next_to_clean = i;
900 tx_ring->total_bytes += total_bytes;
901 tx_ring->total_packets += total_packets;
902 u64_stats_update_begin(&tx_ring->syncp);
903 tx_ring->stats.packets += total_packets;
904 tx_ring->stats.bytes += total_bytes;
905 u64_stats_update_end(&tx_ring->syncp);
906
907 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
908 /* schedule immediate reset if we believe we hung */
909 struct ixgbe_hw *hw = &adapter->hw;
910 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
911 e_err(drv, "Detected Tx Unit Hang\n"
912 " Tx Queue <%d>\n"
913 " TDH, TDT <%x>, <%x>\n"
914 " next_to_use <%x>\n"
915 " next_to_clean <%x>\n"
916 "tx_buffer_info[next_to_clean]\n"
917 " time_stamp <%lx>\n"
918 " jiffies <%lx>\n",
919 tx_ring->queue_index,
920 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
921 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
922 tx_ring->next_to_use, eop,
923 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
924
925 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
926
927 e_info(probe,
928 "tx hang %d detected on queue %d, resetting adapter\n",
929 adapter->tx_timeout_count + 1, tx_ring->queue_index);
930
931 /* schedule immediate reset if we believe we hung */
932 ixgbe_tx_timeout_reset(adapter);
933
934 /* the adapter is about to reset, no point in enabling stuff */
935 return true;
936 }
937
938 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
939 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
940 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
941 /* Make sure that anybody stopping the queue after this
942 * sees the new next_to_clean.
943 */
944 smp_mb();
945 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
946 !test_bit(__IXGBE_DOWN, &adapter->state)) {
947 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
948 ++tx_ring->tx_stats.restart_queue;
949 }
950 }
951
952 return count < tx_ring->work_limit;
953 }
954
955 #ifdef CONFIG_IXGBE_DCA
956 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
957 struct ixgbe_ring *rx_ring,
958 int cpu)
959 {
960 struct ixgbe_hw *hw = &adapter->hw;
961 u32 rxctrl;
962 u8 reg_idx = rx_ring->reg_idx;
963
964 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
965 switch (hw->mac.type) {
966 case ixgbe_mac_82598EB:
967 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
968 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
969 break;
970 case ixgbe_mac_82599EB:
971 case ixgbe_mac_X540:
972 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
973 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
974 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
975 break;
976 default:
977 break;
978 }
979 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
980 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
981 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
982 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
983 }
984
985 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
986 struct ixgbe_ring *tx_ring,
987 int cpu)
988 {
989 struct ixgbe_hw *hw = &adapter->hw;
990 u32 txctrl;
991 u8 reg_idx = tx_ring->reg_idx;
992
993 switch (hw->mac.type) {
994 case ixgbe_mac_82598EB:
995 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
996 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
997 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
998 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
999 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
1000 break;
1001 case ixgbe_mac_82599EB:
1002 case ixgbe_mac_X540:
1003 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
1004 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
1005 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
1006 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
1007 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1008 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
1009 break;
1010 default:
1011 break;
1012 }
1013 }
1014
1015 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1016 {
1017 struct ixgbe_adapter *adapter = q_vector->adapter;
1018 int cpu = get_cpu();
1019 long r_idx;
1020 int i;
1021
1022 if (q_vector->cpu == cpu)
1023 goto out_no_update;
1024
1025 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1026 for (i = 0; i < q_vector->txr_count; i++) {
1027 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
1028 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1029 r_idx + 1);
1030 }
1031
1032 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1033 for (i = 0; i < q_vector->rxr_count; i++) {
1034 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1035 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1036 r_idx + 1);
1037 }
1038
1039 q_vector->cpu = cpu;
1040 out_no_update:
1041 put_cpu();
1042 }
1043
1044 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1045 {
1046 int num_q_vectors;
1047 int i;
1048
1049 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1050 return;
1051
1052 /* always use CB2 mode, difference is masked in the CB driver */
1053 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1054
1055 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1056 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1057 else
1058 num_q_vectors = 1;
1059
1060 for (i = 0; i < num_q_vectors; i++) {
1061 adapter->q_vector[i]->cpu = -1;
1062 ixgbe_update_dca(adapter->q_vector[i]);
1063 }
1064 }
1065
1066 static int __ixgbe_notify_dca(struct device *dev, void *data)
1067 {
1068 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1069 unsigned long event = *(unsigned long *)data;
1070
1071 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1072 return 0;
1073
1074 switch (event) {
1075 case DCA_PROVIDER_ADD:
1076 /* if we're already enabled, don't do it again */
1077 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1078 break;
1079 if (dca_add_requester(dev) == 0) {
1080 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1081 ixgbe_setup_dca(adapter);
1082 break;
1083 }
1084 /* Fall Through since DCA is disabled. */
1085 case DCA_PROVIDER_REMOVE:
1086 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1087 dca_remove_requester(dev);
1088 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1089 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1090 }
1091 break;
1092 }
1093
1094 return 0;
1095 }
1096 #endif /* CONFIG_IXGBE_DCA */
1097
1098 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1099 struct sk_buff *skb)
1100 {
1101 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1102 }
1103
1104 /**
1105 * ixgbe_receive_skb - Send a completed packet up the stack
1106 * @adapter: board private structure
1107 * @skb: packet to send up
1108 * @status: hardware indication of status of receive
1109 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1110 * @rx_desc: rx descriptor
1111 **/
1112 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1113 struct sk_buff *skb, u8 status,
1114 struct ixgbe_ring *ring,
1115 union ixgbe_adv_rx_desc *rx_desc)
1116 {
1117 struct ixgbe_adapter *adapter = q_vector->adapter;
1118 struct napi_struct *napi = &q_vector->napi;
1119 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1120 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1121
1122 if (is_vlan && (tag & VLAN_VID_MASK))
1123 __vlan_hwaccel_put_tag(skb, tag);
1124
1125 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1126 napi_gro_receive(napi, skb);
1127 else
1128 netif_rx(skb);
1129 }
1130
1131 /**
1132 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1133 * @adapter: address of board private structure
1134 * @status_err: hardware indication of status of receive
1135 * @skb: skb currently being received and modified
1136 **/
1137 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1138 union ixgbe_adv_rx_desc *rx_desc,
1139 struct sk_buff *skb)
1140 {
1141 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1142
1143 skb_checksum_none_assert(skb);
1144
1145 /* Rx csum disabled */
1146 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1147 return;
1148
1149 /* if IP and error */
1150 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1151 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1152 adapter->hw_csum_rx_error++;
1153 return;
1154 }
1155
1156 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1157 return;
1158
1159 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1160 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1161
1162 /*
1163 * 82599 errata, UDP frames with a 0 checksum can be marked as
1164 * checksum errors.
1165 */
1166 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1167 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1168 return;
1169
1170 adapter->hw_csum_rx_error++;
1171 return;
1172 }
1173
1174 /* It must be a TCP or UDP packet with a valid checksum */
1175 skb->ip_summed = CHECKSUM_UNNECESSARY;
1176 }
1177
1178 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1179 {
1180 /*
1181 * Force memory writes to complete before letting h/w
1182 * know there are new descriptors to fetch. (Only
1183 * applicable for weak-ordered memory model archs,
1184 * such as IA-64).
1185 */
1186 wmb();
1187 writel(val, rx_ring->tail);
1188 }
1189
1190 /**
1191 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1192 * @rx_ring: ring to place buffers on
1193 * @cleaned_count: number of buffers to replace
1194 **/
1195 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1196 {
1197 union ixgbe_adv_rx_desc *rx_desc;
1198 struct ixgbe_rx_buffer *bi;
1199 struct sk_buff *skb;
1200 u16 i = rx_ring->next_to_use;
1201
1202 /* do nothing if no valid netdev defined */
1203 if (!rx_ring->netdev)
1204 return;
1205
1206 while (cleaned_count--) {
1207 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1208 bi = &rx_ring->rx_buffer_info[i];
1209 skb = bi->skb;
1210
1211 if (!skb) {
1212 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1213 rx_ring->rx_buf_len);
1214 if (!skb) {
1215 rx_ring->rx_stats.alloc_rx_buff_failed++;
1216 goto no_buffers;
1217 }
1218 /* initialize queue mapping */
1219 skb_record_rx_queue(skb, rx_ring->queue_index);
1220 bi->skb = skb;
1221 }
1222
1223 if (!bi->dma) {
1224 bi->dma = dma_map_single(rx_ring->dev,
1225 skb->data,
1226 rx_ring->rx_buf_len,
1227 DMA_FROM_DEVICE);
1228 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1229 rx_ring->rx_stats.alloc_rx_buff_failed++;
1230 bi->dma = 0;
1231 goto no_buffers;
1232 }
1233 }
1234
1235 if (ring_is_ps_enabled(rx_ring)) {
1236 if (!bi->page) {
1237 bi->page = netdev_alloc_page(rx_ring->netdev);
1238 if (!bi->page) {
1239 rx_ring->rx_stats.alloc_rx_page_failed++;
1240 goto no_buffers;
1241 }
1242 }
1243
1244 if (!bi->page_dma) {
1245 /* use a half page if we're re-using */
1246 bi->page_offset ^= PAGE_SIZE / 2;
1247 bi->page_dma = dma_map_page(rx_ring->dev,
1248 bi->page,
1249 bi->page_offset,
1250 PAGE_SIZE / 2,
1251 DMA_FROM_DEVICE);
1252 if (dma_mapping_error(rx_ring->dev,
1253 bi->page_dma)) {
1254 rx_ring->rx_stats.alloc_rx_page_failed++;
1255 bi->page_dma = 0;
1256 goto no_buffers;
1257 }
1258 }
1259
1260 /* Refresh the desc even if buffer_addrs didn't change
1261 * because each write-back erases this info. */
1262 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1263 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1264 } else {
1265 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1266 rx_desc->read.hdr_addr = 0;
1267 }
1268
1269 i++;
1270 if (i == rx_ring->count)
1271 i = 0;
1272 }
1273
1274 no_buffers:
1275 if (rx_ring->next_to_use != i) {
1276 rx_ring->next_to_use = i;
1277 ixgbe_release_rx_desc(rx_ring, i);
1278 }
1279 }
1280
1281 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1282 {
1283 /* HW will not DMA in data larger than the given buffer, even if it
1284 * parses the (NFS, of course) header to be larger. In that case, it
1285 * fills the header buffer and spills the rest into the page.
1286 */
1287 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1288 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1289 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1290 if (hlen > IXGBE_RX_HDR_SIZE)
1291 hlen = IXGBE_RX_HDR_SIZE;
1292 return hlen;
1293 }
1294
1295 /**
1296 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1297 * @skb: pointer to the last skb in the rsc queue
1298 *
1299 * This function changes a queue full of hw rsc buffers into a completed
1300 * packet. It uses the ->prev pointers to find the first packet and then
1301 * turns it into the frag list owner.
1302 **/
1303 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1304 {
1305 unsigned int frag_list_size = 0;
1306 unsigned int skb_cnt = 1;
1307
1308 while (skb->prev) {
1309 struct sk_buff *prev = skb->prev;
1310 frag_list_size += skb->len;
1311 skb->prev = NULL;
1312 skb = prev;
1313 skb_cnt++;
1314 }
1315
1316 skb_shinfo(skb)->frag_list = skb->next;
1317 skb->next = NULL;
1318 skb->len += frag_list_size;
1319 skb->data_len += frag_list_size;
1320 skb->truesize += frag_list_size;
1321 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1322
1323 return skb;
1324 }
1325
1326 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1327 {
1328 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1329 IXGBE_RXDADV_RSCCNT_MASK);
1330 }
1331
1332 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1333 struct ixgbe_ring *rx_ring,
1334 int *work_done, int work_to_do)
1335 {
1336 struct ixgbe_adapter *adapter = q_vector->adapter;
1337 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1338 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1339 struct sk_buff *skb;
1340 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1341 const int current_node = numa_node_id();
1342 #ifdef IXGBE_FCOE
1343 int ddp_bytes = 0;
1344 #endif /* IXGBE_FCOE */
1345 u32 staterr;
1346 u16 i;
1347 u16 cleaned_count = 0;
1348 bool pkt_is_rsc = false;
1349
1350 i = rx_ring->next_to_clean;
1351 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1352 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1353
1354 while (staterr & IXGBE_RXD_STAT_DD) {
1355 u32 upper_len = 0;
1356
1357 rmb(); /* read descriptor and rx_buffer_info after status DD */
1358
1359 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1360
1361 skb = rx_buffer_info->skb;
1362 rx_buffer_info->skb = NULL;
1363 prefetch(skb->data);
1364
1365 if (ring_is_rsc_enabled(rx_ring))
1366 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1367
1368 /* if this is a skb from previous receive DMA will be 0 */
1369 if (rx_buffer_info->dma) {
1370 u16 hlen;
1371 if (pkt_is_rsc &&
1372 !(staterr & IXGBE_RXD_STAT_EOP) &&
1373 !skb->prev) {
1374 /*
1375 * When HWRSC is enabled, delay unmapping
1376 * of the first packet. It carries the
1377 * header information, HW may still
1378 * access the header after the writeback.
1379 * Only unmap it when EOP is reached
1380 */
1381 IXGBE_RSC_CB(skb)->delay_unmap = true;
1382 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1383 } else {
1384 dma_unmap_single(rx_ring->dev,
1385 rx_buffer_info->dma,
1386 rx_ring->rx_buf_len,
1387 DMA_FROM_DEVICE);
1388 }
1389 rx_buffer_info->dma = 0;
1390
1391 if (ring_is_ps_enabled(rx_ring)) {
1392 hlen = ixgbe_get_hlen(rx_desc);
1393 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1394 } else {
1395 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1396 }
1397
1398 skb_put(skb, hlen);
1399 } else {
1400 /* assume packet split since header is unmapped */
1401 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1402 }
1403
1404 if (upper_len) {
1405 dma_unmap_page(rx_ring->dev,
1406 rx_buffer_info->page_dma,
1407 PAGE_SIZE / 2,
1408 DMA_FROM_DEVICE);
1409 rx_buffer_info->page_dma = 0;
1410 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1411 rx_buffer_info->page,
1412 rx_buffer_info->page_offset,
1413 upper_len);
1414
1415 if ((page_count(rx_buffer_info->page) == 1) &&
1416 (page_to_nid(rx_buffer_info->page) == current_node))
1417 get_page(rx_buffer_info->page);
1418 else
1419 rx_buffer_info->page = NULL;
1420
1421 skb->len += upper_len;
1422 skb->data_len += upper_len;
1423 skb->truesize += upper_len;
1424 }
1425
1426 i++;
1427 if (i == rx_ring->count)
1428 i = 0;
1429
1430 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1431 prefetch(next_rxd);
1432 cleaned_count++;
1433
1434 if (pkt_is_rsc) {
1435 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1436 IXGBE_RXDADV_NEXTP_SHIFT;
1437 next_buffer = &rx_ring->rx_buffer_info[nextp];
1438 } else {
1439 next_buffer = &rx_ring->rx_buffer_info[i];
1440 }
1441
1442 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1443 if (ring_is_ps_enabled(rx_ring)) {
1444 rx_buffer_info->skb = next_buffer->skb;
1445 rx_buffer_info->dma = next_buffer->dma;
1446 next_buffer->skb = skb;
1447 next_buffer->dma = 0;
1448 } else {
1449 skb->next = next_buffer->skb;
1450 skb->next->prev = skb;
1451 }
1452 rx_ring->rx_stats.non_eop_descs++;
1453 goto next_desc;
1454 }
1455
1456 if (skb->prev) {
1457 skb = ixgbe_transform_rsc_queue(skb);
1458 /* if we got here without RSC the packet is invalid */
1459 if (!pkt_is_rsc) {
1460 __pskb_trim(skb, 0);
1461 rx_buffer_info->skb = skb;
1462 goto next_desc;
1463 }
1464 }
1465
1466 if (ring_is_rsc_enabled(rx_ring)) {
1467 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1468 dma_unmap_single(rx_ring->dev,
1469 IXGBE_RSC_CB(skb)->dma,
1470 rx_ring->rx_buf_len,
1471 DMA_FROM_DEVICE);
1472 IXGBE_RSC_CB(skb)->dma = 0;
1473 IXGBE_RSC_CB(skb)->delay_unmap = false;
1474 }
1475 }
1476 if (pkt_is_rsc) {
1477 if (ring_is_ps_enabled(rx_ring))
1478 rx_ring->rx_stats.rsc_count +=
1479 skb_shinfo(skb)->nr_frags;
1480 else
1481 rx_ring->rx_stats.rsc_count +=
1482 IXGBE_RSC_CB(skb)->skb_cnt;
1483 rx_ring->rx_stats.rsc_flush++;
1484 }
1485
1486 /* ERR_MASK will only have valid bits if EOP set */
1487 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1488 /* trim packet back to size 0 and recycle it */
1489 __pskb_trim(skb, 0);
1490 rx_buffer_info->skb = skb;
1491 goto next_desc;
1492 }
1493
1494 ixgbe_rx_checksum(adapter, rx_desc, skb);
1495 if (adapter->netdev->features & NETIF_F_RXHASH)
1496 ixgbe_rx_hash(rx_desc, skb);
1497
1498 /* probably a little skewed due to removing CRC */
1499 total_rx_bytes += skb->len;
1500 total_rx_packets++;
1501
1502 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1503 #ifdef IXGBE_FCOE
1504 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1505 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1506 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1507 if (!ddp_bytes)
1508 goto next_desc;
1509 }
1510 #endif /* IXGBE_FCOE */
1511 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1512
1513 next_desc:
1514 rx_desc->wb.upper.status_error = 0;
1515
1516 (*work_done)++;
1517 if (*work_done >= work_to_do)
1518 break;
1519
1520 /* return some buffers to hardware, one at a time is too slow */
1521 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1522 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1523 cleaned_count = 0;
1524 }
1525
1526 /* use prefetched values */
1527 rx_desc = next_rxd;
1528 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1529 }
1530
1531 rx_ring->next_to_clean = i;
1532 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1533
1534 if (cleaned_count)
1535 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1536
1537 #ifdef IXGBE_FCOE
1538 /* include DDPed FCoE data */
1539 if (ddp_bytes > 0) {
1540 unsigned int mss;
1541
1542 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1543 sizeof(struct fc_frame_header) -
1544 sizeof(struct fcoe_crc_eof);
1545 if (mss > 512)
1546 mss &= ~511;
1547 total_rx_bytes += ddp_bytes;
1548 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1549 }
1550 #endif /* IXGBE_FCOE */
1551
1552 rx_ring->total_packets += total_rx_packets;
1553 rx_ring->total_bytes += total_rx_bytes;
1554 u64_stats_update_begin(&rx_ring->syncp);
1555 rx_ring->stats.packets += total_rx_packets;
1556 rx_ring->stats.bytes += total_rx_bytes;
1557 u64_stats_update_end(&rx_ring->syncp);
1558 }
1559
1560 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1561 /**
1562 * ixgbe_configure_msix - Configure MSI-X hardware
1563 * @adapter: board private structure
1564 *
1565 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1566 * interrupts.
1567 **/
1568 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1569 {
1570 struct ixgbe_q_vector *q_vector;
1571 int i, q_vectors, v_idx, r_idx;
1572 u32 mask;
1573
1574 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1575
1576 /*
1577 * Populate the IVAR table and set the ITR values to the
1578 * corresponding register.
1579 */
1580 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1581 q_vector = adapter->q_vector[v_idx];
1582 /* XXX for_each_set_bit(...) */
1583 r_idx = find_first_bit(q_vector->rxr_idx,
1584 adapter->num_rx_queues);
1585
1586 for (i = 0; i < q_vector->rxr_count; i++) {
1587 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1588 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1589 r_idx = find_next_bit(q_vector->rxr_idx,
1590 adapter->num_rx_queues,
1591 r_idx + 1);
1592 }
1593 r_idx = find_first_bit(q_vector->txr_idx,
1594 adapter->num_tx_queues);
1595
1596 for (i = 0; i < q_vector->txr_count; i++) {
1597 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1598 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1599 r_idx = find_next_bit(q_vector->txr_idx,
1600 adapter->num_tx_queues,
1601 r_idx + 1);
1602 }
1603
1604 if (q_vector->txr_count && !q_vector->rxr_count)
1605 /* tx only */
1606 q_vector->eitr = adapter->tx_eitr_param;
1607 else if (q_vector->rxr_count)
1608 /* rx or mixed */
1609 q_vector->eitr = adapter->rx_eitr_param;
1610
1611 ixgbe_write_eitr(q_vector);
1612 /* If Flow Director is enabled, set interrupt affinity */
1613 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1614 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1615 /*
1616 * Allocate the affinity_hint cpumask, assign the mask
1617 * for this vector, and set our affinity_hint for
1618 * this irq.
1619 */
1620 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1621 GFP_KERNEL))
1622 return;
1623 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1624 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1625 q_vector->affinity_mask);
1626 }
1627 }
1628
1629 switch (adapter->hw.mac.type) {
1630 case ixgbe_mac_82598EB:
1631 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1632 v_idx);
1633 break;
1634 case ixgbe_mac_82599EB:
1635 case ixgbe_mac_X540:
1636 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1637 break;
1638
1639 default:
1640 break;
1641 }
1642 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1643
1644 /* set up to autoclear timer, and the vectors */
1645 mask = IXGBE_EIMS_ENABLE_MASK;
1646 if (adapter->num_vfs)
1647 mask &= ~(IXGBE_EIMS_OTHER |
1648 IXGBE_EIMS_MAILBOX |
1649 IXGBE_EIMS_LSC);
1650 else
1651 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1652 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1653 }
1654
1655 enum latency_range {
1656 lowest_latency = 0,
1657 low_latency = 1,
1658 bulk_latency = 2,
1659 latency_invalid = 255
1660 };
1661
1662 /**
1663 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1664 * @adapter: pointer to adapter
1665 * @eitr: eitr setting (ints per sec) to give last timeslice
1666 * @itr_setting: current throttle rate in ints/second
1667 * @packets: the number of packets during this measurement interval
1668 * @bytes: the number of bytes during this measurement interval
1669 *
1670 * Stores a new ITR value based on packets and byte
1671 * counts during the last interrupt. The advantage of per interrupt
1672 * computation is faster updates and more accurate ITR for the current
1673 * traffic pattern. Constants in this function were computed
1674 * based on theoretical maximum wire speed and thresholds were set based
1675 * on testing data as well as attempting to minimize response time
1676 * while increasing bulk throughput.
1677 * this functionality is controlled by the InterruptThrottleRate module
1678 * parameter (see ixgbe_param.c)
1679 **/
1680 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1681 u32 eitr, u8 itr_setting,
1682 int packets, int bytes)
1683 {
1684 unsigned int retval = itr_setting;
1685 u32 timepassed_us;
1686 u64 bytes_perint;
1687
1688 if (packets == 0)
1689 goto update_itr_done;
1690
1691
1692 /* simple throttlerate management
1693 * 0-20MB/s lowest (100000 ints/s)
1694 * 20-100MB/s low (20000 ints/s)
1695 * 100-1249MB/s bulk (8000 ints/s)
1696 */
1697 /* what was last interrupt timeslice? */
1698 timepassed_us = 1000000/eitr;
1699 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1700
1701 switch (itr_setting) {
1702 case lowest_latency:
1703 if (bytes_perint > adapter->eitr_low)
1704 retval = low_latency;
1705 break;
1706 case low_latency:
1707 if (bytes_perint > adapter->eitr_high)
1708 retval = bulk_latency;
1709 else if (bytes_perint <= adapter->eitr_low)
1710 retval = lowest_latency;
1711 break;
1712 case bulk_latency:
1713 if (bytes_perint <= adapter->eitr_high)
1714 retval = low_latency;
1715 break;
1716 }
1717
1718 update_itr_done:
1719 return retval;
1720 }
1721
1722 /**
1723 * ixgbe_write_eitr - write EITR register in hardware specific way
1724 * @q_vector: structure containing interrupt and ring information
1725 *
1726 * This function is made to be called by ethtool and by the driver
1727 * when it needs to update EITR registers at runtime. Hardware
1728 * specific quirks/differences are taken care of here.
1729 */
1730 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1731 {
1732 struct ixgbe_adapter *adapter = q_vector->adapter;
1733 struct ixgbe_hw *hw = &adapter->hw;
1734 int v_idx = q_vector->v_idx;
1735 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1736
1737 switch (adapter->hw.mac.type) {
1738 case ixgbe_mac_82598EB:
1739 /* must write high and low 16 bits to reset counter */
1740 itr_reg |= (itr_reg << 16);
1741 break;
1742 case ixgbe_mac_82599EB:
1743 case ixgbe_mac_X540:
1744 /*
1745 * 82599 and X540 can support a value of zero, so allow it for
1746 * max interrupt rate, but there is an errata where it can
1747 * not be zero with RSC
1748 */
1749 if (itr_reg == 8 &&
1750 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1751 itr_reg = 0;
1752
1753 /*
1754 * set the WDIS bit to not clear the timer bits and cause an
1755 * immediate assertion of the interrupt
1756 */
1757 itr_reg |= IXGBE_EITR_CNT_WDIS;
1758 break;
1759 default:
1760 break;
1761 }
1762 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1763 }
1764
1765 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1766 {
1767 struct ixgbe_adapter *adapter = q_vector->adapter;
1768 int i, r_idx;
1769 u32 new_itr;
1770 u8 current_itr, ret_itr;
1771
1772 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1773 for (i = 0; i < q_vector->txr_count; i++) {
1774 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1775 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1776 q_vector->tx_itr,
1777 tx_ring->total_packets,
1778 tx_ring->total_bytes);
1779 /* if the result for this queue would decrease interrupt
1780 * rate for this vector then use that result */
1781 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1782 q_vector->tx_itr - 1 : ret_itr);
1783 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1784 r_idx + 1);
1785 }
1786
1787 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1788 for (i = 0; i < q_vector->rxr_count; i++) {
1789 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1790 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1791 q_vector->rx_itr,
1792 rx_ring->total_packets,
1793 rx_ring->total_bytes);
1794 /* if the result for this queue would decrease interrupt
1795 * rate for this vector then use that result */
1796 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1797 q_vector->rx_itr - 1 : ret_itr);
1798 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1799 r_idx + 1);
1800 }
1801
1802 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1803
1804 switch (current_itr) {
1805 /* counts and packets in update_itr are dependent on these numbers */
1806 case lowest_latency:
1807 new_itr = 100000;
1808 break;
1809 case low_latency:
1810 new_itr = 20000; /* aka hwitr = ~200 */
1811 break;
1812 case bulk_latency:
1813 default:
1814 new_itr = 8000;
1815 break;
1816 }
1817
1818 if (new_itr != q_vector->eitr) {
1819 /* do an exponential smoothing */
1820 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1821
1822 /* save the algorithm value here, not the smoothed one */
1823 q_vector->eitr = new_itr;
1824
1825 ixgbe_write_eitr(q_vector);
1826 }
1827 }
1828
1829 /**
1830 * ixgbe_check_overtemp_subtask - check for over tempurature
1831 * @adapter: pointer to adapter
1832 **/
1833 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1834 {
1835 struct ixgbe_hw *hw = &adapter->hw;
1836 u32 eicr = adapter->interrupt_event;
1837
1838 if (test_bit(__IXGBE_DOWN, &adapter->state))
1839 return;
1840
1841 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1842 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1843 return;
1844
1845 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1846
1847 switch (hw->device_id) {
1848 case IXGBE_DEV_ID_82599_T3_LOM:
1849 /*
1850 * Since the warning interrupt is for both ports
1851 * we don't have to check if:
1852 * - This interrupt wasn't for our port.
1853 * - We may have missed the interrupt so always have to
1854 * check if we got a LSC
1855 */
1856 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1857 !(eicr & IXGBE_EICR_LSC))
1858 return;
1859
1860 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1861 u32 autoneg;
1862 bool link_up = false;
1863
1864 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1865
1866 if (link_up)
1867 return;
1868 }
1869
1870 /* Check if this is not due to overtemp */
1871 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1872 return;
1873
1874 break;
1875 default:
1876 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1877 return;
1878 break;
1879 }
1880 e_crit(drv,
1881 "Network adapter has been stopped because it has over heated. "
1882 "Restart the computer. If the problem persists, "
1883 "power off the system and replace the adapter\n");
1884
1885 adapter->interrupt_event = 0;
1886 }
1887
1888 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1889 {
1890 struct ixgbe_hw *hw = &adapter->hw;
1891
1892 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1893 (eicr & IXGBE_EICR_GPI_SDP1)) {
1894 e_crit(probe, "Fan has stopped, replace the adapter\n");
1895 /* write to clear the interrupt */
1896 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1897 }
1898 }
1899
1900 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1901 {
1902 struct ixgbe_hw *hw = &adapter->hw;
1903
1904 if (eicr & IXGBE_EICR_GPI_SDP2) {
1905 /* Clear the interrupt */
1906 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1907 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1908 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1909 ixgbe_service_event_schedule(adapter);
1910 }
1911 }
1912
1913 if (eicr & IXGBE_EICR_GPI_SDP1) {
1914 /* Clear the interrupt */
1915 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1916 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1917 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1918 ixgbe_service_event_schedule(adapter);
1919 }
1920 }
1921 }
1922
1923 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1924 {
1925 struct ixgbe_hw *hw = &adapter->hw;
1926
1927 adapter->lsc_int++;
1928 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1929 adapter->link_check_timeout = jiffies;
1930 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1931 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1932 IXGBE_WRITE_FLUSH(hw);
1933 ixgbe_service_event_schedule(adapter);
1934 }
1935 }
1936
1937 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1938 {
1939 struct net_device *netdev = data;
1940 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1941 struct ixgbe_hw *hw = &adapter->hw;
1942 u32 eicr;
1943
1944 /*
1945 * Workaround for Silicon errata. Use clear-by-write instead
1946 * of clear-by-read. Reading with EICS will return the
1947 * interrupt causes without clearing, which later be done
1948 * with the write to EICR.
1949 */
1950 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1951 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1952
1953 if (eicr & IXGBE_EICR_LSC)
1954 ixgbe_check_lsc(adapter);
1955
1956 if (eicr & IXGBE_EICR_MAILBOX)
1957 ixgbe_msg_task(adapter);
1958
1959 switch (hw->mac.type) {
1960 case ixgbe_mac_82599EB:
1961 case ixgbe_mac_X540:
1962 /* Handle Flow Director Full threshold interrupt */
1963 if (eicr & IXGBE_EICR_FLOW_DIR) {
1964 int reinit_count = 0;
1965 int i;
1966 for (i = 0; i < adapter->num_tx_queues; i++) {
1967 struct ixgbe_ring *ring = adapter->tx_ring[i];
1968 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1969 &ring->state))
1970 reinit_count++;
1971 }
1972 if (reinit_count) {
1973 /* no more flow director interrupts until after init */
1974 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1975 eicr &= ~IXGBE_EICR_FLOW_DIR;
1976 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1977 ixgbe_service_event_schedule(adapter);
1978 }
1979 }
1980 ixgbe_check_sfp_event(adapter, eicr);
1981 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1982 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1983 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1984 adapter->interrupt_event = eicr;
1985 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1986 ixgbe_service_event_schedule(adapter);
1987 }
1988 }
1989 break;
1990 default:
1991 break;
1992 }
1993
1994 ixgbe_check_fan_failure(adapter, eicr);
1995
1996 /* re-enable the original interrupt state, no lsc, no queues */
1997 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1998 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1999 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
2000
2001 return IRQ_HANDLED;
2002 }
2003
2004 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2005 u64 qmask)
2006 {
2007 u32 mask;
2008 struct ixgbe_hw *hw = &adapter->hw;
2009
2010 switch (hw->mac.type) {
2011 case ixgbe_mac_82598EB:
2012 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2013 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2014 break;
2015 case ixgbe_mac_82599EB:
2016 case ixgbe_mac_X540:
2017 mask = (qmask & 0xFFFFFFFF);
2018 if (mask)
2019 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2020 mask = (qmask >> 32);
2021 if (mask)
2022 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2023 break;
2024 default:
2025 break;
2026 }
2027 /* skip the flush */
2028 }
2029
2030 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2031 u64 qmask)
2032 {
2033 u32 mask;
2034 struct ixgbe_hw *hw = &adapter->hw;
2035
2036 switch (hw->mac.type) {
2037 case ixgbe_mac_82598EB:
2038 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2039 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2040 break;
2041 case ixgbe_mac_82599EB:
2042 case ixgbe_mac_X540:
2043 mask = (qmask & 0xFFFFFFFF);
2044 if (mask)
2045 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2046 mask = (qmask >> 32);
2047 if (mask)
2048 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2049 break;
2050 default:
2051 break;
2052 }
2053 /* skip the flush */
2054 }
2055
2056 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2057 {
2058 struct ixgbe_q_vector *q_vector = data;
2059 struct ixgbe_adapter *adapter = q_vector->adapter;
2060 struct ixgbe_ring *tx_ring;
2061 int i, r_idx;
2062
2063 if (!q_vector->txr_count)
2064 return IRQ_HANDLED;
2065
2066 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2067 for (i = 0; i < q_vector->txr_count; i++) {
2068 tx_ring = adapter->tx_ring[r_idx];
2069 tx_ring->total_bytes = 0;
2070 tx_ring->total_packets = 0;
2071 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2072 r_idx + 1);
2073 }
2074
2075 /* EIAM disabled interrupts (on this vector) for us */
2076 napi_schedule(&q_vector->napi);
2077
2078 return IRQ_HANDLED;
2079 }
2080
2081 /**
2082 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2083 * @irq: unused
2084 * @data: pointer to our q_vector struct for this interrupt vector
2085 **/
2086 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2087 {
2088 struct ixgbe_q_vector *q_vector = data;
2089 struct ixgbe_adapter *adapter = q_vector->adapter;
2090 struct ixgbe_ring *rx_ring;
2091 int r_idx;
2092 int i;
2093
2094 #ifdef CONFIG_IXGBE_DCA
2095 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2096 ixgbe_update_dca(q_vector);
2097 #endif
2098
2099 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2100 for (i = 0; i < q_vector->rxr_count; i++) {
2101 rx_ring = adapter->rx_ring[r_idx];
2102 rx_ring->total_bytes = 0;
2103 rx_ring->total_packets = 0;
2104 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2105 r_idx + 1);
2106 }
2107
2108 if (!q_vector->rxr_count)
2109 return IRQ_HANDLED;
2110
2111 /* EIAM disabled interrupts (on this vector) for us */
2112 napi_schedule(&q_vector->napi);
2113
2114 return IRQ_HANDLED;
2115 }
2116
2117 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2118 {
2119 struct ixgbe_q_vector *q_vector = data;
2120 struct ixgbe_adapter *adapter = q_vector->adapter;
2121 struct ixgbe_ring *ring;
2122 int r_idx;
2123 int i;
2124
2125 if (!q_vector->txr_count && !q_vector->rxr_count)
2126 return IRQ_HANDLED;
2127
2128 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2129 for (i = 0; i < q_vector->txr_count; i++) {
2130 ring = adapter->tx_ring[r_idx];
2131 ring->total_bytes = 0;
2132 ring->total_packets = 0;
2133 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2134 r_idx + 1);
2135 }
2136
2137 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2138 for (i = 0; i < q_vector->rxr_count; i++) {
2139 ring = adapter->rx_ring[r_idx];
2140 ring->total_bytes = 0;
2141 ring->total_packets = 0;
2142 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2143 r_idx + 1);
2144 }
2145
2146 /* EIAM disabled interrupts (on this vector) for us */
2147 napi_schedule(&q_vector->napi);
2148
2149 return IRQ_HANDLED;
2150 }
2151
2152 /**
2153 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2154 * @napi: napi struct with our devices info in it
2155 * @budget: amount of work driver is allowed to do this pass, in packets
2156 *
2157 * This function is optimized for cleaning one queue only on a single
2158 * q_vector!!!
2159 **/
2160 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2161 {
2162 struct ixgbe_q_vector *q_vector =
2163 container_of(napi, struct ixgbe_q_vector, napi);
2164 struct ixgbe_adapter *adapter = q_vector->adapter;
2165 struct ixgbe_ring *rx_ring = NULL;
2166 int work_done = 0;
2167 long r_idx;
2168
2169 #ifdef CONFIG_IXGBE_DCA
2170 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2171 ixgbe_update_dca(q_vector);
2172 #endif
2173
2174 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2175 rx_ring = adapter->rx_ring[r_idx];
2176
2177 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2178
2179 /* If all Rx work done, exit the polling mode */
2180 if (work_done < budget) {
2181 napi_complete(napi);
2182 if (adapter->rx_itr_setting & 1)
2183 ixgbe_set_itr_msix(q_vector);
2184 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2185 ixgbe_irq_enable_queues(adapter,
2186 ((u64)1 << q_vector->v_idx));
2187 }
2188
2189 return work_done;
2190 }
2191
2192 /**
2193 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2194 * @napi: napi struct with our devices info in it
2195 * @budget: amount of work driver is allowed to do this pass, in packets
2196 *
2197 * This function will clean more than one rx queue associated with a
2198 * q_vector.
2199 **/
2200 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2201 {
2202 struct ixgbe_q_vector *q_vector =
2203 container_of(napi, struct ixgbe_q_vector, napi);
2204 struct ixgbe_adapter *adapter = q_vector->adapter;
2205 struct ixgbe_ring *ring = NULL;
2206 int work_done = 0, i;
2207 long r_idx;
2208 bool tx_clean_complete = true;
2209
2210 #ifdef CONFIG_IXGBE_DCA
2211 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2212 ixgbe_update_dca(q_vector);
2213 #endif
2214
2215 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2216 for (i = 0; i < q_vector->txr_count; i++) {
2217 ring = adapter->tx_ring[r_idx];
2218 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2219 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2220 r_idx + 1);
2221 }
2222
2223 /* attempt to distribute budget to each queue fairly, but don't allow
2224 * the budget to go below 1 because we'll exit polling */
2225 budget /= (q_vector->rxr_count ?: 1);
2226 budget = max(budget, 1);
2227 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2228 for (i = 0; i < q_vector->rxr_count; i++) {
2229 ring = adapter->rx_ring[r_idx];
2230 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2231 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2232 r_idx + 1);
2233 }
2234
2235 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2236 ring = adapter->rx_ring[r_idx];
2237 /* If all Rx work done, exit the polling mode */
2238 if (work_done < budget) {
2239 napi_complete(napi);
2240 if (adapter->rx_itr_setting & 1)
2241 ixgbe_set_itr_msix(q_vector);
2242 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2243 ixgbe_irq_enable_queues(adapter,
2244 ((u64)1 << q_vector->v_idx));
2245 return 0;
2246 }
2247
2248 return work_done;
2249 }
2250
2251 /**
2252 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2253 * @napi: napi struct with our devices info in it
2254 * @budget: amount of work driver is allowed to do this pass, in packets
2255 *
2256 * This function is optimized for cleaning one queue only on a single
2257 * q_vector!!!
2258 **/
2259 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2260 {
2261 struct ixgbe_q_vector *q_vector =
2262 container_of(napi, struct ixgbe_q_vector, napi);
2263 struct ixgbe_adapter *adapter = q_vector->adapter;
2264 struct ixgbe_ring *tx_ring = NULL;
2265 int work_done = 0;
2266 long r_idx;
2267
2268 #ifdef CONFIG_IXGBE_DCA
2269 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2270 ixgbe_update_dca(q_vector);
2271 #endif
2272
2273 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2274 tx_ring = adapter->tx_ring[r_idx];
2275
2276 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2277 work_done = budget;
2278
2279 /* If all Tx work done, exit the polling mode */
2280 if (work_done < budget) {
2281 napi_complete(napi);
2282 if (adapter->tx_itr_setting & 1)
2283 ixgbe_set_itr_msix(q_vector);
2284 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2285 ixgbe_irq_enable_queues(adapter,
2286 ((u64)1 << q_vector->v_idx));
2287 }
2288
2289 return work_done;
2290 }
2291
2292 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2293 int r_idx)
2294 {
2295 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2296 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2297
2298 set_bit(r_idx, q_vector->rxr_idx);
2299 q_vector->rxr_count++;
2300 rx_ring->q_vector = q_vector;
2301 }
2302
2303 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2304 int t_idx)
2305 {
2306 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2307 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2308
2309 set_bit(t_idx, q_vector->txr_idx);
2310 q_vector->txr_count++;
2311 tx_ring->q_vector = q_vector;
2312 }
2313
2314 /**
2315 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2316 * @adapter: board private structure to initialize
2317 *
2318 * This function maps descriptor rings to the queue-specific vectors
2319 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2320 * one vector per ring/queue, but on a constrained vector budget, we
2321 * group the rings as "efficiently" as possible. You would add new
2322 * mapping configurations in here.
2323 **/
2324 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2325 {
2326 int q_vectors;
2327 int v_start = 0;
2328 int rxr_idx = 0, txr_idx = 0;
2329 int rxr_remaining = adapter->num_rx_queues;
2330 int txr_remaining = adapter->num_tx_queues;
2331 int i, j;
2332 int rqpv, tqpv;
2333 int err = 0;
2334
2335 /* No mapping required if MSI-X is disabled. */
2336 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2337 goto out;
2338
2339 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2340
2341 /*
2342 * The ideal configuration...
2343 * We have enough vectors to map one per queue.
2344 */
2345 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2346 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2347 map_vector_to_rxq(adapter, v_start, rxr_idx);
2348
2349 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2350 map_vector_to_txq(adapter, v_start, txr_idx);
2351
2352 goto out;
2353 }
2354
2355 /*
2356 * If we don't have enough vectors for a 1-to-1
2357 * mapping, we'll have to group them so there are
2358 * multiple queues per vector.
2359 */
2360 /* Re-adjusting *qpv takes care of the remainder. */
2361 for (i = v_start; i < q_vectors; i++) {
2362 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2363 for (j = 0; j < rqpv; j++) {
2364 map_vector_to_rxq(adapter, i, rxr_idx);
2365 rxr_idx++;
2366 rxr_remaining--;
2367 }
2368 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2369 for (j = 0; j < tqpv; j++) {
2370 map_vector_to_txq(adapter, i, txr_idx);
2371 txr_idx++;
2372 txr_remaining--;
2373 }
2374 }
2375 out:
2376 return err;
2377 }
2378
2379 /**
2380 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2381 * @adapter: board private structure
2382 *
2383 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2384 * interrupts from the kernel.
2385 **/
2386 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2387 {
2388 struct net_device *netdev = adapter->netdev;
2389 irqreturn_t (*handler)(int, void *);
2390 int i, vector, q_vectors, err;
2391 int ri = 0, ti = 0;
2392
2393 /* Decrement for Other and TCP Timer vectors */
2394 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2395
2396 err = ixgbe_map_rings_to_vectors(adapter);
2397 if (err)
2398 return err;
2399
2400 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2401 ? &ixgbe_msix_clean_many : \
2402 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2403 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2404 NULL)
2405 for (vector = 0; vector < q_vectors; vector++) {
2406 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2407 handler = SET_HANDLER(q_vector);
2408
2409 if (handler == &ixgbe_msix_clean_rx) {
2410 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2411 "%s-%s-%d", netdev->name, "rx", ri++);
2412 } else if (handler == &ixgbe_msix_clean_tx) {
2413 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2414 "%s-%s-%d", netdev->name, "tx", ti++);
2415 } else if (handler == &ixgbe_msix_clean_many) {
2416 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2417 "%s-%s-%d", netdev->name, "TxRx", ri++);
2418 ti++;
2419 } else {
2420 /* skip this unused q_vector */
2421 continue;
2422 }
2423 err = request_irq(adapter->msix_entries[vector].vector,
2424 handler, 0, q_vector->name,
2425 q_vector);
2426 if (err) {
2427 e_err(probe, "request_irq failed for MSIX interrupt "
2428 "Error: %d\n", err);
2429 goto free_queue_irqs;
2430 }
2431 }
2432
2433 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2434 err = request_irq(adapter->msix_entries[vector].vector,
2435 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2436 if (err) {
2437 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2438 goto free_queue_irqs;
2439 }
2440
2441 return 0;
2442
2443 free_queue_irqs:
2444 for (i = vector - 1; i >= 0; i--)
2445 free_irq(adapter->msix_entries[--vector].vector,
2446 adapter->q_vector[i]);
2447 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2448 pci_disable_msix(adapter->pdev);
2449 kfree(adapter->msix_entries);
2450 adapter->msix_entries = NULL;
2451 return err;
2452 }
2453
2454 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2455 {
2456 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2457 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2458 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2459 u32 new_itr = q_vector->eitr;
2460 u8 current_itr;
2461
2462 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2463 q_vector->tx_itr,
2464 tx_ring->total_packets,
2465 tx_ring->total_bytes);
2466 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2467 q_vector->rx_itr,
2468 rx_ring->total_packets,
2469 rx_ring->total_bytes);
2470
2471 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2472
2473 switch (current_itr) {
2474 /* counts and packets in update_itr are dependent on these numbers */
2475 case lowest_latency:
2476 new_itr = 100000;
2477 break;
2478 case low_latency:
2479 new_itr = 20000; /* aka hwitr = ~200 */
2480 break;
2481 case bulk_latency:
2482 new_itr = 8000;
2483 break;
2484 default:
2485 break;
2486 }
2487
2488 if (new_itr != q_vector->eitr) {
2489 /* do an exponential smoothing */
2490 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2491
2492 /* save the algorithm value here */
2493 q_vector->eitr = new_itr;
2494
2495 ixgbe_write_eitr(q_vector);
2496 }
2497 }
2498
2499 /**
2500 * ixgbe_irq_enable - Enable default interrupt generation settings
2501 * @adapter: board private structure
2502 **/
2503 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2504 bool flush)
2505 {
2506 u32 mask;
2507
2508 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2509 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2510 mask |= IXGBE_EIMS_GPI_SDP0;
2511 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2512 mask |= IXGBE_EIMS_GPI_SDP1;
2513 switch (adapter->hw.mac.type) {
2514 case ixgbe_mac_82599EB:
2515 case ixgbe_mac_X540:
2516 mask |= IXGBE_EIMS_ECC;
2517 mask |= IXGBE_EIMS_GPI_SDP1;
2518 mask |= IXGBE_EIMS_GPI_SDP2;
2519 if (adapter->num_vfs)
2520 mask |= IXGBE_EIMS_MAILBOX;
2521 break;
2522 default:
2523 break;
2524 }
2525 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2526 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2527 mask |= IXGBE_EIMS_FLOW_DIR;
2528
2529 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2530 if (queues)
2531 ixgbe_irq_enable_queues(adapter, ~0);
2532 if (flush)
2533 IXGBE_WRITE_FLUSH(&adapter->hw);
2534
2535 if (adapter->num_vfs > 32) {
2536 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2537 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2538 }
2539 }
2540
2541 /**
2542 * ixgbe_intr - legacy mode Interrupt Handler
2543 * @irq: interrupt number
2544 * @data: pointer to a network interface device structure
2545 **/
2546 static irqreturn_t ixgbe_intr(int irq, void *data)
2547 {
2548 struct net_device *netdev = data;
2549 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2550 struct ixgbe_hw *hw = &adapter->hw;
2551 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2552 u32 eicr;
2553
2554 /*
2555 * Workaround for silicon errata on 82598. Mask the interrupts
2556 * before the read of EICR.
2557 */
2558 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2559
2560 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2561 * therefore no explict interrupt disable is necessary */
2562 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2563 if (!eicr) {
2564 /*
2565 * shared interrupt alert!
2566 * make sure interrupts are enabled because the read will
2567 * have disabled interrupts due to EIAM
2568 * finish the workaround of silicon errata on 82598. Unmask
2569 * the interrupt that we masked before the EICR read.
2570 */
2571 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2572 ixgbe_irq_enable(adapter, true, true);
2573 return IRQ_NONE; /* Not our interrupt */
2574 }
2575
2576 if (eicr & IXGBE_EICR_LSC)
2577 ixgbe_check_lsc(adapter);
2578
2579 switch (hw->mac.type) {
2580 case ixgbe_mac_82599EB:
2581 ixgbe_check_sfp_event(adapter, eicr);
2582 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2583 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2584 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2585 adapter->interrupt_event = eicr;
2586 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2587 ixgbe_service_event_schedule(adapter);
2588 }
2589 }
2590 break;
2591 default:
2592 break;
2593 }
2594
2595 ixgbe_check_fan_failure(adapter, eicr);
2596
2597 if (napi_schedule_prep(&(q_vector->napi))) {
2598 adapter->tx_ring[0]->total_packets = 0;
2599 adapter->tx_ring[0]->total_bytes = 0;
2600 adapter->rx_ring[0]->total_packets = 0;
2601 adapter->rx_ring[0]->total_bytes = 0;
2602 /* would disable interrupts here but EIAM disabled it */
2603 __napi_schedule(&(q_vector->napi));
2604 }
2605
2606 /*
2607 * re-enable link(maybe) and non-queue interrupts, no flush.
2608 * ixgbe_poll will re-enable the queue interrupts
2609 */
2610
2611 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2612 ixgbe_irq_enable(adapter, false, false);
2613
2614 return IRQ_HANDLED;
2615 }
2616
2617 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2618 {
2619 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2620
2621 for (i = 0; i < q_vectors; i++) {
2622 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2623 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2624 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2625 q_vector->rxr_count = 0;
2626 q_vector->txr_count = 0;
2627 }
2628 }
2629
2630 /**
2631 * ixgbe_request_irq - initialize interrupts
2632 * @adapter: board private structure
2633 *
2634 * Attempts to configure interrupts using the best available
2635 * capabilities of the hardware and kernel.
2636 **/
2637 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2638 {
2639 struct net_device *netdev = adapter->netdev;
2640 int err;
2641
2642 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2643 err = ixgbe_request_msix_irqs(adapter);
2644 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2645 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2646 netdev->name, netdev);
2647 } else {
2648 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2649 netdev->name, netdev);
2650 }
2651
2652 if (err)
2653 e_err(probe, "request_irq failed, Error %d\n", err);
2654
2655 return err;
2656 }
2657
2658 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2659 {
2660 struct net_device *netdev = adapter->netdev;
2661
2662 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2663 int i, q_vectors;
2664
2665 q_vectors = adapter->num_msix_vectors;
2666
2667 i = q_vectors - 1;
2668 free_irq(adapter->msix_entries[i].vector, netdev);
2669
2670 i--;
2671 for (; i >= 0; i--) {
2672 /* free only the irqs that were actually requested */
2673 if (!adapter->q_vector[i]->rxr_count &&
2674 !adapter->q_vector[i]->txr_count)
2675 continue;
2676
2677 free_irq(adapter->msix_entries[i].vector,
2678 adapter->q_vector[i]);
2679 }
2680
2681 ixgbe_reset_q_vectors(adapter);
2682 } else {
2683 free_irq(adapter->pdev->irq, netdev);
2684 }
2685 }
2686
2687 /**
2688 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2689 * @adapter: board private structure
2690 **/
2691 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2692 {
2693 switch (adapter->hw.mac.type) {
2694 case ixgbe_mac_82598EB:
2695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2696 break;
2697 case ixgbe_mac_82599EB:
2698 case ixgbe_mac_X540:
2699 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2700 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2701 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2702 if (adapter->num_vfs > 32)
2703 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2704 break;
2705 default:
2706 break;
2707 }
2708 IXGBE_WRITE_FLUSH(&adapter->hw);
2709 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2710 int i;
2711 for (i = 0; i < adapter->num_msix_vectors; i++)
2712 synchronize_irq(adapter->msix_entries[i].vector);
2713 } else {
2714 synchronize_irq(adapter->pdev->irq);
2715 }
2716 }
2717
2718 /**
2719 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2720 *
2721 **/
2722 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2723 {
2724 struct ixgbe_hw *hw = &adapter->hw;
2725
2726 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2727 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2728
2729 ixgbe_set_ivar(adapter, 0, 0, 0);
2730 ixgbe_set_ivar(adapter, 1, 0, 0);
2731
2732 map_vector_to_rxq(adapter, 0, 0);
2733 map_vector_to_txq(adapter, 0, 0);
2734
2735 e_info(hw, "Legacy interrupt IVAR setup done\n");
2736 }
2737
2738 /**
2739 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2740 * @adapter: board private structure
2741 * @ring: structure containing ring specific data
2742 *
2743 * Configure the Tx descriptor ring after a reset.
2744 **/
2745 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2746 struct ixgbe_ring *ring)
2747 {
2748 struct ixgbe_hw *hw = &adapter->hw;
2749 u64 tdba = ring->dma;
2750 int wait_loop = 10;
2751 u32 txdctl;
2752 u8 reg_idx = ring->reg_idx;
2753
2754 /* disable queue to avoid issues while updating state */
2755 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2756 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2757 txdctl & ~IXGBE_TXDCTL_ENABLE);
2758 IXGBE_WRITE_FLUSH(hw);
2759
2760 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2761 (tdba & DMA_BIT_MASK(32)));
2762 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2763 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2764 ring->count * sizeof(union ixgbe_adv_tx_desc));
2765 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2766 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2767 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2768
2769 /* configure fetching thresholds */
2770 if (adapter->rx_itr_setting == 0) {
2771 /* cannot set wthresh when itr==0 */
2772 txdctl &= ~0x007F0000;
2773 } else {
2774 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2775 txdctl |= (8 << 16);
2776 }
2777 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2778 /* PThresh workaround for Tx hang with DFP enabled. */
2779 txdctl |= 32;
2780 }
2781
2782 /* reinitialize flowdirector state */
2783 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2784 adapter->atr_sample_rate) {
2785 ring->atr_sample_rate = adapter->atr_sample_rate;
2786 ring->atr_count = 0;
2787 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2788 } else {
2789 ring->atr_sample_rate = 0;
2790 }
2791
2792 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2793
2794 /* enable queue */
2795 txdctl |= IXGBE_TXDCTL_ENABLE;
2796 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2797
2798 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2799 if (hw->mac.type == ixgbe_mac_82598EB &&
2800 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2801 return;
2802
2803 /* poll to verify queue is enabled */
2804 do {
2805 usleep_range(1000, 2000);
2806 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2807 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2808 if (!wait_loop)
2809 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2810 }
2811
2812 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2813 {
2814 struct ixgbe_hw *hw = &adapter->hw;
2815 u32 rttdcs;
2816 u32 mask;
2817
2818 if (hw->mac.type == ixgbe_mac_82598EB)
2819 return;
2820
2821 /* disable the arbiter while setting MTQC */
2822 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2823 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2824 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2825
2826 /* set transmit pool layout */
2827 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2828 switch (adapter->flags & mask) {
2829
2830 case (IXGBE_FLAG_SRIOV_ENABLED):
2831 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2832 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2833 break;
2834
2835 case (IXGBE_FLAG_DCB_ENABLED):
2836 /* We enable 8 traffic classes, DCB only */
2837 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2838 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2839 break;
2840
2841 default:
2842 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2843 break;
2844 }
2845
2846 /* re-enable the arbiter */
2847 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2848 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2849 }
2850
2851 /**
2852 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2853 * @adapter: board private structure
2854 *
2855 * Configure the Tx unit of the MAC after a reset.
2856 **/
2857 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2858 {
2859 struct ixgbe_hw *hw = &adapter->hw;
2860 u32 dmatxctl;
2861 u32 i;
2862
2863 ixgbe_setup_mtqc(adapter);
2864
2865 if (hw->mac.type != ixgbe_mac_82598EB) {
2866 /* DMATXCTL.EN must be before Tx queues are enabled */
2867 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2868 dmatxctl |= IXGBE_DMATXCTL_TE;
2869 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2870 }
2871
2872 /* Setup the HW Tx Head and Tail descriptor pointers */
2873 for (i = 0; i < adapter->num_tx_queues; i++)
2874 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2875 }
2876
2877 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2878
2879 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2880 struct ixgbe_ring *rx_ring)
2881 {
2882 u32 srrctl;
2883 u8 reg_idx = rx_ring->reg_idx;
2884
2885 switch (adapter->hw.mac.type) {
2886 case ixgbe_mac_82598EB: {
2887 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2888 const int mask = feature[RING_F_RSS].mask;
2889 reg_idx = reg_idx & mask;
2890 }
2891 break;
2892 case ixgbe_mac_82599EB:
2893 case ixgbe_mac_X540:
2894 default:
2895 break;
2896 }
2897
2898 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2899
2900 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2901 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2902 if (adapter->num_vfs)
2903 srrctl |= IXGBE_SRRCTL_DROP_EN;
2904
2905 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2906 IXGBE_SRRCTL_BSIZEHDR_MASK;
2907
2908 if (ring_is_ps_enabled(rx_ring)) {
2909 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2910 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2911 #else
2912 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2913 #endif
2914 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2915 } else {
2916 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2917 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2918 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2919 }
2920
2921 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2922 }
2923
2924 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2925 {
2926 struct ixgbe_hw *hw = &adapter->hw;
2927 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2928 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2929 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2930 u32 mrqc = 0, reta = 0;
2931 u32 rxcsum;
2932 int i, j;
2933 int mask;
2934
2935 /* Fill out hash function seeds */
2936 for (i = 0; i < 10; i++)
2937 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2938
2939 /* Fill out redirection table */
2940 for (i = 0, j = 0; i < 128; i++, j++) {
2941 if (j == adapter->ring_feature[RING_F_RSS].indices)
2942 j = 0;
2943 /* reta = 4-byte sliding window of
2944 * 0x00..(indices-1)(indices-1)00..etc. */
2945 reta = (reta << 8) | (j * 0x11);
2946 if ((i & 3) == 3)
2947 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2948 }
2949
2950 /* Disable indicating checksum in descriptor, enables RSS hash */
2951 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2952 rxcsum |= IXGBE_RXCSUM_PCSD;
2953 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2954
2955 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2956 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2957 else
2958 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2959 #ifdef CONFIG_IXGBE_DCB
2960 | IXGBE_FLAG_DCB_ENABLED
2961 #endif
2962 | IXGBE_FLAG_SRIOV_ENABLED
2963 );
2964
2965 switch (mask) {
2966 #ifdef CONFIG_IXGBE_DCB
2967 case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2968 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2969 break;
2970 case (IXGBE_FLAG_DCB_ENABLED):
2971 mrqc = IXGBE_MRQC_RT8TCEN;
2972 break;
2973 #endif /* CONFIG_IXGBE_DCB */
2974 case (IXGBE_FLAG_RSS_ENABLED):
2975 mrqc = IXGBE_MRQC_RSSEN;
2976 break;
2977 case (IXGBE_FLAG_SRIOV_ENABLED):
2978 mrqc = IXGBE_MRQC_VMDQEN;
2979 break;
2980 default:
2981 break;
2982 }
2983
2984 /* Perform hash on these packet types */
2985 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2986 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2987 | IXGBE_MRQC_RSS_FIELD_IPV6
2988 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2989
2990 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2991 }
2992
2993 /**
2994 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2995 * @adapter: address of board private structure
2996 * @ring: structure containing ring specific data
2997 **/
2998 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2999 struct ixgbe_ring *ring)
3000 {
3001 struct ixgbe_hw *hw = &adapter->hw;
3002 u32 rscctrl;
3003 u8 reg_idx = ring->reg_idx;
3004
3005 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3006 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
3007 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3008 }
3009
3010 /**
3011 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3012 * @adapter: address of board private structure
3013 * @index: index of ring to set
3014 **/
3015 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3016 struct ixgbe_ring *ring)
3017 {
3018 struct ixgbe_hw *hw = &adapter->hw;
3019 u32 rscctrl;
3020 int rx_buf_len;
3021 u8 reg_idx = ring->reg_idx;
3022
3023 if (!ring_is_rsc_enabled(ring))
3024 return;
3025
3026 rx_buf_len = ring->rx_buf_len;
3027 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3028 rscctrl |= IXGBE_RSCCTL_RSCEN;
3029 /*
3030 * we must limit the number of descriptors so that the
3031 * total size of max desc * buf_len is not greater
3032 * than 65535
3033 */
3034 if (ring_is_ps_enabled(ring)) {
3035 #if (MAX_SKB_FRAGS > 16)
3036 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3037 #elif (MAX_SKB_FRAGS > 8)
3038 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3039 #elif (MAX_SKB_FRAGS > 4)
3040 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3041 #else
3042 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
3043 #endif
3044 } else {
3045 if (rx_buf_len < IXGBE_RXBUFFER_4096)
3046 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3047 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
3048 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3049 else
3050 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3051 }
3052 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3053 }
3054
3055 /**
3056 * ixgbe_set_uta - Set unicast filter table address
3057 * @adapter: board private structure
3058 *
3059 * The unicast table address is a register array of 32-bit registers.
3060 * The table is meant to be used in a way similar to how the MTA is used
3061 * however due to certain limitations in the hardware it is necessary to
3062 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3063 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3064 **/
3065 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3066 {
3067 struct ixgbe_hw *hw = &adapter->hw;
3068 int i;
3069
3070 /* The UTA table only exists on 82599 hardware and newer */
3071 if (hw->mac.type < ixgbe_mac_82599EB)
3072 return;
3073
3074 /* we only need to do this if VMDq is enabled */
3075 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3076 return;
3077
3078 for (i = 0; i < 128; i++)
3079 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3080 }
3081
3082 #define IXGBE_MAX_RX_DESC_POLL 10
3083 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3084 struct ixgbe_ring *ring)
3085 {
3086 struct ixgbe_hw *hw = &adapter->hw;
3087 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3088 u32 rxdctl;
3089 u8 reg_idx = ring->reg_idx;
3090
3091 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3092 if (hw->mac.type == ixgbe_mac_82598EB &&
3093 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3094 return;
3095
3096 do {
3097 usleep_range(1000, 2000);
3098 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3099 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3100
3101 if (!wait_loop) {
3102 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3103 "the polling period\n", reg_idx);
3104 }
3105 }
3106
3107 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3108 struct ixgbe_ring *ring)
3109 {
3110 struct ixgbe_hw *hw = &adapter->hw;
3111 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3112 u32 rxdctl;
3113 u8 reg_idx = ring->reg_idx;
3114
3115 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3116 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3117
3118 /* write value back with RXDCTL.ENABLE bit cleared */
3119 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3120
3121 if (hw->mac.type == ixgbe_mac_82598EB &&
3122 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3123 return;
3124
3125 /* the hardware may take up to 100us to really disable the rx queue */
3126 do {
3127 udelay(10);
3128 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3129 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3130
3131 if (!wait_loop) {
3132 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3133 "the polling period\n", reg_idx);
3134 }
3135 }
3136
3137 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3138 struct ixgbe_ring *ring)
3139 {
3140 struct ixgbe_hw *hw = &adapter->hw;
3141 u64 rdba = ring->dma;
3142 u32 rxdctl;
3143 u8 reg_idx = ring->reg_idx;
3144
3145 /* disable queue to avoid issues while updating state */
3146 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3147 ixgbe_disable_rx_queue(adapter, ring);
3148
3149 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3150 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3151 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3152 ring->count * sizeof(union ixgbe_adv_rx_desc));
3153 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3154 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3155 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3156
3157 ixgbe_configure_srrctl(adapter, ring);
3158 ixgbe_configure_rscctl(adapter, ring);
3159
3160 /* If operating in IOV mode set RLPML for X540 */
3161 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3162 hw->mac.type == ixgbe_mac_X540) {
3163 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3164 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3165 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3166 }
3167
3168 if (hw->mac.type == ixgbe_mac_82598EB) {
3169 /*
3170 * enable cache line friendly hardware writes:
3171 * PTHRESH=32 descriptors (half the internal cache),
3172 * this also removes ugly rx_no_buffer_count increment
3173 * HTHRESH=4 descriptors (to minimize latency on fetch)
3174 * WTHRESH=8 burst writeback up to two cache lines
3175 */
3176 rxdctl &= ~0x3FFFFF;
3177 rxdctl |= 0x080420;
3178 }
3179
3180 /* enable receive descriptor ring */
3181 rxdctl |= IXGBE_RXDCTL_ENABLE;
3182 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3183
3184 ixgbe_rx_desc_queue_enable(adapter, ring);
3185 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3186 }
3187
3188 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3189 {
3190 struct ixgbe_hw *hw = &adapter->hw;
3191 int p;
3192
3193 /* PSRTYPE must be initialized in non 82598 adapters */
3194 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3195 IXGBE_PSRTYPE_UDPHDR |
3196 IXGBE_PSRTYPE_IPV4HDR |
3197 IXGBE_PSRTYPE_L2HDR |
3198 IXGBE_PSRTYPE_IPV6HDR;
3199
3200 if (hw->mac.type == ixgbe_mac_82598EB)
3201 return;
3202
3203 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3204 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3205
3206 for (p = 0; p < adapter->num_rx_pools; p++)
3207 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3208 psrtype);
3209 }
3210
3211 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3212 {
3213 struct ixgbe_hw *hw = &adapter->hw;
3214 u32 gcr_ext;
3215 u32 vt_reg_bits;
3216 u32 reg_offset, vf_shift;
3217 u32 vmdctl;
3218
3219 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3220 return;
3221
3222 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3223 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3224 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3225 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3226
3227 vf_shift = adapter->num_vfs % 32;
3228 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3229
3230 /* Enable only the PF's pool for Tx/Rx */
3231 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3232 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3233 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3234 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3235 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3236
3237 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3238 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3239
3240 /*
3241 * Set up VF register offsets for selected VT Mode,
3242 * i.e. 32 or 64 VFs for SR-IOV
3243 */
3244 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3245 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3246 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3247 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3248
3249 /* enable Tx loopback for VF/PF communication */
3250 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3251 /* Enable MAC Anti-Spoofing */
3252 hw->mac.ops.set_mac_anti_spoofing(hw,
3253 (adapter->antispoofing_enabled =
3254 (adapter->num_vfs != 0)),
3255 adapter->num_vfs);
3256 }
3257
3258 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3259 {
3260 struct ixgbe_hw *hw = &adapter->hw;
3261 struct net_device *netdev = adapter->netdev;
3262 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3263 int rx_buf_len;
3264 struct ixgbe_ring *rx_ring;
3265 int i;
3266 u32 mhadd, hlreg0;
3267
3268 /* Decide whether to use packet split mode or not */
3269 /* On by default */
3270 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3271
3272 /* Do not use packet split if we're in SR-IOV Mode */
3273 if (adapter->num_vfs)
3274 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3275
3276 /* Disable packet split due to 82599 erratum #45 */
3277 if (hw->mac.type == ixgbe_mac_82599EB)
3278 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3279
3280 /* Set the RX buffer length according to the mode */
3281 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3282 rx_buf_len = IXGBE_RX_HDR_SIZE;
3283 } else {
3284 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3285 (netdev->mtu <= ETH_DATA_LEN))
3286 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3287 else
3288 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3289 }
3290
3291 #ifdef IXGBE_FCOE
3292 /* adjust max frame to be able to do baby jumbo for FCoE */
3293 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3294 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3295 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3296
3297 #endif /* IXGBE_FCOE */
3298 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3299 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3300 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3301 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3302
3303 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3304 }
3305
3306 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3307 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3308 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3309 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3310
3311 /*
3312 * Setup the HW Rx Head and Tail Descriptor Pointers and
3313 * the Base and Length of the Rx Descriptor Ring
3314 */
3315 for (i = 0; i < adapter->num_rx_queues; i++) {
3316 rx_ring = adapter->rx_ring[i];
3317 rx_ring->rx_buf_len = rx_buf_len;
3318
3319 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3320 set_ring_ps_enabled(rx_ring);
3321 else
3322 clear_ring_ps_enabled(rx_ring);
3323
3324 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3325 set_ring_rsc_enabled(rx_ring);
3326 else
3327 clear_ring_rsc_enabled(rx_ring);
3328
3329 #ifdef IXGBE_FCOE
3330 if (netdev->features & NETIF_F_FCOE_MTU) {
3331 struct ixgbe_ring_feature *f;
3332 f = &adapter->ring_feature[RING_F_FCOE];
3333 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3334 clear_ring_ps_enabled(rx_ring);
3335 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3336 rx_ring->rx_buf_len =
3337 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3338 } else if (!ring_is_rsc_enabled(rx_ring) &&
3339 !ring_is_ps_enabled(rx_ring)) {
3340 rx_ring->rx_buf_len =
3341 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3342 }
3343 }
3344 #endif /* IXGBE_FCOE */
3345 }
3346 }
3347
3348 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3349 {
3350 struct ixgbe_hw *hw = &adapter->hw;
3351 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3352
3353 switch (hw->mac.type) {
3354 case ixgbe_mac_82598EB:
3355 /*
3356 * For VMDq support of different descriptor types or
3357 * buffer sizes through the use of multiple SRRCTL
3358 * registers, RDRXCTL.MVMEN must be set to 1
3359 *
3360 * also, the manual doesn't mention it clearly but DCA hints
3361 * will only use queue 0's tags unless this bit is set. Side
3362 * effects of setting this bit are only that SRRCTL must be
3363 * fully programmed [0..15]
3364 */
3365 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3366 break;
3367 case ixgbe_mac_82599EB:
3368 case ixgbe_mac_X540:
3369 /* Disable RSC for ACK packets */
3370 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3371 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3372 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3373 /* hardware requires some bits to be set by default */
3374 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3375 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3376 break;
3377 default:
3378 /* We should do nothing since we don't know this hardware */
3379 return;
3380 }
3381
3382 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3383 }
3384
3385 /**
3386 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3387 * @adapter: board private structure
3388 *
3389 * Configure the Rx unit of the MAC after a reset.
3390 **/
3391 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3392 {
3393 struct ixgbe_hw *hw = &adapter->hw;
3394 int i;
3395 u32 rxctrl;
3396
3397 /* disable receives while setting up the descriptors */
3398 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3399 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3400
3401 ixgbe_setup_psrtype(adapter);
3402 ixgbe_setup_rdrxctl(adapter);
3403
3404 /* Program registers for the distribution of queues */
3405 ixgbe_setup_mrqc(adapter);
3406
3407 ixgbe_set_uta(adapter);
3408
3409 /* set_rx_buffer_len must be called before ring initialization */
3410 ixgbe_set_rx_buffer_len(adapter);
3411
3412 /*
3413 * Setup the HW Rx Head and Tail Descriptor Pointers and
3414 * the Base and Length of the Rx Descriptor Ring
3415 */
3416 for (i = 0; i < adapter->num_rx_queues; i++)
3417 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3418
3419 /* disable drop enable for 82598 parts */
3420 if (hw->mac.type == ixgbe_mac_82598EB)
3421 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3422
3423 /* enable all receives */
3424 rxctrl |= IXGBE_RXCTRL_RXEN;
3425 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3426 }
3427
3428 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3429 {
3430 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3431 struct ixgbe_hw *hw = &adapter->hw;
3432 int pool_ndx = adapter->num_vfs;
3433
3434 /* add VID to filter table */
3435 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3436 set_bit(vid, adapter->active_vlans);
3437 }
3438
3439 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3440 {
3441 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3442 struct ixgbe_hw *hw = &adapter->hw;
3443 int pool_ndx = adapter->num_vfs;
3444
3445 /* remove VID from filter table */
3446 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3447 clear_bit(vid, adapter->active_vlans);
3448 }
3449
3450 /**
3451 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3452 * @adapter: driver data
3453 */
3454 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3455 {
3456 struct ixgbe_hw *hw = &adapter->hw;
3457 u32 vlnctrl;
3458
3459 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3460 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3461 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3462 }
3463
3464 /**
3465 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3466 * @adapter: driver data
3467 */
3468 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3469 {
3470 struct ixgbe_hw *hw = &adapter->hw;
3471 u32 vlnctrl;
3472
3473 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3474 vlnctrl |= IXGBE_VLNCTRL_VFE;
3475 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3476 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3477 }
3478
3479 /**
3480 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3481 * @adapter: driver data
3482 */
3483 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3484 {
3485 struct ixgbe_hw *hw = &adapter->hw;
3486 u32 vlnctrl;
3487 int i, j;
3488
3489 switch (hw->mac.type) {
3490 case ixgbe_mac_82598EB:
3491 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3492 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3493 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3494 break;
3495 case ixgbe_mac_82599EB:
3496 case ixgbe_mac_X540:
3497 for (i = 0; i < adapter->num_rx_queues; i++) {
3498 j = adapter->rx_ring[i]->reg_idx;
3499 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3500 vlnctrl &= ~IXGBE_RXDCTL_VME;
3501 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3502 }
3503 break;
3504 default:
3505 break;
3506 }
3507 }
3508
3509 /**
3510 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3511 * @adapter: driver data
3512 */
3513 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3514 {
3515 struct ixgbe_hw *hw = &adapter->hw;
3516 u32 vlnctrl;
3517 int i, j;
3518
3519 switch (hw->mac.type) {
3520 case ixgbe_mac_82598EB:
3521 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3522 vlnctrl |= IXGBE_VLNCTRL_VME;
3523 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3524 break;
3525 case ixgbe_mac_82599EB:
3526 case ixgbe_mac_X540:
3527 for (i = 0; i < adapter->num_rx_queues; i++) {
3528 j = adapter->rx_ring[i]->reg_idx;
3529 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3530 vlnctrl |= IXGBE_RXDCTL_VME;
3531 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3532 }
3533 break;
3534 default:
3535 break;
3536 }
3537 }
3538
3539 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3540 {
3541 u16 vid;
3542
3543 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3544
3545 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3546 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3547 }
3548
3549 /**
3550 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3551 * @netdev: network interface device structure
3552 *
3553 * Writes unicast address list to the RAR table.
3554 * Returns: -ENOMEM on failure/insufficient address space
3555 * 0 on no addresses written
3556 * X on writing X addresses to the RAR table
3557 **/
3558 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3559 {
3560 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3561 struct ixgbe_hw *hw = &adapter->hw;
3562 unsigned int vfn = adapter->num_vfs;
3563 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3564 int count = 0;
3565
3566 /* return ENOMEM indicating insufficient memory for addresses */
3567 if (netdev_uc_count(netdev) > rar_entries)
3568 return -ENOMEM;
3569
3570 if (!netdev_uc_empty(netdev) && rar_entries) {
3571 struct netdev_hw_addr *ha;
3572 /* return error if we do not support writing to RAR table */
3573 if (!hw->mac.ops.set_rar)
3574 return -ENOMEM;
3575
3576 netdev_for_each_uc_addr(ha, netdev) {
3577 if (!rar_entries)
3578 break;
3579 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3580 vfn, IXGBE_RAH_AV);
3581 count++;
3582 }
3583 }
3584 /* write the addresses in reverse order to avoid write combining */
3585 for (; rar_entries > 0 ; rar_entries--)
3586 hw->mac.ops.clear_rar(hw, rar_entries);
3587
3588 return count;
3589 }
3590
3591 /**
3592 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3593 * @netdev: network interface device structure
3594 *
3595 * The set_rx_method entry point is called whenever the unicast/multicast
3596 * address list or the network interface flags are updated. This routine is
3597 * responsible for configuring the hardware for proper unicast, multicast and
3598 * promiscuous mode.
3599 **/
3600 void ixgbe_set_rx_mode(struct net_device *netdev)
3601 {
3602 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3603 struct ixgbe_hw *hw = &adapter->hw;
3604 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3605 int count;
3606
3607 /* Check for Promiscuous and All Multicast modes */
3608
3609 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3610
3611 /* set all bits that we expect to always be set */
3612 fctrl |= IXGBE_FCTRL_BAM;
3613 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3614 fctrl |= IXGBE_FCTRL_PMCF;
3615
3616 /* clear the bits we are changing the status of */
3617 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3618
3619 if (netdev->flags & IFF_PROMISC) {
3620 hw->addr_ctrl.user_set_promisc = true;
3621 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3622 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3623 /* don't hardware filter vlans in promisc mode */
3624 ixgbe_vlan_filter_disable(adapter);
3625 } else {
3626 if (netdev->flags & IFF_ALLMULTI) {
3627 fctrl |= IXGBE_FCTRL_MPE;
3628 vmolr |= IXGBE_VMOLR_MPE;
3629 } else {
3630 /*
3631 * Write addresses to the MTA, if the attempt fails
3632 * then we should just turn on promiscuous mode so
3633 * that we can at least receive multicast traffic
3634 */
3635 hw->mac.ops.update_mc_addr_list(hw, netdev);
3636 vmolr |= IXGBE_VMOLR_ROMPE;
3637 }
3638 ixgbe_vlan_filter_enable(adapter);
3639 hw->addr_ctrl.user_set_promisc = false;
3640 /*
3641 * Write addresses to available RAR registers, if there is not
3642 * sufficient space to store all the addresses then enable
3643 * unicast promiscuous mode
3644 */
3645 count = ixgbe_write_uc_addr_list(netdev);
3646 if (count < 0) {
3647 fctrl |= IXGBE_FCTRL_UPE;
3648 vmolr |= IXGBE_VMOLR_ROPE;
3649 }
3650 }
3651
3652 if (adapter->num_vfs) {
3653 ixgbe_restore_vf_multicasts(adapter);
3654 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3655 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3656 IXGBE_VMOLR_ROPE);
3657 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3658 }
3659
3660 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3661
3662 if (netdev->features & NETIF_F_HW_VLAN_RX)
3663 ixgbe_vlan_strip_enable(adapter);
3664 else
3665 ixgbe_vlan_strip_disable(adapter);
3666 }
3667
3668 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3669 {
3670 int q_idx;
3671 struct ixgbe_q_vector *q_vector;
3672 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3673
3674 /* legacy and MSI only use one vector */
3675 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3676 q_vectors = 1;
3677
3678 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3679 struct napi_struct *napi;
3680 q_vector = adapter->q_vector[q_idx];
3681 napi = &q_vector->napi;
3682 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3683 if (!q_vector->rxr_count || !q_vector->txr_count) {
3684 if (q_vector->txr_count == 1)
3685 napi->poll = &ixgbe_clean_txonly;
3686 else if (q_vector->rxr_count == 1)
3687 napi->poll = &ixgbe_clean_rxonly;
3688 }
3689 }
3690
3691 napi_enable(napi);
3692 }
3693 }
3694
3695 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3696 {
3697 int q_idx;
3698 struct ixgbe_q_vector *q_vector;
3699 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3700
3701 /* legacy and MSI only use one vector */
3702 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3703 q_vectors = 1;
3704
3705 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3706 q_vector = adapter->q_vector[q_idx];
3707 napi_disable(&q_vector->napi);
3708 }
3709 }
3710
3711 #ifdef CONFIG_IXGBE_DCB
3712 /*
3713 * ixgbe_configure_dcb - Configure DCB hardware
3714 * @adapter: ixgbe adapter struct
3715 *
3716 * This is called by the driver on open to configure the DCB hardware.
3717 * This is also called by the gennetlink interface when reconfiguring
3718 * the DCB state.
3719 */
3720 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3721 {
3722 struct ixgbe_hw *hw = &adapter->hw;
3723 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3724
3725 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3726 if (hw->mac.type == ixgbe_mac_82598EB)
3727 netif_set_gso_max_size(adapter->netdev, 65536);
3728 return;
3729 }
3730
3731 if (hw->mac.type == ixgbe_mac_82598EB)
3732 netif_set_gso_max_size(adapter->netdev, 32768);
3733
3734
3735 /* Enable VLAN tag insert/strip */
3736 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3737
3738 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3739
3740 /* reconfigure the hardware */
3741 if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) {
3742 #ifdef CONFIG_FCOE
3743 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3744 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3745 #endif
3746 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3747 DCB_TX_CONFIG);
3748 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3749 DCB_RX_CONFIG);
3750 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3751 } else {
3752 struct net_device *dev = adapter->netdev;
3753
3754 if (adapter->ixgbe_ieee_ets)
3755 dev->dcbnl_ops->ieee_setets(dev,
3756 adapter->ixgbe_ieee_ets);
3757 if (adapter->ixgbe_ieee_pfc)
3758 dev->dcbnl_ops->ieee_setpfc(dev,
3759 adapter->ixgbe_ieee_pfc);
3760 }
3761
3762 /* Enable RSS Hash per TC */
3763 if (hw->mac.type != ixgbe_mac_82598EB) {
3764 int i;
3765 u32 reg = 0;
3766
3767 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3768 u8 msb = 0;
3769 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3770
3771 while (cnt >>= 1)
3772 msb++;
3773
3774 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3775 }
3776 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3777 }
3778 }
3779
3780 #endif
3781 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3782 {
3783 struct net_device *netdev = adapter->netdev;
3784 struct ixgbe_hw *hw = &adapter->hw;
3785 int i;
3786
3787 #ifdef CONFIG_IXGBE_DCB
3788 ixgbe_configure_dcb(adapter);
3789 #endif
3790
3791 ixgbe_set_rx_mode(netdev);
3792 ixgbe_restore_vlan(adapter);
3793
3794 #ifdef IXGBE_FCOE
3795 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3796 ixgbe_configure_fcoe(adapter);
3797
3798 #endif /* IXGBE_FCOE */
3799 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3800 for (i = 0; i < adapter->num_tx_queues; i++)
3801 adapter->tx_ring[i]->atr_sample_rate =
3802 adapter->atr_sample_rate;
3803 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3804 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3805 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3806 }
3807 ixgbe_configure_virtualization(adapter);
3808
3809 ixgbe_configure_tx(adapter);
3810 ixgbe_configure_rx(adapter);
3811 }
3812
3813 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3814 {
3815 switch (hw->phy.type) {
3816 case ixgbe_phy_sfp_avago:
3817 case ixgbe_phy_sfp_ftl:
3818 case ixgbe_phy_sfp_intel:
3819 case ixgbe_phy_sfp_unknown:
3820 case ixgbe_phy_sfp_passive_tyco:
3821 case ixgbe_phy_sfp_passive_unknown:
3822 case ixgbe_phy_sfp_active_unknown:
3823 case ixgbe_phy_sfp_ftl_active:
3824 return true;
3825 default:
3826 return false;
3827 }
3828 }
3829
3830 /**
3831 * ixgbe_sfp_link_config - set up SFP+ link
3832 * @adapter: pointer to private adapter struct
3833 **/
3834 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3835 {
3836 /*
3837 * We are assuming the worst case scenerio here, and that
3838 * is that an SFP was inserted/removed after the reset
3839 * but before SFP detection was enabled. As such the best
3840 * solution is to just start searching as soon as we start
3841 */
3842 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3843 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3844
3845 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3846 }
3847
3848 /**
3849 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3850 * @hw: pointer to private hardware struct
3851 *
3852 * Returns 0 on success, negative on failure
3853 **/
3854 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3855 {
3856 u32 autoneg;
3857 bool negotiation, link_up = false;
3858 u32 ret = IXGBE_ERR_LINK_SETUP;
3859
3860 if (hw->mac.ops.check_link)
3861 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3862
3863 if (ret)
3864 goto link_cfg_out;
3865
3866 autoneg = hw->phy.autoneg_advertised;
3867 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3868 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3869 &negotiation);
3870 if (ret)
3871 goto link_cfg_out;
3872
3873 if (hw->mac.ops.setup_link)
3874 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3875 link_cfg_out:
3876 return ret;
3877 }
3878
3879 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3880 {
3881 struct ixgbe_hw *hw = &adapter->hw;
3882 u32 gpie = 0;
3883
3884 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3885 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3886 IXGBE_GPIE_OCD;
3887 gpie |= IXGBE_GPIE_EIAME;
3888 /*
3889 * use EIAM to auto-mask when MSI-X interrupt is asserted
3890 * this saves a register write for every interrupt
3891 */
3892 switch (hw->mac.type) {
3893 case ixgbe_mac_82598EB:
3894 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3895 break;
3896 case ixgbe_mac_82599EB:
3897 case ixgbe_mac_X540:
3898 default:
3899 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3900 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3901 break;
3902 }
3903 } else {
3904 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3905 * specifically only auto mask tx and rx interrupts */
3906 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3907 }
3908
3909 /* XXX: to interrupt immediately for EICS writes, enable this */
3910 /* gpie |= IXGBE_GPIE_EIMEN; */
3911
3912 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3913 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3914 gpie |= IXGBE_GPIE_VTMODE_64;
3915 }
3916
3917 /* Enable fan failure interrupt */
3918 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3919 gpie |= IXGBE_SDP1_GPIEN;
3920
3921 if (hw->mac.type == ixgbe_mac_82599EB) {
3922 gpie |= IXGBE_SDP1_GPIEN;
3923 gpie |= IXGBE_SDP2_GPIEN;
3924 }
3925
3926 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3927 }
3928
3929 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3930 {
3931 struct ixgbe_hw *hw = &adapter->hw;
3932 int err;
3933 u32 ctrl_ext;
3934
3935 ixgbe_get_hw_control(adapter);
3936 ixgbe_setup_gpie(adapter);
3937
3938 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3939 ixgbe_configure_msix(adapter);
3940 else
3941 ixgbe_configure_msi_and_legacy(adapter);
3942
3943 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3944 if (hw->mac.ops.enable_tx_laser &&
3945 ((hw->phy.multispeed_fiber) ||
3946 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3947 (hw->mac.type == ixgbe_mac_82599EB))))
3948 hw->mac.ops.enable_tx_laser(hw);
3949
3950 clear_bit(__IXGBE_DOWN, &adapter->state);
3951 ixgbe_napi_enable_all(adapter);
3952
3953 if (ixgbe_is_sfp(hw)) {
3954 ixgbe_sfp_link_config(adapter);
3955 } else {
3956 err = ixgbe_non_sfp_link_config(hw);
3957 if (err)
3958 e_err(probe, "link_config FAILED %d\n", err);
3959 }
3960
3961 /* clear any pending interrupts, may auto mask */
3962 IXGBE_READ_REG(hw, IXGBE_EICR);
3963 ixgbe_irq_enable(adapter, true, true);
3964
3965 /*
3966 * If this adapter has a fan, check to see if we had a failure
3967 * before we enabled the interrupt.
3968 */
3969 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3970 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3971 if (esdp & IXGBE_ESDP_SDP1)
3972 e_crit(drv, "Fan has stopped, replace the adapter\n");
3973 }
3974
3975 /* enable transmits */
3976 netif_tx_start_all_queues(adapter->netdev);
3977
3978 /* bring the link up in the watchdog, this could race with our first
3979 * link up interrupt but shouldn't be a problem */
3980 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3981 adapter->link_check_timeout = jiffies;
3982 mod_timer(&adapter->service_timer, jiffies);
3983
3984 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3985 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3986 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3987 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3988
3989 return 0;
3990 }
3991
3992 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3993 {
3994 WARN_ON(in_interrupt());
3995 /* put off any impending NetWatchDogTimeout */
3996 adapter->netdev->trans_start = jiffies;
3997
3998 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3999 usleep_range(1000, 2000);
4000 ixgbe_down(adapter);
4001 /*
4002 * If SR-IOV enabled then wait a bit before bringing the adapter
4003 * back up to give the VFs time to respond to the reset. The
4004 * two second wait is based upon the watchdog timer cycle in
4005 * the VF driver.
4006 */
4007 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4008 msleep(2000);
4009 ixgbe_up(adapter);
4010 clear_bit(__IXGBE_RESETTING, &adapter->state);
4011 }
4012
4013 int ixgbe_up(struct ixgbe_adapter *adapter)
4014 {
4015 /* hardware has been reset, we need to reload some things */
4016 ixgbe_configure(adapter);
4017
4018 return ixgbe_up_complete(adapter);
4019 }
4020
4021 void ixgbe_reset(struct ixgbe_adapter *adapter)
4022 {
4023 struct ixgbe_hw *hw = &adapter->hw;
4024 int err;
4025
4026 /* lock SFP init bit to prevent race conditions with the watchdog */
4027 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4028 usleep_range(1000, 2000);
4029
4030 /* clear all SFP and link config related flags while holding SFP_INIT */
4031 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4032 IXGBE_FLAG2_SFP_NEEDS_RESET);
4033 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4034
4035 err = hw->mac.ops.init_hw(hw);
4036 switch (err) {
4037 case 0:
4038 case IXGBE_ERR_SFP_NOT_PRESENT:
4039 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4040 break;
4041 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4042 e_dev_err("master disable timed out\n");
4043 break;
4044 case IXGBE_ERR_EEPROM_VERSION:
4045 /* We are running on a pre-production device, log a warning */
4046 e_dev_warn("This device is a pre-production adapter/LOM. "
4047 "Please be aware there may be issuesassociated with "
4048 "your hardware. If you are experiencing problems "
4049 "please contact your Intel or hardware "
4050 "representative who provided you with this "
4051 "hardware.\n");
4052 break;
4053 default:
4054 e_dev_err("Hardware Error: %d\n", err);
4055 }
4056
4057 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4058
4059 /* reprogram the RAR[0] in case user changed it. */
4060 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4061 IXGBE_RAH_AV);
4062 }
4063
4064 /**
4065 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4066 * @rx_ring: ring to free buffers from
4067 **/
4068 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4069 {
4070 struct device *dev = rx_ring->dev;
4071 unsigned long size;
4072 u16 i;
4073
4074 /* ring already cleared, nothing to do */
4075 if (!rx_ring->rx_buffer_info)
4076 return;
4077
4078 /* Free all the Rx ring sk_buffs */
4079 for (i = 0; i < rx_ring->count; i++) {
4080 struct ixgbe_rx_buffer *rx_buffer_info;
4081
4082 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4083 if (rx_buffer_info->dma) {
4084 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4085 rx_ring->rx_buf_len,
4086 DMA_FROM_DEVICE);
4087 rx_buffer_info->dma = 0;
4088 }
4089 if (rx_buffer_info->skb) {
4090 struct sk_buff *skb = rx_buffer_info->skb;
4091 rx_buffer_info->skb = NULL;
4092 do {
4093 struct sk_buff *this = skb;
4094 if (IXGBE_RSC_CB(this)->delay_unmap) {
4095 dma_unmap_single(dev,
4096 IXGBE_RSC_CB(this)->dma,
4097 rx_ring->rx_buf_len,
4098 DMA_FROM_DEVICE);
4099 IXGBE_RSC_CB(this)->dma = 0;
4100 IXGBE_RSC_CB(skb)->delay_unmap = false;
4101 }
4102 skb = skb->prev;
4103 dev_kfree_skb(this);
4104 } while (skb);
4105 }
4106 if (!rx_buffer_info->page)
4107 continue;
4108 if (rx_buffer_info->page_dma) {
4109 dma_unmap_page(dev, rx_buffer_info->page_dma,
4110 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4111 rx_buffer_info->page_dma = 0;
4112 }
4113 put_page(rx_buffer_info->page);
4114 rx_buffer_info->page = NULL;
4115 rx_buffer_info->page_offset = 0;
4116 }
4117
4118 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4119 memset(rx_ring->rx_buffer_info, 0, size);
4120
4121 /* Zero out the descriptor ring */
4122 memset(rx_ring->desc, 0, rx_ring->size);
4123
4124 rx_ring->next_to_clean = 0;
4125 rx_ring->next_to_use = 0;
4126 }
4127
4128 /**
4129 * ixgbe_clean_tx_ring - Free Tx Buffers
4130 * @tx_ring: ring to be cleaned
4131 **/
4132 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4133 {
4134 struct ixgbe_tx_buffer *tx_buffer_info;
4135 unsigned long size;
4136 u16 i;
4137
4138 /* ring already cleared, nothing to do */
4139 if (!tx_ring->tx_buffer_info)
4140 return;
4141
4142 /* Free all the Tx ring sk_buffs */
4143 for (i = 0; i < tx_ring->count; i++) {
4144 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4145 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4146 }
4147
4148 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4149 memset(tx_ring->tx_buffer_info, 0, size);
4150
4151 /* Zero out the descriptor ring */
4152 memset(tx_ring->desc, 0, tx_ring->size);
4153
4154 tx_ring->next_to_use = 0;
4155 tx_ring->next_to_clean = 0;
4156 }
4157
4158 /**
4159 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4160 * @adapter: board private structure
4161 **/
4162 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4163 {
4164 int i;
4165
4166 for (i = 0; i < adapter->num_rx_queues; i++)
4167 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4168 }
4169
4170 /**
4171 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4172 * @adapter: board private structure
4173 **/
4174 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4175 {
4176 int i;
4177
4178 for (i = 0; i < adapter->num_tx_queues; i++)
4179 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4180 }
4181
4182 void ixgbe_down(struct ixgbe_adapter *adapter)
4183 {
4184 struct net_device *netdev = adapter->netdev;
4185 struct ixgbe_hw *hw = &adapter->hw;
4186 u32 rxctrl;
4187 int i;
4188 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4189
4190 /* signal that we are down to the interrupt handler */
4191 set_bit(__IXGBE_DOWN, &adapter->state);
4192
4193 /* disable receives */
4194 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4195 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4196
4197 /* disable all enabled rx queues */
4198 for (i = 0; i < adapter->num_rx_queues; i++)
4199 /* this call also flushes the previous write */
4200 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4201
4202 usleep_range(10000, 20000);
4203
4204 netif_tx_stop_all_queues(netdev);
4205
4206 /* call carrier off first to avoid false dev_watchdog timeouts */
4207 netif_carrier_off(netdev);
4208 netif_tx_disable(netdev);
4209
4210 ixgbe_irq_disable(adapter);
4211
4212 ixgbe_napi_disable_all(adapter);
4213
4214 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4215 IXGBE_FLAG2_RESET_REQUESTED);
4216 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4217
4218 del_timer_sync(&adapter->service_timer);
4219
4220 /* disable receive for all VFs and wait one second */
4221 if (adapter->num_vfs) {
4222 /* ping all the active vfs to let them know we are going down */
4223 ixgbe_ping_all_vfs(adapter);
4224
4225 /* Disable all VFTE/VFRE TX/RX */
4226 ixgbe_disable_tx_rx(adapter);
4227
4228 /* Mark all the VFs as inactive */
4229 for (i = 0 ; i < adapter->num_vfs; i++)
4230 adapter->vfinfo[i].clear_to_send = 0;
4231 }
4232
4233 /* Cleanup the affinity_hint CPU mask memory and callback */
4234 for (i = 0; i < num_q_vectors; i++) {
4235 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4236 /* clear the affinity_mask in the IRQ descriptor */
4237 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4238 /* release the CPU mask memory */
4239 free_cpumask_var(q_vector->affinity_mask);
4240 }
4241
4242 /* disable transmits in the hardware now that interrupts are off */
4243 for (i = 0; i < adapter->num_tx_queues; i++) {
4244 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4245 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4246 }
4247
4248 /* Disable the Tx DMA engine on 82599 and X540 */
4249 switch (hw->mac.type) {
4250 case ixgbe_mac_82599EB:
4251 case ixgbe_mac_X540:
4252 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4253 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4254 ~IXGBE_DMATXCTL_TE));
4255 break;
4256 default:
4257 break;
4258 }
4259
4260 if (!pci_channel_offline(adapter->pdev))
4261 ixgbe_reset(adapter);
4262
4263 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4264 if (hw->mac.ops.disable_tx_laser &&
4265 ((hw->phy.multispeed_fiber) ||
4266 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4267 (hw->mac.type == ixgbe_mac_82599EB))))
4268 hw->mac.ops.disable_tx_laser(hw);
4269
4270 ixgbe_clean_all_tx_rings(adapter);
4271 ixgbe_clean_all_rx_rings(adapter);
4272
4273 #ifdef CONFIG_IXGBE_DCA
4274 /* since we reset the hardware DCA settings were cleared */
4275 ixgbe_setup_dca(adapter);
4276 #endif
4277 }
4278
4279 /**
4280 * ixgbe_poll - NAPI Rx polling callback
4281 * @napi: structure for representing this polling device
4282 * @budget: how many packets driver is allowed to clean
4283 *
4284 * This function is used for legacy and MSI, NAPI mode
4285 **/
4286 static int ixgbe_poll(struct napi_struct *napi, int budget)
4287 {
4288 struct ixgbe_q_vector *q_vector =
4289 container_of(napi, struct ixgbe_q_vector, napi);
4290 struct ixgbe_adapter *adapter = q_vector->adapter;
4291 int tx_clean_complete, work_done = 0;
4292
4293 #ifdef CONFIG_IXGBE_DCA
4294 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4295 ixgbe_update_dca(q_vector);
4296 #endif
4297
4298 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4299 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4300
4301 if (!tx_clean_complete)
4302 work_done = budget;
4303
4304 /* If budget not fully consumed, exit the polling mode */
4305 if (work_done < budget) {
4306 napi_complete(napi);
4307 if (adapter->rx_itr_setting & 1)
4308 ixgbe_set_itr(adapter);
4309 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4310 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4311 }
4312 return work_done;
4313 }
4314
4315 /**
4316 * ixgbe_tx_timeout - Respond to a Tx Hang
4317 * @netdev: network interface device structure
4318 **/
4319 static void ixgbe_tx_timeout(struct net_device *netdev)
4320 {
4321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4322
4323 /* Do the reset outside of interrupt context */
4324 ixgbe_tx_timeout_reset(adapter);
4325 }
4326
4327 /**
4328 * ixgbe_set_rss_queues: Allocate queues for RSS
4329 * @adapter: board private structure to initialize
4330 *
4331 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4332 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4333 *
4334 **/
4335 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4336 {
4337 bool ret = false;
4338 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4339
4340 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4341 f->mask = 0xF;
4342 adapter->num_rx_queues = f->indices;
4343 adapter->num_tx_queues = f->indices;
4344 ret = true;
4345 } else {
4346 ret = false;
4347 }
4348
4349 return ret;
4350 }
4351
4352 /**
4353 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4354 * @adapter: board private structure to initialize
4355 *
4356 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4357 * to the original CPU that initiated the Tx session. This runs in addition
4358 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4359 * Rx load across CPUs using RSS.
4360 *
4361 **/
4362 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4363 {
4364 bool ret = false;
4365 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4366
4367 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4368 f_fdir->mask = 0;
4369
4370 /* Flow Director must have RSS enabled */
4371 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4372 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4373 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4374 adapter->num_tx_queues = f_fdir->indices;
4375 adapter->num_rx_queues = f_fdir->indices;
4376 ret = true;
4377 } else {
4378 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4379 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4380 }
4381 return ret;
4382 }
4383
4384 #ifdef IXGBE_FCOE
4385 /**
4386 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4387 * @adapter: board private structure to initialize
4388 *
4389 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4390 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4391 * rx queues out of the max number of rx queues, instead, it is used as the
4392 * index of the first rx queue used by FCoE.
4393 *
4394 **/
4395 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4396 {
4397 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4398
4399 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4400 return false;
4401
4402 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4403 #ifdef CONFIG_IXGBE_DCB
4404 int tc;
4405 struct net_device *dev = adapter->netdev;
4406
4407 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4408 f->indices = dev->tc_to_txq[tc].count;
4409 f->mask = dev->tc_to_txq[tc].offset;
4410 #endif
4411 } else {
4412 f->indices = min((int)num_online_cpus(), f->indices);
4413
4414 adapter->num_rx_queues = 1;
4415 adapter->num_tx_queues = 1;
4416
4417 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4418 e_info(probe, "FCoE enabled with RSS\n");
4419 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4420 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4421 ixgbe_set_fdir_queues(adapter);
4422 else
4423 ixgbe_set_rss_queues(adapter);
4424 }
4425 /* adding FCoE rx rings to the end */
4426 f->mask = adapter->num_rx_queues;
4427 adapter->num_rx_queues += f->indices;
4428 adapter->num_tx_queues += f->indices;
4429 }
4430
4431 return true;
4432 }
4433 #endif /* IXGBE_FCOE */
4434
4435 #ifdef CONFIG_IXGBE_DCB
4436 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4437 {
4438 bool ret = false;
4439 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4440 int i, q;
4441
4442 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4443 return ret;
4444
4445 f->indices = 0;
4446 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4447 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4448 f->indices += q;
4449 }
4450
4451 f->mask = 0x7 << 3;
4452 adapter->num_rx_queues = f->indices;
4453 adapter->num_tx_queues = f->indices;
4454 ret = true;
4455
4456 #ifdef IXGBE_FCOE
4457 /* FCoE enabled queues require special configuration done through
4458 * configure_fcoe() and others. Here we map FCoE indices onto the
4459 * DCB queue pairs allowing FCoE to own configuration later.
4460 */
4461 ixgbe_set_fcoe_queues(adapter);
4462 #endif
4463
4464 return ret;
4465 }
4466 #endif
4467
4468 /**
4469 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4470 * @adapter: board private structure to initialize
4471 *
4472 * IOV doesn't actually use anything, so just NAK the
4473 * request for now and let the other queue routines
4474 * figure out what to do.
4475 */
4476 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4477 {
4478 return false;
4479 }
4480
4481 /*
4482 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4483 * @adapter: board private structure to initialize
4484 *
4485 * This is the top level queue allocation routine. The order here is very
4486 * important, starting with the "most" number of features turned on at once,
4487 * and ending with the smallest set of features. This way large combinations
4488 * can be allocated if they're turned on, and smaller combinations are the
4489 * fallthrough conditions.
4490 *
4491 **/
4492 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4493 {
4494 /* Start with base case */
4495 adapter->num_rx_queues = 1;
4496 adapter->num_tx_queues = 1;
4497 adapter->num_rx_pools = adapter->num_rx_queues;
4498 adapter->num_rx_queues_per_pool = 1;
4499
4500 if (ixgbe_set_sriov_queues(adapter))
4501 goto done;
4502
4503 #ifdef CONFIG_IXGBE_DCB
4504 if (ixgbe_set_dcb_queues(adapter))
4505 goto done;
4506
4507 #endif
4508 #ifdef IXGBE_FCOE
4509 if (ixgbe_set_fcoe_queues(adapter))
4510 goto done;
4511
4512 #endif /* IXGBE_FCOE */
4513 if (ixgbe_set_fdir_queues(adapter))
4514 goto done;
4515
4516 if (ixgbe_set_rss_queues(adapter))
4517 goto done;
4518
4519 /* fallback to base case */
4520 adapter->num_rx_queues = 1;
4521 adapter->num_tx_queues = 1;
4522
4523 done:
4524 /* Notify the stack of the (possibly) reduced queue counts. */
4525 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4526 return netif_set_real_num_rx_queues(adapter->netdev,
4527 adapter->num_rx_queues);
4528 }
4529
4530 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4531 int vectors)
4532 {
4533 int err, vector_threshold;
4534
4535 /* We'll want at least 3 (vector_threshold):
4536 * 1) TxQ[0] Cleanup
4537 * 2) RxQ[0] Cleanup
4538 * 3) Other (Link Status Change, etc.)
4539 * 4) TCP Timer (optional)
4540 */
4541 vector_threshold = MIN_MSIX_COUNT;
4542
4543 /* The more we get, the more we will assign to Tx/Rx Cleanup
4544 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4545 * Right now, we simply care about how many we'll get; we'll
4546 * set them up later while requesting irq's.
4547 */
4548 while (vectors >= vector_threshold) {
4549 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4550 vectors);
4551 if (!err) /* Success in acquiring all requested vectors. */
4552 break;
4553 else if (err < 0)
4554 vectors = 0; /* Nasty failure, quit now */
4555 else /* err == number of vectors we should try again with */
4556 vectors = err;
4557 }
4558
4559 if (vectors < vector_threshold) {
4560 /* Can't allocate enough MSI-X interrupts? Oh well.
4561 * This just means we'll go with either a single MSI
4562 * vector or fall back to legacy interrupts.
4563 */
4564 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4565 "Unable to allocate MSI-X interrupts\n");
4566 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4567 kfree(adapter->msix_entries);
4568 adapter->msix_entries = NULL;
4569 } else {
4570 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4571 /*
4572 * Adjust for only the vectors we'll use, which is minimum
4573 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4574 * vectors we were allocated.
4575 */
4576 adapter->num_msix_vectors = min(vectors,
4577 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4578 }
4579 }
4580
4581 /**
4582 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4583 * @adapter: board private structure to initialize
4584 *
4585 * Cache the descriptor ring offsets for RSS to the assigned rings.
4586 *
4587 **/
4588 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4589 {
4590 int i;
4591
4592 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4593 return false;
4594
4595 for (i = 0; i < adapter->num_rx_queues; i++)
4596 adapter->rx_ring[i]->reg_idx = i;
4597 for (i = 0; i < adapter->num_tx_queues; i++)
4598 adapter->tx_ring[i]->reg_idx = i;
4599
4600 return true;
4601 }
4602
4603 #ifdef CONFIG_IXGBE_DCB
4604
4605 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4606 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4607 unsigned int *tx, unsigned int *rx)
4608 {
4609 struct net_device *dev = adapter->netdev;
4610 struct ixgbe_hw *hw = &adapter->hw;
4611 u8 num_tcs = netdev_get_num_tc(dev);
4612
4613 *tx = 0;
4614 *rx = 0;
4615
4616 switch (hw->mac.type) {
4617 case ixgbe_mac_82598EB:
4618 *tx = tc << 3;
4619 *rx = tc << 2;
4620 break;
4621 case ixgbe_mac_82599EB:
4622 case ixgbe_mac_X540:
4623 if (num_tcs == 8) {
4624 if (tc < 3) {
4625 *tx = tc << 5;
4626 *rx = tc << 4;
4627 } else if (tc < 5) {
4628 *tx = ((tc + 2) << 4);
4629 *rx = tc << 4;
4630 } else if (tc < num_tcs) {
4631 *tx = ((tc + 8) << 3);
4632 *rx = tc << 4;
4633 }
4634 } else if (num_tcs == 4) {
4635 *rx = tc << 5;
4636 switch (tc) {
4637 case 0:
4638 *tx = 0;
4639 break;
4640 case 1:
4641 *tx = 64;
4642 break;
4643 case 2:
4644 *tx = 96;
4645 break;
4646 case 3:
4647 *tx = 112;
4648 break;
4649 default:
4650 break;
4651 }
4652 }
4653 break;
4654 default:
4655 break;
4656 }
4657 }
4658
4659 #define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4660
4661 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4662 * classes.
4663 *
4664 * @netdev: net device to configure
4665 * @tc: number of traffic classes to enable
4666 */
4667 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4668 {
4669 int i;
4670 unsigned int q, offset = 0;
4671
4672 if (!tc) {
4673 netdev_reset_tc(dev);
4674 } else {
4675 struct ixgbe_adapter *adapter = netdev_priv(dev);
4676
4677 /* Hardware supports up to 8 traffic classes */
4678 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
4679 return -EINVAL;
4680
4681 /* Partition Tx queues evenly amongst traffic classes */
4682 for (i = 0; i < tc; i++) {
4683 q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4684 netdev_set_prio_tc_map(dev, i, i);
4685 netdev_set_tc_queue(dev, i, q, offset);
4686 offset += q;
4687 }
4688
4689 /* This enables multiple traffic class support in the hardware
4690 * which defaults to strict priority transmission by default.
4691 * If traffic classes are already enabled perhaps through DCB
4692 * code path then existing configuration will be used.
4693 */
4694 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4695 dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4696 struct ieee_ets ets = {
4697 .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4698 };
4699 u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4700
4701 dev->dcbnl_ops->setdcbx(dev, mode);
4702 dev->dcbnl_ops->ieee_setets(dev, &ets);
4703 }
4704 }
4705 return 0;
4706 }
4707
4708 /**
4709 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4710 * @adapter: board private structure to initialize
4711 *
4712 * Cache the descriptor ring offsets for DCB to the assigned rings.
4713 *
4714 **/
4715 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4716 {
4717 struct net_device *dev = adapter->netdev;
4718 int i, j, k;
4719 u8 num_tcs = netdev_get_num_tc(dev);
4720
4721 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4722 return false;
4723
4724 for (i = 0, k = 0; i < num_tcs; i++) {
4725 unsigned int tx_s, rx_s;
4726 u16 count = dev->tc_to_txq[i].count;
4727
4728 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4729 for (j = 0; j < count; j++, k++) {
4730 adapter->tx_ring[k]->reg_idx = tx_s + j;
4731 adapter->rx_ring[k]->reg_idx = rx_s + j;
4732 adapter->tx_ring[k]->dcb_tc = i;
4733 adapter->rx_ring[k]->dcb_tc = i;
4734 }
4735 }
4736
4737 return true;
4738 }
4739 #endif
4740
4741 /**
4742 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4743 * @adapter: board private structure to initialize
4744 *
4745 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4746 *
4747 **/
4748 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4749 {
4750 int i;
4751 bool ret = false;
4752
4753 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4754 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4755 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4756 for (i = 0; i < adapter->num_rx_queues; i++)
4757 adapter->rx_ring[i]->reg_idx = i;
4758 for (i = 0; i < adapter->num_tx_queues; i++)
4759 adapter->tx_ring[i]->reg_idx = i;
4760 ret = true;
4761 }
4762
4763 return ret;
4764 }
4765
4766 #ifdef IXGBE_FCOE
4767 /**
4768 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4769 * @adapter: board private structure to initialize
4770 *
4771 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4772 *
4773 */
4774 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4775 {
4776 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4777 int i;
4778 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4779
4780 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4781 return false;
4782
4783 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4784 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4785 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4786 ixgbe_cache_ring_fdir(adapter);
4787 else
4788 ixgbe_cache_ring_rss(adapter);
4789
4790 fcoe_rx_i = f->mask;
4791 fcoe_tx_i = f->mask;
4792 }
4793 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4794 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4795 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4796 }
4797 return true;
4798 }
4799
4800 #endif /* IXGBE_FCOE */
4801 /**
4802 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4803 * @adapter: board private structure to initialize
4804 *
4805 * SR-IOV doesn't use any descriptor rings but changes the default if
4806 * no other mapping is used.
4807 *
4808 */
4809 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4810 {
4811 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4812 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4813 if (adapter->num_vfs)
4814 return true;
4815 else
4816 return false;
4817 }
4818
4819 /**
4820 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4821 * @adapter: board private structure to initialize
4822 *
4823 * Once we know the feature-set enabled for the device, we'll cache
4824 * the register offset the descriptor ring is assigned to.
4825 *
4826 * Note, the order the various feature calls is important. It must start with
4827 * the "most" features enabled at the same time, then trickle down to the
4828 * least amount of features turned on at once.
4829 **/
4830 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4831 {
4832 /* start with default case */
4833 adapter->rx_ring[0]->reg_idx = 0;
4834 adapter->tx_ring[0]->reg_idx = 0;
4835
4836 if (ixgbe_cache_ring_sriov(adapter))
4837 return;
4838
4839 #ifdef CONFIG_IXGBE_DCB
4840 if (ixgbe_cache_ring_dcb(adapter))
4841 return;
4842 #endif
4843
4844 #ifdef IXGBE_FCOE
4845 if (ixgbe_cache_ring_fcoe(adapter))
4846 return;
4847 #endif /* IXGBE_FCOE */
4848
4849 if (ixgbe_cache_ring_fdir(adapter))
4850 return;
4851
4852 if (ixgbe_cache_ring_rss(adapter))
4853 return;
4854 }
4855
4856 /**
4857 * ixgbe_alloc_queues - Allocate memory for all rings
4858 * @adapter: board private structure to initialize
4859 *
4860 * We allocate one ring per queue at run-time since we don't know the
4861 * number of queues at compile-time. The polling_netdev array is
4862 * intended for Multiqueue, but should work fine with a single queue.
4863 **/
4864 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4865 {
4866 int rx = 0, tx = 0, nid = adapter->node;
4867
4868 if (nid < 0 || !node_online(nid))
4869 nid = first_online_node;
4870
4871 for (; tx < adapter->num_tx_queues; tx++) {
4872 struct ixgbe_ring *ring;
4873
4874 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4875 if (!ring)
4876 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4877 if (!ring)
4878 goto err_allocation;
4879 ring->count = adapter->tx_ring_count;
4880 ring->queue_index = tx;
4881 ring->numa_node = nid;
4882 ring->dev = &adapter->pdev->dev;
4883 ring->netdev = adapter->netdev;
4884
4885 adapter->tx_ring[tx] = ring;
4886 }
4887
4888 for (; rx < adapter->num_rx_queues; rx++) {
4889 struct ixgbe_ring *ring;
4890
4891 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4892 if (!ring)
4893 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4894 if (!ring)
4895 goto err_allocation;
4896 ring->count = adapter->rx_ring_count;
4897 ring->queue_index = rx;
4898 ring->numa_node = nid;
4899 ring->dev = &adapter->pdev->dev;
4900 ring->netdev = adapter->netdev;
4901
4902 adapter->rx_ring[rx] = ring;
4903 }
4904
4905 ixgbe_cache_ring_register(adapter);
4906
4907 return 0;
4908
4909 err_allocation:
4910 while (tx)
4911 kfree(adapter->tx_ring[--tx]);
4912
4913 while (rx)
4914 kfree(adapter->rx_ring[--rx]);
4915 return -ENOMEM;
4916 }
4917
4918 /**
4919 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4920 * @adapter: board private structure to initialize
4921 *
4922 * Attempt to configure the interrupts using the best available
4923 * capabilities of the hardware and the kernel.
4924 **/
4925 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4926 {
4927 struct ixgbe_hw *hw = &adapter->hw;
4928 int err = 0;
4929 int vector, v_budget;
4930
4931 /*
4932 * It's easy to be greedy for MSI-X vectors, but it really
4933 * doesn't do us much good if we have a lot more vectors
4934 * than CPU's. So let's be conservative and only ask for
4935 * (roughly) the same number of vectors as there are CPU's.
4936 */
4937 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4938 (int)num_online_cpus()) + NON_Q_VECTORS;
4939
4940 /*
4941 * At the same time, hardware can only support a maximum of
4942 * hw.mac->max_msix_vectors vectors. With features
4943 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4944 * descriptor queues supported by our device. Thus, we cap it off in
4945 * those rare cases where the cpu count also exceeds our vector limit.
4946 */
4947 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4948
4949 /* A failure in MSI-X entry allocation isn't fatal, but it does
4950 * mean we disable MSI-X capabilities of the adapter. */
4951 adapter->msix_entries = kcalloc(v_budget,
4952 sizeof(struct msix_entry), GFP_KERNEL);
4953 if (adapter->msix_entries) {
4954 for (vector = 0; vector < v_budget; vector++)
4955 adapter->msix_entries[vector].entry = vector;
4956
4957 ixgbe_acquire_msix_vectors(adapter, v_budget);
4958
4959 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4960 goto out;
4961 }
4962
4963 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4964 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4965 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4966 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4967 e_err(probe,
4968 "Flow Director is not supported while multiple "
4969 "queues are disabled. Disabling Flow Director\n");
4970 }
4971 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4972 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4973 adapter->atr_sample_rate = 0;
4974 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4975 ixgbe_disable_sriov(adapter);
4976
4977 err = ixgbe_set_num_queues(adapter);
4978 if (err)
4979 return err;
4980
4981 err = pci_enable_msi(adapter->pdev);
4982 if (!err) {
4983 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4984 } else {
4985 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4986 "Unable to allocate MSI interrupt, "
4987 "falling back to legacy. Error: %d\n", err);
4988 /* reset err */
4989 err = 0;
4990 }
4991
4992 out:
4993 return err;
4994 }
4995
4996 /**
4997 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4998 * @adapter: board private structure to initialize
4999 *
5000 * We allocate one q_vector per queue interrupt. If allocation fails we
5001 * return -ENOMEM.
5002 **/
5003 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
5004 {
5005 int q_idx, num_q_vectors;
5006 struct ixgbe_q_vector *q_vector;
5007 int (*poll)(struct napi_struct *, int);
5008
5009 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5010 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5011 poll = &ixgbe_clean_rxtx_many;
5012 } else {
5013 num_q_vectors = 1;
5014 poll = &ixgbe_poll;
5015 }
5016
5017 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5018 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
5019 GFP_KERNEL, adapter->node);
5020 if (!q_vector)
5021 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
5022 GFP_KERNEL);
5023 if (!q_vector)
5024 goto err_out;
5025 q_vector->adapter = adapter;
5026 if (q_vector->txr_count && !q_vector->rxr_count)
5027 q_vector->eitr = adapter->tx_eitr_param;
5028 else
5029 q_vector->eitr = adapter->rx_eitr_param;
5030 q_vector->v_idx = q_idx;
5031 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
5032 adapter->q_vector[q_idx] = q_vector;
5033 }
5034
5035 return 0;
5036
5037 err_out:
5038 while (q_idx) {
5039 q_idx--;
5040 q_vector = adapter->q_vector[q_idx];
5041 netif_napi_del(&q_vector->napi);
5042 kfree(q_vector);
5043 adapter->q_vector[q_idx] = NULL;
5044 }
5045 return -ENOMEM;
5046 }
5047
5048 /**
5049 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5050 * @adapter: board private structure to initialize
5051 *
5052 * This function frees the memory allocated to the q_vectors. In addition if
5053 * NAPI is enabled it will delete any references to the NAPI struct prior
5054 * to freeing the q_vector.
5055 **/
5056 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5057 {
5058 int q_idx, num_q_vectors;
5059
5060 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5061 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5062 else
5063 num_q_vectors = 1;
5064
5065 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5066 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
5067 adapter->q_vector[q_idx] = NULL;
5068 netif_napi_del(&q_vector->napi);
5069 kfree(q_vector);
5070 }
5071 }
5072
5073 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
5074 {
5075 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5076 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5077 pci_disable_msix(adapter->pdev);
5078 kfree(adapter->msix_entries);
5079 adapter->msix_entries = NULL;
5080 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5081 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5082 pci_disable_msi(adapter->pdev);
5083 }
5084 }
5085
5086 /**
5087 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5088 * @adapter: board private structure to initialize
5089 *
5090 * We determine which interrupt scheme to use based on...
5091 * - Kernel support (MSI, MSI-X)
5092 * - which can be user-defined (via MODULE_PARAM)
5093 * - Hardware queue count (num_*_queues)
5094 * - defined by miscellaneous hardware support/features (RSS, etc.)
5095 **/
5096 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
5097 {
5098 int err;
5099
5100 /* Number of supported queues */
5101 err = ixgbe_set_num_queues(adapter);
5102 if (err)
5103 return err;
5104
5105 err = ixgbe_set_interrupt_capability(adapter);
5106 if (err) {
5107 e_dev_err("Unable to setup interrupt capabilities\n");
5108 goto err_set_interrupt;
5109 }
5110
5111 err = ixgbe_alloc_q_vectors(adapter);
5112 if (err) {
5113 e_dev_err("Unable to allocate memory for queue vectors\n");
5114 goto err_alloc_q_vectors;
5115 }
5116
5117 err = ixgbe_alloc_queues(adapter);
5118 if (err) {
5119 e_dev_err("Unable to allocate memory for queues\n");
5120 goto err_alloc_queues;
5121 }
5122
5123 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5124 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5125 adapter->num_rx_queues, adapter->num_tx_queues);
5126
5127 set_bit(__IXGBE_DOWN, &adapter->state);
5128
5129 return 0;
5130
5131 err_alloc_queues:
5132 ixgbe_free_q_vectors(adapter);
5133 err_alloc_q_vectors:
5134 ixgbe_reset_interrupt_capability(adapter);
5135 err_set_interrupt:
5136 return err;
5137 }
5138
5139 static void ring_free_rcu(struct rcu_head *head)
5140 {
5141 kfree(container_of(head, struct ixgbe_ring, rcu));
5142 }
5143
5144 /**
5145 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5146 * @adapter: board private structure to clear interrupt scheme on
5147 *
5148 * We go through and clear interrupt specific resources and reset the structure
5149 * to pre-load conditions
5150 **/
5151 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5152 {
5153 int i;
5154
5155 for (i = 0; i < adapter->num_tx_queues; i++) {
5156 kfree(adapter->tx_ring[i]);
5157 adapter->tx_ring[i] = NULL;
5158 }
5159 for (i = 0; i < adapter->num_rx_queues; i++) {
5160 struct ixgbe_ring *ring = adapter->rx_ring[i];
5161
5162 /* ixgbe_get_stats64() might access this ring, we must wait
5163 * a grace period before freeing it.
5164 */
5165 call_rcu(&ring->rcu, ring_free_rcu);
5166 adapter->rx_ring[i] = NULL;
5167 }
5168
5169 adapter->num_tx_queues = 0;
5170 adapter->num_rx_queues = 0;
5171
5172 ixgbe_free_q_vectors(adapter);
5173 ixgbe_reset_interrupt_capability(adapter);
5174 }
5175
5176 /**
5177 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5178 * @adapter: board private structure to initialize
5179 *
5180 * ixgbe_sw_init initializes the Adapter private data structure.
5181 * Fields are initialized based on PCI device information and
5182 * OS network device settings (MTU size).
5183 **/
5184 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5185 {
5186 struct ixgbe_hw *hw = &adapter->hw;
5187 struct pci_dev *pdev = adapter->pdev;
5188 struct net_device *dev = adapter->netdev;
5189 unsigned int rss;
5190 #ifdef CONFIG_IXGBE_DCB
5191 int j;
5192 struct tc_configuration *tc;
5193 #endif
5194 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5195
5196 /* PCI config space info */
5197
5198 hw->vendor_id = pdev->vendor;
5199 hw->device_id = pdev->device;
5200 hw->revision_id = pdev->revision;
5201 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5202 hw->subsystem_device_id = pdev->subsystem_device;
5203
5204 /* Set capability flags */
5205 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5206 adapter->ring_feature[RING_F_RSS].indices = rss;
5207 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5208 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5209 switch (hw->mac.type) {
5210 case ixgbe_mac_82598EB:
5211 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5212 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5213 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5214 break;
5215 case ixgbe_mac_82599EB:
5216 case ixgbe_mac_X540:
5217 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5218 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5219 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5220 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5221 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5222 /* n-tuple support exists, always init our spinlock */
5223 spin_lock_init(&adapter->fdir_perfect_lock);
5224 /* Flow Director hash filters enabled */
5225 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5226 adapter->atr_sample_rate = 20;
5227 adapter->ring_feature[RING_F_FDIR].indices =
5228 IXGBE_MAX_FDIR_INDICES;
5229 adapter->fdir_pballoc = 0;
5230 #ifdef IXGBE_FCOE
5231 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5232 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5233 adapter->ring_feature[RING_F_FCOE].indices = 0;
5234 #ifdef CONFIG_IXGBE_DCB
5235 /* Default traffic class to use for FCoE */
5236 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5237 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5238 #endif
5239 #endif /* IXGBE_FCOE */
5240 break;
5241 default:
5242 break;
5243 }
5244
5245 #ifdef CONFIG_IXGBE_DCB
5246 /* Configure DCB traffic classes */
5247 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5248 tc = &adapter->dcb_cfg.tc_config[j];
5249 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5250 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5251 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5252 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5253 tc->dcb_pfc = pfc_disabled;
5254 }
5255 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5256 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5257 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5258 adapter->dcb_cfg.pfc_mode_enable = false;
5259 adapter->dcb_set_bitmap = 0x00;
5260 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5261 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5262 MAX_TRAFFIC_CLASS);
5263
5264 #endif
5265
5266 /* default flow control settings */
5267 hw->fc.requested_mode = ixgbe_fc_full;
5268 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5269 #ifdef CONFIG_DCB
5270 adapter->last_lfc_mode = hw->fc.current_mode;
5271 #endif
5272 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5273 hw->fc.low_water = FC_LOW_WATER(max_frame);
5274 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5275 hw->fc.send_xon = true;
5276 hw->fc.disable_fc_autoneg = false;
5277
5278 /* enable itr by default in dynamic mode */
5279 adapter->rx_itr_setting = 1;
5280 adapter->rx_eitr_param = 20000;
5281 adapter->tx_itr_setting = 1;
5282 adapter->tx_eitr_param = 10000;
5283
5284 /* set defaults for eitr in MegaBytes */
5285 adapter->eitr_low = 10;
5286 adapter->eitr_high = 20;
5287
5288 /* set default ring sizes */
5289 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5290 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5291
5292 /* initialize eeprom parameters */
5293 if (ixgbe_init_eeprom_params_generic(hw)) {
5294 e_dev_err("EEPROM initialization failed\n");
5295 return -EIO;
5296 }
5297
5298 /* enable rx csum by default */
5299 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5300
5301 /* get assigned NUMA node */
5302 adapter->node = dev_to_node(&pdev->dev);
5303
5304 set_bit(__IXGBE_DOWN, &adapter->state);
5305
5306 return 0;
5307 }
5308
5309 /**
5310 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5311 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5312 *
5313 * Return 0 on success, negative on failure
5314 **/
5315 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5316 {
5317 struct device *dev = tx_ring->dev;
5318 int size;
5319
5320 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5321 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5322 if (!tx_ring->tx_buffer_info)
5323 tx_ring->tx_buffer_info = vzalloc(size);
5324 if (!tx_ring->tx_buffer_info)
5325 goto err;
5326
5327 /* round up to nearest 4K */
5328 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5329 tx_ring->size = ALIGN(tx_ring->size, 4096);
5330
5331 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5332 &tx_ring->dma, GFP_KERNEL);
5333 if (!tx_ring->desc)
5334 goto err;
5335
5336 tx_ring->next_to_use = 0;
5337 tx_ring->next_to_clean = 0;
5338 tx_ring->work_limit = tx_ring->count;
5339 return 0;
5340
5341 err:
5342 vfree(tx_ring->tx_buffer_info);
5343 tx_ring->tx_buffer_info = NULL;
5344 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5345 return -ENOMEM;
5346 }
5347
5348 /**
5349 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5350 * @adapter: board private structure
5351 *
5352 * If this function returns with an error, then it's possible one or
5353 * more of the rings is populated (while the rest are not). It is the
5354 * callers duty to clean those orphaned rings.
5355 *
5356 * Return 0 on success, negative on failure
5357 **/
5358 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5359 {
5360 int i, err = 0;
5361
5362 for (i = 0; i < adapter->num_tx_queues; i++) {
5363 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5364 if (!err)
5365 continue;
5366 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5367 break;
5368 }
5369
5370 return err;
5371 }
5372
5373 /**
5374 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5375 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5376 *
5377 * Returns 0 on success, negative on failure
5378 **/
5379 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5380 {
5381 struct device *dev = rx_ring->dev;
5382 int size;
5383
5384 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5385 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5386 if (!rx_ring->rx_buffer_info)
5387 rx_ring->rx_buffer_info = vzalloc(size);
5388 if (!rx_ring->rx_buffer_info)
5389 goto err;
5390
5391 /* Round up to nearest 4K */
5392 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5393 rx_ring->size = ALIGN(rx_ring->size, 4096);
5394
5395 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5396 &rx_ring->dma, GFP_KERNEL);
5397
5398 if (!rx_ring->desc)
5399 goto err;
5400
5401 rx_ring->next_to_clean = 0;
5402 rx_ring->next_to_use = 0;
5403
5404 return 0;
5405 err:
5406 vfree(rx_ring->rx_buffer_info);
5407 rx_ring->rx_buffer_info = NULL;
5408 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5409 return -ENOMEM;
5410 }
5411
5412 /**
5413 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5414 * @adapter: board private structure
5415 *
5416 * If this function returns with an error, then it's possible one or
5417 * more of the rings is populated (while the rest are not). It is the
5418 * callers duty to clean those orphaned rings.
5419 *
5420 * Return 0 on success, negative on failure
5421 **/
5422 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5423 {
5424 int i, err = 0;
5425
5426 for (i = 0; i < adapter->num_rx_queues; i++) {
5427 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5428 if (!err)
5429 continue;
5430 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5431 break;
5432 }
5433
5434 return err;
5435 }
5436
5437 /**
5438 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5439 * @tx_ring: Tx descriptor ring for a specific queue
5440 *
5441 * Free all transmit software resources
5442 **/
5443 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5444 {
5445 ixgbe_clean_tx_ring(tx_ring);
5446
5447 vfree(tx_ring->tx_buffer_info);
5448 tx_ring->tx_buffer_info = NULL;
5449
5450 /* if not set, then don't free */
5451 if (!tx_ring->desc)
5452 return;
5453
5454 dma_free_coherent(tx_ring->dev, tx_ring->size,
5455 tx_ring->desc, tx_ring->dma);
5456
5457 tx_ring->desc = NULL;
5458 }
5459
5460 /**
5461 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5462 * @adapter: board private structure
5463 *
5464 * Free all transmit software resources
5465 **/
5466 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5467 {
5468 int i;
5469
5470 for (i = 0; i < adapter->num_tx_queues; i++)
5471 if (adapter->tx_ring[i]->desc)
5472 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5473 }
5474
5475 /**
5476 * ixgbe_free_rx_resources - Free Rx Resources
5477 * @rx_ring: ring to clean the resources from
5478 *
5479 * Free all receive software resources
5480 **/
5481 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5482 {
5483 ixgbe_clean_rx_ring(rx_ring);
5484
5485 vfree(rx_ring->rx_buffer_info);
5486 rx_ring->rx_buffer_info = NULL;
5487
5488 /* if not set, then don't free */
5489 if (!rx_ring->desc)
5490 return;
5491
5492 dma_free_coherent(rx_ring->dev, rx_ring->size,
5493 rx_ring->desc, rx_ring->dma);
5494
5495 rx_ring->desc = NULL;
5496 }
5497
5498 /**
5499 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5500 * @adapter: board private structure
5501 *
5502 * Free all receive software resources
5503 **/
5504 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5505 {
5506 int i;
5507
5508 for (i = 0; i < adapter->num_rx_queues; i++)
5509 if (adapter->rx_ring[i]->desc)
5510 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5511 }
5512
5513 /**
5514 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5515 * @netdev: network interface device structure
5516 * @new_mtu: new value for maximum frame size
5517 *
5518 * Returns 0 on success, negative on failure
5519 **/
5520 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5521 {
5522 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5523 struct ixgbe_hw *hw = &adapter->hw;
5524 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5525
5526 /* MTU < 68 is an error and causes problems on some kernels */
5527 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5528 hw->mac.type != ixgbe_mac_X540) {
5529 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5530 return -EINVAL;
5531 } else {
5532 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5533 return -EINVAL;
5534 }
5535
5536 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5537 /* must set new MTU before calling down or up */
5538 netdev->mtu = new_mtu;
5539
5540 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5541 hw->fc.low_water = FC_LOW_WATER(max_frame);
5542
5543 if (netif_running(netdev))
5544 ixgbe_reinit_locked(adapter);
5545
5546 return 0;
5547 }
5548
5549 /**
5550 * ixgbe_open - Called when a network interface is made active
5551 * @netdev: network interface device structure
5552 *
5553 * Returns 0 on success, negative value on failure
5554 *
5555 * The open entry point is called when a network interface is made
5556 * active by the system (IFF_UP). At this point all resources needed
5557 * for transmit and receive operations are allocated, the interrupt
5558 * handler is registered with the OS, the watchdog timer is started,
5559 * and the stack is notified that the interface is ready.
5560 **/
5561 static int ixgbe_open(struct net_device *netdev)
5562 {
5563 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5564 int err;
5565
5566 /* disallow open during test */
5567 if (test_bit(__IXGBE_TESTING, &adapter->state))
5568 return -EBUSY;
5569
5570 netif_carrier_off(netdev);
5571
5572 /* allocate transmit descriptors */
5573 err = ixgbe_setup_all_tx_resources(adapter);
5574 if (err)
5575 goto err_setup_tx;
5576
5577 /* allocate receive descriptors */
5578 err = ixgbe_setup_all_rx_resources(adapter);
5579 if (err)
5580 goto err_setup_rx;
5581
5582 ixgbe_configure(adapter);
5583
5584 err = ixgbe_request_irq(adapter);
5585 if (err)
5586 goto err_req_irq;
5587
5588 err = ixgbe_up_complete(adapter);
5589 if (err)
5590 goto err_up;
5591
5592 netif_tx_start_all_queues(netdev);
5593
5594 return 0;
5595
5596 err_up:
5597 ixgbe_release_hw_control(adapter);
5598 ixgbe_free_irq(adapter);
5599 err_req_irq:
5600 err_setup_rx:
5601 ixgbe_free_all_rx_resources(adapter);
5602 err_setup_tx:
5603 ixgbe_free_all_tx_resources(adapter);
5604 ixgbe_reset(adapter);
5605
5606 return err;
5607 }
5608
5609 /**
5610 * ixgbe_close - Disables a network interface
5611 * @netdev: network interface device structure
5612 *
5613 * Returns 0, this is not allowed to fail
5614 *
5615 * The close entry point is called when an interface is de-activated
5616 * by the OS. The hardware is still under the drivers control, but
5617 * needs to be disabled. A global MAC reset is issued to stop the
5618 * hardware, and all transmit and receive resources are freed.
5619 **/
5620 static int ixgbe_close(struct net_device *netdev)
5621 {
5622 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5623
5624 ixgbe_down(adapter);
5625 ixgbe_free_irq(adapter);
5626
5627 ixgbe_free_all_tx_resources(adapter);
5628 ixgbe_free_all_rx_resources(adapter);
5629
5630 ixgbe_release_hw_control(adapter);
5631
5632 return 0;
5633 }
5634
5635 #ifdef CONFIG_PM
5636 static int ixgbe_resume(struct pci_dev *pdev)
5637 {
5638 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5639 struct net_device *netdev = adapter->netdev;
5640 u32 err;
5641
5642 pci_set_power_state(pdev, PCI_D0);
5643 pci_restore_state(pdev);
5644 /*
5645 * pci_restore_state clears dev->state_saved so call
5646 * pci_save_state to restore it.
5647 */
5648 pci_save_state(pdev);
5649
5650 err = pci_enable_device_mem(pdev);
5651 if (err) {
5652 e_dev_err("Cannot enable PCI device from suspend\n");
5653 return err;
5654 }
5655 pci_set_master(pdev);
5656
5657 pci_wake_from_d3(pdev, false);
5658
5659 err = ixgbe_init_interrupt_scheme(adapter);
5660 if (err) {
5661 e_dev_err("Cannot initialize interrupts for device\n");
5662 return err;
5663 }
5664
5665 ixgbe_reset(adapter);
5666
5667 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5668
5669 if (netif_running(netdev)) {
5670 err = ixgbe_open(netdev);
5671 if (err)
5672 return err;
5673 }
5674
5675 netif_device_attach(netdev);
5676
5677 return 0;
5678 }
5679 #endif /* CONFIG_PM */
5680
5681 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5682 {
5683 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5684 struct net_device *netdev = adapter->netdev;
5685 struct ixgbe_hw *hw = &adapter->hw;
5686 u32 ctrl, fctrl;
5687 u32 wufc = adapter->wol;
5688 #ifdef CONFIG_PM
5689 int retval = 0;
5690 #endif
5691
5692 netif_device_detach(netdev);
5693
5694 if (netif_running(netdev)) {
5695 ixgbe_down(adapter);
5696 ixgbe_free_irq(adapter);
5697 ixgbe_free_all_tx_resources(adapter);
5698 ixgbe_free_all_rx_resources(adapter);
5699 }
5700
5701 ixgbe_clear_interrupt_scheme(adapter);
5702 #ifdef CONFIG_DCB
5703 kfree(adapter->ixgbe_ieee_pfc);
5704 kfree(adapter->ixgbe_ieee_ets);
5705 #endif
5706
5707 #ifdef CONFIG_PM
5708 retval = pci_save_state(pdev);
5709 if (retval)
5710 return retval;
5711
5712 #endif
5713 if (wufc) {
5714 ixgbe_set_rx_mode(netdev);
5715
5716 /* turn on all-multi mode if wake on multicast is enabled */
5717 if (wufc & IXGBE_WUFC_MC) {
5718 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5719 fctrl |= IXGBE_FCTRL_MPE;
5720 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5721 }
5722
5723 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5724 ctrl |= IXGBE_CTRL_GIO_DIS;
5725 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5726
5727 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5728 } else {
5729 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5730 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5731 }
5732
5733 switch (hw->mac.type) {
5734 case ixgbe_mac_82598EB:
5735 pci_wake_from_d3(pdev, false);
5736 break;
5737 case ixgbe_mac_82599EB:
5738 case ixgbe_mac_X540:
5739 pci_wake_from_d3(pdev, !!wufc);
5740 break;
5741 default:
5742 break;
5743 }
5744
5745 *enable_wake = !!wufc;
5746
5747 ixgbe_release_hw_control(adapter);
5748
5749 pci_disable_device(pdev);
5750
5751 return 0;
5752 }
5753
5754 #ifdef CONFIG_PM
5755 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5756 {
5757 int retval;
5758 bool wake;
5759
5760 retval = __ixgbe_shutdown(pdev, &wake);
5761 if (retval)
5762 return retval;
5763
5764 if (wake) {
5765 pci_prepare_to_sleep(pdev);
5766 } else {
5767 pci_wake_from_d3(pdev, false);
5768 pci_set_power_state(pdev, PCI_D3hot);
5769 }
5770
5771 return 0;
5772 }
5773 #endif /* CONFIG_PM */
5774
5775 static void ixgbe_shutdown(struct pci_dev *pdev)
5776 {
5777 bool wake;
5778
5779 __ixgbe_shutdown(pdev, &wake);
5780
5781 if (system_state == SYSTEM_POWER_OFF) {
5782 pci_wake_from_d3(pdev, wake);
5783 pci_set_power_state(pdev, PCI_D3hot);
5784 }
5785 }
5786
5787 /**
5788 * ixgbe_update_stats - Update the board statistics counters.
5789 * @adapter: board private structure
5790 **/
5791 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5792 {
5793 struct net_device *netdev = adapter->netdev;
5794 struct ixgbe_hw *hw = &adapter->hw;
5795 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5796 u64 total_mpc = 0;
5797 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5798 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5799 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5800 u64 bytes = 0, packets = 0;
5801
5802 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5803 test_bit(__IXGBE_RESETTING, &adapter->state))
5804 return;
5805
5806 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5807 u64 rsc_count = 0;
5808 u64 rsc_flush = 0;
5809 for (i = 0; i < 16; i++)
5810 adapter->hw_rx_no_dma_resources +=
5811 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5812 for (i = 0; i < adapter->num_rx_queues; i++) {
5813 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5814 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5815 }
5816 adapter->rsc_total_count = rsc_count;
5817 adapter->rsc_total_flush = rsc_flush;
5818 }
5819
5820 for (i = 0; i < adapter->num_rx_queues; i++) {
5821 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5822 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5823 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5824 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5825 bytes += rx_ring->stats.bytes;
5826 packets += rx_ring->stats.packets;
5827 }
5828 adapter->non_eop_descs = non_eop_descs;
5829 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5830 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5831 netdev->stats.rx_bytes = bytes;
5832 netdev->stats.rx_packets = packets;
5833
5834 bytes = 0;
5835 packets = 0;
5836 /* gather some stats to the adapter struct that are per queue */
5837 for (i = 0; i < adapter->num_tx_queues; i++) {
5838 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5839 restart_queue += tx_ring->tx_stats.restart_queue;
5840 tx_busy += tx_ring->tx_stats.tx_busy;
5841 bytes += tx_ring->stats.bytes;
5842 packets += tx_ring->stats.packets;
5843 }
5844 adapter->restart_queue = restart_queue;
5845 adapter->tx_busy = tx_busy;
5846 netdev->stats.tx_bytes = bytes;
5847 netdev->stats.tx_packets = packets;
5848
5849 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5850 for (i = 0; i < 8; i++) {
5851 /* for packet buffers not used, the register should read 0 */
5852 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5853 missed_rx += mpc;
5854 hwstats->mpc[i] += mpc;
5855 total_mpc += hwstats->mpc[i];
5856 if (hw->mac.type == ixgbe_mac_82598EB)
5857 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5858 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5859 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5860 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5861 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5862 switch (hw->mac.type) {
5863 case ixgbe_mac_82598EB:
5864 hwstats->pxonrxc[i] +=
5865 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5866 break;
5867 case ixgbe_mac_82599EB:
5868 case ixgbe_mac_X540:
5869 hwstats->pxonrxc[i] +=
5870 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5871 break;
5872 default:
5873 break;
5874 }
5875 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5876 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5877 }
5878 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5879 /* work around hardware counting issue */
5880 hwstats->gprc -= missed_rx;
5881
5882 ixgbe_update_xoff_received(adapter);
5883
5884 /* 82598 hardware only has a 32 bit counter in the high register */
5885 switch (hw->mac.type) {
5886 case ixgbe_mac_82598EB:
5887 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5888 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5889 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5890 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5891 break;
5892 case ixgbe_mac_X540:
5893 /* OS2BMC stats are X540 only*/
5894 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5895 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5896 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5897 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5898 case ixgbe_mac_82599EB:
5899 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5900 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5901 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5902 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5903 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5904 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5905 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5906 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5907 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5908 #ifdef IXGBE_FCOE
5909 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5910 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5911 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5912 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5913 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5914 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5915 #endif /* IXGBE_FCOE */
5916 break;
5917 default:
5918 break;
5919 }
5920 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5921 hwstats->bprc += bprc;
5922 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5923 if (hw->mac.type == ixgbe_mac_82598EB)
5924 hwstats->mprc -= bprc;
5925 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5926 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5927 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5928 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5929 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5930 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5931 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5932 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5933 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5934 hwstats->lxontxc += lxon;
5935 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5936 hwstats->lxofftxc += lxoff;
5937 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5938 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5939 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5940 /*
5941 * 82598 errata - tx of flow control packets is included in tx counters
5942 */
5943 xon_off_tot = lxon + lxoff;
5944 hwstats->gptc -= xon_off_tot;
5945 hwstats->mptc -= xon_off_tot;
5946 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5947 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5948 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5949 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5950 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5951 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5952 hwstats->ptc64 -= xon_off_tot;
5953 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5954 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5955 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5956 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5957 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5958 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5959
5960 /* Fill out the OS statistics structure */
5961 netdev->stats.multicast = hwstats->mprc;
5962
5963 /* Rx Errors */
5964 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5965 netdev->stats.rx_dropped = 0;
5966 netdev->stats.rx_length_errors = hwstats->rlec;
5967 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5968 netdev->stats.rx_missed_errors = total_mpc;
5969 }
5970
5971 /**
5972 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5973 * @adapter - pointer to the device adapter structure
5974 **/
5975 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5976 {
5977 struct ixgbe_hw *hw = &adapter->hw;
5978 int i;
5979
5980 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5981 return;
5982
5983 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5984
5985 /* if interface is down do nothing */
5986 if (test_bit(__IXGBE_DOWN, &adapter->state))
5987 return;
5988
5989 /* do nothing if we are not using signature filters */
5990 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5991 return;
5992
5993 adapter->fdir_overflow++;
5994
5995 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5996 for (i = 0; i < adapter->num_tx_queues; i++)
5997 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5998 &(adapter->tx_ring[i]->state));
5999 /* re-enable flow director interrupts */
6000 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6001 } else {
6002 e_err(probe, "failed to finish FDIR re-initialization, "
6003 "ignored adding FDIR ATR filters\n");
6004 }
6005 }
6006
6007 /**
6008 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6009 * @adapter - pointer to the device adapter structure
6010 *
6011 * This function serves two purposes. First it strobes the interrupt lines
6012 * in order to make certain interrupts are occuring. Secondly it sets the
6013 * bits needed to check for TX hangs. As a result we should immediately
6014 * determine if a hang has occured.
6015 */
6016 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6017 {
6018 struct ixgbe_hw *hw = &adapter->hw;
6019 u64 eics = 0;
6020 int i;
6021
6022 /* If we're down or resetting, just bail */
6023 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6024 test_bit(__IXGBE_RESETTING, &adapter->state))
6025 return;
6026
6027 /* Force detection of hung controller */
6028 if (netif_carrier_ok(adapter->netdev)) {
6029 for (i = 0; i < adapter->num_tx_queues; i++)
6030 set_check_for_tx_hang(adapter->tx_ring[i]);
6031 }
6032
6033 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6034 /*
6035 * for legacy and MSI interrupts don't set any bits
6036 * that are enabled for EIAM, because this operation
6037 * would set *both* EIMS and EICS for any bit in EIAM
6038 */
6039 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6040 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6041 } else {
6042 /* get one bit for every active tx/rx interrupt vector */
6043 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6044 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6045 if (qv->rxr_count || qv->txr_count)
6046 eics |= ((u64)1 << i);
6047 }
6048 }
6049
6050 /* Cause software interrupt to ensure rings are cleaned */
6051 ixgbe_irq_rearm_queues(adapter, eics);
6052
6053 }
6054
6055 /**
6056 * ixgbe_watchdog_update_link - update the link status
6057 * @adapter - pointer to the device adapter structure
6058 * @link_speed - pointer to a u32 to store the link_speed
6059 **/
6060 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6061 {
6062 struct ixgbe_hw *hw = &adapter->hw;
6063 u32 link_speed = adapter->link_speed;
6064 bool link_up = adapter->link_up;
6065 int i;
6066
6067 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6068 return;
6069
6070 if (hw->mac.ops.check_link) {
6071 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6072 } else {
6073 /* always assume link is up, if no check link function */
6074 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6075 link_up = true;
6076 }
6077 if (link_up) {
6078 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6079 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6080 hw->mac.ops.fc_enable(hw, i);
6081 } else {
6082 hw->mac.ops.fc_enable(hw, 0);
6083 }
6084 }
6085
6086 if (link_up ||
6087 time_after(jiffies, (adapter->link_check_timeout +
6088 IXGBE_TRY_LINK_TIMEOUT))) {
6089 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6090 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6091 IXGBE_WRITE_FLUSH(hw);
6092 }
6093
6094 adapter->link_up = link_up;
6095 adapter->link_speed = link_speed;
6096 }
6097
6098 /**
6099 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6100 * print link up message
6101 * @adapter - pointer to the device adapter structure
6102 **/
6103 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6104 {
6105 struct net_device *netdev = adapter->netdev;
6106 struct ixgbe_hw *hw = &adapter->hw;
6107 u32 link_speed = adapter->link_speed;
6108 bool flow_rx, flow_tx;
6109
6110 /* only continue if link was previously down */
6111 if (netif_carrier_ok(netdev))
6112 return;
6113
6114 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6115
6116 switch (hw->mac.type) {
6117 case ixgbe_mac_82598EB: {
6118 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6119 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6120 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6121 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6122 }
6123 break;
6124 case ixgbe_mac_X540:
6125 case ixgbe_mac_82599EB: {
6126 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6127 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6128 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6129 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6130 }
6131 break;
6132 default:
6133 flow_tx = false;
6134 flow_rx = false;
6135 break;
6136 }
6137 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6138 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6139 "10 Gbps" :
6140 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6141 "1 Gbps" :
6142 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6143 "100 Mbps" :
6144 "unknown speed"))),
6145 ((flow_rx && flow_tx) ? "RX/TX" :
6146 (flow_rx ? "RX" :
6147 (flow_tx ? "TX" : "None"))));
6148
6149 netif_carrier_on(netdev);
6150 #ifdef HAVE_IPLINK_VF_CONFIG
6151 ixgbe_check_vf_rate_limit(adapter);
6152 #endif /* HAVE_IPLINK_VF_CONFIG */
6153 }
6154
6155 /**
6156 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6157 * print link down message
6158 * @adapter - pointer to the adapter structure
6159 **/
6160 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6161 {
6162 struct net_device *netdev = adapter->netdev;
6163 struct ixgbe_hw *hw = &adapter->hw;
6164
6165 adapter->link_up = false;
6166 adapter->link_speed = 0;
6167
6168 /* only continue if link was up previously */
6169 if (!netif_carrier_ok(netdev))
6170 return;
6171
6172 /* poll for SFP+ cable when link is down */
6173 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6174 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6175
6176 e_info(drv, "NIC Link is Down\n");
6177 netif_carrier_off(netdev);
6178 }
6179
6180 /**
6181 * ixgbe_watchdog_flush_tx - flush queues on link down
6182 * @adapter - pointer to the device adapter structure
6183 **/
6184 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6185 {
6186 int i;
6187 int some_tx_pending = 0;
6188
6189 if (!netif_carrier_ok(adapter->netdev)) {
6190 for (i = 0; i < adapter->num_tx_queues; i++) {
6191 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6192 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6193 some_tx_pending = 1;
6194 break;
6195 }
6196 }
6197
6198 if (some_tx_pending) {
6199 /* We've lost link, so the controller stops DMA,
6200 * but we've got queued Tx work that's never going
6201 * to get done, so reset controller to flush Tx.
6202 * (Do the reset outside of interrupt context).
6203 */
6204 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6205 }
6206 }
6207 }
6208
6209 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6210 {
6211 u32 ssvpc;
6212
6213 /* Do not perform spoof check for 82598 */
6214 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6215 return;
6216
6217 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6218
6219 /*
6220 * ssvpc register is cleared on read, if zero then no
6221 * spoofed packets in the last interval.
6222 */
6223 if (!ssvpc)
6224 return;
6225
6226 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6227 }
6228
6229 /**
6230 * ixgbe_watchdog_subtask - check and bring link up
6231 * @adapter - pointer to the device adapter structure
6232 **/
6233 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6234 {
6235 /* if interface is down do nothing */
6236 if (test_bit(__IXGBE_DOWN, &adapter->state))
6237 return;
6238
6239 ixgbe_watchdog_update_link(adapter);
6240
6241 if (adapter->link_up)
6242 ixgbe_watchdog_link_is_up(adapter);
6243 else
6244 ixgbe_watchdog_link_is_down(adapter);
6245
6246 ixgbe_spoof_check(adapter);
6247 ixgbe_update_stats(adapter);
6248
6249 ixgbe_watchdog_flush_tx(adapter);
6250 }
6251
6252 /**
6253 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6254 * @adapter - the ixgbe adapter structure
6255 **/
6256 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6257 {
6258 struct ixgbe_hw *hw = &adapter->hw;
6259 s32 err;
6260
6261 /* not searching for SFP so there is nothing to do here */
6262 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6263 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6264 return;
6265
6266 /* someone else is in init, wait until next service event */
6267 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6268 return;
6269
6270 err = hw->phy.ops.identify_sfp(hw);
6271 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6272 goto sfp_out;
6273
6274 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6275 /* If no cable is present, then we need to reset
6276 * the next time we find a good cable. */
6277 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6278 }
6279
6280 /* exit on error */
6281 if (err)
6282 goto sfp_out;
6283
6284 /* exit if reset not needed */
6285 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6286 goto sfp_out;
6287
6288 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6289
6290 /*
6291 * A module may be identified correctly, but the EEPROM may not have
6292 * support for that module. setup_sfp() will fail in that case, so
6293 * we should not allow that module to load.
6294 */
6295 if (hw->mac.type == ixgbe_mac_82598EB)
6296 err = hw->phy.ops.reset(hw);
6297 else
6298 err = hw->mac.ops.setup_sfp(hw);
6299
6300 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6301 goto sfp_out;
6302
6303 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6304 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6305
6306 sfp_out:
6307 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6308
6309 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6310 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6311 e_dev_err("failed to initialize because an unsupported "
6312 "SFP+ module type was detected.\n");
6313 e_dev_err("Reload the driver after installing a "
6314 "supported module.\n");
6315 unregister_netdev(adapter->netdev);
6316 }
6317 }
6318
6319 /**
6320 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6321 * @adapter - the ixgbe adapter structure
6322 **/
6323 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6324 {
6325 struct ixgbe_hw *hw = &adapter->hw;
6326 u32 autoneg;
6327 bool negotiation;
6328
6329 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6330 return;
6331
6332 /* someone else is in init, wait until next service event */
6333 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6334 return;
6335
6336 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6337
6338 autoneg = hw->phy.autoneg_advertised;
6339 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6340 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6341 hw->mac.autotry_restart = false;
6342 if (hw->mac.ops.setup_link)
6343 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6344
6345 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6346 adapter->link_check_timeout = jiffies;
6347 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6348 }
6349
6350 /**
6351 * ixgbe_service_timer - Timer Call-back
6352 * @data: pointer to adapter cast into an unsigned long
6353 **/
6354 static void ixgbe_service_timer(unsigned long data)
6355 {
6356 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6357 unsigned long next_event_offset;
6358
6359 /* poll faster when waiting for link */
6360 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6361 next_event_offset = HZ / 10;
6362 else
6363 next_event_offset = HZ * 2;
6364
6365 /* Reset the timer */
6366 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6367
6368 ixgbe_service_event_schedule(adapter);
6369 }
6370
6371 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6372 {
6373 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6374 return;
6375
6376 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6377
6378 /* If we're already down or resetting, just bail */
6379 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6380 test_bit(__IXGBE_RESETTING, &adapter->state))
6381 return;
6382
6383 ixgbe_dump(adapter);
6384 netdev_err(adapter->netdev, "Reset adapter\n");
6385 adapter->tx_timeout_count++;
6386
6387 ixgbe_reinit_locked(adapter);
6388 }
6389
6390 /**
6391 * ixgbe_service_task - manages and runs subtasks
6392 * @work: pointer to work_struct containing our data
6393 **/
6394 static void ixgbe_service_task(struct work_struct *work)
6395 {
6396 struct ixgbe_adapter *adapter = container_of(work,
6397 struct ixgbe_adapter,
6398 service_task);
6399
6400 ixgbe_reset_subtask(adapter);
6401 ixgbe_sfp_detection_subtask(adapter);
6402 ixgbe_sfp_link_config_subtask(adapter);
6403 ixgbe_check_overtemp_subtask(adapter);
6404 ixgbe_watchdog_subtask(adapter);
6405 ixgbe_fdir_reinit_subtask(adapter);
6406 ixgbe_check_hang_subtask(adapter);
6407
6408 ixgbe_service_event_complete(adapter);
6409 }
6410
6411 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6412 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6413 u32 tx_flags, u8 *hdr_len, __be16 protocol)
6414 {
6415 struct ixgbe_adv_tx_context_desc *context_desc;
6416 unsigned int i;
6417 int err;
6418 struct ixgbe_tx_buffer *tx_buffer_info;
6419 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6420 u32 mss_l4len_idx, l4len;
6421
6422 if (skb_is_gso(skb)) {
6423 if (skb_header_cloned(skb)) {
6424 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6425 if (err)
6426 return err;
6427 }
6428 l4len = tcp_hdrlen(skb);
6429 *hdr_len += l4len;
6430
6431 if (protocol == htons(ETH_P_IP)) {
6432 struct iphdr *iph = ip_hdr(skb);
6433 iph->tot_len = 0;
6434 iph->check = 0;
6435 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6436 iph->daddr, 0,
6437 IPPROTO_TCP,
6438 0);
6439 } else if (skb_is_gso_v6(skb)) {
6440 ipv6_hdr(skb)->payload_len = 0;
6441 tcp_hdr(skb)->check =
6442 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6443 &ipv6_hdr(skb)->daddr,
6444 0, IPPROTO_TCP, 0);
6445 }
6446
6447 i = tx_ring->next_to_use;
6448
6449 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6450 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6451
6452 /* VLAN MACLEN IPLEN */
6453 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6454 vlan_macip_lens |=
6455 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6456 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6457 IXGBE_ADVTXD_MACLEN_SHIFT);
6458 *hdr_len += skb_network_offset(skb);
6459 vlan_macip_lens |=
6460 (skb_transport_header(skb) - skb_network_header(skb));
6461 *hdr_len +=
6462 (skb_transport_header(skb) - skb_network_header(skb));
6463 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6464 context_desc->seqnum_seed = 0;
6465
6466 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6467 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6468 IXGBE_ADVTXD_DTYP_CTXT);
6469
6470 if (protocol == htons(ETH_P_IP))
6471 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6472 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6473 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6474
6475 /* MSS L4LEN IDX */
6476 mss_l4len_idx =
6477 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6478 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6479 /* use index 1 for TSO */
6480 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6481 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6482
6483 tx_buffer_info->time_stamp = jiffies;
6484 tx_buffer_info->next_to_watch = i;
6485
6486 i++;
6487 if (i == tx_ring->count)
6488 i = 0;
6489 tx_ring->next_to_use = i;
6490
6491 return true;
6492 }
6493 return false;
6494 }
6495
6496 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6497 __be16 protocol)
6498 {
6499 u32 rtn = 0;
6500
6501 switch (protocol) {
6502 case cpu_to_be16(ETH_P_IP):
6503 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6504 switch (ip_hdr(skb)->protocol) {
6505 case IPPROTO_TCP:
6506 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6507 break;
6508 case IPPROTO_SCTP:
6509 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6510 break;
6511 }
6512 break;
6513 case cpu_to_be16(ETH_P_IPV6):
6514 /* XXX what about other V6 headers?? */
6515 switch (ipv6_hdr(skb)->nexthdr) {
6516 case IPPROTO_TCP:
6517 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6518 break;
6519 case IPPROTO_SCTP:
6520 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6521 break;
6522 }
6523 break;
6524 default:
6525 if (unlikely(net_ratelimit()))
6526 e_warn(probe, "partial checksum but proto=%x!\n",
6527 protocol);
6528 break;
6529 }
6530
6531 return rtn;
6532 }
6533
6534 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6535 struct ixgbe_ring *tx_ring,
6536 struct sk_buff *skb, u32 tx_flags,
6537 __be16 protocol)
6538 {
6539 struct ixgbe_adv_tx_context_desc *context_desc;
6540 unsigned int i;
6541 struct ixgbe_tx_buffer *tx_buffer_info;
6542 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6543
6544 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6545 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6546 i = tx_ring->next_to_use;
6547 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6548 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6549
6550 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6551 vlan_macip_lens |=
6552 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6553 vlan_macip_lens |= (skb_network_offset(skb) <<
6554 IXGBE_ADVTXD_MACLEN_SHIFT);
6555 if (skb->ip_summed == CHECKSUM_PARTIAL)
6556 vlan_macip_lens |= (skb_transport_header(skb) -
6557 skb_network_header(skb));
6558
6559 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6560 context_desc->seqnum_seed = 0;
6561
6562 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6563 IXGBE_ADVTXD_DTYP_CTXT);
6564
6565 if (skb->ip_summed == CHECKSUM_PARTIAL)
6566 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6567
6568 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6569 /* use index zero for tx checksum offload */
6570 context_desc->mss_l4len_idx = 0;
6571
6572 tx_buffer_info->time_stamp = jiffies;
6573 tx_buffer_info->next_to_watch = i;
6574
6575 i++;
6576 if (i == tx_ring->count)
6577 i = 0;
6578 tx_ring->next_to_use = i;
6579
6580 return true;
6581 }
6582
6583 return false;
6584 }
6585
6586 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6587 struct ixgbe_ring *tx_ring,
6588 struct sk_buff *skb, u32 tx_flags,
6589 unsigned int first, const u8 hdr_len)
6590 {
6591 struct device *dev = tx_ring->dev;
6592 struct ixgbe_tx_buffer *tx_buffer_info;
6593 unsigned int len;
6594 unsigned int total = skb->len;
6595 unsigned int offset = 0, size, count = 0, i;
6596 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6597 unsigned int f;
6598 unsigned int bytecount = skb->len;
6599 u16 gso_segs = 1;
6600
6601 i = tx_ring->next_to_use;
6602
6603 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6604 /* excluding fcoe_crc_eof for FCoE */
6605 total -= sizeof(struct fcoe_crc_eof);
6606
6607 len = min(skb_headlen(skb), total);
6608 while (len) {
6609 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6610 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6611
6612 tx_buffer_info->length = size;
6613 tx_buffer_info->mapped_as_page = false;
6614 tx_buffer_info->dma = dma_map_single(dev,
6615 skb->data + offset,
6616 size, DMA_TO_DEVICE);
6617 if (dma_mapping_error(dev, tx_buffer_info->dma))
6618 goto dma_error;
6619 tx_buffer_info->time_stamp = jiffies;
6620 tx_buffer_info->next_to_watch = i;
6621
6622 len -= size;
6623 total -= size;
6624 offset += size;
6625 count++;
6626
6627 if (len) {
6628 i++;
6629 if (i == tx_ring->count)
6630 i = 0;
6631 }
6632 }
6633
6634 for (f = 0; f < nr_frags; f++) {
6635 struct skb_frag_struct *frag;
6636
6637 frag = &skb_shinfo(skb)->frags[f];
6638 len = min((unsigned int)frag->size, total);
6639 offset = frag->page_offset;
6640
6641 while (len) {
6642 i++;
6643 if (i == tx_ring->count)
6644 i = 0;
6645
6646 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6647 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6648
6649 tx_buffer_info->length = size;
6650 tx_buffer_info->dma = dma_map_page(dev,
6651 frag->page,
6652 offset, size,
6653 DMA_TO_DEVICE);
6654 tx_buffer_info->mapped_as_page = true;
6655 if (dma_mapping_error(dev, tx_buffer_info->dma))
6656 goto dma_error;
6657 tx_buffer_info->time_stamp = jiffies;
6658 tx_buffer_info->next_to_watch = i;
6659
6660 len -= size;
6661 total -= size;
6662 offset += size;
6663 count++;
6664 }
6665 if (total == 0)
6666 break;
6667 }
6668
6669 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6670 gso_segs = skb_shinfo(skb)->gso_segs;
6671 #ifdef IXGBE_FCOE
6672 /* adjust for FCoE Sequence Offload */
6673 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6674 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6675 skb_shinfo(skb)->gso_size);
6676 #endif /* IXGBE_FCOE */
6677 bytecount += (gso_segs - 1) * hdr_len;
6678
6679 /* multiply data chunks by size of headers */
6680 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6681 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6682 tx_ring->tx_buffer_info[i].skb = skb;
6683 tx_ring->tx_buffer_info[first].next_to_watch = i;
6684
6685 return count;
6686
6687 dma_error:
6688 e_dev_err("TX DMA map failed\n");
6689
6690 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6691 tx_buffer_info->dma = 0;
6692 tx_buffer_info->time_stamp = 0;
6693 tx_buffer_info->next_to_watch = 0;
6694 if (count)
6695 count--;
6696
6697 /* clear timestamp and dma mappings for remaining portion of packet */
6698 while (count--) {
6699 if (i == 0)
6700 i += tx_ring->count;
6701 i--;
6702 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6703 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6704 }
6705
6706 return 0;
6707 }
6708
6709 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6710 int tx_flags, int count, u32 paylen, u8 hdr_len)
6711 {
6712 union ixgbe_adv_tx_desc *tx_desc = NULL;
6713 struct ixgbe_tx_buffer *tx_buffer_info;
6714 u32 olinfo_status = 0, cmd_type_len = 0;
6715 unsigned int i;
6716 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6717
6718 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6719
6720 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6721
6722 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6723 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6724
6725 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6726 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6727
6728 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6729 IXGBE_ADVTXD_POPTS_SHIFT;
6730
6731 /* use index 1 context for tso */
6732 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6733 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6734 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6735 IXGBE_ADVTXD_POPTS_SHIFT;
6736
6737 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6738 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6739 IXGBE_ADVTXD_POPTS_SHIFT;
6740
6741 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6742 olinfo_status |= IXGBE_ADVTXD_CC;
6743 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6744 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6745 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6746 }
6747
6748 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6749
6750 i = tx_ring->next_to_use;
6751 while (count--) {
6752 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6753 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6754 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6755 tx_desc->read.cmd_type_len =
6756 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6757 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6758 i++;
6759 if (i == tx_ring->count)
6760 i = 0;
6761 }
6762
6763 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6764
6765 /*
6766 * Force memory writes to complete before letting h/w
6767 * know there are new descriptors to fetch. (Only
6768 * applicable for weak-ordered memory model archs,
6769 * such as IA-64).
6770 */
6771 wmb();
6772
6773 tx_ring->next_to_use = i;
6774 writel(i, tx_ring->tail);
6775 }
6776
6777 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6778 u32 tx_flags, __be16 protocol)
6779 {
6780 struct ixgbe_q_vector *q_vector = ring->q_vector;
6781 union ixgbe_atr_hash_dword input = { .dword = 0 };
6782 union ixgbe_atr_hash_dword common = { .dword = 0 };
6783 union {
6784 unsigned char *network;
6785 struct iphdr *ipv4;
6786 struct ipv6hdr *ipv6;
6787 } hdr;
6788 struct tcphdr *th;
6789 __be16 vlan_id;
6790
6791 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6792 if (!q_vector)
6793 return;
6794
6795 /* do nothing if sampling is disabled */
6796 if (!ring->atr_sample_rate)
6797 return;
6798
6799 ring->atr_count++;
6800
6801 /* snag network header to get L4 type and address */
6802 hdr.network = skb_network_header(skb);
6803
6804 /* Currently only IPv4/IPv6 with TCP is supported */
6805 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6806 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6807 (protocol != __constant_htons(ETH_P_IP) ||
6808 hdr.ipv4->protocol != IPPROTO_TCP))
6809 return;
6810
6811 th = tcp_hdr(skb);
6812
6813 /* skip this packet since the socket is closing */
6814 if (th->fin)
6815 return;
6816
6817 /* sample on all syn packets or once every atr sample count */
6818 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6819 return;
6820
6821 /* reset sample count */
6822 ring->atr_count = 0;
6823
6824 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6825
6826 /*
6827 * src and dst are inverted, think how the receiver sees them
6828 *
6829 * The input is broken into two sections, a non-compressed section
6830 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6831 * is XORed together and stored in the compressed dword.
6832 */
6833 input.formatted.vlan_id = vlan_id;
6834
6835 /*
6836 * since src port and flex bytes occupy the same word XOR them together
6837 * and write the value to source port portion of compressed dword
6838 */
6839 if (vlan_id)
6840 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6841 else
6842 common.port.src ^= th->dest ^ protocol;
6843 common.port.dst ^= th->source;
6844
6845 if (protocol == __constant_htons(ETH_P_IP)) {
6846 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6847 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6848 } else {
6849 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6850 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6851 hdr.ipv6->saddr.s6_addr32[1] ^
6852 hdr.ipv6->saddr.s6_addr32[2] ^
6853 hdr.ipv6->saddr.s6_addr32[3] ^
6854 hdr.ipv6->daddr.s6_addr32[0] ^
6855 hdr.ipv6->daddr.s6_addr32[1] ^
6856 hdr.ipv6->daddr.s6_addr32[2] ^
6857 hdr.ipv6->daddr.s6_addr32[3];
6858 }
6859
6860 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6861 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6862 input, common, ring->queue_index);
6863 }
6864
6865 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6866 {
6867 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6868 /* Herbert's original patch had:
6869 * smp_mb__after_netif_stop_queue();
6870 * but since that doesn't exist yet, just open code it. */
6871 smp_mb();
6872
6873 /* We need to check again in a case another CPU has just
6874 * made room available. */
6875 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6876 return -EBUSY;
6877
6878 /* A reprieve! - use start_queue because it doesn't call schedule */
6879 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6880 ++tx_ring->tx_stats.restart_queue;
6881 return 0;
6882 }
6883
6884 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6885 {
6886 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6887 return 0;
6888 return __ixgbe_maybe_stop_tx(tx_ring, size);
6889 }
6890
6891 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6892 {
6893 struct ixgbe_adapter *adapter = netdev_priv(dev);
6894 int txq = smp_processor_id();
6895 #ifdef IXGBE_FCOE
6896 __be16 protocol;
6897
6898 protocol = vlan_get_protocol(skb);
6899
6900 if (((protocol == htons(ETH_P_FCOE)) ||
6901 (protocol == htons(ETH_P_FIP))) &&
6902 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6903 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6904 txq += adapter->ring_feature[RING_F_FCOE].mask;
6905 return txq;
6906 }
6907 #endif
6908
6909 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6910 while (unlikely(txq >= dev->real_num_tx_queues))
6911 txq -= dev->real_num_tx_queues;
6912 return txq;
6913 }
6914
6915 return skb_tx_hash(dev, skb);
6916 }
6917
6918 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6919 struct ixgbe_adapter *adapter,
6920 struct ixgbe_ring *tx_ring)
6921 {
6922 unsigned int first;
6923 unsigned int tx_flags = 0;
6924 u8 hdr_len = 0;
6925 int tso;
6926 int count = 0;
6927 unsigned int f;
6928 __be16 protocol;
6929
6930 protocol = vlan_get_protocol(skb);
6931
6932 if (vlan_tx_tag_present(skb)) {
6933 tx_flags |= vlan_tx_tag_get(skb);
6934 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6935 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6936 tx_flags |= tx_ring->dcb_tc << 13;
6937 }
6938 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6939 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6940 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6941 skb->priority != TC_PRIO_CONTROL) {
6942 tx_flags |= tx_ring->dcb_tc << 13;
6943 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6944 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6945 }
6946
6947 #ifdef IXGBE_FCOE
6948 /* for FCoE with DCB, we force the priority to what
6949 * was specified by the switch */
6950 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6951 (protocol == htons(ETH_P_FCOE)))
6952 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6953 #endif
6954
6955 /* four things can cause us to need a context descriptor */
6956 if (skb_is_gso(skb) ||
6957 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6958 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6959 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6960 count++;
6961
6962 count += TXD_USE_COUNT(skb_headlen(skb));
6963 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6964 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6965
6966 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6967 tx_ring->tx_stats.tx_busy++;
6968 return NETDEV_TX_BUSY;
6969 }
6970
6971 first = tx_ring->next_to_use;
6972 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6973 #ifdef IXGBE_FCOE
6974 /* setup tx offload for FCoE */
6975 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6976 if (tso < 0) {
6977 dev_kfree_skb_any(skb);
6978 return NETDEV_TX_OK;
6979 }
6980 if (tso)
6981 tx_flags |= IXGBE_TX_FLAGS_FSO;
6982 #endif /* IXGBE_FCOE */
6983 } else {
6984 if (protocol == htons(ETH_P_IP))
6985 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6986 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6987 protocol);
6988 if (tso < 0) {
6989 dev_kfree_skb_any(skb);
6990 return NETDEV_TX_OK;
6991 }
6992
6993 if (tso)
6994 tx_flags |= IXGBE_TX_FLAGS_TSO;
6995 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6996 protocol) &&
6997 (skb->ip_summed == CHECKSUM_PARTIAL))
6998 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6999 }
7000
7001 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
7002 if (count) {
7003 /* add the ATR filter if ATR is on */
7004 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7005 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
7006 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
7007 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7008
7009 } else {
7010 dev_kfree_skb_any(skb);
7011 tx_ring->tx_buffer_info[first].time_stamp = 0;
7012 tx_ring->next_to_use = first;
7013 }
7014
7015 return NETDEV_TX_OK;
7016 }
7017
7018 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
7019 {
7020 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7021 struct ixgbe_ring *tx_ring;
7022
7023 tx_ring = adapter->tx_ring[skb->queue_mapping];
7024 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7025 }
7026
7027 /**
7028 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7029 * @netdev: network interface device structure
7030 * @p: pointer to an address structure
7031 *
7032 * Returns 0 on success, negative on failure
7033 **/
7034 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7035 {
7036 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7037 struct ixgbe_hw *hw = &adapter->hw;
7038 struct sockaddr *addr = p;
7039
7040 if (!is_valid_ether_addr(addr->sa_data))
7041 return -EADDRNOTAVAIL;
7042
7043 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7044 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7045
7046 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7047 IXGBE_RAH_AV);
7048
7049 return 0;
7050 }
7051
7052 static int
7053 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7054 {
7055 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7056 struct ixgbe_hw *hw = &adapter->hw;
7057 u16 value;
7058 int rc;
7059
7060 if (prtad != hw->phy.mdio.prtad)
7061 return -EINVAL;
7062 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7063 if (!rc)
7064 rc = value;
7065 return rc;
7066 }
7067
7068 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7069 u16 addr, u16 value)
7070 {
7071 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7072 struct ixgbe_hw *hw = &adapter->hw;
7073
7074 if (prtad != hw->phy.mdio.prtad)
7075 return -EINVAL;
7076 return hw->phy.ops.write_reg(hw, addr, devad, value);
7077 }
7078
7079 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7080 {
7081 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7082
7083 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7084 }
7085
7086 /**
7087 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7088 * netdev->dev_addrs
7089 * @netdev: network interface device structure
7090 *
7091 * Returns non-zero on failure
7092 **/
7093 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7094 {
7095 int err = 0;
7096 struct ixgbe_adapter *adapter = netdev_priv(dev);
7097 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7098
7099 if (is_valid_ether_addr(mac->san_addr)) {
7100 rtnl_lock();
7101 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7102 rtnl_unlock();
7103 }
7104 return err;
7105 }
7106
7107 /**
7108 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7109 * netdev->dev_addrs
7110 * @netdev: network interface device structure
7111 *
7112 * Returns non-zero on failure
7113 **/
7114 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7115 {
7116 int err = 0;
7117 struct ixgbe_adapter *adapter = netdev_priv(dev);
7118 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7119
7120 if (is_valid_ether_addr(mac->san_addr)) {
7121 rtnl_lock();
7122 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7123 rtnl_unlock();
7124 }
7125 return err;
7126 }
7127
7128 #ifdef CONFIG_NET_POLL_CONTROLLER
7129 /*
7130 * Polling 'interrupt' - used by things like netconsole to send skbs
7131 * without having to re-enable interrupts. It's not called while
7132 * the interrupt routine is executing.
7133 */
7134 static void ixgbe_netpoll(struct net_device *netdev)
7135 {
7136 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7137 int i;
7138
7139 /* if interface is down do nothing */
7140 if (test_bit(__IXGBE_DOWN, &adapter->state))
7141 return;
7142
7143 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7144 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7145 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7146 for (i = 0; i < num_q_vectors; i++) {
7147 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7148 ixgbe_msix_clean_many(0, q_vector);
7149 }
7150 } else {
7151 ixgbe_intr(adapter->pdev->irq, netdev);
7152 }
7153 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7154 }
7155 #endif
7156
7157 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7158 struct rtnl_link_stats64 *stats)
7159 {
7160 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7161 int i;
7162
7163 rcu_read_lock();
7164 for (i = 0; i < adapter->num_rx_queues; i++) {
7165 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7166 u64 bytes, packets;
7167 unsigned int start;
7168
7169 if (ring) {
7170 do {
7171 start = u64_stats_fetch_begin_bh(&ring->syncp);
7172 packets = ring->stats.packets;
7173 bytes = ring->stats.bytes;
7174 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7175 stats->rx_packets += packets;
7176 stats->rx_bytes += bytes;
7177 }
7178 }
7179
7180 for (i = 0; i < adapter->num_tx_queues; i++) {
7181 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7182 u64 bytes, packets;
7183 unsigned int start;
7184
7185 if (ring) {
7186 do {
7187 start = u64_stats_fetch_begin_bh(&ring->syncp);
7188 packets = ring->stats.packets;
7189 bytes = ring->stats.bytes;
7190 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7191 stats->tx_packets += packets;
7192 stats->tx_bytes += bytes;
7193 }
7194 }
7195 rcu_read_unlock();
7196 /* following stats updated by ixgbe_watchdog_task() */
7197 stats->multicast = netdev->stats.multicast;
7198 stats->rx_errors = netdev->stats.rx_errors;
7199 stats->rx_length_errors = netdev->stats.rx_length_errors;
7200 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7201 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7202 return stats;
7203 }
7204
7205
7206 static const struct net_device_ops ixgbe_netdev_ops = {
7207 .ndo_open = ixgbe_open,
7208 .ndo_stop = ixgbe_close,
7209 .ndo_start_xmit = ixgbe_xmit_frame,
7210 .ndo_select_queue = ixgbe_select_queue,
7211 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7212 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7213 .ndo_validate_addr = eth_validate_addr,
7214 .ndo_set_mac_address = ixgbe_set_mac,
7215 .ndo_change_mtu = ixgbe_change_mtu,
7216 .ndo_tx_timeout = ixgbe_tx_timeout,
7217 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7218 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7219 .ndo_do_ioctl = ixgbe_ioctl,
7220 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7221 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7222 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7223 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7224 .ndo_get_stats64 = ixgbe_get_stats64,
7225 #ifdef CONFIG_IXGBE_DCB
7226 .ndo_setup_tc = ixgbe_setup_tc,
7227 #endif
7228 #ifdef CONFIG_NET_POLL_CONTROLLER
7229 .ndo_poll_controller = ixgbe_netpoll,
7230 #endif
7231 #ifdef IXGBE_FCOE
7232 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7233 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7234 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7235 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7236 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7237 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7238 #endif /* IXGBE_FCOE */
7239 };
7240
7241 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7242 const struct ixgbe_info *ii)
7243 {
7244 #ifdef CONFIG_PCI_IOV
7245 struct ixgbe_hw *hw = &adapter->hw;
7246 int err;
7247 int num_vf_macvlans, i;
7248 struct vf_macvlans *mv_list;
7249
7250 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7251 return;
7252
7253 /* The 82599 supports up to 64 VFs per physical function
7254 * but this implementation limits allocation to 63 so that
7255 * basic networking resources are still available to the
7256 * physical function
7257 */
7258 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7259 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7260 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7261 if (err) {
7262 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7263 goto err_novfs;
7264 }
7265
7266 num_vf_macvlans = hw->mac.num_rar_entries -
7267 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7268
7269 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7270 sizeof(struct vf_macvlans),
7271 GFP_KERNEL);
7272 if (mv_list) {
7273 /* Initialize list of VF macvlans */
7274 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7275 for (i = 0; i < num_vf_macvlans; i++) {
7276 mv_list->vf = -1;
7277 mv_list->free = true;
7278 mv_list->rar_entry = hw->mac.num_rar_entries -
7279 (i + adapter->num_vfs + 1);
7280 list_add(&mv_list->l, &adapter->vf_mvs.l);
7281 mv_list++;
7282 }
7283 }
7284
7285 /* If call to enable VFs succeeded then allocate memory
7286 * for per VF control structures.
7287 */
7288 adapter->vfinfo =
7289 kcalloc(adapter->num_vfs,
7290 sizeof(struct vf_data_storage), GFP_KERNEL);
7291 if (adapter->vfinfo) {
7292 /* Now that we're sure SR-IOV is enabled
7293 * and memory allocated set up the mailbox parameters
7294 */
7295 ixgbe_init_mbx_params_pf(hw);
7296 memcpy(&hw->mbx.ops, ii->mbx_ops,
7297 sizeof(hw->mbx.ops));
7298
7299 /* Disable RSC when in SR-IOV mode */
7300 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7301 IXGBE_FLAG2_RSC_ENABLED);
7302 return;
7303 }
7304
7305 /* Oh oh */
7306 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7307 "SRIOV disabled\n");
7308 pci_disable_sriov(adapter->pdev);
7309
7310 err_novfs:
7311 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7312 adapter->num_vfs = 0;
7313 #endif /* CONFIG_PCI_IOV */
7314 }
7315
7316 /**
7317 * ixgbe_probe - Device Initialization Routine
7318 * @pdev: PCI device information struct
7319 * @ent: entry in ixgbe_pci_tbl
7320 *
7321 * Returns 0 on success, negative on failure
7322 *
7323 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7324 * The OS initialization, configuring of the adapter private structure,
7325 * and a hardware reset occur.
7326 **/
7327 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7328 const struct pci_device_id *ent)
7329 {
7330 struct net_device *netdev;
7331 struct ixgbe_adapter *adapter = NULL;
7332 struct ixgbe_hw *hw;
7333 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7334 static int cards_found;
7335 int i, err, pci_using_dac;
7336 u8 part_str[IXGBE_PBANUM_LENGTH];
7337 unsigned int indices = num_possible_cpus();
7338 #ifdef IXGBE_FCOE
7339 u16 device_caps;
7340 #endif
7341 u32 eec;
7342
7343 /* Catch broken hardware that put the wrong VF device ID in
7344 * the PCIe SR-IOV capability.
7345 */
7346 if (pdev->is_virtfn) {
7347 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7348 pci_name(pdev), pdev->vendor, pdev->device);
7349 return -EINVAL;
7350 }
7351
7352 err = pci_enable_device_mem(pdev);
7353 if (err)
7354 return err;
7355
7356 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7357 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7358 pci_using_dac = 1;
7359 } else {
7360 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7361 if (err) {
7362 err = dma_set_coherent_mask(&pdev->dev,
7363 DMA_BIT_MASK(32));
7364 if (err) {
7365 dev_err(&pdev->dev,
7366 "No usable DMA configuration, aborting\n");
7367 goto err_dma;
7368 }
7369 }
7370 pci_using_dac = 0;
7371 }
7372
7373 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7374 IORESOURCE_MEM), ixgbe_driver_name);
7375 if (err) {
7376 dev_err(&pdev->dev,
7377 "pci_request_selected_regions failed 0x%x\n", err);
7378 goto err_pci_reg;
7379 }
7380
7381 pci_enable_pcie_error_reporting(pdev);
7382
7383 pci_set_master(pdev);
7384 pci_save_state(pdev);
7385
7386 if (ii->mac == ixgbe_mac_82598EB)
7387 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7388 else
7389 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7390
7391 #if defined(CONFIG_DCB)
7392 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7393 #elif defined(IXGBE_FCOE)
7394 indices += min_t(unsigned int, num_possible_cpus(),
7395 IXGBE_MAX_FCOE_INDICES);
7396 #endif
7397 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7398 if (!netdev) {
7399 err = -ENOMEM;
7400 goto err_alloc_etherdev;
7401 }
7402
7403 SET_NETDEV_DEV(netdev, &pdev->dev);
7404
7405 adapter = netdev_priv(netdev);
7406 pci_set_drvdata(pdev, adapter);
7407
7408 adapter->netdev = netdev;
7409 adapter->pdev = pdev;
7410 hw = &adapter->hw;
7411 hw->back = adapter;
7412 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7413
7414 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7415 pci_resource_len(pdev, 0));
7416 if (!hw->hw_addr) {
7417 err = -EIO;
7418 goto err_ioremap;
7419 }
7420
7421 for (i = 1; i <= 5; i++) {
7422 if (pci_resource_len(pdev, i) == 0)
7423 continue;
7424 }
7425
7426 netdev->netdev_ops = &ixgbe_netdev_ops;
7427 ixgbe_set_ethtool_ops(netdev);
7428 netdev->watchdog_timeo = 5 * HZ;
7429 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7430
7431 adapter->bd_number = cards_found;
7432
7433 /* Setup hw api */
7434 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7435 hw->mac.type = ii->mac;
7436
7437 /* EEPROM */
7438 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7439 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7440 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7441 if (!(eec & (1 << 8)))
7442 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7443
7444 /* PHY */
7445 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7446 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7447 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7448 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7449 hw->phy.mdio.mmds = 0;
7450 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7451 hw->phy.mdio.dev = netdev;
7452 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7453 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7454
7455 ii->get_invariants(hw);
7456
7457 /* setup the private structure */
7458 err = ixgbe_sw_init(adapter);
7459 if (err)
7460 goto err_sw_init;
7461
7462 /* Make it possible the adapter to be woken up via WOL */
7463 switch (adapter->hw.mac.type) {
7464 case ixgbe_mac_82599EB:
7465 case ixgbe_mac_X540:
7466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7467 break;
7468 default:
7469 break;
7470 }
7471
7472 /*
7473 * If there is a fan on this device and it has failed log the
7474 * failure.
7475 */
7476 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7477 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7478 if (esdp & IXGBE_ESDP_SDP1)
7479 e_crit(probe, "Fan has stopped, replace the adapter\n");
7480 }
7481
7482 /* reset_hw fills in the perm_addr as well */
7483 hw->phy.reset_if_overtemp = true;
7484 err = hw->mac.ops.reset_hw(hw);
7485 hw->phy.reset_if_overtemp = false;
7486 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7487 hw->mac.type == ixgbe_mac_82598EB) {
7488 err = 0;
7489 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7490 e_dev_err("failed to load because an unsupported SFP+ "
7491 "module type was detected.\n");
7492 e_dev_err("Reload the driver after installing a supported "
7493 "module.\n");
7494 goto err_sw_init;
7495 } else if (err) {
7496 e_dev_err("HW Init failed: %d\n", err);
7497 goto err_sw_init;
7498 }
7499
7500 ixgbe_probe_vf(adapter, ii);
7501
7502 netdev->features = NETIF_F_SG |
7503 NETIF_F_IP_CSUM |
7504 NETIF_F_HW_VLAN_TX |
7505 NETIF_F_HW_VLAN_RX |
7506 NETIF_F_HW_VLAN_FILTER;
7507
7508 netdev->features |= NETIF_F_IPV6_CSUM;
7509 netdev->features |= NETIF_F_TSO;
7510 netdev->features |= NETIF_F_TSO6;
7511 netdev->features |= NETIF_F_GRO;
7512 netdev->features |= NETIF_F_RXHASH;
7513
7514 switch (adapter->hw.mac.type) {
7515 case ixgbe_mac_82599EB:
7516 case ixgbe_mac_X540:
7517 netdev->features |= NETIF_F_SCTP_CSUM;
7518 break;
7519 default:
7520 break;
7521 }
7522
7523 netdev->vlan_features |= NETIF_F_TSO;
7524 netdev->vlan_features |= NETIF_F_TSO6;
7525 netdev->vlan_features |= NETIF_F_IP_CSUM;
7526 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7527 netdev->vlan_features |= NETIF_F_SG;
7528
7529 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7530 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7531 IXGBE_FLAG_DCB_ENABLED);
7532
7533 #ifdef CONFIG_IXGBE_DCB
7534 netdev->dcbnl_ops = &dcbnl_ops;
7535 #endif
7536
7537 #ifdef IXGBE_FCOE
7538 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7539 if (hw->mac.ops.get_device_caps) {
7540 hw->mac.ops.get_device_caps(hw, &device_caps);
7541 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7542 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7543 }
7544 }
7545 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7546 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7547 netdev->vlan_features |= NETIF_F_FSO;
7548 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7549 }
7550 #endif /* IXGBE_FCOE */
7551 if (pci_using_dac) {
7552 netdev->features |= NETIF_F_HIGHDMA;
7553 netdev->vlan_features |= NETIF_F_HIGHDMA;
7554 }
7555
7556 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7557 netdev->features |= NETIF_F_LRO;
7558
7559 /* make sure the EEPROM is good */
7560 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7561 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7562 err = -EIO;
7563 goto err_eeprom;
7564 }
7565
7566 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7567 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7568
7569 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7570 e_dev_err("invalid MAC address\n");
7571 err = -EIO;
7572 goto err_eeprom;
7573 }
7574
7575 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7576 if (hw->mac.ops.disable_tx_laser &&
7577 ((hw->phy.multispeed_fiber) ||
7578 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7579 (hw->mac.type == ixgbe_mac_82599EB))))
7580 hw->mac.ops.disable_tx_laser(hw);
7581
7582 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7583 (unsigned long) adapter);
7584
7585 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7586 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7587
7588 err = ixgbe_init_interrupt_scheme(adapter);
7589 if (err)
7590 goto err_sw_init;
7591
7592 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7593 netdev->features &= ~NETIF_F_RXHASH;
7594
7595 switch (pdev->device) {
7596 case IXGBE_DEV_ID_82599_SFP:
7597 /* Only this subdevice supports WOL */
7598 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7599 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7600 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7601 break;
7602 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7603 /* All except this subdevice support WOL */
7604 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7605 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7606 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7607 break;
7608 case IXGBE_DEV_ID_82599_KX4:
7609 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7610 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7611 break;
7612 default:
7613 adapter->wol = 0;
7614 break;
7615 }
7616 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7617
7618 /* pick up the PCI bus settings for reporting later */
7619 hw->mac.ops.get_bus_info(hw);
7620
7621 /* print bus type/speed/width info */
7622 e_dev_info("(PCI Express:%s:%s) %pM\n",
7623 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7624 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7625 "Unknown"),
7626 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7627 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7628 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7629 "Unknown"),
7630 netdev->dev_addr);
7631
7632 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7633 if (err)
7634 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7635 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7636 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7637 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7638 part_str);
7639 else
7640 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7641 hw->mac.type, hw->phy.type, part_str);
7642
7643 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7644 e_dev_warn("PCI-Express bandwidth available for this card is "
7645 "not sufficient for optimal performance.\n");
7646 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7647 "is required.\n");
7648 }
7649
7650 /* save off EEPROM version number */
7651 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7652
7653 /* reset the hardware with the new settings */
7654 err = hw->mac.ops.start_hw(hw);
7655
7656 if (err == IXGBE_ERR_EEPROM_VERSION) {
7657 /* We are running on a pre-production device, log a warning */
7658 e_dev_warn("This device is a pre-production adapter/LOM. "
7659 "Please be aware there may be issues associated "
7660 "with your hardware. If you are experiencing "
7661 "problems please contact your Intel or hardware "
7662 "representative who provided you with this "
7663 "hardware.\n");
7664 }
7665 strcpy(netdev->name, "eth%d");
7666 err = register_netdev(netdev);
7667 if (err)
7668 goto err_register;
7669
7670 /* carrier off reporting is important to ethtool even BEFORE open */
7671 netif_carrier_off(netdev);
7672
7673 #ifdef CONFIG_IXGBE_DCA
7674 if (dca_add_requester(&pdev->dev) == 0) {
7675 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7676 ixgbe_setup_dca(adapter);
7677 }
7678 #endif
7679 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7680 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7681 for (i = 0; i < adapter->num_vfs; i++)
7682 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7683 }
7684
7685 /* add san mac addr to netdev */
7686 ixgbe_add_sanmac_netdev(netdev);
7687
7688 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7689 cards_found++;
7690 return 0;
7691
7692 err_register:
7693 ixgbe_release_hw_control(adapter);
7694 ixgbe_clear_interrupt_scheme(adapter);
7695 err_sw_init:
7696 err_eeprom:
7697 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7698 ixgbe_disable_sriov(adapter);
7699 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7700 iounmap(hw->hw_addr);
7701 err_ioremap:
7702 free_netdev(netdev);
7703 err_alloc_etherdev:
7704 pci_release_selected_regions(pdev,
7705 pci_select_bars(pdev, IORESOURCE_MEM));
7706 err_pci_reg:
7707 err_dma:
7708 pci_disable_device(pdev);
7709 return err;
7710 }
7711
7712 /**
7713 * ixgbe_remove - Device Removal Routine
7714 * @pdev: PCI device information struct
7715 *
7716 * ixgbe_remove is called by the PCI subsystem to alert the driver
7717 * that it should release a PCI device. The could be caused by a
7718 * Hot-Plug event, or because the driver is going to be removed from
7719 * memory.
7720 **/
7721 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7722 {
7723 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7724 struct net_device *netdev = adapter->netdev;
7725
7726 set_bit(__IXGBE_DOWN, &adapter->state);
7727 cancel_work_sync(&adapter->service_task);
7728
7729 #ifdef CONFIG_IXGBE_DCA
7730 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7731 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7732 dca_remove_requester(&pdev->dev);
7733 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7734 }
7735
7736 #endif
7737 #ifdef IXGBE_FCOE
7738 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7739 ixgbe_cleanup_fcoe(adapter);
7740
7741 #endif /* IXGBE_FCOE */
7742
7743 /* remove the added san mac */
7744 ixgbe_del_sanmac_netdev(netdev);
7745
7746 if (netdev->reg_state == NETREG_REGISTERED)
7747 unregister_netdev(netdev);
7748
7749 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7750 ixgbe_disable_sriov(adapter);
7751
7752 ixgbe_clear_interrupt_scheme(adapter);
7753
7754 ixgbe_release_hw_control(adapter);
7755
7756 iounmap(adapter->hw.hw_addr);
7757 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7758 IORESOURCE_MEM));
7759
7760 e_dev_info("complete\n");
7761
7762 free_netdev(netdev);
7763
7764 pci_disable_pcie_error_reporting(pdev);
7765
7766 pci_disable_device(pdev);
7767 }
7768
7769 /**
7770 * ixgbe_io_error_detected - called when PCI error is detected
7771 * @pdev: Pointer to PCI device
7772 * @state: The current pci connection state
7773 *
7774 * This function is called after a PCI bus error affecting
7775 * this device has been detected.
7776 */
7777 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7778 pci_channel_state_t state)
7779 {
7780 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7781 struct net_device *netdev = adapter->netdev;
7782
7783 netif_device_detach(netdev);
7784
7785 if (state == pci_channel_io_perm_failure)
7786 return PCI_ERS_RESULT_DISCONNECT;
7787
7788 if (netif_running(netdev))
7789 ixgbe_down(adapter);
7790 pci_disable_device(pdev);
7791
7792 /* Request a slot reset. */
7793 return PCI_ERS_RESULT_NEED_RESET;
7794 }
7795
7796 /**
7797 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7798 * @pdev: Pointer to PCI device
7799 *
7800 * Restart the card from scratch, as if from a cold-boot.
7801 */
7802 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7803 {
7804 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7805 pci_ers_result_t result;
7806 int err;
7807
7808 if (pci_enable_device_mem(pdev)) {
7809 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7810 result = PCI_ERS_RESULT_DISCONNECT;
7811 } else {
7812 pci_set_master(pdev);
7813 pci_restore_state(pdev);
7814 pci_save_state(pdev);
7815
7816 pci_wake_from_d3(pdev, false);
7817
7818 ixgbe_reset(adapter);
7819 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7820 result = PCI_ERS_RESULT_RECOVERED;
7821 }
7822
7823 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7824 if (err) {
7825 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7826 "failed 0x%0x\n", err);
7827 /* non-fatal, continue */
7828 }
7829
7830 return result;
7831 }
7832
7833 /**
7834 * ixgbe_io_resume - called when traffic can start flowing again.
7835 * @pdev: Pointer to PCI device
7836 *
7837 * This callback is called when the error recovery driver tells us that
7838 * its OK to resume normal operation.
7839 */
7840 static void ixgbe_io_resume(struct pci_dev *pdev)
7841 {
7842 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7843 struct net_device *netdev = adapter->netdev;
7844
7845 if (netif_running(netdev)) {
7846 if (ixgbe_up(adapter)) {
7847 e_info(probe, "ixgbe_up failed after reset\n");
7848 return;
7849 }
7850 }
7851
7852 netif_device_attach(netdev);
7853 }
7854
7855 static struct pci_error_handlers ixgbe_err_handler = {
7856 .error_detected = ixgbe_io_error_detected,
7857 .slot_reset = ixgbe_io_slot_reset,
7858 .resume = ixgbe_io_resume,
7859 };
7860
7861 static struct pci_driver ixgbe_driver = {
7862 .name = ixgbe_driver_name,
7863 .id_table = ixgbe_pci_tbl,
7864 .probe = ixgbe_probe,
7865 .remove = __devexit_p(ixgbe_remove),
7866 #ifdef CONFIG_PM
7867 .suspend = ixgbe_suspend,
7868 .resume = ixgbe_resume,
7869 #endif
7870 .shutdown = ixgbe_shutdown,
7871 .err_handler = &ixgbe_err_handler
7872 };
7873
7874 /**
7875 * ixgbe_init_module - Driver Registration Routine
7876 *
7877 * ixgbe_init_module is the first routine called when the driver is
7878 * loaded. All it does is register with the PCI subsystem.
7879 **/
7880 static int __init ixgbe_init_module(void)
7881 {
7882 int ret;
7883 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7884 pr_info("%s\n", ixgbe_copyright);
7885
7886 #ifdef CONFIG_IXGBE_DCA
7887 dca_register_notify(&dca_notifier);
7888 #endif
7889
7890 ret = pci_register_driver(&ixgbe_driver);
7891 return ret;
7892 }
7893
7894 module_init(ixgbe_init_module);
7895
7896 /**
7897 * ixgbe_exit_module - Driver Exit Cleanup Routine
7898 *
7899 * ixgbe_exit_module is called just before the driver is removed
7900 * from memory.
7901 **/
7902 static void __exit ixgbe_exit_module(void)
7903 {
7904 #ifdef CONFIG_IXGBE_DCA
7905 dca_unregister_notify(&dca_notifier);
7906 #endif
7907 pci_unregister_driver(&ixgbe_driver);
7908 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7909 }
7910
7911 #ifdef CONFIG_IXGBE_DCA
7912 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7913 void *p)
7914 {
7915 int ret_val;
7916
7917 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7918 __ixgbe_notify_dca);
7919
7920 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7921 }
7922
7923 #endif /* CONFIG_IXGBE_DCA */
7924
7925 module_exit(ixgbe_exit_module);
7926
7927 /* ixgbe_main.c */