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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / net / pch_gbe / pch_gbe_main.c
blobc2476fd965737c68c5e1b9f13cd2cb6ace48e609
1 /*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include "pch_gbe.h"
22 #include "pch_gbe_api.h"
23
24 #define DRV_VERSION "1.00"
25 const char pch_driver_version[] = DRV_VERSION;
26
27 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
28 #define PCH_GBE_MAR_ENTRIES 16
29 #define PCH_GBE_SHORT_PKT 64
30 #define DSC_INIT16 0xC000
31 #define PCH_GBE_DMA_ALIGN 0
32 #define PCH_GBE_DMA_PADDING 2
33 #define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */
34 #define PCH_GBE_COPYBREAK_DEFAULT 256
35 #define PCH_GBE_PCI_BAR 1
36
37 /* Macros for ML7223 */
38 #define PCI_VENDOR_ID_ROHM 0x10db
39 #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
40
41 #define PCH_GBE_TX_WEIGHT 64
42 #define PCH_GBE_RX_WEIGHT 64
43 #define PCH_GBE_RX_BUFFER_WRITE 16
44
45 /* Initialize the wake-on-LAN settings */
46 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
47
48 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
49 PCH_GBE_CHIP_TYPE_INTERNAL | \
50 PCH_GBE_RGMII_MODE_RGMII \
51 )
52
53 /* Ethertype field values */
54 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
55 #define PCH_GBE_FRAME_SIZE_2048 2048
56 #define PCH_GBE_FRAME_SIZE_4096 4096
57 #define PCH_GBE_FRAME_SIZE_8192 8192
58
59 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
60 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
61 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
62 #define PCH_GBE_DESC_UNUSED(R) \
63 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
64 (R)->next_to_clean - (R)->next_to_use - 1)
65
66 /* Pause packet value */
67 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
68 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
69 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
70 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
71
72 #define PCH_GBE_ETH_ALEN 6
73
74 /* This defines the bits that are set in the Interrupt Mask
75 * Set/Read Register. Each bit is documented below:
76 * o RXT0 = Receiver Timer Interrupt (ring 0)
77 * o TXDW = Transmit Descriptor Written Back
78 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
79 * o RXSEQ = Receive Sequence Error
80 * o LSC = Link Status Change
81 */
82 #define PCH_GBE_INT_ENABLE_MASK ( \
83 PCH_GBE_INT_RX_DMA_CMPLT | \
84 PCH_GBE_INT_RX_DSC_EMP | \
85 PCH_GBE_INT_WOL_DET | \
86 PCH_GBE_INT_TX_CMPLT \
87 )
88
89
90 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
91
92 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
93 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
94 int data);
95
96 inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
97 {
98 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
99 }
100
101 /**
102 * pch_gbe_mac_read_mac_addr - Read MAC address
103 * @hw: Pointer to the HW structure
104 * Returns
105 * 0: Successful.
106 */
107 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
108 {
109 u32 adr1a, adr1b;
110
111 adr1a = ioread32(&hw->reg->mac_adr[0].high);
112 adr1b = ioread32(&hw->reg->mac_adr[0].low);
113
114 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
115 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
116 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
117 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
118 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
119 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
120
121 pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
122 return 0;
123 }
124
125 /**
126 * pch_gbe_wait_clr_bit - Wait to clear a bit
127 * @reg: Pointer of register
128 * @busy: Busy bit
129 */
130 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
131 {
132 u32 tmp;
133 /* wait busy */
134 tmp = 1000;
135 while ((ioread32(reg) & bit) && --tmp)
136 cpu_relax();
137 if (!tmp)
138 pr_err("Error: busy bit is not cleared\n");
139 }
140 /**
141 * pch_gbe_mac_mar_set - Set MAC address register
142 * @hw: Pointer to the HW structure
143 * @addr: Pointer to the MAC address
144 * @index: MAC address array register
145 */
146 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
147 {
148 u32 mar_low, mar_high, adrmask;
149
150 pr_debug("index : 0x%x\n", index);
151
152 /*
153 * HW expects these in little endian so we reverse the byte order
154 * from network order (big endian) to little endian
155 */
156 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
157 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
158 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
159 /* Stop the MAC Address of index. */
160 adrmask = ioread32(&hw->reg->ADDR_MASK);
161 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
162 /* wait busy */
163 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
164 /* Set the MAC address to the MAC address 1A/1B register */
165 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
166 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
167 /* Start the MAC address of index */
168 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
169 /* wait busy */
170 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
171 }
172
173 /**
174 * pch_gbe_mac_reset_hw - Reset hardware
175 * @hw: Pointer to the HW structure
176 */
177 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
178 {
179 /* Read the MAC address. and store to the private data */
180 pch_gbe_mac_read_mac_addr(hw);
181 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
182 #ifdef PCH_GBE_MAC_IFOP_RGMII
183 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
184 #endif
185 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
186 /* Setup the receive address */
187 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
188 return;
189 }
190
191 /**
192 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
193 * @hw: Pointer to the HW structure
194 * @mar_count: Receive address registers
195 */
196 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
197 {
198 u32 i;
199
200 /* Setup the receive address */
201 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
202
203 /* Zero out the other receive addresses */
204 for (i = 1; i < mar_count; i++) {
205 iowrite32(0, &hw->reg->mac_adr[i].high);
206 iowrite32(0, &hw->reg->mac_adr[i].low);
207 }
208 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
209 /* wait busy */
210 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
211 }
212
213
214 /**
215 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
216 * @hw: Pointer to the HW structure
217 * @mc_addr_list: Array of multicast addresses to program
218 * @mc_addr_count: Number of multicast addresses to program
219 * @mar_used_count: The first MAC Address register free to program
220 * @mar_total_num: Total number of supported MAC Address Registers
221 */
222 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
223 u8 *mc_addr_list, u32 mc_addr_count,
224 u32 mar_used_count, u32 mar_total_num)
225 {
226 u32 i, adrmask;
227
228 /* Load the first set of multicast addresses into the exact
229 * filters (RAR). If there are not enough to fill the RAR
230 * array, clear the filters.
231 */
232 for (i = mar_used_count; i < mar_total_num; i++) {
233 if (mc_addr_count) {
234 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
235 mc_addr_count--;
236 mc_addr_list += PCH_GBE_ETH_ALEN;
237 } else {
238 /* Clear MAC address mask */
239 adrmask = ioread32(&hw->reg->ADDR_MASK);
240 iowrite32((adrmask | (0x0001 << i)),
241 &hw->reg->ADDR_MASK);
242 /* wait busy */
243 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
244 /* Clear MAC address */
245 iowrite32(0, &hw->reg->mac_adr[i].high);
246 iowrite32(0, &hw->reg->mac_adr[i].low);
247 }
248 }
249 }
250
251 /**
252 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
253 * @hw: Pointer to the HW structure
254 * Returns
255 * 0: Successful.
256 * Negative value: Failed.
257 */
258 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
259 {
260 struct pch_gbe_mac_info *mac = &hw->mac;
261 u32 rx_fctrl;
262
263 pr_debug("mac->fc = %u\n", mac->fc);
264
265 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
266
267 switch (mac->fc) {
268 case PCH_GBE_FC_NONE:
269 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
270 mac->tx_fc_enable = false;
271 break;
272 case PCH_GBE_FC_RX_PAUSE:
273 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
274 mac->tx_fc_enable = false;
275 break;
276 case PCH_GBE_FC_TX_PAUSE:
277 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
278 mac->tx_fc_enable = true;
279 break;
280 case PCH_GBE_FC_FULL:
281 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
282 mac->tx_fc_enable = true;
283 break;
284 default:
285 pr_err("Flow control param set incorrectly\n");
286 return -EINVAL;
287 }
288 if (mac->link_duplex == DUPLEX_HALF)
289 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
290 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
291 pr_debug("RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
292 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
293 return 0;
294 }
295
296 /**
297 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
298 * @hw: Pointer to the HW structure
299 * @wu_evt: Wake up event
300 */
301 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
302 {
303 u32 addr_mask;
304
305 pr_debug("wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
306 wu_evt, ioread32(&hw->reg->ADDR_MASK));
307
308 if (wu_evt) {
309 /* Set Wake-On-Lan address mask */
310 addr_mask = ioread32(&hw->reg->ADDR_MASK);
311 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
312 /* wait busy */
313 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
314 iowrite32(0, &hw->reg->WOL_ST);
315 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
316 iowrite32(0x02, &hw->reg->TCPIP_ACC);
317 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
318 } else {
319 iowrite32(0, &hw->reg->WOL_CTRL);
320 iowrite32(0, &hw->reg->WOL_ST);
321 }
322 return;
323 }
324
325 /**
326 * pch_gbe_mac_ctrl_miim - Control MIIM interface
327 * @hw: Pointer to the HW structure
328 * @addr: Address of PHY
329 * @dir: Operetion. (Write or Read)
330 * @reg: Access register of PHY
331 * @data: Write data.
332 *
333 * Returns: Read date.
334 */
335 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
336 u16 data)
337 {
338 u32 data_out = 0;
339 unsigned int i;
340 unsigned long flags;
341
342 spin_lock_irqsave(&hw->miim_lock, flags);
343
344 for (i = 100; i; --i) {
345 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
346 break;
347 udelay(20);
348 }
349 if (i == 0) {
350 pr_err("pch-gbe.miim won't go Ready\n");
351 spin_unlock_irqrestore(&hw->miim_lock, flags);
352 return 0; /* No way to indicate timeout error */
353 }
354 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
355 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
356 dir | data), &hw->reg->MIIM);
357 for (i = 0; i < 100; i++) {
358 udelay(20);
359 data_out = ioread32(&hw->reg->MIIM);
360 if ((data_out & PCH_GBE_MIIM_OPER_READY))
361 break;
362 }
363 spin_unlock_irqrestore(&hw->miim_lock, flags);
364
365 pr_debug("PHY %s: reg=%d, data=0x%04X\n",
366 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
367 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
368 return (u16) data_out;
369 }
370
371 /**
372 * pch_gbe_mac_set_pause_packet - Set pause packet
373 * @hw: Pointer to the HW structure
374 */
375 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
376 {
377 unsigned long tmp2, tmp3;
378
379 /* Set Pause packet */
380 tmp2 = hw->mac.addr[1];
381 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
382 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
383
384 tmp3 = hw->mac.addr[5];
385 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
386 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
387 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
388
389 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
390 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
391 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
392 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
393 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
394
395 /* Transmit Pause Packet */
396 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
397
398 pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
399 ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
400 ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
401 ioread32(&hw->reg->PAUSE_PKT5));
402
403 return;
404 }
405
406
407 /**
408 * pch_gbe_alloc_queues - Allocate memory for all rings
409 * @adapter: Board private structure to initialize
410 * Returns
411 * 0: Successfully
412 * Negative value: Failed
413 */
414 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
415 {
416 int size;
417
418 size = (int)sizeof(struct pch_gbe_tx_ring);
419 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
420 if (!adapter->tx_ring)
421 return -ENOMEM;
422 size = (int)sizeof(struct pch_gbe_rx_ring);
423 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
424 if (!adapter->rx_ring) {
425 kfree(adapter->tx_ring);
426 return -ENOMEM;
427 }
428 return 0;
429 }
430
431 /**
432 * pch_gbe_init_stats - Initialize status
433 * @adapter: Board private structure to initialize
434 */
435 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
436 {
437 memset(&adapter->stats, 0, sizeof(adapter->stats));
438 return;
439 }
440
441 /**
442 * pch_gbe_init_phy - Initialize PHY
443 * @adapter: Board private structure to initialize
444 * Returns
445 * 0: Successfully
446 * Negative value: Failed
447 */
448 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
449 {
450 struct net_device *netdev = adapter->netdev;
451 u32 addr;
452 u16 bmcr, stat;
453
454 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
455 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
456 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
457 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
458 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
459 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
460 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
461 break;
462 }
463 adapter->hw.phy.addr = adapter->mii.phy_id;
464 pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
465 if (addr == 32)
466 return -EAGAIN;
467 /* Selected the phy and isolate the rest */
468 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
469 if (addr != adapter->mii.phy_id) {
470 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
471 BMCR_ISOLATE);
472 } else {
473 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
474 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
475 bmcr & ~BMCR_ISOLATE);
476 }
477 }
478
479 /* MII setup */
480 adapter->mii.phy_id_mask = 0x1F;
481 adapter->mii.reg_num_mask = 0x1F;
482 adapter->mii.dev = adapter->netdev;
483 adapter->mii.mdio_read = pch_gbe_mdio_read;
484 adapter->mii.mdio_write = pch_gbe_mdio_write;
485 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
486 return 0;
487 }
488
489 /**
490 * pch_gbe_mdio_read - The read function for mii
491 * @netdev: Network interface device structure
492 * @addr: Phy ID
493 * @reg: Access location
494 * Returns
495 * 0: Successfully
496 * Negative value: Failed
497 */
498 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
499 {
500 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
501 struct pch_gbe_hw *hw = &adapter->hw;
502
503 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
504 (u16) 0);
505 }
506
507 /**
508 * pch_gbe_mdio_write - The write function for mii
509 * @netdev: Network interface device structure
510 * @addr: Phy ID (not used)
511 * @reg: Access location
512 * @data: Write data
513 */
514 static void pch_gbe_mdio_write(struct net_device *netdev,
515 int addr, int reg, int data)
516 {
517 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
518 struct pch_gbe_hw *hw = &adapter->hw;
519
520 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
521 }
522
523 /**
524 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
525 * @work: Pointer of board private structure
526 */
527 static void pch_gbe_reset_task(struct work_struct *work)
528 {
529 struct pch_gbe_adapter *adapter;
530 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
531
532 rtnl_lock();
533 pch_gbe_reinit_locked(adapter);
534 rtnl_unlock();
535 }
536
537 /**
538 * pch_gbe_reinit_locked- Re-initialization
539 * @adapter: Board private structure
540 */
541 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
542 {
543 pch_gbe_down(adapter);
544 pch_gbe_up(adapter);
545 }
546
547 /**
548 * pch_gbe_reset - Reset GbE
549 * @adapter: Board private structure
550 */
551 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
552 {
553 pch_gbe_mac_reset_hw(&adapter->hw);
554 /* Setup the receive address. */
555 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
556 if (pch_gbe_hal_init_hw(&adapter->hw))
557 pr_err("Hardware Error\n");
558 }
559
560 /**
561 * pch_gbe_free_irq - Free an interrupt
562 * @adapter: Board private structure
563 */
564 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
565 {
566 struct net_device *netdev = adapter->netdev;
567
568 free_irq(adapter->pdev->irq, netdev);
569 if (adapter->have_msi) {
570 pci_disable_msi(adapter->pdev);
571 pr_debug("call pci_disable_msi\n");
572 }
573 }
574
575 /**
576 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
577 * @adapter: Board private structure
578 */
579 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
580 {
581 struct pch_gbe_hw *hw = &adapter->hw;
582
583 atomic_inc(&adapter->irq_sem);
584 iowrite32(0, &hw->reg->INT_EN);
585 ioread32(&hw->reg->INT_ST);
586 synchronize_irq(adapter->pdev->irq);
587
588 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
589 }
590
591 /**
592 * pch_gbe_irq_enable - Enable default interrupt generation settings
593 * @adapter: Board private structure
594 */
595 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
596 {
597 struct pch_gbe_hw *hw = &adapter->hw;
598
599 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
600 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
601 ioread32(&hw->reg->INT_ST);
602 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
603 }
604
605
606
607 /**
608 * pch_gbe_setup_tctl - configure the Transmit control registers
609 * @adapter: Board private structure
610 */
611 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
612 {
613 struct pch_gbe_hw *hw = &adapter->hw;
614 u32 tx_mode, tcpip;
615
616 tx_mode = PCH_GBE_TM_LONG_PKT |
617 PCH_GBE_TM_ST_AND_FD |
618 PCH_GBE_TM_SHORT_PKT |
619 PCH_GBE_TM_TH_TX_STRT_8 |
620 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
621
622 iowrite32(tx_mode, &hw->reg->TX_MODE);
623
624 tcpip = ioread32(&hw->reg->TCPIP_ACC);
625 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
626 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
627 return;
628 }
629
630 /**
631 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
632 * @adapter: Board private structure
633 */
634 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
635 {
636 struct pch_gbe_hw *hw = &adapter->hw;
637 u32 tdba, tdlen, dctrl;
638
639 pr_debug("dma addr = 0x%08llx size = 0x%08x\n",
640 (unsigned long long)adapter->tx_ring->dma,
641 adapter->tx_ring->size);
642
643 /* Setup the HW Tx Head and Tail descriptor pointers */
644 tdba = adapter->tx_ring->dma;
645 tdlen = adapter->tx_ring->size - 0x10;
646 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
647 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
648 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
649
650 /* Enables Transmission DMA */
651 dctrl = ioread32(&hw->reg->DMA_CTRL);
652 dctrl |= PCH_GBE_TX_DMA_EN;
653 iowrite32(dctrl, &hw->reg->DMA_CTRL);
654 }
655
656 /**
657 * pch_gbe_setup_rctl - Configure the receive control registers
658 * @adapter: Board private structure
659 */
660 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
661 {
662 struct net_device *netdev = adapter->netdev;
663 struct pch_gbe_hw *hw = &adapter->hw;
664 u32 rx_mode, tcpip;
665
666 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
667 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
668
669 iowrite32(rx_mode, &hw->reg->RX_MODE);
670
671 tcpip = ioread32(&hw->reg->TCPIP_ACC);
672
673 if (netdev->features & NETIF_F_RXCSUM) {
674 tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF;
675 tcpip |= PCH_GBE_RX_TCPIPACC_EN;
676 } else {
677 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
678 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
679 }
680 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
681 return;
682 }
683
684 /**
685 * pch_gbe_configure_rx - Configure Receive Unit after Reset
686 * @adapter: Board private structure
687 */
688 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
689 {
690 struct pch_gbe_hw *hw = &adapter->hw;
691 u32 rdba, rdlen, rctl, rxdma;
692
693 pr_debug("dma adr = 0x%08llx size = 0x%08x\n",
694 (unsigned long long)adapter->rx_ring->dma,
695 adapter->rx_ring->size);
696
697 pch_gbe_mac_force_mac_fc(hw);
698
699 /* Disables Receive MAC */
700 rctl = ioread32(&hw->reg->MAC_RX_EN);
701 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
702
703 /* Disables Receive DMA */
704 rxdma = ioread32(&hw->reg->DMA_CTRL);
705 rxdma &= ~PCH_GBE_RX_DMA_EN;
706 iowrite32(rxdma, &hw->reg->DMA_CTRL);
707
708 pr_debug("MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
709 ioread32(&hw->reg->MAC_RX_EN),
710 ioread32(&hw->reg->DMA_CTRL));
711
712 /* Setup the HW Rx Head and Tail Descriptor Pointers and
713 * the Base and Length of the Rx Descriptor Ring */
714 rdba = adapter->rx_ring->dma;
715 rdlen = adapter->rx_ring->size - 0x10;
716 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
717 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
718 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
719
720 /* Enables Receive DMA */
721 rxdma = ioread32(&hw->reg->DMA_CTRL);
722 rxdma |= PCH_GBE_RX_DMA_EN;
723 iowrite32(rxdma, &hw->reg->DMA_CTRL);
724 /* Enables Receive */
725 iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
726 }
727
728 /**
729 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
730 * @adapter: Board private structure
731 * @buffer_info: Buffer information structure
732 */
733 static void pch_gbe_unmap_and_free_tx_resource(
734 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
735 {
736 if (buffer_info->mapped) {
737 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
738 buffer_info->length, DMA_TO_DEVICE);
739 buffer_info->mapped = false;
740 }
741 if (buffer_info->skb) {
742 dev_kfree_skb_any(buffer_info->skb);
743 buffer_info->skb = NULL;
744 }
745 }
746
747 /**
748 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
749 * @adapter: Board private structure
750 * @buffer_info: Buffer information structure
751 */
752 static void pch_gbe_unmap_and_free_rx_resource(
753 struct pch_gbe_adapter *adapter,
754 struct pch_gbe_buffer *buffer_info)
755 {
756 if (buffer_info->mapped) {
757 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
758 buffer_info->length, DMA_FROM_DEVICE);
759 buffer_info->mapped = false;
760 }
761 if (buffer_info->skb) {
762 dev_kfree_skb_any(buffer_info->skb);
763 buffer_info->skb = NULL;
764 }
765 }
766
767 /**
768 * pch_gbe_clean_tx_ring - Free Tx Buffers
769 * @adapter: Board private structure
770 * @tx_ring: Ring to be cleaned
771 */
772 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
773 struct pch_gbe_tx_ring *tx_ring)
774 {
775 struct pch_gbe_hw *hw = &adapter->hw;
776 struct pch_gbe_buffer *buffer_info;
777 unsigned long size;
778 unsigned int i;
779
780 /* Free all the Tx ring sk_buffs */
781 for (i = 0; i < tx_ring->count; i++) {
782 buffer_info = &tx_ring->buffer_info[i];
783 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
784 }
785 pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
786
787 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
788 memset(tx_ring->buffer_info, 0, size);
789
790 /* Zero out the descriptor ring */
791 memset(tx_ring->desc, 0, tx_ring->size);
792 tx_ring->next_to_use = 0;
793 tx_ring->next_to_clean = 0;
794 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
795 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
796 }
797
798 /**
799 * pch_gbe_clean_rx_ring - Free Rx Buffers
800 * @adapter: Board private structure
801 * @rx_ring: Ring to free buffers from
802 */
803 static void
804 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
805 struct pch_gbe_rx_ring *rx_ring)
806 {
807 struct pch_gbe_hw *hw = &adapter->hw;
808 struct pch_gbe_buffer *buffer_info;
809 unsigned long size;
810 unsigned int i;
811
812 /* Free all the Rx ring sk_buffs */
813 for (i = 0; i < rx_ring->count; i++) {
814 buffer_info = &rx_ring->buffer_info[i];
815 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
816 }
817 pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
818 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
819 memset(rx_ring->buffer_info, 0, size);
820
821 /* Zero out the descriptor ring */
822 memset(rx_ring->desc, 0, rx_ring->size);
823 rx_ring->next_to_clean = 0;
824 rx_ring->next_to_use = 0;
825 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
826 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
827 }
828
829 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
830 u16 duplex)
831 {
832 struct pch_gbe_hw *hw = &adapter->hw;
833 unsigned long rgmii = 0;
834
835 /* Set the RGMII control. */
836 #ifdef PCH_GBE_MAC_IFOP_RGMII
837 switch (speed) {
838 case SPEED_10:
839 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
840 PCH_GBE_MAC_RGMII_CTRL_SETTING);
841 break;
842 case SPEED_100:
843 rgmii = (PCH_GBE_RGMII_RATE_25M |
844 PCH_GBE_MAC_RGMII_CTRL_SETTING);
845 break;
846 case SPEED_1000:
847 rgmii = (PCH_GBE_RGMII_RATE_125M |
848 PCH_GBE_MAC_RGMII_CTRL_SETTING);
849 break;
850 }
851 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
852 #else /* GMII */
853 rgmii = 0;
854 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
855 #endif
856 }
857 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
858 u16 duplex)
859 {
860 struct net_device *netdev = adapter->netdev;
861 struct pch_gbe_hw *hw = &adapter->hw;
862 unsigned long mode = 0;
863
864 /* Set the communication mode */
865 switch (speed) {
866 case SPEED_10:
867 mode = PCH_GBE_MODE_MII_ETHER;
868 netdev->tx_queue_len = 10;
869 break;
870 case SPEED_100:
871 mode = PCH_GBE_MODE_MII_ETHER;
872 netdev->tx_queue_len = 100;
873 break;
874 case SPEED_1000:
875 mode = PCH_GBE_MODE_GMII_ETHER;
876 break;
877 }
878 if (duplex == DUPLEX_FULL)
879 mode |= PCH_GBE_MODE_FULL_DUPLEX;
880 else
881 mode |= PCH_GBE_MODE_HALF_DUPLEX;
882 iowrite32(mode, &hw->reg->MODE);
883 }
884
885 /**
886 * pch_gbe_watchdog - Watchdog process
887 * @data: Board private structure
888 */
889 static void pch_gbe_watchdog(unsigned long data)
890 {
891 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
892 struct net_device *netdev = adapter->netdev;
893 struct pch_gbe_hw *hw = &adapter->hw;
894
895 pr_debug("right now = %ld\n", jiffies);
896
897 pch_gbe_update_stats(adapter);
898 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
899 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
900 netdev->tx_queue_len = adapter->tx_queue_len;
901 /* mii library handles link maintenance tasks */
902 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
903 pr_err("ethtool get setting Error\n");
904 mod_timer(&adapter->watchdog_timer,
905 round_jiffies(jiffies +
906 PCH_GBE_WATCHDOG_PERIOD));
907 return;
908 }
909 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
910 hw->mac.link_duplex = cmd.duplex;
911 /* Set the RGMII control. */
912 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
913 hw->mac.link_duplex);
914 /* Set the communication mode */
915 pch_gbe_set_mode(adapter, hw->mac.link_speed,
916 hw->mac.link_duplex);
917 netdev_dbg(netdev,
918 "Link is Up %d Mbps %s-Duplex\n",
919 hw->mac.link_speed,
920 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
921 netif_carrier_on(netdev);
922 netif_wake_queue(netdev);
923 } else if ((!mii_link_ok(&adapter->mii)) &&
924 (netif_carrier_ok(netdev))) {
925 netdev_dbg(netdev, "NIC Link is Down\n");
926 hw->mac.link_speed = SPEED_10;
927 hw->mac.link_duplex = DUPLEX_HALF;
928 netif_carrier_off(netdev);
929 netif_stop_queue(netdev);
930 }
931 mod_timer(&adapter->watchdog_timer,
932 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
933 }
934
935 /**
936 * pch_gbe_tx_queue - Carry out queuing of the transmission data
937 * @adapter: Board private structure
938 * @tx_ring: Tx descriptor ring structure
939 * @skb: Sockt buffer structure
940 */
941 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
942 struct pch_gbe_tx_ring *tx_ring,
943 struct sk_buff *skb)
944 {
945 struct pch_gbe_hw *hw = &adapter->hw;
946 struct pch_gbe_tx_desc *tx_desc;
947 struct pch_gbe_buffer *buffer_info;
948 struct sk_buff *tmp_skb;
949 unsigned int frame_ctrl;
950 unsigned int ring_num;
951 unsigned long flags;
952
953 /*-- Set frame control --*/
954 frame_ctrl = 0;
955 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
956 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
957 if (skb->ip_summed == CHECKSUM_NONE)
958 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
959
960 /* Performs checksum processing */
961 /*
962 * It is because the hardware accelerator does not support a checksum,
963 * when the received data size is less than 64 bytes.
964 */
965 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
966 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
967 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
968 if (skb->protocol == htons(ETH_P_IP)) {
969 struct iphdr *iph = ip_hdr(skb);
970 unsigned int offset;
971 iph->check = 0;
972 iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
973 offset = skb_transport_offset(skb);
974 if (iph->protocol == IPPROTO_TCP) {
975 skb->csum = 0;
976 tcp_hdr(skb)->check = 0;
977 skb->csum = skb_checksum(skb, offset,
978 skb->len - offset, 0);
979 tcp_hdr(skb)->check =
980 csum_tcpudp_magic(iph->saddr,
981 iph->daddr,
982 skb->len - offset,
983 IPPROTO_TCP,
984 skb->csum);
985 } else if (iph->protocol == IPPROTO_UDP) {
986 skb->csum = 0;
987 udp_hdr(skb)->check = 0;
988 skb->csum =
989 skb_checksum(skb, offset,
990 skb->len - offset, 0);
991 udp_hdr(skb)->check =
992 csum_tcpudp_magic(iph->saddr,
993 iph->daddr,
994 skb->len - offset,
995 IPPROTO_UDP,
996 skb->csum);
997 }
998 }
999 }
1000 spin_lock_irqsave(&tx_ring->tx_lock, flags);
1001 ring_num = tx_ring->next_to_use;
1002 if (unlikely((ring_num + 1) == tx_ring->count))
1003 tx_ring->next_to_use = 0;
1004 else
1005 tx_ring->next_to_use = ring_num + 1;
1006
1007 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1008 buffer_info = &tx_ring->buffer_info[ring_num];
1009 tmp_skb = buffer_info->skb;
1010
1011 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1012 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1013 tmp_skb->data[ETH_HLEN] = 0x00;
1014 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1015 tmp_skb->len = skb->len;
1016 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1017 (skb->len - ETH_HLEN));
1018 /*-- Set Buffer information --*/
1019 buffer_info->length = tmp_skb->len;
1020 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1021 buffer_info->length,
1022 DMA_TO_DEVICE);
1023 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1024 pr_err("TX DMA map failed\n");
1025 buffer_info->dma = 0;
1026 buffer_info->time_stamp = 0;
1027 tx_ring->next_to_use = ring_num;
1028 return;
1029 }
1030 buffer_info->mapped = true;
1031 buffer_info->time_stamp = jiffies;
1032
1033 /*-- Set Tx descriptor --*/
1034 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1035 tx_desc->buffer_addr = (buffer_info->dma);
1036 tx_desc->length = (tmp_skb->len);
1037 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1038 tx_desc->tx_frame_ctrl = (frame_ctrl);
1039 tx_desc->gbec_status = (DSC_INIT16);
1040
1041 if (unlikely(++ring_num == tx_ring->count))
1042 ring_num = 0;
1043
1044 /* Update software pointer of TX descriptor */
1045 iowrite32(tx_ring->dma +
1046 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1047 &hw->reg->TX_DSC_SW_P);
1048 dev_kfree_skb_any(skb);
1049 }
1050
1051 /**
1052 * pch_gbe_update_stats - Update the board statistics counters
1053 * @adapter: Board private structure
1054 */
1055 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1056 {
1057 struct net_device *netdev = adapter->netdev;
1058 struct pci_dev *pdev = adapter->pdev;
1059 struct pch_gbe_hw_stats *stats = &adapter->stats;
1060 unsigned long flags;
1061
1062 /*
1063 * Prevent stats update while adapter is being reset, or if the pci
1064 * connection is down.
1065 */
1066 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1067 return;
1068
1069 spin_lock_irqsave(&adapter->stats_lock, flags);
1070
1071 /* Update device status "adapter->stats" */
1072 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1073 stats->tx_errors = stats->tx_length_errors +
1074 stats->tx_aborted_errors +
1075 stats->tx_carrier_errors + stats->tx_timeout_count;
1076
1077 /* Update network device status "adapter->net_stats" */
1078 netdev->stats.rx_packets = stats->rx_packets;
1079 netdev->stats.rx_bytes = stats->rx_bytes;
1080 netdev->stats.rx_dropped = stats->rx_dropped;
1081 netdev->stats.tx_packets = stats->tx_packets;
1082 netdev->stats.tx_bytes = stats->tx_bytes;
1083 netdev->stats.tx_dropped = stats->tx_dropped;
1084 /* Fill out the OS statistics structure */
1085 netdev->stats.multicast = stats->multicast;
1086 netdev->stats.collisions = stats->collisions;
1087 /* Rx Errors */
1088 netdev->stats.rx_errors = stats->rx_errors;
1089 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1090 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1091 /* Tx Errors */
1092 netdev->stats.tx_errors = stats->tx_errors;
1093 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1094 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1095
1096 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1097 }
1098
1099 /**
1100 * pch_gbe_intr - Interrupt Handler
1101 * @irq: Interrupt number
1102 * @data: Pointer to a network interface device structure
1103 * Returns
1104 * - IRQ_HANDLED: Our interrupt
1105 * - IRQ_NONE: Not our interrupt
1106 */
1107 static irqreturn_t pch_gbe_intr(int irq, void *data)
1108 {
1109 struct net_device *netdev = data;
1110 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1111 struct pch_gbe_hw *hw = &adapter->hw;
1112 u32 int_st;
1113 u32 int_en;
1114
1115 /* Check request status */
1116 int_st = ioread32(&hw->reg->INT_ST);
1117 int_st = int_st & ioread32(&hw->reg->INT_EN);
1118 /* When request status is no interruption factor */
1119 if (unlikely(!int_st))
1120 return IRQ_NONE; /* Not our interrupt. End processing. */
1121 pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1122 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1123 adapter->stats.intr_rx_frame_err_count++;
1124 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1125 adapter->stats.intr_rx_fifo_err_count++;
1126 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1127 adapter->stats.intr_rx_dma_err_count++;
1128 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1129 adapter->stats.intr_tx_fifo_err_count++;
1130 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1131 adapter->stats.intr_tx_dma_err_count++;
1132 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1133 adapter->stats.intr_tcpip_err_count++;
1134 /* When Rx descriptor is empty */
1135 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1136 adapter->stats.intr_rx_dsc_empty_count++;
1137 pr_err("Rx descriptor is empty\n");
1138 int_en = ioread32(&hw->reg->INT_EN);
1139 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1140 if (hw->mac.tx_fc_enable) {
1141 /* Set Pause packet */
1142 pch_gbe_mac_set_pause_packet(hw);
1143 }
1144 if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
1145 == 0) {
1146 return IRQ_HANDLED;
1147 }
1148 }
1149
1150 /* When request status is Receive interruption */
1151 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
1152 if (likely(napi_schedule_prep(&adapter->napi))) {
1153 /* Enable only Rx Descriptor empty */
1154 atomic_inc(&adapter->irq_sem);
1155 int_en = ioread32(&hw->reg->INT_EN);
1156 int_en &=
1157 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1158 iowrite32(int_en, &hw->reg->INT_EN);
1159 /* Start polling for NAPI */
1160 __napi_schedule(&adapter->napi);
1161 }
1162 }
1163 pr_debug("return = 0x%08x INT_EN reg = 0x%08x\n",
1164 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1165 return IRQ_HANDLED;
1166 }
1167
1168 /**
1169 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1170 * @adapter: Board private structure
1171 * @rx_ring: Rx descriptor ring
1172 * @cleaned_count: Cleaned count
1173 */
1174 static void
1175 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1176 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1177 {
1178 struct net_device *netdev = adapter->netdev;
1179 struct pci_dev *pdev = adapter->pdev;
1180 struct pch_gbe_hw *hw = &adapter->hw;
1181 struct pch_gbe_rx_desc *rx_desc;
1182 struct pch_gbe_buffer *buffer_info;
1183 struct sk_buff *skb;
1184 unsigned int i;
1185 unsigned int bufsz;
1186
1187 bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN;
1188 i = rx_ring->next_to_use;
1189
1190 while ((cleaned_count--)) {
1191 buffer_info = &rx_ring->buffer_info[i];
1192 skb = buffer_info->skb;
1193 if (skb) {
1194 skb_trim(skb, 0);
1195 } else {
1196 skb = netdev_alloc_skb(netdev, bufsz);
1197 if (unlikely(!skb)) {
1198 /* Better luck next round */
1199 adapter->stats.rx_alloc_buff_failed++;
1200 break;
1201 }
1202 /* 64byte align */
1203 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1204
1205 buffer_info->skb = skb;
1206 buffer_info->length = adapter->rx_buffer_len;
1207 }
1208 buffer_info->dma = dma_map_single(&pdev->dev,
1209 skb->data,
1210 buffer_info->length,
1211 DMA_FROM_DEVICE);
1212 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1213 dev_kfree_skb(skb);
1214 buffer_info->skb = NULL;
1215 buffer_info->dma = 0;
1216 adapter->stats.rx_alloc_buff_failed++;
1217 break; /* while !buffer_info->skb */
1218 }
1219 buffer_info->mapped = true;
1220 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1221 rx_desc->buffer_addr = (buffer_info->dma);
1222 rx_desc->gbec_status = DSC_INIT16;
1223
1224 pr_debug("i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1225 i, (unsigned long long)buffer_info->dma,
1226 buffer_info->length);
1227
1228 if (unlikely(++i == rx_ring->count))
1229 i = 0;
1230 }
1231 if (likely(rx_ring->next_to_use != i)) {
1232 rx_ring->next_to_use = i;
1233 if (unlikely(i-- == 0))
1234 i = (rx_ring->count - 1);
1235 iowrite32(rx_ring->dma +
1236 (int)sizeof(struct pch_gbe_rx_desc) * i,
1237 &hw->reg->RX_DSC_SW_P);
1238 }
1239 return;
1240 }
1241
1242 /**
1243 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1244 * @adapter: Board private structure
1245 * @tx_ring: Tx descriptor ring
1246 */
1247 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1248 struct pch_gbe_tx_ring *tx_ring)
1249 {
1250 struct pch_gbe_buffer *buffer_info;
1251 struct sk_buff *skb;
1252 unsigned int i;
1253 unsigned int bufsz;
1254 struct pch_gbe_tx_desc *tx_desc;
1255
1256 bufsz =
1257 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1258
1259 for (i = 0; i < tx_ring->count; i++) {
1260 buffer_info = &tx_ring->buffer_info[i];
1261 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1262 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1263 buffer_info->skb = skb;
1264 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1265 tx_desc->gbec_status = (DSC_INIT16);
1266 }
1267 return;
1268 }
1269
1270 /**
1271 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1272 * @adapter: Board private structure
1273 * @tx_ring: Tx descriptor ring
1274 * Returns
1275 * true: Cleaned the descriptor
1276 * false: Not cleaned the descriptor
1277 */
1278 static bool
1279 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1280 struct pch_gbe_tx_ring *tx_ring)
1281 {
1282 struct pch_gbe_tx_desc *tx_desc;
1283 struct pch_gbe_buffer *buffer_info;
1284 struct sk_buff *skb;
1285 unsigned int i;
1286 unsigned int cleaned_count = 0;
1287 bool cleaned = false;
1288
1289 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1290
1291 i = tx_ring->next_to_clean;
1292 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1293 pr_debug("gbec_status:0x%04x dma_status:0x%04x\n",
1294 tx_desc->gbec_status, tx_desc->dma_status);
1295
1296 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1297 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1298 cleaned = true;
1299 buffer_info = &tx_ring->buffer_info[i];
1300 skb = buffer_info->skb;
1301
1302 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1303 adapter->stats.tx_aborted_errors++;
1304 pr_err("Transfer Abort Error\n");
1305 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1306 ) {
1307 adapter->stats.tx_carrier_errors++;
1308 pr_err("Transfer Carrier Sense Error\n");
1309 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1310 ) {
1311 adapter->stats.tx_aborted_errors++;
1312 pr_err("Transfer Collision Abort Error\n");
1313 } else if ((tx_desc->gbec_status &
1314 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1315 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1316 adapter->stats.collisions++;
1317 adapter->stats.tx_packets++;
1318 adapter->stats.tx_bytes += skb->len;
1319 pr_debug("Transfer Collision\n");
1320 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1321 ) {
1322 adapter->stats.tx_packets++;
1323 adapter->stats.tx_bytes += skb->len;
1324 }
1325 if (buffer_info->mapped) {
1326 pr_debug("unmap buffer_info->dma : %d\n", i);
1327 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1328 buffer_info->length, DMA_TO_DEVICE);
1329 buffer_info->mapped = false;
1330 }
1331 if (buffer_info->skb) {
1332 pr_debug("trim buffer_info->skb : %d\n", i);
1333 skb_trim(buffer_info->skb, 0);
1334 }
1335 tx_desc->gbec_status = DSC_INIT16;
1336 if (unlikely(++i == tx_ring->count))
1337 i = 0;
1338 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1339
1340 /* weight of a sort for tx, to avoid endless transmit cleanup */
1341 if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
1342 break;
1343 }
1344 pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1345 cleaned_count);
1346 /* Recover from running out of Tx resources in xmit_frame */
1347 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1348 netif_wake_queue(adapter->netdev);
1349 adapter->stats.tx_restart_count++;
1350 pr_debug("Tx wake queue\n");
1351 }
1352 spin_lock(&adapter->tx_queue_lock);
1353 tx_ring->next_to_clean = i;
1354 spin_unlock(&adapter->tx_queue_lock);
1355 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1356 return cleaned;
1357 }
1358
1359 /**
1360 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1361 * @adapter: Board private structure
1362 * @rx_ring: Rx descriptor ring
1363 * @work_done: Completed count
1364 * @work_to_do: Request count
1365 * Returns
1366 * true: Cleaned the descriptor
1367 * false: Not cleaned the descriptor
1368 */
1369 static bool
1370 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1371 struct pch_gbe_rx_ring *rx_ring,
1372 int *work_done, int work_to_do)
1373 {
1374 struct net_device *netdev = adapter->netdev;
1375 struct pci_dev *pdev = adapter->pdev;
1376 struct pch_gbe_buffer *buffer_info;
1377 struct pch_gbe_rx_desc *rx_desc;
1378 u32 length;
1379 unsigned int i;
1380 unsigned int cleaned_count = 0;
1381 bool cleaned = false;
1382 struct sk_buff *skb, *new_skb;
1383 u8 dma_status;
1384 u16 gbec_status;
1385 u32 tcp_ip_status;
1386
1387 i = rx_ring->next_to_clean;
1388
1389 while (*work_done < work_to_do) {
1390 /* Check Rx descriptor status */
1391 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1392 if (rx_desc->gbec_status == DSC_INIT16)
1393 break;
1394 cleaned = true;
1395 cleaned_count++;
1396
1397 dma_status = rx_desc->dma_status;
1398 gbec_status = rx_desc->gbec_status;
1399 tcp_ip_status = rx_desc->tcp_ip_status;
1400 rx_desc->gbec_status = DSC_INIT16;
1401 buffer_info = &rx_ring->buffer_info[i];
1402 skb = buffer_info->skb;
1403
1404 /* unmap dma */
1405 dma_unmap_single(&pdev->dev, buffer_info->dma,
1406 buffer_info->length, DMA_FROM_DEVICE);
1407 buffer_info->mapped = false;
1408 /* Prefetch the packet */
1409 prefetch(skb->data);
1410
1411 pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x "
1412 "TCP:0x%08x] BufInf = 0x%p\n",
1413 i, dma_status, gbec_status, tcp_ip_status,
1414 buffer_info);
1415 /* Error check */
1416 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1417 adapter->stats.rx_frame_errors++;
1418 pr_err("Receive Not Octal Error\n");
1419 } else if (unlikely(gbec_status &
1420 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1421 adapter->stats.rx_frame_errors++;
1422 pr_err("Receive Nibble Error\n");
1423 } else if (unlikely(gbec_status &
1424 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1425 adapter->stats.rx_crc_errors++;
1426 pr_err("Receive CRC Error\n");
1427 } else {
1428 /* get receive length */
1429 /* length convert[-3] */
1430 length = (rx_desc->rx_words_eob) - 3;
1431
1432 /* Decide the data conversion method */
1433 if (!(netdev->features & NETIF_F_RXCSUM)) {
1434 /* [Header:14][payload] */
1435 if (NET_IP_ALIGN) {
1436 /* Because alignment differs,
1437 * the new_skb is newly allocated,
1438 * and data is copied to new_skb.*/
1439 new_skb = netdev_alloc_skb(netdev,
1440 length + NET_IP_ALIGN);
1441 if (!new_skb) {
1442 /* dorrop error */
1443 pr_err("New skb allocation "
1444 "Error\n");
1445 goto dorrop;
1446 }
1447 skb_reserve(new_skb, NET_IP_ALIGN);
1448 memcpy(new_skb->data, skb->data,
1449 length);
1450 skb = new_skb;
1451 } else {
1452 /* DMA buffer is used as SKB as it is.*/
1453 buffer_info->skb = NULL;
1454 }
1455 } else {
1456 /* [Header:14][padding:2][payload] */
1457 /* The length includes padding length */
1458 length = length - PCH_GBE_DMA_PADDING;
1459 if ((length < copybreak) ||
1460 (NET_IP_ALIGN != PCH_GBE_DMA_PADDING)) {
1461 /* Because alignment differs,
1462 * the new_skb is newly allocated,
1463 * and data is copied to new_skb.
1464 * Padding data is deleted
1465 * at the time of a copy.*/
1466 new_skb = netdev_alloc_skb(netdev,
1467 length + NET_IP_ALIGN);
1468 if (!new_skb) {
1469 /* dorrop error */
1470 pr_err("New skb allocation "
1471 "Error\n");
1472 goto dorrop;
1473 }
1474 skb_reserve(new_skb, NET_IP_ALIGN);
1475 memcpy(new_skb->data, skb->data,
1476 ETH_HLEN);
1477 memcpy(&new_skb->data[ETH_HLEN],
1478 &skb->data[ETH_HLEN +
1479 PCH_GBE_DMA_PADDING],
1480 length - ETH_HLEN);
1481 skb = new_skb;
1482 } else {
1483 /* Padding data is deleted
1484 * by moving header data.*/
1485 memmove(&skb->data[PCH_GBE_DMA_PADDING],
1486 &skb->data[0], ETH_HLEN);
1487 skb_reserve(skb, NET_IP_ALIGN);
1488 buffer_info->skb = NULL;
1489 }
1490 }
1491 /* The length includes FCS length */
1492 length = length - ETH_FCS_LEN;
1493 /* update status of driver */
1494 adapter->stats.rx_bytes += length;
1495 adapter->stats.rx_packets++;
1496 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1497 adapter->stats.multicast++;
1498 /* Write meta date of skb */
1499 skb_put(skb, length);
1500 skb->protocol = eth_type_trans(skb, netdev);
1501 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1502 skb->ip_summed = CHECKSUM_NONE;
1503 else
1504 skb->ip_summed = CHECKSUM_UNNECESSARY;
1505
1506 napi_gro_receive(&adapter->napi, skb);
1507 (*work_done)++;
1508 pr_debug("Receive skb->ip_summed: %d length: %d\n",
1509 skb->ip_summed, length);
1510 }
1511 dorrop:
1512 /* return some buffers to hardware, one at a time is too slow */
1513 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1514 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1515 cleaned_count);
1516 cleaned_count = 0;
1517 }
1518 if (++i == rx_ring->count)
1519 i = 0;
1520 }
1521 rx_ring->next_to_clean = i;
1522 if (cleaned_count)
1523 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1524 return cleaned;
1525 }
1526
1527 /**
1528 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1529 * @adapter: Board private structure
1530 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1531 * Returns
1532 * 0: Successfully
1533 * Negative value: Failed
1534 */
1535 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1536 struct pch_gbe_tx_ring *tx_ring)
1537 {
1538 struct pci_dev *pdev = adapter->pdev;
1539 struct pch_gbe_tx_desc *tx_desc;
1540 int size;
1541 int desNo;
1542
1543 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1544 tx_ring->buffer_info = vzalloc(size);
1545 if (!tx_ring->buffer_info) {
1546 pr_err("Unable to allocate memory for the buffer information\n");
1547 return -ENOMEM;
1548 }
1549
1550 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1551
1552 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1553 &tx_ring->dma, GFP_KERNEL);
1554 if (!tx_ring->desc) {
1555 vfree(tx_ring->buffer_info);
1556 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1557 return -ENOMEM;
1558 }
1559 memset(tx_ring->desc, 0, tx_ring->size);
1560
1561 tx_ring->next_to_use = 0;
1562 tx_ring->next_to_clean = 0;
1563 spin_lock_init(&tx_ring->tx_lock);
1564
1565 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1566 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1567 tx_desc->gbec_status = DSC_INIT16;
1568 }
1569 pr_debug("tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx\n"
1570 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1571 tx_ring->desc, (unsigned long long)tx_ring->dma,
1572 tx_ring->next_to_clean, tx_ring->next_to_use);
1573 return 0;
1574 }
1575
1576 /**
1577 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1578 * @adapter: Board private structure
1579 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1580 * Returns
1581 * 0: Successfully
1582 * Negative value: Failed
1583 */
1584 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1585 struct pch_gbe_rx_ring *rx_ring)
1586 {
1587 struct pci_dev *pdev = adapter->pdev;
1588 struct pch_gbe_rx_desc *rx_desc;
1589 int size;
1590 int desNo;
1591
1592 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1593 rx_ring->buffer_info = vzalloc(size);
1594 if (!rx_ring->buffer_info) {
1595 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1596 return -ENOMEM;
1597 }
1598 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1599 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1600 &rx_ring->dma, GFP_KERNEL);
1601
1602 if (!rx_ring->desc) {
1603 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1604 vfree(rx_ring->buffer_info);
1605 return -ENOMEM;
1606 }
1607 memset(rx_ring->desc, 0, rx_ring->size);
1608 rx_ring->next_to_clean = 0;
1609 rx_ring->next_to_use = 0;
1610 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1611 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1612 rx_desc->gbec_status = DSC_INIT16;
1613 }
1614 pr_debug("rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx "
1615 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1616 rx_ring->desc, (unsigned long long)rx_ring->dma,
1617 rx_ring->next_to_clean, rx_ring->next_to_use);
1618 return 0;
1619 }
1620
1621 /**
1622 * pch_gbe_free_tx_resources - Free Tx Resources
1623 * @adapter: Board private structure
1624 * @tx_ring: Tx descriptor ring for a specific queue
1625 */
1626 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1627 struct pch_gbe_tx_ring *tx_ring)
1628 {
1629 struct pci_dev *pdev = adapter->pdev;
1630
1631 pch_gbe_clean_tx_ring(adapter, tx_ring);
1632 vfree(tx_ring->buffer_info);
1633 tx_ring->buffer_info = NULL;
1634 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1635 tx_ring->desc = NULL;
1636 }
1637
1638 /**
1639 * pch_gbe_free_rx_resources - Free Rx Resources
1640 * @adapter: Board private structure
1641 * @rx_ring: Ring to clean the resources from
1642 */
1643 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1644 struct pch_gbe_rx_ring *rx_ring)
1645 {
1646 struct pci_dev *pdev = adapter->pdev;
1647
1648 pch_gbe_clean_rx_ring(adapter, rx_ring);
1649 vfree(rx_ring->buffer_info);
1650 rx_ring->buffer_info = NULL;
1651 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1652 rx_ring->desc = NULL;
1653 }
1654
1655 /**
1656 * pch_gbe_request_irq - Allocate an interrupt line
1657 * @adapter: Board private structure
1658 * Returns
1659 * 0: Successfully
1660 * Negative value: Failed
1661 */
1662 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1663 {
1664 struct net_device *netdev = adapter->netdev;
1665 int err;
1666 int flags;
1667
1668 flags = IRQF_SHARED;
1669 adapter->have_msi = false;
1670 err = pci_enable_msi(adapter->pdev);
1671 pr_debug("call pci_enable_msi\n");
1672 if (err) {
1673 pr_debug("call pci_enable_msi - Error: %d\n", err);
1674 } else {
1675 flags = 0;
1676 adapter->have_msi = true;
1677 }
1678 err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1679 flags, netdev->name, netdev);
1680 if (err)
1681 pr_err("Unable to allocate interrupt Error: %d\n", err);
1682 pr_debug("adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n",
1683 adapter->have_msi, flags, err);
1684 return err;
1685 }
1686
1687
1688 static void pch_gbe_set_multi(struct net_device *netdev);
1689 /**
1690 * pch_gbe_up - Up GbE network device
1691 * @adapter: Board private structure
1692 * Returns
1693 * 0: Successfully
1694 * Negative value: Failed
1695 */
1696 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1697 {
1698 struct net_device *netdev = adapter->netdev;
1699 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1700 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1701 int err;
1702
1703 /* hardware has been reset, we need to reload some things */
1704 pch_gbe_set_multi(netdev);
1705
1706 pch_gbe_setup_tctl(adapter);
1707 pch_gbe_configure_tx(adapter);
1708 pch_gbe_setup_rctl(adapter);
1709 pch_gbe_configure_rx(adapter);
1710
1711 err = pch_gbe_request_irq(adapter);
1712 if (err) {
1713 pr_err("Error: can't bring device up\n");
1714 return err;
1715 }
1716 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1717 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1718 adapter->tx_queue_len = netdev->tx_queue_len;
1719
1720 mod_timer(&adapter->watchdog_timer, jiffies);
1721
1722 napi_enable(&adapter->napi);
1723 pch_gbe_irq_enable(adapter);
1724 netif_start_queue(adapter->netdev);
1725
1726 return 0;
1727 }
1728
1729 /**
1730 * pch_gbe_down - Down GbE network device
1731 * @adapter: Board private structure
1732 */
1733 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1734 {
1735 struct net_device *netdev = adapter->netdev;
1736
1737 /* signal that we're down so the interrupt handler does not
1738 * reschedule our watchdog timer */
1739 napi_disable(&adapter->napi);
1740 atomic_set(&adapter->irq_sem, 0);
1741
1742 pch_gbe_irq_disable(adapter);
1743 pch_gbe_free_irq(adapter);
1744
1745 del_timer_sync(&adapter->watchdog_timer);
1746
1747 netdev->tx_queue_len = adapter->tx_queue_len;
1748 netif_carrier_off(netdev);
1749 netif_stop_queue(netdev);
1750
1751 pch_gbe_reset(adapter);
1752 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1753 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1754 }
1755
1756 /**
1757 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1758 * @adapter: Board private structure to initialize
1759 * Returns
1760 * 0: Successfully
1761 * Negative value: Failed
1762 */
1763 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1764 {
1765 struct pch_gbe_hw *hw = &adapter->hw;
1766 struct net_device *netdev = adapter->netdev;
1767
1768 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1769 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1770 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1771
1772 /* Initialize the hardware-specific values */
1773 if (pch_gbe_hal_setup_init_funcs(hw)) {
1774 pr_err("Hardware Initialization Failure\n");
1775 return -EIO;
1776 }
1777 if (pch_gbe_alloc_queues(adapter)) {
1778 pr_err("Unable to allocate memory for queues\n");
1779 return -ENOMEM;
1780 }
1781 spin_lock_init(&adapter->hw.miim_lock);
1782 spin_lock_init(&adapter->tx_queue_lock);
1783 spin_lock_init(&adapter->stats_lock);
1784 spin_lock_init(&adapter->ethtool_lock);
1785 atomic_set(&adapter->irq_sem, 0);
1786 pch_gbe_irq_disable(adapter);
1787
1788 pch_gbe_init_stats(adapter);
1789
1790 pr_debug("rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
1791 (u32) adapter->rx_buffer_len,
1792 hw->mac.min_frame_size, hw->mac.max_frame_size);
1793 return 0;
1794 }
1795
1796 /**
1797 * pch_gbe_open - Called when a network interface is made active
1798 * @netdev: Network interface device structure
1799 * Returns
1800 * 0: Successfully
1801 * Negative value: Failed
1802 */
1803 static int pch_gbe_open(struct net_device *netdev)
1804 {
1805 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1806 struct pch_gbe_hw *hw = &adapter->hw;
1807 int err;
1808
1809 /* allocate transmit descriptors */
1810 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1811 if (err)
1812 goto err_setup_tx;
1813 /* allocate receive descriptors */
1814 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1815 if (err)
1816 goto err_setup_rx;
1817 pch_gbe_hal_power_up_phy(hw);
1818 err = pch_gbe_up(adapter);
1819 if (err)
1820 goto err_up;
1821 pr_debug("Success End\n");
1822 return 0;
1823
1824 err_up:
1825 if (!adapter->wake_up_evt)
1826 pch_gbe_hal_power_down_phy(hw);
1827 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1828 err_setup_rx:
1829 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1830 err_setup_tx:
1831 pch_gbe_reset(adapter);
1832 pr_err("Error End\n");
1833 return err;
1834 }
1835
1836 /**
1837 * pch_gbe_stop - Disables a network interface
1838 * @netdev: Network interface device structure
1839 * Returns
1840 * 0: Successfully
1841 */
1842 static int pch_gbe_stop(struct net_device *netdev)
1843 {
1844 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1845 struct pch_gbe_hw *hw = &adapter->hw;
1846
1847 pch_gbe_down(adapter);
1848 if (!adapter->wake_up_evt)
1849 pch_gbe_hal_power_down_phy(hw);
1850 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1851 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1852 return 0;
1853 }
1854
1855 /**
1856 * pch_gbe_xmit_frame - Packet transmitting start
1857 * @skb: Socket buffer structure
1858 * @netdev: Network interface device structure
1859 * Returns
1860 * - NETDEV_TX_OK: Normal end
1861 * - NETDEV_TX_BUSY: Error end
1862 */
1863 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1864 {
1865 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1866 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1867 unsigned long flags;
1868
1869 if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
1870 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1871 skb->len, adapter->hw.mac.max_frame_size);
1872 dev_kfree_skb_any(skb);
1873 adapter->stats.tx_length_errors++;
1874 return NETDEV_TX_OK;
1875 }
1876 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1877 /* Collision - tell upper layer to requeue */
1878 return NETDEV_TX_LOCKED;
1879 }
1880 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1881 netif_stop_queue(netdev);
1882 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1883 pr_debug("Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
1884 tx_ring->next_to_use, tx_ring->next_to_clean);
1885 return NETDEV_TX_BUSY;
1886 }
1887 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1888
1889 /* CRC,ITAG no support */
1890 pch_gbe_tx_queue(adapter, tx_ring, skb);
1891 return NETDEV_TX_OK;
1892 }
1893
1894 /**
1895 * pch_gbe_get_stats - Get System Network Statistics
1896 * @netdev: Network interface device structure
1897 * Returns: The current stats
1898 */
1899 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1900 {
1901 /* only return the current stats */
1902 return &netdev->stats;
1903 }
1904
1905 /**
1906 * pch_gbe_set_multi - Multicast and Promiscuous mode set
1907 * @netdev: Network interface device structure
1908 */
1909 static void pch_gbe_set_multi(struct net_device *netdev)
1910 {
1911 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1912 struct pch_gbe_hw *hw = &adapter->hw;
1913 struct netdev_hw_addr *ha;
1914 u8 *mta_list;
1915 u32 rctl;
1916 int i;
1917 int mc_count;
1918
1919 pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1920
1921 /* Check for Promiscuous and All Multicast modes */
1922 rctl = ioread32(&hw->reg->RX_MODE);
1923 mc_count = netdev_mc_count(netdev);
1924 if ((netdev->flags & IFF_PROMISC)) {
1925 rctl &= ~PCH_GBE_ADD_FIL_EN;
1926 rctl &= ~PCH_GBE_MLT_FIL_EN;
1927 } else if ((netdev->flags & IFF_ALLMULTI)) {
1928 /* all the multicasting receive permissions */
1929 rctl |= PCH_GBE_ADD_FIL_EN;
1930 rctl &= ~PCH_GBE_MLT_FIL_EN;
1931 } else {
1932 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1933 /* all the multicasting receive permissions */
1934 rctl |= PCH_GBE_ADD_FIL_EN;
1935 rctl &= ~PCH_GBE_MLT_FIL_EN;
1936 } else {
1937 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1938 }
1939 }
1940 iowrite32(rctl, &hw->reg->RX_MODE);
1941
1942 if (mc_count >= PCH_GBE_MAR_ENTRIES)
1943 return;
1944 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
1945 if (!mta_list)
1946 return;
1947
1948 /* The shared function expects a packed array of only addresses. */
1949 i = 0;
1950 netdev_for_each_mc_addr(ha, netdev) {
1951 if (i == mc_count)
1952 break;
1953 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
1954 }
1955 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
1956 PCH_GBE_MAR_ENTRIES);
1957 kfree(mta_list);
1958
1959 pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
1960 ioread32(&hw->reg->RX_MODE), mc_count);
1961 }
1962
1963 /**
1964 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
1965 * @netdev: Network interface device structure
1966 * @addr: Pointer to an address structure
1967 * Returns
1968 * 0: Successfully
1969 * -EADDRNOTAVAIL: Failed
1970 */
1971 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
1972 {
1973 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1974 struct sockaddr *skaddr = addr;
1975 int ret_val;
1976
1977 if (!is_valid_ether_addr(skaddr->sa_data)) {
1978 ret_val = -EADDRNOTAVAIL;
1979 } else {
1980 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
1981 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
1982 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1983 ret_val = 0;
1984 }
1985 pr_debug("ret_val : 0x%08x\n", ret_val);
1986 pr_debug("dev_addr : %pM\n", netdev->dev_addr);
1987 pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
1988 pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
1989 ioread32(&adapter->hw.reg->mac_adr[0].high),
1990 ioread32(&adapter->hw.reg->mac_adr[0].low));
1991 return ret_val;
1992 }
1993
1994 /**
1995 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
1996 * @netdev: Network interface device structure
1997 * @new_mtu: New value for maximum frame size
1998 * Returns
1999 * 0: Successfully
2000 * -EINVAL: Failed
2001 */
2002 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2003 {
2004 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2005 int max_frame;
2006
2007 max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2008 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2009 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2010 pr_err("Invalid MTU setting\n");
2011 return -EINVAL;
2012 }
2013 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2014 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2015 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2016 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2017 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2018 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2019 else
2020 adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE;
2021 netdev->mtu = new_mtu;
2022 adapter->hw.mac.max_frame_size = max_frame;
2023
2024 if (netif_running(netdev))
2025 pch_gbe_reinit_locked(adapter);
2026 else
2027 pch_gbe_reset(adapter);
2028
2029 pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2030 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2031 adapter->hw.mac.max_frame_size);
2032 return 0;
2033 }
2034
2035 /**
2036 * pch_gbe_set_features - Reset device after features changed
2037 * @netdev: Network interface device structure
2038 * @features: New features
2039 * Returns
2040 * 0: HW state updated successfully
2041 */
2042 static int pch_gbe_set_features(struct net_device *netdev, u32 features)
2043 {
2044 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2045 u32 changed = features ^ netdev->features;
2046
2047 if (!(changed & NETIF_F_RXCSUM))
2048 return 0;
2049
2050 if (netif_running(netdev))
2051 pch_gbe_reinit_locked(adapter);
2052 else
2053 pch_gbe_reset(adapter);
2054
2055 return 0;
2056 }
2057
2058 /**
2059 * pch_gbe_ioctl - Controls register through a MII interface
2060 * @netdev: Network interface device structure
2061 * @ifr: Pointer to ifr structure
2062 * @cmd: Control command
2063 * Returns
2064 * 0: Successfully
2065 * Negative value: Failed
2066 */
2067 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2068 {
2069 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2070
2071 pr_debug("cmd : 0x%04x\n", cmd);
2072
2073 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2074 }
2075
2076 /**
2077 * pch_gbe_tx_timeout - Respond to a Tx Hang
2078 * @netdev: Network interface device structure
2079 */
2080 static void pch_gbe_tx_timeout(struct net_device *netdev)
2081 {
2082 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2083
2084 /* Do the reset outside of interrupt context */
2085 adapter->stats.tx_timeout_count++;
2086 schedule_work(&adapter->reset_task);
2087 }
2088
2089 /**
2090 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2091 * @napi: Pointer of polling device struct
2092 * @budget: The maximum number of a packet
2093 * Returns
2094 * false: Exit the polling mode
2095 * true: Continue the polling mode
2096 */
2097 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2098 {
2099 struct pch_gbe_adapter *adapter =
2100 container_of(napi, struct pch_gbe_adapter, napi);
2101 struct net_device *netdev = adapter->netdev;
2102 int work_done = 0;
2103 bool poll_end_flag = false;
2104 bool cleaned = false;
2105
2106 pr_debug("budget : %d\n", budget);
2107
2108 /* Keep link state information with original netdev */
2109 if (!netif_carrier_ok(netdev)) {
2110 poll_end_flag = true;
2111 } else {
2112 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2113 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2114
2115 if (cleaned)
2116 work_done = budget;
2117 /* If no Tx and not enough Rx work done,
2118 * exit the polling mode
2119 */
2120 if ((work_done < budget) || !netif_running(netdev))
2121 poll_end_flag = true;
2122 }
2123
2124 if (poll_end_flag) {
2125 napi_complete(napi);
2126 pch_gbe_irq_enable(adapter);
2127 }
2128
2129 pr_debug("poll_end_flag : %d work_done : %d budget : %d\n",
2130 poll_end_flag, work_done, budget);
2131
2132 return work_done;
2133 }
2134
2135 #ifdef CONFIG_NET_POLL_CONTROLLER
2136 /**
2137 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2138 * @netdev: Network interface device structure
2139 */
2140 static void pch_gbe_netpoll(struct net_device *netdev)
2141 {
2142 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2143
2144 disable_irq(adapter->pdev->irq);
2145 pch_gbe_intr(adapter->pdev->irq, netdev);
2146 enable_irq(adapter->pdev->irq);
2147 }
2148 #endif
2149
2150 static const struct net_device_ops pch_gbe_netdev_ops = {
2151 .ndo_open = pch_gbe_open,
2152 .ndo_stop = pch_gbe_stop,
2153 .ndo_start_xmit = pch_gbe_xmit_frame,
2154 .ndo_get_stats = pch_gbe_get_stats,
2155 .ndo_set_mac_address = pch_gbe_set_mac,
2156 .ndo_tx_timeout = pch_gbe_tx_timeout,
2157 .ndo_change_mtu = pch_gbe_change_mtu,
2158 .ndo_set_features = pch_gbe_set_features,
2159 .ndo_do_ioctl = pch_gbe_ioctl,
2160 .ndo_set_multicast_list = &pch_gbe_set_multi,
2161 #ifdef CONFIG_NET_POLL_CONTROLLER
2162 .ndo_poll_controller = pch_gbe_netpoll,
2163 #endif
2164 };
2165
2166 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2167 pci_channel_state_t state)
2168 {
2169 struct net_device *netdev = pci_get_drvdata(pdev);
2170 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2171
2172 netif_device_detach(netdev);
2173 if (netif_running(netdev))
2174 pch_gbe_down(adapter);
2175 pci_disable_device(pdev);
2176 /* Request a slot slot reset. */
2177 return PCI_ERS_RESULT_NEED_RESET;
2178 }
2179
2180 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2181 {
2182 struct net_device *netdev = pci_get_drvdata(pdev);
2183 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2184 struct pch_gbe_hw *hw = &adapter->hw;
2185
2186 if (pci_enable_device(pdev)) {
2187 pr_err("Cannot re-enable PCI device after reset\n");
2188 return PCI_ERS_RESULT_DISCONNECT;
2189 }
2190 pci_set_master(pdev);
2191 pci_enable_wake(pdev, PCI_D0, 0);
2192 pch_gbe_hal_power_up_phy(hw);
2193 pch_gbe_reset(adapter);
2194 /* Clear wake up status */
2195 pch_gbe_mac_set_wol_event(hw, 0);
2196
2197 return PCI_ERS_RESULT_RECOVERED;
2198 }
2199
2200 static void pch_gbe_io_resume(struct pci_dev *pdev)
2201 {
2202 struct net_device *netdev = pci_get_drvdata(pdev);
2203 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2204
2205 if (netif_running(netdev)) {
2206 if (pch_gbe_up(adapter)) {
2207 pr_debug("can't bring device back up after reset\n");
2208 return;
2209 }
2210 }
2211 netif_device_attach(netdev);
2212 }
2213
2214 static int __pch_gbe_suspend(struct pci_dev *pdev)
2215 {
2216 struct net_device *netdev = pci_get_drvdata(pdev);
2217 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2218 struct pch_gbe_hw *hw = &adapter->hw;
2219 u32 wufc = adapter->wake_up_evt;
2220 int retval = 0;
2221
2222 netif_device_detach(netdev);
2223 if (netif_running(netdev))
2224 pch_gbe_down(adapter);
2225 if (wufc) {
2226 pch_gbe_set_multi(netdev);
2227 pch_gbe_setup_rctl(adapter);
2228 pch_gbe_configure_rx(adapter);
2229 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2230 hw->mac.link_duplex);
2231 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2232 hw->mac.link_duplex);
2233 pch_gbe_mac_set_wol_event(hw, wufc);
2234 pci_disable_device(pdev);
2235 } else {
2236 pch_gbe_hal_power_down_phy(hw);
2237 pch_gbe_mac_set_wol_event(hw, wufc);
2238 pci_disable_device(pdev);
2239 }
2240 return retval;
2241 }
2242
2243 #ifdef CONFIG_PM
2244 static int pch_gbe_suspend(struct device *device)
2245 {
2246 struct pci_dev *pdev = to_pci_dev(device);
2247
2248 return __pch_gbe_suspend(pdev);
2249 }
2250
2251 static int pch_gbe_resume(struct device *device)
2252 {
2253 struct pci_dev *pdev = to_pci_dev(device);
2254 struct net_device *netdev = pci_get_drvdata(pdev);
2255 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2256 struct pch_gbe_hw *hw = &adapter->hw;
2257 u32 err;
2258
2259 err = pci_enable_device(pdev);
2260 if (err) {
2261 pr_err("Cannot enable PCI device from suspend\n");
2262 return err;
2263 }
2264 pci_set_master(pdev);
2265 pch_gbe_hal_power_up_phy(hw);
2266 pch_gbe_reset(adapter);
2267 /* Clear wake on lan control and status */
2268 pch_gbe_mac_set_wol_event(hw, 0);
2269
2270 if (netif_running(netdev))
2271 pch_gbe_up(adapter);
2272 netif_device_attach(netdev);
2273
2274 return 0;
2275 }
2276 #endif /* CONFIG_PM */
2277
2278 static void pch_gbe_shutdown(struct pci_dev *pdev)
2279 {
2280 __pch_gbe_suspend(pdev);
2281 if (system_state == SYSTEM_POWER_OFF) {
2282 pci_wake_from_d3(pdev, true);
2283 pci_set_power_state(pdev, PCI_D3hot);
2284 }
2285 }
2286
2287 static void pch_gbe_remove(struct pci_dev *pdev)
2288 {
2289 struct net_device *netdev = pci_get_drvdata(pdev);
2290 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2291
2292 cancel_work_sync(&adapter->reset_task);
2293 unregister_netdev(netdev);
2294
2295 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2296
2297 kfree(adapter->tx_ring);
2298 kfree(adapter->rx_ring);
2299
2300 iounmap(adapter->hw.reg);
2301 pci_release_regions(pdev);
2302 free_netdev(netdev);
2303 pci_disable_device(pdev);
2304 }
2305
2306 static int pch_gbe_probe(struct pci_dev *pdev,
2307 const struct pci_device_id *pci_id)
2308 {
2309 struct net_device *netdev;
2310 struct pch_gbe_adapter *adapter;
2311 int ret;
2312
2313 ret = pci_enable_device(pdev);
2314 if (ret)
2315 return ret;
2316
2317 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2318 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2319 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2320 if (ret) {
2321 ret = pci_set_consistent_dma_mask(pdev,
2322 DMA_BIT_MASK(32));
2323 if (ret) {
2324 dev_err(&pdev->dev, "ERR: No usable DMA "
2325 "configuration, aborting\n");
2326 goto err_disable_device;
2327 }
2328 }
2329 }
2330
2331 ret = pci_request_regions(pdev, KBUILD_MODNAME);
2332 if (ret) {
2333 dev_err(&pdev->dev,
2334 "ERR: Can't reserve PCI I/O and memory resources\n");
2335 goto err_disable_device;
2336 }
2337 pci_set_master(pdev);
2338
2339 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2340 if (!netdev) {
2341 ret = -ENOMEM;
2342 dev_err(&pdev->dev,
2343 "ERR: Can't allocate and set up an Ethernet device\n");
2344 goto err_release_pci;
2345 }
2346 SET_NETDEV_DEV(netdev, &pdev->dev);
2347
2348 pci_set_drvdata(pdev, netdev);
2349 adapter = netdev_priv(netdev);
2350 adapter->netdev = netdev;
2351 adapter->pdev = pdev;
2352 adapter->hw.back = adapter;
2353 adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2354 if (!adapter->hw.reg) {
2355 ret = -EIO;
2356 dev_err(&pdev->dev, "Can't ioremap\n");
2357 goto err_free_netdev;
2358 }
2359
2360 netdev->netdev_ops = &pch_gbe_netdev_ops;
2361 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2362 netif_napi_add(netdev, &adapter->napi,
2363 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2364 netdev->hw_features = NETIF_F_RXCSUM |
2365 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2366 netdev->features = netdev->hw_features;
2367 pch_gbe_set_ethtool_ops(netdev);
2368
2369 pch_gbe_mac_load_mac_addr(&adapter->hw);
2370 pch_gbe_mac_reset_hw(&adapter->hw);
2371
2372 /* setup the private structure */
2373 ret = pch_gbe_sw_init(adapter);
2374 if (ret)
2375 goto err_iounmap;
2376
2377 /* Initialize PHY */
2378 ret = pch_gbe_init_phy(adapter);
2379 if (ret) {
2380 dev_err(&pdev->dev, "PHY initialize error\n");
2381 goto err_free_adapter;
2382 }
2383 pch_gbe_hal_get_bus_info(&adapter->hw);
2384
2385 /* Read the MAC address. and store to the private data */
2386 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2387 if (ret) {
2388 dev_err(&pdev->dev, "MAC address Read Error\n");
2389 goto err_free_adapter;
2390 }
2391
2392 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2393 if (!is_valid_ether_addr(netdev->dev_addr)) {
2394 dev_err(&pdev->dev, "Invalid MAC Address\n");
2395 ret = -EIO;
2396 goto err_free_adapter;
2397 }
2398 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2399 (unsigned long)adapter);
2400
2401 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2402
2403 pch_gbe_check_options(adapter);
2404
2405 /* initialize the wol settings based on the eeprom settings */
2406 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2407 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2408
2409 /* reset the hardware with the new settings */
2410 pch_gbe_reset(adapter);
2411
2412 ret = register_netdev(netdev);
2413 if (ret)
2414 goto err_free_adapter;
2415 /* tell the stack to leave us alone until pch_gbe_open() is called */
2416 netif_carrier_off(netdev);
2417 netif_stop_queue(netdev);
2418
2419 dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2420
2421 device_set_wakeup_enable(&pdev->dev, 1);
2422 return 0;
2423
2424 err_free_adapter:
2425 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2426 kfree(adapter->tx_ring);
2427 kfree(adapter->rx_ring);
2428 err_iounmap:
2429 iounmap(adapter->hw.reg);
2430 err_free_netdev:
2431 free_netdev(netdev);
2432 err_release_pci:
2433 pci_release_regions(pdev);
2434 err_disable_device:
2435 pci_disable_device(pdev);
2436 return ret;
2437 }
2438
2439 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2440 {.vendor = PCI_VENDOR_ID_INTEL,
2441 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2442 .subvendor = PCI_ANY_ID,
2443 .subdevice = PCI_ANY_ID,
2444 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2445 .class_mask = (0xFFFF00)
2446 },
2447 {.vendor = PCI_VENDOR_ID_ROHM,
2448 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2449 .subvendor = PCI_ANY_ID,
2450 .subdevice = PCI_ANY_ID,
2451 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2452 .class_mask = (0xFFFF00)
2453 },
2454 /* required last entry */
2455 {0}
2456 };
2457
2458 #ifdef CONFIG_PM
2459 static const struct dev_pm_ops pch_gbe_pm_ops = {
2460 .suspend = pch_gbe_suspend,
2461 .resume = pch_gbe_resume,
2462 .freeze = pch_gbe_suspend,
2463 .thaw = pch_gbe_resume,
2464 .poweroff = pch_gbe_suspend,
2465 .restore = pch_gbe_resume,
2466 };
2467 #endif
2468
2469 static struct pci_error_handlers pch_gbe_err_handler = {
2470 .error_detected = pch_gbe_io_error_detected,
2471 .slot_reset = pch_gbe_io_slot_reset,
2472 .resume = pch_gbe_io_resume
2473 };
2474
2475 static struct pci_driver pch_gbe_driver = {
2476 .name = KBUILD_MODNAME,
2477 .id_table = pch_gbe_pcidev_id,
2478 .probe = pch_gbe_probe,
2479 .remove = pch_gbe_remove,
2480 #ifdef CONFIG_PM
2481 .driver.pm = &pch_gbe_pm_ops,
2482 #endif
2483 .shutdown = pch_gbe_shutdown,
2484 .err_handler = &pch_gbe_err_handler
2485 };
2486
2487
2488 static int __init pch_gbe_init_module(void)
2489 {
2490 int ret;
2491
2492 ret = pci_register_driver(&pch_gbe_driver);
2493 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2494 if (copybreak == 0) {
2495 pr_info("copybreak disabled\n");
2496 } else {
2497 pr_info("copybreak enabled for packets <= %u bytes\n",
2498 copybreak);
2499 }
2500 }
2501 return ret;
2502 }
2503
2504 static void __exit pch_gbe_exit_module(void)
2505 {
2506 pci_unregister_driver(&pch_gbe_driver);
2507 }
2508
2509 module_init(pch_gbe_init_module);
2510 module_exit(pch_gbe_exit_module);
2511
2512 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2513 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
2514 MODULE_LICENSE("GPL");
2515 MODULE_VERSION(DRV_VERSION);
2516 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2517
2518 module_param(copybreak, uint, 0644);
2519 MODULE_PARM_DESC(copybreak,
2520 "Maximum size of packet that is copied to a new buffer on receive");
2521
2522 /* pch_gbe_main.c */