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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / net / qlcnic / qlcnic.h
blob480ef5cb6ef95f2484ea8fdeed5125a3e818db9a
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
27
28 #include <linux/vmalloc.h>
29
30 #include <linux/io.h>
31 #include <asm/byteorder.h>
32 #include <linux/bitops.h>
33 #include <linux/if_vlan.h>
34
35 #include "qlcnic_hdr.h"
36
37 #define _QLCNIC_LINUX_MAJOR 5
38 #define _QLCNIC_LINUX_MINOR 0
39 #define _QLCNIC_LINUX_SUBVERSION 18
40 #define QLCNIC_LINUX_VERSIONID "5.0.18"
41 #define QLCNIC_DRV_IDC_VER 0x01
42 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
44
45 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
46 #define _major(v) (((v) >> 24) & 0xff)
47 #define _minor(v) (((v) >> 16) & 0xff)
48 #define _build(v) ((v) & 0xffff)
49
50 /* version in image has weird encoding:
51 * 7:0 - major
52 * 15:8 - minor
53 * 31:16 - build (little endian)
54 */
55 #define QLCNIC_DECODE_VERSION(v) \
56 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
57
58 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
59 #define QLCNIC_NUM_FLASH_SECTORS (64)
60 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
61 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
62 * QLCNIC_FLASH_SECTOR_SIZE)
63
64 #define RCV_DESC_RINGSIZE(rds_ring) \
65 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
66 #define RCV_BUFF_RINGSIZE(rds_ring) \
67 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
68 #define STATUS_DESC_RINGSIZE(sds_ring) \
69 (sizeof(struct status_desc) * (sds_ring)->num_desc)
70 #define TX_BUFF_RINGSIZE(tx_ring) \
71 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
72 #define TX_DESC_RINGSIZE(tx_ring) \
73 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
74
75 #define QLCNIC_P3P_A0 0x50
76
77 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
78
79 #define FIRST_PAGE_GROUP_START 0
80 #define FIRST_PAGE_GROUP_END 0x100000
81
82 #define P3P_MAX_MTU (9600)
83 #define P3P_MIN_MTU (68)
84 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
85
86 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
87 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
88 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
89 #define QLCNIC_LRO_BUFFER_EXTRA 2048
90
91 /* Opcodes to be used with the commands */
92 #define TX_ETHER_PKT 0x01
93 #define TX_TCP_PKT 0x02
94 #define TX_UDP_PKT 0x03
95 #define TX_IP_PKT 0x04
96 #define TX_TCP_LSO 0x05
97 #define TX_TCP_LSO6 0x06
98 #define TX_TCPV6_PKT 0x0b
99 #define TX_UDPV6_PKT 0x0c
100
101 /* Tx defines */
102 #define QLCNIC_MAX_FRAGS_PER_TX 14
103 #define MAX_TSO_HEADER_DESC 2
104 #define MGMT_CMD_DESC_RESV 4
105 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
106 + MGMT_CMD_DESC_RESV)
107 #define QLCNIC_MAX_TX_TIMEOUTS 2
108
109 /*
110 * Following are the states of the Phantom. Phantom will set them and
111 * Host will read to check if the fields are correct.
112 */
113 #define PHAN_INITIALIZE_FAILED 0xffff
114 #define PHAN_INITIALIZE_COMPLETE 0xff01
115
116 /* Host writes the following to notify that it has done the init-handshake */
117 #define PHAN_INITIALIZE_ACK 0xf00f
118 #define PHAN_PEG_RCV_INITIALIZED 0xff01
119
120 #define NUM_RCV_DESC_RINGS 3
121
122 #define RCV_RING_NORMAL 0
123 #define RCV_RING_JUMBO 1
124
125 #define MIN_CMD_DESCRIPTORS 64
126 #define MIN_RCV_DESCRIPTORS 64
127 #define MIN_JUMBO_DESCRIPTORS 32
128
129 #define MAX_CMD_DESCRIPTORS 1024
130 #define MAX_RCV_DESCRIPTORS_1G 4096
131 #define MAX_RCV_DESCRIPTORS_10G 8192
132 #define MAX_RCV_DESCRIPTORS_VF 2048
133 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
134 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
135
136 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
137 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
138 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
139 #define MAX_RDS_RINGS 2
140
141 #define get_next_index(index, length) \
142 (((index) + 1) & ((length) - 1))
143
144 /*
145 * Following data structures describe the descriptors that will be used.
146 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
147 * we are doing LSO (above the 1500 size packet) only.
148 */
149
150 #define FLAGS_VLAN_TAGGED 0x10
151 #define FLAGS_VLAN_OOB 0x40
152
153 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
154 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
155 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
156 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
157 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
158 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
159
160 #define qlcnic_set_tx_port(_desc, _port) \
161 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
162
163 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
164 ((_desc)->flags_opcode |= \
165 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
166
167 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
168 ((_desc)->nfrags__length = \
169 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
170
171 struct cmd_desc_type0 {
172 u8 tcp_hdr_offset; /* For LSO only */
173 u8 ip_hdr_offset; /* For LSO only */
174 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
175 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
176
177 __le64 addr_buffer2;
178
179 __le16 reference_handle;
180 __le16 mss;
181 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
182 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
183 __le16 conn_id; /* IPSec offoad only */
184
185 __le64 addr_buffer3;
186 __le64 addr_buffer1;
187
188 __le16 buffer_length[4];
189
190 __le64 addr_buffer4;
191
192 u8 eth_addr[ETH_ALEN];
193 __le16 vlan_TCI;
194
195 } __attribute__ ((aligned(64)));
196
197 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
198 struct rcv_desc {
199 __le16 reference_handle;
200 __le16 reserved;
201 __le32 buffer_length; /* allocated buffer length (usually 2K) */
202 __le64 addr_buffer;
203 } __packed;
204
205 /* opcode field in status_desc */
206 #define QLCNIC_SYN_OFFLOAD 0x03
207 #define QLCNIC_RXPKT_DESC 0x04
208 #define QLCNIC_OLD_RXPKT_DESC 0x3f
209 #define QLCNIC_RESPONSE_DESC 0x05
210 #define QLCNIC_LRO_DESC 0x12
211
212 /* for status field in status_desc */
213 #define STATUS_CKSUM_LOOP 0
214 #define STATUS_CKSUM_OK 2
215
216 /* owner bits of status_desc */
217 #define STATUS_OWNER_HOST (0x1ULL << 56)
218 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
219
220 /* Status descriptor:
221 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
222 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
223 53-55 desc_cnt, 56-57 owner, 58-63 opcode
224 */
225 #define qlcnic_get_sts_port(sts_data) \
226 ((sts_data) & 0x0F)
227 #define qlcnic_get_sts_status(sts_data) \
228 (((sts_data) >> 4) & 0x0F)
229 #define qlcnic_get_sts_type(sts_data) \
230 (((sts_data) >> 8) & 0x0F)
231 #define qlcnic_get_sts_totallength(sts_data) \
232 (((sts_data) >> 12) & 0xFFFF)
233 #define qlcnic_get_sts_refhandle(sts_data) \
234 (((sts_data) >> 28) & 0xFFFF)
235 #define qlcnic_get_sts_prot(sts_data) \
236 (((sts_data) >> 44) & 0x0F)
237 #define qlcnic_get_sts_pkt_offset(sts_data) \
238 (((sts_data) >> 48) & 0x1F)
239 #define qlcnic_get_sts_desc_cnt(sts_data) \
240 (((sts_data) >> 53) & 0x7)
241 #define qlcnic_get_sts_opcode(sts_data) \
242 (((sts_data) >> 58) & 0x03F)
243
244 #define qlcnic_get_lro_sts_refhandle(sts_data) \
245 ((sts_data) & 0x0FFFF)
246 #define qlcnic_get_lro_sts_length(sts_data) \
247 (((sts_data) >> 16) & 0x0FFFF)
248 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
249 (((sts_data) >> 32) & 0x0FF)
250 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
251 (((sts_data) >> 40) & 0x0FF)
252 #define qlcnic_get_lro_sts_timestamp(sts_data) \
253 (((sts_data) >> 48) & 0x1)
254 #define qlcnic_get_lro_sts_type(sts_data) \
255 (((sts_data) >> 49) & 0x7)
256 #define qlcnic_get_lro_sts_push_flag(sts_data) \
257 (((sts_data) >> 52) & 0x1)
258 #define qlcnic_get_lro_sts_seq_number(sts_data) \
259 ((sts_data) & 0x0FFFFFFFF)
260
261
262 struct status_desc {
263 __le64 status_desc_data[2];
264 } __attribute__ ((aligned(16)));
265
266 /* UNIFIED ROMIMAGE */
267 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
268 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
269 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
270 #define QLCNIC_UNI_DIR_SECT_FW 0x7
271
272 /*Offsets */
273 #define QLCNIC_UNI_CHIP_REV_OFF 10
274 #define QLCNIC_UNI_FLAGS_OFF 11
275 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
276 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
277 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
278
279 struct uni_table_desc{
280 u32 findex;
281 u32 num_entries;
282 u32 entry_size;
283 u32 reserved[5];
284 };
285
286 struct uni_data_desc{
287 u32 findex;
288 u32 size;
289 u32 reserved[5];
290 };
291
292 /* Flash Defines and Structures */
293 #define QLCNIC_FLT_LOCATION 0x3F1000
294 #define QLCNIC_FW_IMAGE_REGION 0x74
295 #define QLCNIC_BOOTLD_REGION 0X72
296 struct qlcnic_flt_header {
297 u16 version;
298 u16 len;
299 u16 checksum;
300 u16 reserved;
301 };
302
303 struct qlcnic_flt_entry {
304 u8 region;
305 u8 reserved0;
306 u8 attrib;
307 u8 reserved1;
308 u32 size;
309 u32 start_addr;
310 u32 end_addr;
311 };
312
313 /* Magic number to let user know flash is programmed */
314 #define QLCNIC_BDINFO_MAGIC 0x12345678
315
316 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
317 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
318 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
319 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
320 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
321 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
322 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
323 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
324 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
325 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
326 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
327 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
328 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
329 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
330
331 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
332
333 /* Flash memory map */
334 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
335 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
336 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
337 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
338
339 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
340 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
341 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
342 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
343
344 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
345 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
346
347 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
348 #define QLCNIC_UNIFIED_ROMIMAGE 0
349 #define QLCNIC_FLASH_ROMIMAGE 1
350 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
351
352 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
353 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
354
355 extern char qlcnic_driver_name[];
356
357 /* Number of status descriptors to handle per interrupt */
358 #define MAX_STATUS_HANDLE (64)
359
360 /*
361 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
362 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
363 */
364 struct qlcnic_skb_frag {
365 u64 dma;
366 u64 length;
367 };
368
369 /* Following defines are for the state of the buffers */
370 #define QLCNIC_BUFFER_FREE 0
371 #define QLCNIC_BUFFER_BUSY 1
372
373 /*
374 * There will be one qlcnic_buffer per skb packet. These will be
375 * used to save the dma info for pci_unmap_page()
376 */
377 struct qlcnic_cmd_buffer {
378 struct sk_buff *skb;
379 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
380 u32 frag_count;
381 };
382
383 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
384 struct qlcnic_rx_buffer {
385 u16 ref_handle;
386 struct sk_buff *skb;
387 struct list_head list;
388 u64 dma;
389 };
390
391 /* Board types */
392 #define QLCNIC_GBE 0x01
393 #define QLCNIC_XGBE 0x02
394
395 /*
396 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
397 * adjusted based on configured MTU.
398 */
399 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
400 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
401
402 #define QLCNIC_INTR_DEFAULT 0x04
403 #define QLCNIC_CONFIG_INTR_COALESCE 3
404
405 struct qlcnic_nic_intr_coalesce {
406 u8 type;
407 u8 sts_ring_mask;
408 u16 rx_packets;
409 u16 rx_time_us;
410 u16 flag;
411 u32 timer_out;
412 };
413
414 struct qlcnic_dump_template_hdr {
415 __le32 type;
416 __le32 offset;
417 __le32 size;
418 __le32 cap_mask;
419 __le32 num_entries;
420 __le32 version;
421 __le32 timestamp;
422 __le32 checksum;
423 __le32 drv_cap_mask;
424 __le32 sys_info[3];
425 __le32 saved_state[16];
426 __le32 cap_sizes[8];
427 __le32 rsvd[0];
428 };
429
430 struct qlcnic_fw_dump {
431 u8 clr; /* flag to indicate if dump is cleared */
432 u32 size; /* total size of the dump */
433 void *data; /* dump data area */
434 struct qlcnic_dump_template_hdr *tmpl_hdr;
435 };
436
437 /*
438 * One hardware_context{} per adapter
439 * contains interrupt info as well shared hardware info.
440 */
441 struct qlcnic_hardware_context {
442 void __iomem *pci_base0;
443 void __iomem *ocm_win_crb;
444
445 unsigned long pci_len0;
446
447 rwlock_t crb_lock;
448 struct mutex mem_lock;
449
450 u8 revision_id;
451 u8 pci_func;
452 u8 linkup;
453 u16 port_type;
454 u16 board_type;
455
456 struct qlcnic_nic_intr_coalesce coal;
457 struct qlcnic_fw_dump fw_dump;
458 };
459
460 struct qlcnic_adapter_stats {
461 u64 xmitcalled;
462 u64 xmitfinished;
463 u64 rxdropped;
464 u64 txdropped;
465 u64 csummed;
466 u64 rx_pkts;
467 u64 lro_pkts;
468 u64 rxbytes;
469 u64 txbytes;
470 u64 lrobytes;
471 u64 lso_frames;
472 u64 xmit_on;
473 u64 xmit_off;
474 u64 skb_alloc_failure;
475 u64 null_rxbuf;
476 u64 rx_dma_map_error;
477 u64 tx_dma_map_error;
478 };
479
480 /*
481 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
482 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
483 */
484 struct qlcnic_host_rds_ring {
485 void __iomem *crb_rcv_producer;
486 struct rcv_desc *desc_head;
487 struct qlcnic_rx_buffer *rx_buf_arr;
488 u32 num_desc;
489 u32 producer;
490 u32 dma_size;
491 u32 skb_size;
492 u32 flags;
493 struct list_head free_list;
494 spinlock_t lock;
495 dma_addr_t phys_addr;
496 } ____cacheline_internodealigned_in_smp;
497
498 struct qlcnic_host_sds_ring {
499 u32 consumer;
500 u32 num_desc;
501 void __iomem *crb_sts_consumer;
502
503 struct status_desc *desc_head;
504 struct qlcnic_adapter *adapter;
505 struct napi_struct napi;
506 struct list_head free_list[NUM_RCV_DESC_RINGS];
507
508 void __iomem *crb_intr_mask;
509 int irq;
510
511 dma_addr_t phys_addr;
512 char name[IFNAMSIZ+4];
513 } ____cacheline_internodealigned_in_smp;
514
515 struct qlcnic_host_tx_ring {
516 u32 producer;
517 u32 sw_consumer;
518 u32 num_desc;
519 void __iomem *crb_cmd_producer;
520 struct cmd_desc_type0 *desc_head;
521 struct qlcnic_cmd_buffer *cmd_buf_arr;
522 __le32 *hw_consumer;
523
524 dma_addr_t phys_addr;
525 dma_addr_t hw_cons_phys_addr;
526 struct netdev_queue *txq;
527 } ____cacheline_internodealigned_in_smp;
528
529 /*
530 * Receive context. There is one such structure per instance of the
531 * receive processing. Any state information that is relevant to
532 * the receive, and is must be in this structure. The global data may be
533 * present elsewhere.
534 */
535 struct qlcnic_recv_context {
536 struct qlcnic_host_rds_ring *rds_rings;
537 struct qlcnic_host_sds_ring *sds_rings;
538 u32 state;
539 u16 context_id;
540 u16 virt_port;
541
542 };
543
544 /* HW context creation */
545
546 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
547 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
548 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
549
550 #define QLCNIC_CDRP_CMD_BIT 0x80000000
551
552 /*
553 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
554 * in the crb QLCNIC_CDRP_CRB_OFFSET.
555 */
556 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
557 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
558
559 #define QLCNIC_CDRP_RSP_OK 0x00000001
560 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
561 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
562
563 /*
564 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
565 * the crb QLCNIC_CDRP_CRB_OFFSET.
566 */
567 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
568 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
569
570 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
571 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
572 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
573 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
574 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
575 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
576 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
577 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
578 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
579 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
580 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
581 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
582 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
583 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
584 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
585 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
586 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
587 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
588 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
589
590 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
591 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
592 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
593 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
594 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
595 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
596 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
597 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
598 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
599 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
600 #define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E
601 #define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f
602 #define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030
603
604 #define QLCNIC_RCODE_SUCCESS 0
605 #define QLCNIC_RCODE_NOT_SUPPORTED 9
606 #define QLCNIC_RCODE_TIMEOUT 17
607 #define QLCNIC_DESTROY_CTX_RESET 0
608
609 /*
610 * Capabilities Announced
611 */
612 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
613 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
614 #define QLCNIC_CAP0_LSO (1 << 6)
615 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
616 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
617 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
618
619 /*
620 * Context state
621 */
622 #define QLCNIC_HOST_CTX_STATE_FREED 0
623 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
624
625 /*
626 * Rx context
627 */
628
629 struct qlcnic_hostrq_sds_ring {
630 __le64 host_phys_addr; /* Ring base addr */
631 __le32 ring_size; /* Ring entries */
632 __le16 msi_index;
633 __le16 rsvd; /* Padding */
634 } __packed;
635
636 struct qlcnic_hostrq_rds_ring {
637 __le64 host_phys_addr; /* Ring base addr */
638 __le64 buff_size; /* Packet buffer size */
639 __le32 ring_size; /* Ring entries */
640 __le32 ring_kind; /* Class of ring */
641 } __packed;
642
643 struct qlcnic_hostrq_rx_ctx {
644 __le64 host_rsp_dma_addr; /* Response dma'd here */
645 __le32 capabilities[4]; /* Flag bit vector */
646 __le32 host_int_crb_mode; /* Interrupt crb usage */
647 __le32 host_rds_crb_mode; /* RDS crb usage */
648 /* These ring offsets are relative to data[0] below */
649 __le32 rds_ring_offset; /* Offset to RDS config */
650 __le32 sds_ring_offset; /* Offset to SDS config */
651 __le16 num_rds_rings; /* Count of RDS rings */
652 __le16 num_sds_rings; /* Count of SDS rings */
653 __le16 valid_field_offset;
654 u8 txrx_sds_binding;
655 u8 msix_handler;
656 u8 reserved[128]; /* reserve space for future expansion*/
657 /* MUST BE 64-bit aligned.
658 The following is packed:
659 - N hostrq_rds_rings
660 - N hostrq_sds_rings */
661 char data[0];
662 } __packed;
663
664 struct qlcnic_cardrsp_rds_ring{
665 __le32 host_producer_crb; /* Crb to use */
666 __le32 rsvd1; /* Padding */
667 } __packed;
668
669 struct qlcnic_cardrsp_sds_ring {
670 __le32 host_consumer_crb; /* Crb to use */
671 __le32 interrupt_crb; /* Crb to use */
672 } __packed;
673
674 struct qlcnic_cardrsp_rx_ctx {
675 /* These ring offsets are relative to data[0] below */
676 __le32 rds_ring_offset; /* Offset to RDS config */
677 __le32 sds_ring_offset; /* Offset to SDS config */
678 __le32 host_ctx_state; /* Starting State */
679 __le32 num_fn_per_port; /* How many PCI fn share the port */
680 __le16 num_rds_rings; /* Count of RDS rings */
681 __le16 num_sds_rings; /* Count of SDS rings */
682 __le16 context_id; /* Handle for context */
683 u8 phys_port; /* Physical id of port */
684 u8 virt_port; /* Virtual/Logical id of port */
685 u8 reserved[128]; /* save space for future expansion */
686 /* MUST BE 64-bit aligned.
687 The following is packed:
688 - N cardrsp_rds_rings
689 - N cardrs_sds_rings */
690 char data[0];
691 } __packed;
692
693 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
694 (sizeof(HOSTRQ_RX) + \
695 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
696 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
697
698 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
699 (sizeof(CARDRSP_RX) + \
700 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
701 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
702
703 /*
704 * Tx context
705 */
706
707 struct qlcnic_hostrq_cds_ring {
708 __le64 host_phys_addr; /* Ring base addr */
709 __le32 ring_size; /* Ring entries */
710 __le32 rsvd; /* Padding */
711 } __packed;
712
713 struct qlcnic_hostrq_tx_ctx {
714 __le64 host_rsp_dma_addr; /* Response dma'd here */
715 __le64 cmd_cons_dma_addr; /* */
716 __le64 dummy_dma_addr; /* */
717 __le32 capabilities[4]; /* Flag bit vector */
718 __le32 host_int_crb_mode; /* Interrupt crb usage */
719 __le32 rsvd1; /* Padding */
720 __le16 rsvd2; /* Padding */
721 __le16 interrupt_ctl;
722 __le16 msi_index;
723 __le16 rsvd3; /* Padding */
724 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
725 u8 reserved[128]; /* future expansion */
726 } __packed;
727
728 struct qlcnic_cardrsp_cds_ring {
729 __le32 host_producer_crb; /* Crb to use */
730 __le32 interrupt_crb; /* Crb to use */
731 } __packed;
732
733 struct qlcnic_cardrsp_tx_ctx {
734 __le32 host_ctx_state; /* Starting state */
735 __le16 context_id; /* Handle for context */
736 u8 phys_port; /* Physical id of port */
737 u8 virt_port; /* Virtual/Logical id of port */
738 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
739 u8 reserved[128]; /* future expansion */
740 } __packed;
741
742 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
743 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
744
745 /* CRB */
746
747 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
748 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
749 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
750 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
751
752 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
753 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
754 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
755 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
756 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
757
758
759 /* MAC */
760
761 #define MC_COUNT_P3P 38
762
763 #define QLCNIC_MAC_NOOP 0
764 #define QLCNIC_MAC_ADD 1
765 #define QLCNIC_MAC_DEL 2
766 #define QLCNIC_MAC_VLAN_ADD 3
767 #define QLCNIC_MAC_VLAN_DEL 4
768
769 struct qlcnic_mac_list_s {
770 struct list_head list;
771 uint8_t mac_addr[ETH_ALEN+2];
772 };
773
774 #define QLCNIC_HOST_REQUEST 0x13
775 #define QLCNIC_REQUEST 0x14
776
777 #define QLCNIC_MAC_EVENT 0x1
778
779 #define QLCNIC_IP_UP 2
780 #define QLCNIC_IP_DOWN 3
781
782 /*
783 * Driver --> Firmware
784 */
785 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
786 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
787 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
788 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
789 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
790 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
791 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
792 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
793 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
794 /*
795 * Firmware --> Driver
796 */
797
798 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
799
800 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
801 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
802 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
803
804 #define QLCNIC_LRO_REQUEST_CLEANUP 4
805
806 /* Capabilites received */
807 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
808 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
809 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
810 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
811
812 /* module types */
813 #define LINKEVENT_MODULE_NOT_PRESENT 1
814 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
815 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
816 #define LINKEVENT_MODULE_OPTICAL_LRM 4
817 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
818 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
819 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
820 #define LINKEVENT_MODULE_TWINAX 8
821
822 #define LINKSPEED_10GBPS 10000
823 #define LINKSPEED_1GBPS 1000
824 #define LINKSPEED_100MBPS 100
825 #define LINKSPEED_10MBPS 10
826
827 #define LINKSPEED_ENCODED_10MBPS 0
828 #define LINKSPEED_ENCODED_100MBPS 1
829 #define LINKSPEED_ENCODED_1GBPS 2
830
831 #define LINKEVENT_AUTONEG_DISABLED 0
832 #define LINKEVENT_AUTONEG_ENABLED 1
833
834 #define LINKEVENT_HALF_DUPLEX 0
835 #define LINKEVENT_FULL_DUPLEX 1
836
837 #define LINKEVENT_LINKSPEED_MBPS 0
838 #define LINKEVENT_LINKSPEED_ENCODED 1
839
840 /* firmware response header:
841 * 63:58 - message type
842 * 57:56 - owner
843 * 55:53 - desc count
844 * 52:48 - reserved
845 * 47:40 - completion id
846 * 39:32 - opcode
847 * 31:16 - error code
848 * 15:00 - reserved
849 */
850 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
851 ((msg_hdr >> 32) & 0xFF)
852
853 struct qlcnic_fw_msg {
854 union {
855 struct {
856 u64 hdr;
857 u64 body[7];
858 };
859 u64 words[8];
860 };
861 };
862
863 struct qlcnic_nic_req {
864 __le64 qhdr;
865 __le64 req_hdr;
866 __le64 words[6];
867 } __packed;
868
869 struct qlcnic_mac_req {
870 u8 op;
871 u8 tag;
872 u8 mac_addr[6];
873 };
874
875 struct qlcnic_vlan_req {
876 __le16 vlan_id;
877 __le16 rsvd[3];
878 } __packed;
879
880 struct qlcnic_ipaddr {
881 __be32 ipv4;
882 __be32 ipv6[4];
883 };
884
885 #define QLCNIC_MSI_ENABLED 0x02
886 #define QLCNIC_MSIX_ENABLED 0x04
887 #define QLCNIC_LRO_ENABLED 0x08
888 #define QLCNIC_LRO_DISABLED 0x00
889 #define QLCNIC_BRIDGE_ENABLED 0X10
890 #define QLCNIC_DIAG_ENABLED 0x20
891 #define QLCNIC_ESWITCH_ENABLED 0x40
892 #define QLCNIC_ADAPTER_INITIALIZED 0x80
893 #define QLCNIC_TAGGING_ENABLED 0x100
894 #define QLCNIC_MACSPOOF 0x200
895 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
896 #define QLCNIC_PROMISC_DISABLED 0x800
897 #define QLCNIC_NEED_FLR 0x1000
898 #define QLCNIC_IS_MSI_FAMILY(adapter) \
899 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
900
901 #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4
902 #define QLCNIC_MIN_NUM_RSS_RINGS 2
903 #define QLCNIC_MSIX_TBL_SPACE 8192
904 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
905 #define QLCNIC_MSIX_TBL_PGSIZE 4096
906
907 #define QLCNIC_NETDEV_WEIGHT 128
908 #define QLCNIC_ADAPTER_UP_MAGIC 777
909
910 #define __QLCNIC_FW_ATTACHED 0
911 #define __QLCNIC_DEV_UP 1
912 #define __QLCNIC_RESETTING 2
913 #define __QLCNIC_START_FW 4
914 #define __QLCNIC_AER 5
915 #define __QLCNIC_DIAG_RES_ALLOC 6
916
917 #define QLCNIC_INTERRUPT_TEST 1
918 #define QLCNIC_LOOPBACK_TEST 2
919 #define QLCNIC_LED_TEST 3
920
921 #define QLCNIC_FILTER_AGE 80
922 #define QLCNIC_READD_AGE 20
923 #define QLCNIC_LB_MAX_FILTERS 64
924
925 struct qlcnic_filter {
926 struct hlist_node fnode;
927 u8 faddr[ETH_ALEN];
928 __le16 vlan_id;
929 unsigned long ftime;
930 };
931
932 struct qlcnic_filter_hash {
933 struct hlist_head *fhead;
934 u8 fnum;
935 u8 fmax;
936 };
937
938 struct qlcnic_adapter {
939 struct qlcnic_hardware_context *ahw;
940 struct qlcnic_recv_context *recv_ctx;
941 struct qlcnic_host_tx_ring *tx_ring;
942 struct net_device *netdev;
943 struct pci_dev *pdev;
944
945 unsigned long state;
946 u32 flags;
947
948 u16 num_txd;
949 u16 num_rxd;
950 u16 num_jumbo_rxd;
951 u16 max_rxd;
952 u16 max_jumbo_rxd;
953
954 u8 max_rds_rings;
955 u8 max_sds_rings;
956 u8 msix_supported;
957 u8 portnum;
958 u8 physical_port;
959 u8 reset_context;
960
961 u8 mc_enabled;
962 u8 max_mc_count;
963 u8 fw_wait_cnt;
964 u8 fw_fail_cnt;
965 u8 tx_timeo_cnt;
966 u8 need_fw_reset;
967
968 u8 has_link_events;
969 u8 fw_type;
970 u16 tx_context_id;
971 u16 is_up;
972
973 u16 link_speed;
974 u16 link_duplex;
975 u16 link_autoneg;
976 u16 module_type;
977
978 u16 op_mode;
979 u16 switch_mode;
980 u16 max_tx_ques;
981 u16 max_rx_ques;
982 u16 max_mtu;
983 u16 pvid;
984
985 u32 fw_hal_version;
986 u32 capabilities;
987 u32 irq;
988 u32 temp;
989
990 u32 int_vec_bit;
991 u32 heartbeat;
992
993 u8 max_mac_filters;
994 u8 dev_state;
995 u8 diag_test;
996 u8 diag_cnt;
997 u8 reset_ack_timeo;
998 u8 dev_init_timeo;
999 u16 msg_enable;
1000
1001 u8 mac_addr[ETH_ALEN];
1002
1003 u64 dev_rst_time;
1004 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1005
1006 struct qlcnic_npar_info *npars;
1007 struct qlcnic_eswitch *eswitch;
1008 struct qlcnic_nic_template *nic_ops;
1009
1010 struct qlcnic_adapter_stats stats;
1011 struct list_head mac_list;
1012
1013 void __iomem *tgt_mask_reg;
1014 void __iomem *tgt_status_reg;
1015 void __iomem *crb_int_state_reg;
1016 void __iomem *isr_int_vec;
1017
1018 struct msix_entry *msix_entries;
1019
1020 struct delayed_work fw_work;
1021
1022
1023 struct qlcnic_filter_hash fhash;
1024
1025 spinlock_t tx_clean_lock;
1026 spinlock_t mac_learn_lock;
1027 __le32 file_prd_off; /*File fw product offset*/
1028 u32 fw_version;
1029 const struct firmware *fw;
1030 };
1031
1032 struct qlcnic_info {
1033 __le16 pci_func;
1034 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1035 __le16 phys_port;
1036 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1037
1038 __le32 capabilities;
1039 u8 max_mac_filters;
1040 u8 reserved1;
1041 __le16 max_mtu;
1042
1043 __le16 max_tx_ques;
1044 __le16 max_rx_ques;
1045 __le16 min_tx_bw;
1046 __le16 max_tx_bw;
1047 u8 reserved2[104];
1048 } __packed;
1049
1050 struct qlcnic_pci_info {
1051 __le16 id; /* pci function id */
1052 __le16 active; /* 1 = Enabled */
1053 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1054 __le16 default_port; /* default port number */
1055
1056 __le16 tx_min_bw; /* Multiple of 100mbpc */
1057 __le16 tx_max_bw;
1058 __le16 reserved1[2];
1059
1060 u8 mac[ETH_ALEN];
1061 u8 reserved2[106];
1062 } __packed;
1063
1064 struct qlcnic_npar_info {
1065 u16 pvid;
1066 u16 min_bw;
1067 u16 max_bw;
1068 u8 phy_port;
1069 u8 type;
1070 u8 active;
1071 u8 enable_pm;
1072 u8 dest_npar;
1073 u8 discard_tagged;
1074 u8 mac_override;
1075 u8 mac_anti_spoof;
1076 u8 promisc_mode;
1077 u8 offload_flags;
1078 };
1079
1080 struct qlcnic_eswitch {
1081 u8 port;
1082 u8 active_vports;
1083 u8 active_vlans;
1084 u8 active_ucast_filters;
1085 u8 max_ucast_filters;
1086 u8 max_active_vlans;
1087
1088 u32 flags;
1089 #define QLCNIC_SWITCH_ENABLE BIT_1
1090 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1091 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1092 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1093 };
1094
1095
1096 /* Return codes for Error handling */
1097 #define QL_STATUS_INVALID_PARAM -1
1098
1099 #define MAX_BW 100 /* % of link speed */
1100 #define MAX_VLAN_ID 4095
1101 #define MIN_VLAN_ID 2
1102 #define DEFAULT_MAC_LEARN 1
1103
1104 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1105 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1106
1107 struct qlcnic_pci_func_cfg {
1108 u16 func_type;
1109 u16 min_bw;
1110 u16 max_bw;
1111 u16 port_num;
1112 u8 pci_func;
1113 u8 func_state;
1114 u8 def_mac_addr[6];
1115 };
1116
1117 struct qlcnic_npar_func_cfg {
1118 u32 fw_capab;
1119 u16 port_num;
1120 u16 min_bw;
1121 u16 max_bw;
1122 u16 max_tx_queues;
1123 u16 max_rx_queues;
1124 u8 pci_func;
1125 u8 op_mode;
1126 };
1127
1128 struct qlcnic_pm_func_cfg {
1129 u8 pci_func;
1130 u8 action;
1131 u8 dest_npar;
1132 u8 reserved[5];
1133 };
1134
1135 struct qlcnic_esw_func_cfg {
1136 u16 vlan_id;
1137 u8 op_mode;
1138 u8 op_type;
1139 u8 pci_func;
1140 u8 host_vlan_tag;
1141 u8 promisc_mode;
1142 u8 discard_tagged;
1143 u8 mac_override;
1144 u8 mac_anti_spoof;
1145 u8 offload_flags;
1146 u8 reserved[5];
1147 };
1148
1149 #define QLCNIC_STATS_VERSION 1
1150 #define QLCNIC_STATS_PORT 1
1151 #define QLCNIC_STATS_ESWITCH 2
1152 #define QLCNIC_QUERY_RX_COUNTER 0
1153 #define QLCNIC_QUERY_TX_COUNTER 1
1154 #define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL
1155
1156 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1157 do { \
1158 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1159 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1160 (VAL1) = (VAL2); \
1161 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1162 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1163 (VAL1) += (VAL2); \
1164 } while (0)
1165
1166 struct __qlcnic_esw_statistics {
1167 __le16 context_id;
1168 __le16 version;
1169 __le16 size;
1170 __le16 unused;
1171 __le64 unicast_frames;
1172 __le64 multicast_frames;
1173 __le64 broadcast_frames;
1174 __le64 dropped_frames;
1175 __le64 errors;
1176 __le64 local_frames;
1177 __le64 numbytes;
1178 __le64 rsvd[3];
1179 } __packed;
1180
1181 struct qlcnic_esw_statistics {
1182 struct __qlcnic_esw_statistics rx;
1183 struct __qlcnic_esw_statistics tx;
1184 };
1185
1186 struct qlcnic_common_entry_hdr {
1187 __le32 type;
1188 __le32 offset;
1189 __le32 cap_size;
1190 u8 mask;
1191 u8 rsvd[2];
1192 u8 flags;
1193 } __packed;
1194
1195 struct __crb {
1196 __le32 addr;
1197 u8 stride;
1198 u8 rsvd1[3];
1199 __le32 data_size;
1200 __le32 no_ops;
1201 __le32 rsvd2[4];
1202 } __packed;
1203
1204 struct __ctrl {
1205 __le32 addr;
1206 u8 stride;
1207 u8 index_a;
1208 __le16 timeout;
1209 __le32 data_size;
1210 __le32 no_ops;
1211 u8 opcode;
1212 u8 index_v;
1213 u8 shl_val;
1214 u8 shr_val;
1215 __le32 val1;
1216 __le32 val2;
1217 __le32 val3;
1218 } __packed;
1219
1220 struct __cache {
1221 __le32 addr;
1222 u8 stride;
1223 u8 rsvd;
1224 __le16 init_tag_val;
1225 __le32 size;
1226 __le32 no_ops;
1227 __le32 ctrl_addr;
1228 __le32 ctrl_val;
1229 __le32 read_addr;
1230 u8 read_addr_stride;
1231 u8 read_addr_num;
1232 u8 rsvd1[2];
1233 } __packed;
1234
1235 struct __ocm {
1236 u8 rsvd[8];
1237 __le32 size;
1238 __le32 no_ops;
1239 u8 rsvd1[8];
1240 __le32 read_addr;
1241 __le32 read_addr_stride;
1242 } __packed;
1243
1244 struct __mem {
1245 u8 rsvd[24];
1246 __le32 addr;
1247 __le32 size;
1248 } __packed;
1249
1250 struct __mux {
1251 __le32 addr;
1252 u8 rsvd[4];
1253 __le32 size;
1254 __le32 no_ops;
1255 __le32 val;
1256 __le32 val_stride;
1257 __le32 read_addr;
1258 u8 rsvd2[4];
1259 } __packed;
1260
1261 struct __queue {
1262 __le32 sel_addr;
1263 __le16 stride;
1264 u8 rsvd[2];
1265 __le32 size;
1266 __le32 no_ops;
1267 u8 rsvd2[8];
1268 __le32 read_addr;
1269 u8 read_addr_stride;
1270 u8 read_addr_cnt;
1271 u8 rsvd3[2];
1272 } __packed;
1273
1274 struct qlcnic_dump_entry {
1275 struct qlcnic_common_entry_hdr hdr;
1276 union {
1277 struct __crb crb;
1278 struct __cache cache;
1279 struct __ocm ocm;
1280 struct __mem mem;
1281 struct __mux mux;
1282 struct __queue que;
1283 struct __ctrl ctrl;
1284 } region;
1285 } __packed;
1286
1287 enum op_codes {
1288 QLCNIC_DUMP_NOP = 0,
1289 QLCNIC_DUMP_READ_CRB = 1,
1290 QLCNIC_DUMP_READ_MUX = 2,
1291 QLCNIC_DUMP_QUEUE = 3,
1292 QLCNIC_DUMP_BRD_CONFIG = 4,
1293 QLCNIC_DUMP_READ_OCM = 6,
1294 QLCNIC_DUMP_PEG_REG = 7,
1295 QLCNIC_DUMP_L1_DTAG = 8,
1296 QLCNIC_DUMP_L1_ITAG = 9,
1297 QLCNIC_DUMP_L1_DATA = 11,
1298 QLCNIC_DUMP_L1_INST = 12,
1299 QLCNIC_DUMP_L2_DTAG = 21,
1300 QLCNIC_DUMP_L2_ITAG = 22,
1301 QLCNIC_DUMP_L2_DATA = 23,
1302 QLCNIC_DUMP_L2_INST = 24,
1303 QLCNIC_DUMP_READ_ROM = 71,
1304 QLCNIC_DUMP_READ_MEM = 72,
1305 QLCNIC_DUMP_READ_CTRL = 98,
1306 QLCNIC_DUMP_TLHDR = 99,
1307 QLCNIC_DUMP_RDEND = 255
1308 };
1309
1310 #define QLCNIC_DUMP_WCRB BIT_0
1311 #define QLCNIC_DUMP_RWCRB BIT_1
1312 #define QLCNIC_DUMP_ANDCRB BIT_2
1313 #define QLCNIC_DUMP_ORCRB BIT_3
1314 #define QLCNIC_DUMP_POLLCRB BIT_4
1315 #define QLCNIC_DUMP_RD_SAVE BIT_5
1316 #define QLCNIC_DUMP_WRT_SAVED BIT_6
1317 #define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
1318 #define QLCNIC_DUMP_SKIP BIT_7
1319
1320 #define QLCNIC_DUMP_MASK_MIN 3
1321 #define QLCNIC_DUMP_MASK_DEF 0x0f
1322 #define QLCNIC_DUMP_MASK_MAX 0xff
1323 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1324
1325 struct qlcnic_dump_operations {
1326 enum op_codes opcode;
1327 u32 (*handler)(struct qlcnic_adapter *,
1328 struct qlcnic_dump_entry *, u32 *);
1329 };
1330
1331 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1332 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1333
1334 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1335 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1336 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1337 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1338 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1339 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1340
1341 #define ADDR_IN_RANGE(addr, low, high) \
1342 (((addr) < (high)) && ((addr) >= (low)))
1343
1344 #define QLCRD32(adapter, off) \
1345 (qlcnic_hw_read_wx_2M(adapter, off))
1346 #define QLCWR32(adapter, off, val) \
1347 (qlcnic_hw_write_wx_2M(adapter, off, val))
1348
1349 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1350 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1351
1352 #define qlcnic_rom_lock(a) \
1353 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1354 #define qlcnic_rom_unlock(a) \
1355 qlcnic_pcie_sem_unlock((a), 2)
1356 #define qlcnic_phy_lock(a) \
1357 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1358 #define qlcnic_phy_unlock(a) \
1359 qlcnic_pcie_sem_unlock((a), 3)
1360 #define qlcnic_api_lock(a) \
1361 qlcnic_pcie_sem_lock((a), 5, 0)
1362 #define qlcnic_api_unlock(a) \
1363 qlcnic_pcie_sem_unlock((a), 5)
1364 #define qlcnic_sw_lock(a) \
1365 qlcnic_pcie_sem_lock((a), 6, 0)
1366 #define qlcnic_sw_unlock(a) \
1367 qlcnic_pcie_sem_unlock((a), 6)
1368 #define crb_win_lock(a) \
1369 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1370 #define crb_win_unlock(a) \
1371 qlcnic_pcie_sem_unlock((a), 7)
1372
1373 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1374 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1375 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1376 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1377 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1378 int qlcnic_dump_fw(struct qlcnic_adapter *);
1379
1380 /* Functions from qlcnic_init.c */
1381 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1382 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1383 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1384 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1385 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1386 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1387 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1388
1389 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1390 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1391 u8 *bytes, size_t size);
1392 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1393 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1394
1395 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1396
1397 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1398 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1399
1400 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1401 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1402
1403 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1404 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1405 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1406
1407 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1408 void qlcnic_watchdog_task(struct work_struct *work);
1409 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1410 struct qlcnic_host_rds_ring *rds_ring);
1411 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1412 void qlcnic_set_multi(struct net_device *netdev);
1413 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1414 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1415 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1416 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1417 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1418 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1419 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1420
1421 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1422 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1423 u32 qlcnic_fix_features(struct net_device *netdev, u32 features);
1424 int qlcnic_set_features(struct net_device *netdev, u32 features);
1425 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1426 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1427 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1428 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1429 struct qlcnic_host_tx_ring *tx_ring);
1430 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1431
1432 /* Functions from qlcnic_main.c */
1433 int qlcnic_reset_context(struct qlcnic_adapter *);
1434 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1435 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1436 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1437 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1438 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1439 int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val);
1440 int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data);
1441 void qlcnic_dev_request_reset(struct qlcnic_adapter *);
1442
1443 /* Management functions */
1444 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1445 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1446 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1447 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1448
1449 /* eSwitch management functions */
1450 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1451 struct qlcnic_esw_func_cfg *);
1452 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1453 struct qlcnic_esw_func_cfg *);
1454 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1455 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1456 struct __qlcnic_esw_statistics *);
1457 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1458 struct __qlcnic_esw_statistics *);
1459 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1460 extern int qlcnic_config_tso;
1461
1462 /*
1463 * QLOGIC Board information
1464 */
1465
1466 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1467 struct qlcnic_brdinfo {
1468 unsigned short vendor;
1469 unsigned short device;
1470 unsigned short sub_vendor;
1471 unsigned short sub_device;
1472 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1473 };
1474
1475 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1476 {0x1077, 0x8020, 0x1077, 0x203,
1477 "8200 Series Single Port 10GbE Converged Network Adapter "
1478 "(TCP/IP Networking)"},
1479 {0x1077, 0x8020, 0x1077, 0x207,
1480 "8200 Series Dual Port 10GbE Converged Network Adapter "
1481 "(TCP/IP Networking)"},
1482 {0x1077, 0x8020, 0x1077, 0x20b,
1483 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1484 {0x1077, 0x8020, 0x1077, 0x20c,
1485 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1486 {0x1077, 0x8020, 0x1077, 0x20f,
1487 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1488 {0x1077, 0x8020, 0x103c, 0x3733,
1489 "NC523SFP 10Gb 2-port Server Adapter"},
1490 {0x1077, 0x8020, 0x103c, 0x3346,
1491 "CN1000Q Dual Port Converged Network Adapter"},
1492 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1493 };
1494
1495 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1496
1497 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1498 {
1499 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1500 return tx_ring->sw_consumer - tx_ring->producer;
1501 else
1502 return tx_ring->sw_consumer + tx_ring->num_desc -
1503 tx_ring->producer;
1504 }
1505
1506 extern const struct ethtool_ops qlcnic_ethtool_ops;
1507
1508 struct qlcnic_nic_template {
1509 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1510 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1511 int (*start_firmware) (struct qlcnic_adapter *);
1512 };
1513
1514 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1515 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1516 printk(KERN_INFO "%s: %s: " _fmt, \
1517 dev_name(&adapter->pdev->dev), \
1518 __func__, ##_args); \
1519 } while (0)
1520
1521 #endif /* __QLCNIC_H_ */