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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / net / wireless / ath / ath9k / hw.c
blobb75b5dca4e2905dfc020846d1939a01ff47f3d57
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 if (!ah->curchan) /* should really check for CCK instead */
91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
96 else
97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
103 }
104
105 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
106 {
107 struct ath_common *common = ath9k_hw_common(ah);
108
109 return usecs * common->clockrate;
110 }
111
112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
113 {
114 int i;
115
116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
124
125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
128
129 return false;
130 }
131 EXPORT_SYMBOL(ath9k_hw_wait);
132
133 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
134 int column, unsigned int *writecnt)
135 {
136 int r;
137
138 ENABLE_REGWRITE_BUFFER(ah);
139 for (r = 0; r < array->ia_rows; r++) {
140 REG_WRITE(ah, INI_RA(array, r, 0),
141 INI_RA(array, r, column));
142 DO_DELAY(*writecnt);
143 }
144 REGWRITE_BUFFER_FLUSH(ah);
145 }
146
147 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
148 {
149 u32 retval;
150 int i;
151
152 for (i = 0, retval = 0; i < n; i++) {
153 retval = (retval << 1) | (val & 1);
154 val >>= 1;
155 }
156 return retval;
157 }
158
159 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
160 u8 phy, int kbps,
161 u32 frameLen, u16 rateix,
162 bool shortPreamble)
163 {
164 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
165
166 if (kbps == 0)
167 return 0;
168
169 switch (phy) {
170 case WLAN_RC_PHY_CCK:
171 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
172 if (shortPreamble)
173 phyTime >>= 1;
174 numBits = frameLen << 3;
175 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
176 break;
177 case WLAN_RC_PHY_OFDM:
178 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
179 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
180 numBits = OFDM_PLCP_BITS + (frameLen << 3);
181 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
182 txTime = OFDM_SIFS_TIME_QUARTER
183 + OFDM_PREAMBLE_TIME_QUARTER
184 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
185 } else if (ah->curchan &&
186 IS_CHAN_HALF_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_HALF +
191 OFDM_PREAMBLE_TIME_HALF
192 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
193 } else {
194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
195 numBits = OFDM_PLCP_BITS + (frameLen << 3);
196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
197 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
198 + (numSymbols * OFDM_SYMBOL_TIME);
199 }
200 break;
201 default:
202 ath_err(ath9k_hw_common(ah),
203 "Unknown phy %u (rate ix %u)\n", phy, rateix);
204 txTime = 0;
205 break;
206 }
207
208 return txTime;
209 }
210 EXPORT_SYMBOL(ath9k_hw_computetxtime);
211
212 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
213 struct ath9k_channel *chan,
214 struct chan_centers *centers)
215 {
216 int8_t extoff;
217
218 if (!IS_CHAN_HT40(chan)) {
219 centers->ctl_center = centers->ext_center =
220 centers->synth_center = chan->channel;
221 return;
222 }
223
224 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
225 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
226 centers->synth_center =
227 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
228 extoff = 1;
229 } else {
230 centers->synth_center =
231 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
232 extoff = -1;
233 }
234
235 centers->ctl_center =
236 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
237 /* 25 MHz spacing is supported by hw but not on upper layers */
238 centers->ext_center =
239 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
240 }
241
242 /******************/
243 /* Chip Revisions */
244 /******************/
245
246 static void ath9k_hw_read_revisions(struct ath_hw *ah)
247 {
248 u32 val;
249
250 switch (ah->hw_version.devid) {
251 case AR5416_AR9100_DEVID:
252 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
253 break;
254 case AR9300_DEVID_AR9340:
255 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
256 val = REG_READ(ah, AR_SREV);
257 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
258 return;
259 }
260
261 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
262
263 if (val == 0xFF) {
264 val = REG_READ(ah, AR_SREV);
265 ah->hw_version.macVersion =
266 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
267 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
268 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
269 } else {
270 if (!AR_SREV_9100(ah))
271 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
272
273 ah->hw_version.macRev = val & AR_SREV_REVISION;
274
275 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
276 ah->is_pciexpress = true;
277 }
278 }
279
280 /************************************/
281 /* HW Attach, Detach, Init Routines */
282 /************************************/
283
284 static void ath9k_hw_disablepcie(struct ath_hw *ah)
285 {
286 if (!AR_SREV_5416(ah))
287 return;
288
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
298
299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
300 }
301
302 /* This should work for all families including legacy */
303 static bool ath9k_hw_chip_test(struct ath_hw *ah)
304 {
305 struct ath_common *common = ath9k_hw_common(ah);
306 u32 regAddr[2] = { AR_STA_ID0 };
307 u32 regHold[2];
308 static const u32 patternData[4] = {
309 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
310 };
311 int i, j, loop_max;
312
313 if (!AR_SREV_9300_20_OR_LATER(ah)) {
314 loop_max = 2;
315 regAddr[1] = AR_PHY_BASE + (8 << 2);
316 } else
317 loop_max = 1;
318
319 for (i = 0; i < loop_max; i++) {
320 u32 addr = regAddr[i];
321 u32 wrData, rdData;
322
323 regHold[i] = REG_READ(ah, addr);
324 for (j = 0; j < 0x100; j++) {
325 wrData = (j << 16) | j;
326 REG_WRITE(ah, addr, wrData);
327 rdData = REG_READ(ah, addr);
328 if (rdData != wrData) {
329 ath_err(common,
330 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
331 addr, wrData, rdData);
332 return false;
333 }
334 }
335 for (j = 0; j < 4; j++) {
336 wrData = patternData[j];
337 REG_WRITE(ah, addr, wrData);
338 rdData = REG_READ(ah, addr);
339 if (wrData != rdData) {
340 ath_err(common,
341 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
342 addr, wrData, rdData);
343 return false;
344 }
345 }
346 REG_WRITE(ah, regAddr[i], regHold[i]);
347 }
348 udelay(100);
349
350 return true;
351 }
352
353 static void ath9k_hw_init_config(struct ath_hw *ah)
354 {
355 int i;
356
357 ah->config.dma_beacon_response_time = 2;
358 ah->config.sw_beacon_response_time = 10;
359 ah->config.additional_swba_backoff = 0;
360 ah->config.ack_6mb = 0x0;
361 ah->config.cwm_ignore_extcca = 0;
362 ah->config.pcie_powersave_enable = 0;
363 ah->config.pcie_clock_req = 0;
364 ah->config.pcie_waen = 0;
365 ah->config.analog_shiftreg = 1;
366 ah->config.enable_ani = true;
367
368 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
369 ah->config.spurchans[i][0] = AR_NO_SPUR;
370 ah->config.spurchans[i][1] = AR_NO_SPUR;
371 }
372
373 /* PAPRD needs some more work to be enabled */
374 ah->config.paprd_disable = 1;
375
376 ah->config.rx_intr_mitigation = true;
377 ah->config.pcieSerDesWrite = true;
378
379 /*
380 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
381 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
382 * This means we use it for all AR5416 devices, and the few
383 * minor PCI AR9280 devices out there.
384 *
385 * Serialization is required because these devices do not handle
386 * well the case of two concurrent reads/writes due to the latency
387 * involved. During one read/write another read/write can be issued
388 * on another CPU while the previous read/write may still be working
389 * on our hardware, if we hit this case the hardware poops in a loop.
390 * We prevent this by serializing reads and writes.
391 *
392 * This issue is not present on PCI-Express devices or pre-AR5416
393 * devices (legacy, 802.11abg).
394 */
395 if (num_possible_cpus() > 1)
396 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
397 }
398
399 static void ath9k_hw_init_defaults(struct ath_hw *ah)
400 {
401 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
402
403 regulatory->country_code = CTRY_DEFAULT;
404 regulatory->power_limit = MAX_RATE_POWER;
405 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
406
407 ah->hw_version.magic = AR5416_MAGIC;
408 ah->hw_version.subvendorid = 0;
409
410 ah->atim_window = 0;
411 ah->sta_id1_defaults =
412 AR_STA_ID1_CRPT_MIC_ENABLE |
413 AR_STA_ID1_MCAST_KSRCH;
414 if (AR_SREV_9100(ah))
415 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
416 ah->enable_32kHz_clock = DONT_USE_32KHZ;
417 ah->slottime = 20;
418 ah->globaltxtimeout = (u32) -1;
419 ah->power_mode = ATH9K_PM_UNDEFINED;
420 }
421
422 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
423 {
424 struct ath_common *common = ath9k_hw_common(ah);
425 u32 sum;
426 int i;
427 u16 eeval;
428 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
429
430 sum = 0;
431 for (i = 0; i < 3; i++) {
432 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
433 sum += eeval;
434 common->macaddr[2 * i] = eeval >> 8;
435 common->macaddr[2 * i + 1] = eeval & 0xff;
436 }
437 if (sum == 0 || sum == 0xffff * 3)
438 return -EADDRNOTAVAIL;
439
440 return 0;
441 }
442
443 static int ath9k_hw_post_init(struct ath_hw *ah)
444 {
445 struct ath_common *common = ath9k_hw_common(ah);
446 int ecode;
447
448 if (common->bus_ops->ath_bus_type != ATH_USB) {
449 if (!ath9k_hw_chip_test(ah))
450 return -ENODEV;
451 }
452
453 if (!AR_SREV_9300_20_OR_LATER(ah)) {
454 ecode = ar9002_hw_rf_claim(ah);
455 if (ecode != 0)
456 return ecode;
457 }
458
459 ecode = ath9k_hw_eeprom_init(ah);
460 if (ecode != 0)
461 return ecode;
462
463 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
464 "Eeprom VER: %d, REV: %d\n",
465 ah->eep_ops->get_eeprom_ver(ah),
466 ah->eep_ops->get_eeprom_rev(ah));
467
468 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
469 if (ecode) {
470 ath_err(ath9k_hw_common(ah),
471 "Failed allocating banks for external radio\n");
472 ath9k_hw_rf_free_ext_banks(ah);
473 return ecode;
474 }
475
476 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
477 ath9k_hw_ani_setup(ah);
478 ath9k_hw_ani_init(ah);
479 }
480
481 return 0;
482 }
483
484 static void ath9k_hw_attach_ops(struct ath_hw *ah)
485 {
486 if (AR_SREV_9300_20_OR_LATER(ah))
487 ar9003_hw_attach_ops(ah);
488 else
489 ar9002_hw_attach_ops(ah);
490 }
491
492 /* Called for all hardware families */
493 static int __ath9k_hw_init(struct ath_hw *ah)
494 {
495 struct ath_common *common = ath9k_hw_common(ah);
496 int r = 0;
497
498 ath9k_hw_read_revisions(ah);
499
500 /*
501 * Read back AR_WA into a permanent copy and set bits 14 and 17.
502 * We need to do this to avoid RMW of this register. We cannot
503 * read the reg when chip is asleep.
504 */
505 ah->WARegVal = REG_READ(ah, AR_WA);
506 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
507 AR_WA_ASPM_TIMER_BASED_DISABLE);
508
509 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
510 ath_err(common, "Couldn't reset chip\n");
511 return -EIO;
512 }
513
514 ath9k_hw_init_defaults(ah);
515 ath9k_hw_init_config(ah);
516
517 ath9k_hw_attach_ops(ah);
518
519 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
520 ath_err(common, "Couldn't wakeup chip\n");
521 return -EIO;
522 }
523
524 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
525 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
526 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
527 !ah->is_pciexpress)) {
528 ah->config.serialize_regmode =
529 SER_REG_MODE_ON;
530 } else {
531 ah->config.serialize_regmode =
532 SER_REG_MODE_OFF;
533 }
534 }
535
536 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
537 ah->config.serialize_regmode);
538
539 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
540 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
541 else
542 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
543
544 switch (ah->hw_version.macVersion) {
545 case AR_SREV_VERSION_5416_PCI:
546 case AR_SREV_VERSION_5416_PCIE:
547 case AR_SREV_VERSION_9160:
548 case AR_SREV_VERSION_9100:
549 case AR_SREV_VERSION_9280:
550 case AR_SREV_VERSION_9285:
551 case AR_SREV_VERSION_9287:
552 case AR_SREV_VERSION_9271:
553 case AR_SREV_VERSION_9300:
554 case AR_SREV_VERSION_9485:
555 case AR_SREV_VERSION_9340:
556 break;
557 default:
558 ath_err(common,
559 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
560 ah->hw_version.macVersion, ah->hw_version.macRev);
561 return -EOPNOTSUPP;
562 }
563
564 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah))
565 ah->is_pciexpress = false;
566
567 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
568 ath9k_hw_init_cal_settings(ah);
569
570 ah->ani_function = ATH9K_ANI_ALL;
571 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
572 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
573 if (!AR_SREV_9300_20_OR_LATER(ah))
574 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
575
576 ath9k_hw_init_mode_regs(ah);
577
578
579 if (ah->is_pciexpress)
580 ath9k_hw_configpcipowersave(ah, 0, 0);
581 else
582 ath9k_hw_disablepcie(ah);
583
584 if (!AR_SREV_9300_20_OR_LATER(ah))
585 ar9002_hw_cck_chan14_spread(ah);
586
587 r = ath9k_hw_post_init(ah);
588 if (r)
589 return r;
590
591 ath9k_hw_init_mode_gain_regs(ah);
592 r = ath9k_hw_fill_cap_info(ah);
593 if (r)
594 return r;
595
596 r = ath9k_hw_init_macaddr(ah);
597 if (r) {
598 ath_err(common, "Failed to initialize MAC address\n");
599 return r;
600 }
601
602 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
603 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
604 else
605 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
606
607 ah->bb_watchdog_timeout_ms = 25;
608
609 common->state = ATH_HW_INITIALIZED;
610
611 return 0;
612 }
613
614 int ath9k_hw_init(struct ath_hw *ah)
615 {
616 int ret;
617 struct ath_common *common = ath9k_hw_common(ah);
618
619 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
620 switch (ah->hw_version.devid) {
621 case AR5416_DEVID_PCI:
622 case AR5416_DEVID_PCIE:
623 case AR5416_AR9100_DEVID:
624 case AR9160_DEVID_PCI:
625 case AR9280_DEVID_PCI:
626 case AR9280_DEVID_PCIE:
627 case AR9285_DEVID_PCIE:
628 case AR9287_DEVID_PCI:
629 case AR9287_DEVID_PCIE:
630 case AR2427_DEVID_PCIE:
631 case AR9300_DEVID_PCIE:
632 case AR9300_DEVID_AR9485_PCIE:
633 case AR9300_DEVID_AR9340:
634 break;
635 default:
636 if (common->bus_ops->ath_bus_type == ATH_USB)
637 break;
638 ath_err(common, "Hardware device ID 0x%04x not supported\n",
639 ah->hw_version.devid);
640 return -EOPNOTSUPP;
641 }
642
643 ret = __ath9k_hw_init(ah);
644 if (ret) {
645 ath_err(common,
646 "Unable to initialize hardware; initialization status: %d\n",
647 ret);
648 return ret;
649 }
650
651 return 0;
652 }
653 EXPORT_SYMBOL(ath9k_hw_init);
654
655 static void ath9k_hw_init_qos(struct ath_hw *ah)
656 {
657 ENABLE_REGWRITE_BUFFER(ah);
658
659 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
660 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
661
662 REG_WRITE(ah, AR_QOS_NO_ACK,
663 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
664 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
665 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
666
667 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
668 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
670 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
671 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
672
673 REGWRITE_BUFFER_FLUSH(ah);
674 }
675
676 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
677 {
678 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
679 udelay(100);
680 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
681
682 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
683 udelay(100);
684
685 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
686 }
687 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
688
689 static void ath9k_hw_init_pll(struct ath_hw *ah,
690 struct ath9k_channel *chan)
691 {
692 u32 pll;
693
694 if (AR_SREV_9485(ah)) {
695
696 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
697 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
698 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
699 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
700 AR_CH0_DPLL2_KD, 0x40);
701 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
702 AR_CH0_DPLL2_KI, 0x4);
703
704 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
705 AR_CH0_BB_DPLL1_REFDIV, 0x5);
706 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
707 AR_CH0_BB_DPLL1_NINI, 0x58);
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
709 AR_CH0_BB_DPLL1_NFRAC, 0x0);
710
711 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
712 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
713 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
714 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
716 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
717
718 /* program BB PLL phase_shift to 0x6 */
719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
720 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
721
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
723 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
724 udelay(1000);
725 } else if (AR_SREV_9340(ah)) {
726 u32 regval, pll2_divint, pll2_divfrac, refdiv;
727
728 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
729 udelay(1000);
730
731 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
732 udelay(100);
733
734 if (ah->is_clk_25mhz) {
735 pll2_divint = 0x54;
736 pll2_divfrac = 0x1eb85;
737 refdiv = 3;
738 } else {
739 pll2_divint = 88;
740 pll2_divfrac = 0;
741 refdiv = 5;
742 }
743
744 regval = REG_READ(ah, AR_PHY_PLL_MODE);
745 regval |= (0x1 << 16);
746 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
747 udelay(100);
748
749 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
750 (pll2_divint << 18) | pll2_divfrac);
751 udelay(100);
752
753 regval = REG_READ(ah, AR_PHY_PLL_MODE);
754 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
755 (0x4 << 26) | (0x18 << 19);
756 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
757 REG_WRITE(ah, AR_PHY_PLL_MODE,
758 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
759 udelay(1000);
760 }
761
762 pll = ath9k_hw_compute_pll_control(ah, chan);
763
764 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
765
766 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
767 udelay(1000);
768
769 /* Switch the core clock for ar9271 to 117Mhz */
770 if (AR_SREV_9271(ah)) {
771 udelay(500);
772 REG_WRITE(ah, 0x50040, 0x304);
773 }
774
775 udelay(RTC_PLL_SETTLE_DELAY);
776
777 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
778
779 if (AR_SREV_9340(ah)) {
780 if (ah->is_clk_25mhz) {
781 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
782 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
783 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
784 } else {
785 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
786 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
787 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
788 }
789 udelay(100);
790 }
791 }
792
793 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
794 enum nl80211_iftype opmode)
795 {
796 u32 sync_default = AR_INTR_SYNC_DEFAULT;
797 u32 imr_reg = AR_IMR_TXERR |
798 AR_IMR_TXURN |
799 AR_IMR_RXERR |
800 AR_IMR_RXORN |
801 AR_IMR_BCNMISC;
802
803 if (AR_SREV_9340(ah))
804 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
805
806 if (AR_SREV_9300_20_OR_LATER(ah)) {
807 imr_reg |= AR_IMR_RXOK_HP;
808 if (ah->config.rx_intr_mitigation)
809 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
810 else
811 imr_reg |= AR_IMR_RXOK_LP;
812
813 } else {
814 if (ah->config.rx_intr_mitigation)
815 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
816 else
817 imr_reg |= AR_IMR_RXOK;
818 }
819
820 if (ah->config.tx_intr_mitigation)
821 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
822 else
823 imr_reg |= AR_IMR_TXOK;
824
825 if (opmode == NL80211_IFTYPE_AP)
826 imr_reg |= AR_IMR_MIB;
827
828 ENABLE_REGWRITE_BUFFER(ah);
829
830 REG_WRITE(ah, AR_IMR, imr_reg);
831 ah->imrs2_reg |= AR_IMR_S2_GTT;
832 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
833
834 if (!AR_SREV_9100(ah)) {
835 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
836 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
837 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
838 }
839
840 REGWRITE_BUFFER_FLUSH(ah);
841
842 if (AR_SREV_9300_20_OR_LATER(ah)) {
843 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
844 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
845 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
846 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
847 }
848 }
849
850 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
851 {
852 u32 val = ath9k_hw_mac_to_clks(ah, us);
853 val = min(val, (u32) 0xFFFF);
854 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
855 }
856
857 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
858 {
859 u32 val = ath9k_hw_mac_to_clks(ah, us);
860 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
861 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
862 }
863
864 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
865 {
866 u32 val = ath9k_hw_mac_to_clks(ah, us);
867 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
868 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
869 }
870
871 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
872 {
873 if (tu > 0xFFFF) {
874 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
875 "bad global tx timeout %u\n", tu);
876 ah->globaltxtimeout = (u32) -1;
877 return false;
878 } else {
879 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
880 ah->globaltxtimeout = tu;
881 return true;
882 }
883 }
884
885 void ath9k_hw_init_global_settings(struct ath_hw *ah)
886 {
887 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
888 int acktimeout;
889 int slottime;
890 int sifstime;
891
892 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
893 ah->misc_mode);
894
895 if (ah->misc_mode != 0)
896 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
897
898 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
899 sifstime = 16;
900 else
901 sifstime = 10;
902
903 /* As defined by IEEE 802.11-2007 17.3.8.6 */
904 slottime = ah->slottime + 3 * ah->coverage_class;
905 acktimeout = slottime + sifstime;
906
907 /*
908 * Workaround for early ACK timeouts, add an offset to match the
909 * initval's 64us ack timeout value.
910 * This was initially only meant to work around an issue with delayed
911 * BA frames in some implementations, but it has been found to fix ACK
912 * timeout issues in other cases as well.
913 */
914 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
915 acktimeout += 64 - sifstime - ah->slottime;
916
917 ath9k_hw_setslottime(ah, ah->slottime);
918 ath9k_hw_set_ack_timeout(ah, acktimeout);
919 ath9k_hw_set_cts_timeout(ah, acktimeout);
920 if (ah->globaltxtimeout != (u32) -1)
921 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
922 }
923 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
924
925 void ath9k_hw_deinit(struct ath_hw *ah)
926 {
927 struct ath_common *common = ath9k_hw_common(ah);
928
929 if (common->state < ATH_HW_INITIALIZED)
930 goto free_hw;
931
932 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
933
934 free_hw:
935 ath9k_hw_rf_free_ext_banks(ah);
936 }
937 EXPORT_SYMBOL(ath9k_hw_deinit);
938
939 /*******/
940 /* INI */
941 /*******/
942
943 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
944 {
945 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
946
947 if (IS_CHAN_B(chan))
948 ctl |= CTL_11B;
949 else if (IS_CHAN_G(chan))
950 ctl |= CTL_11G;
951 else
952 ctl |= CTL_11A;
953
954 return ctl;
955 }
956
957 /****************************************/
958 /* Reset and Channel Switching Routines */
959 /****************************************/
960
961 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
962 {
963 struct ath_common *common = ath9k_hw_common(ah);
964
965 ENABLE_REGWRITE_BUFFER(ah);
966
967 /*
968 * set AHB_MODE not to do cacheline prefetches
969 */
970 if (!AR_SREV_9300_20_OR_LATER(ah))
971 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
972
973 /*
974 * let mac dma reads be in 128 byte chunks
975 */
976 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
977
978 REGWRITE_BUFFER_FLUSH(ah);
979
980 /*
981 * Restore TX Trigger Level to its pre-reset value.
982 * The initial value depends on whether aggregation is enabled, and is
983 * adjusted whenever underruns are detected.
984 */
985 if (!AR_SREV_9300_20_OR_LATER(ah))
986 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
987
988 ENABLE_REGWRITE_BUFFER(ah);
989
990 /*
991 * let mac dma writes be in 128 byte chunks
992 */
993 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
994
995 /*
996 * Setup receive FIFO threshold to hold off TX activities
997 */
998 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
999
1000 if (AR_SREV_9300_20_OR_LATER(ah)) {
1001 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1002 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1003
1004 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1005 ah->caps.rx_status_len);
1006 }
1007
1008 /*
1009 * reduce the number of usable entries in PCU TXBUF to avoid
1010 * wrap around issues.
1011 */
1012 if (AR_SREV_9285(ah)) {
1013 /* For AR9285 the number of Fifos are reduced to half.
1014 * So set the usable tx buf size also to half to
1015 * avoid data/delimiter underruns
1016 */
1017 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1018 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1019 } else if (!AR_SREV_9271(ah)) {
1020 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1021 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1022 }
1023
1024 REGWRITE_BUFFER_FLUSH(ah);
1025
1026 if (AR_SREV_9300_20_OR_LATER(ah))
1027 ath9k_hw_reset_txstatus_ring(ah);
1028 }
1029
1030 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1031 {
1032 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1033 u32 set = AR_STA_ID1_KSRCH_MODE;
1034
1035 switch (opmode) {
1036 case NL80211_IFTYPE_ADHOC:
1037 case NL80211_IFTYPE_MESH_POINT:
1038 set |= AR_STA_ID1_ADHOC;
1039 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1040 break;
1041 case NL80211_IFTYPE_AP:
1042 set |= AR_STA_ID1_STA_AP;
1043 /* fall through */
1044 case NL80211_IFTYPE_STATION:
1045 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1046 break;
1047 default:
1048 if (!ah->is_monitoring)
1049 set = 0;
1050 break;
1051 }
1052 REG_RMW(ah, AR_STA_ID1, set, mask);
1053 }
1054
1055 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1056 u32 *coef_mantissa, u32 *coef_exponent)
1057 {
1058 u32 coef_exp, coef_man;
1059
1060 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1061 if ((coef_scaled >> coef_exp) & 0x1)
1062 break;
1063
1064 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1065
1066 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1067
1068 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1069 *coef_exponent = coef_exp - 16;
1070 }
1071
1072 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1073 {
1074 u32 rst_flags;
1075 u32 tmpReg;
1076
1077 if (AR_SREV_9100(ah)) {
1078 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1079 AR_RTC_DERIVED_CLK_PERIOD, 1);
1080 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1081 }
1082
1083 ENABLE_REGWRITE_BUFFER(ah);
1084
1085 if (AR_SREV_9300_20_OR_LATER(ah)) {
1086 REG_WRITE(ah, AR_WA, ah->WARegVal);
1087 udelay(10);
1088 }
1089
1090 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1091 AR_RTC_FORCE_WAKE_ON_INT);
1092
1093 if (AR_SREV_9100(ah)) {
1094 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1095 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1096 } else {
1097 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1098 if (tmpReg &
1099 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1100 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1101 u32 val;
1102 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1103
1104 val = AR_RC_HOSTIF;
1105 if (!AR_SREV_9300_20_OR_LATER(ah))
1106 val |= AR_RC_AHB;
1107 REG_WRITE(ah, AR_RC, val);
1108
1109 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1110 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1111
1112 rst_flags = AR_RTC_RC_MAC_WARM;
1113 if (type == ATH9K_RESET_COLD)
1114 rst_flags |= AR_RTC_RC_MAC_COLD;
1115 }
1116
1117 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1118
1119 REGWRITE_BUFFER_FLUSH(ah);
1120
1121 udelay(50);
1122
1123 REG_WRITE(ah, AR_RTC_RC, 0);
1124 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1126 "RTC stuck in MAC reset\n");
1127 return false;
1128 }
1129
1130 if (!AR_SREV_9100(ah))
1131 REG_WRITE(ah, AR_RC, 0);
1132
1133 if (AR_SREV_9100(ah))
1134 udelay(50);
1135
1136 return true;
1137 }
1138
1139 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1140 {
1141 ENABLE_REGWRITE_BUFFER(ah);
1142
1143 if (AR_SREV_9300_20_OR_LATER(ah)) {
1144 REG_WRITE(ah, AR_WA, ah->WARegVal);
1145 udelay(10);
1146 }
1147
1148 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1149 AR_RTC_FORCE_WAKE_ON_INT);
1150
1151 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1152 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1153
1154 REG_WRITE(ah, AR_RTC_RESET, 0);
1155
1156 REGWRITE_BUFFER_FLUSH(ah);
1157
1158 if (!AR_SREV_9300_20_OR_LATER(ah))
1159 udelay(2);
1160
1161 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1162 REG_WRITE(ah, AR_RC, 0);
1163
1164 REG_WRITE(ah, AR_RTC_RESET, 1);
1165
1166 if (!ath9k_hw_wait(ah,
1167 AR_RTC_STATUS,
1168 AR_RTC_STATUS_M,
1169 AR_RTC_STATUS_ON,
1170 AH_WAIT_TIMEOUT)) {
1171 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1172 "RTC not waking up\n");
1173 return false;
1174 }
1175
1176 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1177 }
1178
1179 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1180 {
1181 if (AR_SREV_9300_20_OR_LATER(ah)) {
1182 REG_WRITE(ah, AR_WA, ah->WARegVal);
1183 udelay(10);
1184 }
1185
1186 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1187 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1188
1189 switch (type) {
1190 case ATH9K_RESET_POWER_ON:
1191 return ath9k_hw_set_reset_power_on(ah);
1192 case ATH9K_RESET_WARM:
1193 case ATH9K_RESET_COLD:
1194 return ath9k_hw_set_reset(ah, type);
1195 default:
1196 return false;
1197 }
1198 }
1199
1200 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1201 struct ath9k_channel *chan)
1202 {
1203 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1204 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1205 return false;
1206 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1207 return false;
1208
1209 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1210 return false;
1211
1212 ah->chip_fullsleep = false;
1213 ath9k_hw_init_pll(ah, chan);
1214 ath9k_hw_set_rfmode(ah, chan);
1215
1216 return true;
1217 }
1218
1219 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1220 struct ath9k_channel *chan)
1221 {
1222 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1223 struct ath_common *common = ath9k_hw_common(ah);
1224 struct ieee80211_channel *channel = chan->chan;
1225 u32 qnum;
1226 int r;
1227
1228 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1229 if (ath9k_hw_numtxpending(ah, qnum)) {
1230 ath_dbg(common, ATH_DBG_QUEUE,
1231 "Transmit frames pending on queue %d\n", qnum);
1232 return false;
1233 }
1234 }
1235
1236 if (!ath9k_hw_rfbus_req(ah)) {
1237 ath_err(common, "Could not kill baseband RX\n");
1238 return false;
1239 }
1240
1241 ath9k_hw_set_channel_regs(ah, chan);
1242
1243 r = ath9k_hw_rf_set_freq(ah, chan);
1244 if (r) {
1245 ath_err(common, "Failed to set channel\n");
1246 return false;
1247 }
1248 ath9k_hw_set_clockrate(ah);
1249
1250 ah->eep_ops->set_txpower(ah, chan,
1251 ath9k_regd_get_ctl(regulatory, chan),
1252 channel->max_antenna_gain * 2,
1253 channel->max_power * 2,
1254 min((u32) MAX_RATE_POWER,
1255 (u32) regulatory->power_limit), false);
1256
1257 ath9k_hw_rfbus_done(ah);
1258
1259 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1260 ath9k_hw_set_delta_slope(ah, chan);
1261
1262 ath9k_hw_spur_mitigate_freq(ah, chan);
1263
1264 return true;
1265 }
1266
1267 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1268 {
1269 u32 gpio_mask = ah->gpio_mask;
1270 int i;
1271
1272 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1273 if (!(gpio_mask & 1))
1274 continue;
1275
1276 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1277 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1278 }
1279 }
1280
1281 bool ath9k_hw_check_alive(struct ath_hw *ah)
1282 {
1283 int count = 50;
1284 u32 reg;
1285
1286 if (AR_SREV_9285_12_OR_LATER(ah))
1287 return true;
1288
1289 do {
1290 reg = REG_READ(ah, AR_OBS_BUS_1);
1291
1292 if ((reg & 0x7E7FFFEF) == 0x00702400)
1293 continue;
1294
1295 switch (reg & 0x7E000B00) {
1296 case 0x1E000000:
1297 case 0x52000B00:
1298 case 0x18000B00:
1299 continue;
1300 default:
1301 return true;
1302 }
1303 } while (count-- > 0);
1304
1305 return false;
1306 }
1307 EXPORT_SYMBOL(ath9k_hw_check_alive);
1308
1309 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1310 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1311 {
1312 struct ath_common *common = ath9k_hw_common(ah);
1313 u32 saveLedState;
1314 struct ath9k_channel *curchan = ah->curchan;
1315 u32 saveDefAntenna;
1316 u32 macStaId1;
1317 u64 tsf = 0;
1318 int i, r;
1319
1320 ah->txchainmask = common->tx_chainmask;
1321 ah->rxchainmask = common->rx_chainmask;
1322
1323 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1324 return -EIO;
1325
1326 if (curchan && !ah->chip_fullsleep)
1327 ath9k_hw_getnf(ah, curchan);
1328
1329 ah->caldata = caldata;
1330 if (caldata &&
1331 (chan->channel != caldata->channel ||
1332 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1333 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1334 /* Operating channel changed, reset channel calibration data */
1335 memset(caldata, 0, sizeof(*caldata));
1336 ath9k_init_nfcal_hist_buffer(ah, chan);
1337 }
1338
1339 if (bChannelChange &&
1340 (ah->chip_fullsleep != true) &&
1341 (ah->curchan != NULL) &&
1342 (chan->channel != ah->curchan->channel) &&
1343 ((chan->channelFlags & CHANNEL_ALL) ==
1344 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1345 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1346
1347 if (ath9k_hw_channel_change(ah, chan)) {
1348 ath9k_hw_loadnf(ah, ah->curchan);
1349 ath9k_hw_start_nfcal(ah, true);
1350 if (AR_SREV_9271(ah))
1351 ar9002_hw_load_ani_reg(ah, chan);
1352 return 0;
1353 }
1354 }
1355
1356 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1357 if (saveDefAntenna == 0)
1358 saveDefAntenna = 1;
1359
1360 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1361
1362 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1363 if (AR_SREV_9100(ah) ||
1364 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1365 tsf = ath9k_hw_gettsf64(ah);
1366
1367 saveLedState = REG_READ(ah, AR_CFG_LED) &
1368 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1369 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1370
1371 ath9k_hw_mark_phy_inactive(ah);
1372
1373 ah->paprd_table_write_done = false;
1374
1375 /* Only required on the first reset */
1376 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1377 REG_WRITE(ah,
1378 AR9271_RESET_POWER_DOWN_CONTROL,
1379 AR9271_RADIO_RF_RST);
1380 udelay(50);
1381 }
1382
1383 if (!ath9k_hw_chip_reset(ah, chan)) {
1384 ath_err(common, "Chip reset failed\n");
1385 return -EINVAL;
1386 }
1387
1388 /* Only required on the first reset */
1389 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1390 ah->htc_reset_init = false;
1391 REG_WRITE(ah,
1392 AR9271_RESET_POWER_DOWN_CONTROL,
1393 AR9271_GATE_MAC_CTL);
1394 udelay(50);
1395 }
1396
1397 /* Restore TSF */
1398 if (tsf)
1399 ath9k_hw_settsf64(ah, tsf);
1400
1401 if (AR_SREV_9280_20_OR_LATER(ah))
1402 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1403
1404 if (!AR_SREV_9300_20_OR_LATER(ah))
1405 ar9002_hw_enable_async_fifo(ah);
1406
1407 r = ath9k_hw_process_ini(ah, chan);
1408 if (r)
1409 return r;
1410
1411 /*
1412 * Some AR91xx SoC devices frequently fail to accept TSF writes
1413 * right after the chip reset. When that happens, write a new
1414 * value after the initvals have been applied, with an offset
1415 * based on measured time difference
1416 */
1417 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1418 tsf += 1500;
1419 ath9k_hw_settsf64(ah, tsf);
1420 }
1421
1422 /* Setup MFP options for CCMP */
1423 if (AR_SREV_9280_20_OR_LATER(ah)) {
1424 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1425 * frames when constructing CCMP AAD. */
1426 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1427 0xc7ff);
1428 ah->sw_mgmt_crypto = false;
1429 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1430 /* Disable hardware crypto for management frames */
1431 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1432 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1433 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1434 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1435 ah->sw_mgmt_crypto = true;
1436 } else
1437 ah->sw_mgmt_crypto = true;
1438
1439 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1440 ath9k_hw_set_delta_slope(ah, chan);
1441
1442 ath9k_hw_spur_mitigate_freq(ah, chan);
1443 ah->eep_ops->set_board_values(ah, chan);
1444
1445 ENABLE_REGWRITE_BUFFER(ah);
1446
1447 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1448 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1449 | macStaId1
1450 | AR_STA_ID1_RTS_USE_DEF
1451 | (ah->config.
1452 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1453 | ah->sta_id1_defaults);
1454 ath_hw_setbssidmask(common);
1455 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1456 ath9k_hw_write_associd(ah);
1457 REG_WRITE(ah, AR_ISR, ~0);
1458 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1459
1460 REGWRITE_BUFFER_FLUSH(ah);
1461
1462 ath9k_hw_set_operating_mode(ah, ah->opmode);
1463
1464 r = ath9k_hw_rf_set_freq(ah, chan);
1465 if (r)
1466 return r;
1467
1468 ath9k_hw_set_clockrate(ah);
1469
1470 ENABLE_REGWRITE_BUFFER(ah);
1471
1472 for (i = 0; i < AR_NUM_DCU; i++)
1473 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1474
1475 REGWRITE_BUFFER_FLUSH(ah);
1476
1477 ah->intr_txqs = 0;
1478 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1479 ath9k_hw_resettxqueue(ah, i);
1480
1481 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1482 ath9k_hw_ani_cache_ini_regs(ah);
1483 ath9k_hw_init_qos(ah);
1484
1485 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1486 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1487
1488 ath9k_hw_init_global_settings(ah);
1489
1490 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1491 ar9002_hw_update_async_fifo(ah);
1492 ar9002_hw_enable_wep_aggregation(ah);
1493 }
1494
1495 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1496
1497 ath9k_hw_set_dma(ah);
1498
1499 REG_WRITE(ah, AR_OBS, 8);
1500
1501 if (ah->config.rx_intr_mitigation) {
1502 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1503 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1504 }
1505
1506 if (ah->config.tx_intr_mitigation) {
1507 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1508 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1509 }
1510
1511 ath9k_hw_init_bb(ah, chan);
1512
1513 if (!ath9k_hw_init_cal(ah, chan))
1514 return -EIO;
1515
1516 ENABLE_REGWRITE_BUFFER(ah);
1517
1518 ath9k_hw_restore_chainmask(ah);
1519 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1520
1521 REGWRITE_BUFFER_FLUSH(ah);
1522
1523 /*
1524 * For big endian systems turn on swapping for descriptors
1525 */
1526 if (AR_SREV_9100(ah)) {
1527 u32 mask;
1528 mask = REG_READ(ah, AR_CFG);
1529 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1530 ath_dbg(common, ATH_DBG_RESET,
1531 "CFG Byte Swap Set 0x%x\n", mask);
1532 } else {
1533 mask =
1534 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1535 REG_WRITE(ah, AR_CFG, mask);
1536 ath_dbg(common, ATH_DBG_RESET,
1537 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1538 }
1539 } else {
1540 if (common->bus_ops->ath_bus_type == ATH_USB) {
1541 /* Configure AR9271 target WLAN */
1542 if (AR_SREV_9271(ah))
1543 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1544 else
1545 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1546 }
1547 #ifdef __BIG_ENDIAN
1548 else if (AR_SREV_9340(ah))
1549 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1550 else
1551 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1552 #endif
1553 }
1554
1555 if (ah->btcoex_hw.enabled)
1556 ath9k_hw_btcoex_enable(ah);
1557
1558 if (AR_SREV_9300_20_OR_LATER(ah))
1559 ar9003_hw_bb_watchdog_config(ah);
1560
1561 ath9k_hw_apply_gpio_override(ah);
1562
1563 return 0;
1564 }
1565 EXPORT_SYMBOL(ath9k_hw_reset);
1566
1567 /******************************/
1568 /* Power Management (Chipset) */
1569 /******************************/
1570
1571 /*
1572 * Notify Power Mgt is disabled in self-generated frames.
1573 * If requested, force chip to sleep.
1574 */
1575 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1576 {
1577 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1578 if (setChip) {
1579 /*
1580 * Clear the RTC force wake bit to allow the
1581 * mac to go to sleep.
1582 */
1583 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1584 AR_RTC_FORCE_WAKE_EN);
1585 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1586 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1587
1588 /* Shutdown chip. Active low */
1589 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1590 REG_CLR_BIT(ah, (AR_RTC_RESET),
1591 AR_RTC_RESET_EN);
1592 }
1593
1594 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1595 if (AR_SREV_9300_20_OR_LATER(ah))
1596 REG_WRITE(ah, AR_WA,
1597 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1598 }
1599
1600 /*
1601 * Notify Power Management is enabled in self-generating
1602 * frames. If request, set power mode of chip to
1603 * auto/normal. Duration in units of 128us (1/8 TU).
1604 */
1605 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1606 {
1607 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1608 if (setChip) {
1609 struct ath9k_hw_capabilities *pCap = &ah->caps;
1610
1611 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1612 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1613 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1614 AR_RTC_FORCE_WAKE_ON_INT);
1615 } else {
1616 /*
1617 * Clear the RTC force wake bit to allow the
1618 * mac to go to sleep.
1619 */
1620 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1621 AR_RTC_FORCE_WAKE_EN);
1622 }
1623 }
1624
1625 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1626 if (AR_SREV_9300_20_OR_LATER(ah))
1627 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1628 }
1629
1630 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1631 {
1632 u32 val;
1633 int i;
1634
1635 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1636 if (AR_SREV_9300_20_OR_LATER(ah)) {
1637 REG_WRITE(ah, AR_WA, ah->WARegVal);
1638 udelay(10);
1639 }
1640
1641 if (setChip) {
1642 if ((REG_READ(ah, AR_RTC_STATUS) &
1643 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1644 if (ath9k_hw_set_reset_reg(ah,
1645 ATH9K_RESET_POWER_ON) != true) {
1646 return false;
1647 }
1648 if (!AR_SREV_9300_20_OR_LATER(ah))
1649 ath9k_hw_init_pll(ah, NULL);
1650 }
1651 if (AR_SREV_9100(ah))
1652 REG_SET_BIT(ah, AR_RTC_RESET,
1653 AR_RTC_RESET_EN);
1654
1655 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1656 AR_RTC_FORCE_WAKE_EN);
1657 udelay(50);
1658
1659 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1660 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1661 if (val == AR_RTC_STATUS_ON)
1662 break;
1663 udelay(50);
1664 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1665 AR_RTC_FORCE_WAKE_EN);
1666 }
1667 if (i == 0) {
1668 ath_err(ath9k_hw_common(ah),
1669 "Failed to wakeup in %uus\n",
1670 POWER_UP_TIME / 20);
1671 return false;
1672 }
1673 }
1674
1675 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1676
1677 return true;
1678 }
1679
1680 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1681 {
1682 struct ath_common *common = ath9k_hw_common(ah);
1683 int status = true, setChip = true;
1684 static const char *modes[] = {
1685 "AWAKE",
1686 "FULL-SLEEP",
1687 "NETWORK SLEEP",
1688 "UNDEFINED"
1689 };
1690
1691 if (ah->power_mode == mode)
1692 return status;
1693
1694 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1695 modes[ah->power_mode], modes[mode]);
1696
1697 switch (mode) {
1698 case ATH9K_PM_AWAKE:
1699 status = ath9k_hw_set_power_awake(ah, setChip);
1700 break;
1701 case ATH9K_PM_FULL_SLEEP:
1702 ath9k_set_power_sleep(ah, setChip);
1703 ah->chip_fullsleep = true;
1704 break;
1705 case ATH9K_PM_NETWORK_SLEEP:
1706 ath9k_set_power_network_sleep(ah, setChip);
1707 break;
1708 default:
1709 ath_err(common, "Unknown power mode %u\n", mode);
1710 return false;
1711 }
1712 ah->power_mode = mode;
1713
1714 /*
1715 * XXX: If this warning never comes up after a while then
1716 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1717 * ath9k_hw_setpower() return type void.
1718 */
1719
1720 if (!(ah->ah_flags & AH_UNPLUGGED))
1721 ATH_DBG_WARN_ON_ONCE(!status);
1722
1723 return status;
1724 }
1725 EXPORT_SYMBOL(ath9k_hw_setpower);
1726
1727 /*******************/
1728 /* Beacon Handling */
1729 /*******************/
1730
1731 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1732 {
1733 int flags = 0;
1734
1735 ENABLE_REGWRITE_BUFFER(ah);
1736
1737 switch (ah->opmode) {
1738 case NL80211_IFTYPE_ADHOC:
1739 case NL80211_IFTYPE_MESH_POINT:
1740 REG_SET_BIT(ah, AR_TXCFG,
1741 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1742 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1743 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1744 flags |= AR_NDP_TIMER_EN;
1745 case NL80211_IFTYPE_AP:
1746 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1747 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1748 TU_TO_USEC(ah->config.dma_beacon_response_time));
1749 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1750 TU_TO_USEC(ah->config.sw_beacon_response_time));
1751 flags |=
1752 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1753 break;
1754 default:
1755 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1756 "%s: unsupported opmode: %d\n",
1757 __func__, ah->opmode);
1758 return;
1759 break;
1760 }
1761
1762 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1763 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1764 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1765 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1766
1767 REGWRITE_BUFFER_FLUSH(ah);
1768
1769 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1770 }
1771 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1772
1773 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1774 const struct ath9k_beacon_state *bs)
1775 {
1776 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1777 struct ath9k_hw_capabilities *pCap = &ah->caps;
1778 struct ath_common *common = ath9k_hw_common(ah);
1779
1780 ENABLE_REGWRITE_BUFFER(ah);
1781
1782 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1783
1784 REG_WRITE(ah, AR_BEACON_PERIOD,
1785 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1786 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1787 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1788
1789 REGWRITE_BUFFER_FLUSH(ah);
1790
1791 REG_RMW_FIELD(ah, AR_RSSI_THR,
1792 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1793
1794 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1795
1796 if (bs->bs_sleepduration > beaconintval)
1797 beaconintval = bs->bs_sleepduration;
1798
1799 dtimperiod = bs->bs_dtimperiod;
1800 if (bs->bs_sleepduration > dtimperiod)
1801 dtimperiod = bs->bs_sleepduration;
1802
1803 if (beaconintval == dtimperiod)
1804 nextTbtt = bs->bs_nextdtim;
1805 else
1806 nextTbtt = bs->bs_nexttbtt;
1807
1808 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1809 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1810 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1811 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1812
1813 ENABLE_REGWRITE_BUFFER(ah);
1814
1815 REG_WRITE(ah, AR_NEXT_DTIM,
1816 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1817 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1818
1819 REG_WRITE(ah, AR_SLEEP1,
1820 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1821 | AR_SLEEP1_ASSUME_DTIM);
1822
1823 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1824 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1825 else
1826 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1827
1828 REG_WRITE(ah, AR_SLEEP2,
1829 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1830
1831 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1832 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1833
1834 REGWRITE_BUFFER_FLUSH(ah);
1835
1836 REG_SET_BIT(ah, AR_TIMER_MODE,
1837 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1838 AR_DTIM_TIMER_EN);
1839
1840 /* TSF Out of Range Threshold */
1841 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1842 }
1843 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1844
1845 /*******************/
1846 /* HW Capabilities */
1847 /*******************/
1848
1849 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1850 {
1851 struct ath9k_hw_capabilities *pCap = &ah->caps;
1852 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1853 struct ath_common *common = ath9k_hw_common(ah);
1854 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1855
1856 u16 eeval;
1857 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1858
1859 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1860 regulatory->current_rd = eeval;
1861
1862 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1863 if (AR_SREV_9285_12_OR_LATER(ah))
1864 eeval |= AR9285_RDEXT_DEFAULT;
1865 regulatory->current_rd_ext = eeval;
1866
1867 if (ah->opmode != NL80211_IFTYPE_AP &&
1868 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1869 if (regulatory->current_rd == 0x64 ||
1870 regulatory->current_rd == 0x65)
1871 regulatory->current_rd += 5;
1872 else if (regulatory->current_rd == 0x41)
1873 regulatory->current_rd = 0x43;
1874 ath_dbg(common, ATH_DBG_REGULATORY,
1875 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1876 }
1877
1878 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1879 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1880 ath_err(common,
1881 "no band has been marked as supported in EEPROM\n");
1882 return -EINVAL;
1883 }
1884
1885 if (eeval & AR5416_OPFLAGS_11A)
1886 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1887
1888 if (eeval & AR5416_OPFLAGS_11G)
1889 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1890
1891 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1892 /*
1893 * For AR9271 we will temporarilly uses the rx chainmax as read from
1894 * the EEPROM.
1895 */
1896 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1897 !(eeval & AR5416_OPFLAGS_11A) &&
1898 !(AR_SREV_9271(ah)))
1899 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1900 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1901 else if (AR_SREV_9100(ah))
1902 pCap->rx_chainmask = 0x7;
1903 else
1904 /* Use rx_chainmask from EEPROM. */
1905 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1906
1907 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1908
1909 /* enable key search for every frame in an aggregate */
1910 if (AR_SREV_9300_20_OR_LATER(ah))
1911 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1912
1913 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1914
1915 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
1916 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1917 else
1918 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1919
1920 if (AR_SREV_9271(ah))
1921 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1922 else if (AR_DEVID_7010(ah))
1923 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1924 else if (AR_SREV_9285_12_OR_LATER(ah))
1925 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1926 else if (AR_SREV_9280_20_OR_LATER(ah))
1927 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1928 else
1929 pCap->num_gpio_pins = AR_NUM_GPIO;
1930
1931 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1932 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1933 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1934 } else {
1935 pCap->rts_aggr_limit = (8 * 1024);
1936 }
1937
1938 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1939 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1940 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1941 ah->rfkill_gpio =
1942 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1943 ah->rfkill_polarity =
1944 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1945
1946 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1947 }
1948 #endif
1949 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1950 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1951 else
1952 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1953
1954 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1955 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1956 else
1957 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1958
1959 if (common->btcoex_enabled) {
1960 if (AR_SREV_9300_20_OR_LATER(ah)) {
1961 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1962 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
1963 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
1964 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
1965 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1966 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
1967 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
1968
1969 if (AR_SREV_9285(ah)) {
1970 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1971 btcoex_hw->btpriority_gpio =
1972 ATH_BTPRIORITY_GPIO_9285;
1973 } else {
1974 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1975 }
1976 }
1977 } else {
1978 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1979 }
1980
1981 if (AR_SREV_9300_20_OR_LATER(ah)) {
1982 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1983 if (!AR_SREV_9485(ah))
1984 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1985
1986 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1987 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1988 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1989 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1990 pCap->txs_len = sizeof(struct ar9003_txs);
1991 if (!ah->config.paprd_disable &&
1992 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1993 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1994 } else {
1995 pCap->tx_desc_len = sizeof(struct ath_desc);
1996 if (AR_SREV_9280_20(ah) &&
1997 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1998 AR5416_EEP_MINOR_VER_16) ||
1999 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2000 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2001 }
2002
2003 if (AR_SREV_9300_20_OR_LATER(ah))
2004 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2005
2006 if (AR_SREV_9300_20_OR_LATER(ah))
2007 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2008
2009 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2010 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2011
2012 if (AR_SREV_9285(ah))
2013 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2014 ant_div_ctl1 =
2015 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2016 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2017 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2018 }
2019 if (AR_SREV_9300_20_OR_LATER(ah)) {
2020 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2021 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2022 }
2023
2024
2025 if (AR_SREV_9485(ah)) {
2026 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2027 /*
2028 * enable the diversity-combining algorithm only when
2029 * both enable_lna_div and enable_fast_div are set
2030 * Table for Diversity
2031 * ant_div_alt_lnaconf bit 0-1
2032 * ant_div_main_lnaconf bit 2-3
2033 * ant_div_alt_gaintb bit 4
2034 * ant_div_main_gaintb bit 5
2035 * enable_ant_div_lnadiv bit 6
2036 * enable_ant_fast_div bit 7
2037 */
2038 if ((ant_div_ctl1 >> 0x6) == 0x3)
2039 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2040 }
2041
2042 if (AR_SREV_9485_10(ah)) {
2043 pCap->pcie_lcr_extsync_en = true;
2044 pCap->pcie_lcr_offset = 0x80;
2045 }
2046
2047 tx_chainmask = pCap->tx_chainmask;
2048 rx_chainmask = pCap->rx_chainmask;
2049 while (tx_chainmask || rx_chainmask) {
2050 if (tx_chainmask & BIT(0))
2051 pCap->max_txchains++;
2052 if (rx_chainmask & BIT(0))
2053 pCap->max_rxchains++;
2054
2055 tx_chainmask >>= 1;
2056 rx_chainmask >>= 1;
2057 }
2058
2059 return 0;
2060 }
2061
2062 /****************************/
2063 /* GPIO / RFKILL / Antennae */
2064 /****************************/
2065
2066 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2067 u32 gpio, u32 type)
2068 {
2069 int addr;
2070 u32 gpio_shift, tmp;
2071
2072 if (gpio > 11)
2073 addr = AR_GPIO_OUTPUT_MUX3;
2074 else if (gpio > 5)
2075 addr = AR_GPIO_OUTPUT_MUX2;
2076 else
2077 addr = AR_GPIO_OUTPUT_MUX1;
2078
2079 gpio_shift = (gpio % 6) * 5;
2080
2081 if (AR_SREV_9280_20_OR_LATER(ah)
2082 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2083 REG_RMW(ah, addr, (type << gpio_shift),
2084 (0x1f << gpio_shift));
2085 } else {
2086 tmp = REG_READ(ah, addr);
2087 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2088 tmp &= ~(0x1f << gpio_shift);
2089 tmp |= (type << gpio_shift);
2090 REG_WRITE(ah, addr, tmp);
2091 }
2092 }
2093
2094 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2095 {
2096 u32 gpio_shift;
2097
2098 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2099
2100 if (AR_DEVID_7010(ah)) {
2101 gpio_shift = gpio;
2102 REG_RMW(ah, AR7010_GPIO_OE,
2103 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2104 (AR7010_GPIO_OE_MASK << gpio_shift));
2105 return;
2106 }
2107
2108 gpio_shift = gpio << 1;
2109 REG_RMW(ah,
2110 AR_GPIO_OE_OUT,
2111 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2112 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2113 }
2114 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2115
2116 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2117 {
2118 #define MS_REG_READ(x, y) \
2119 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2120
2121 if (gpio >= ah->caps.num_gpio_pins)
2122 return 0xffffffff;
2123
2124 if (AR_DEVID_7010(ah)) {
2125 u32 val;
2126 val = REG_READ(ah, AR7010_GPIO_IN);
2127 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2128 } else if (AR_SREV_9300_20_OR_LATER(ah))
2129 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2130 AR_GPIO_BIT(gpio)) != 0;
2131 else if (AR_SREV_9271(ah))
2132 return MS_REG_READ(AR9271, gpio) != 0;
2133 else if (AR_SREV_9287_11_OR_LATER(ah))
2134 return MS_REG_READ(AR9287, gpio) != 0;
2135 else if (AR_SREV_9285_12_OR_LATER(ah))
2136 return MS_REG_READ(AR9285, gpio) != 0;
2137 else if (AR_SREV_9280_20_OR_LATER(ah))
2138 return MS_REG_READ(AR928X, gpio) != 0;
2139 else
2140 return MS_REG_READ(AR, gpio) != 0;
2141 }
2142 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2143
2144 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2145 u32 ah_signal_type)
2146 {
2147 u32 gpio_shift;
2148
2149 if (AR_DEVID_7010(ah)) {
2150 gpio_shift = gpio;
2151 REG_RMW(ah, AR7010_GPIO_OE,
2152 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2153 (AR7010_GPIO_OE_MASK << gpio_shift));
2154 return;
2155 }
2156
2157 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2158 gpio_shift = 2 * gpio;
2159 REG_RMW(ah,
2160 AR_GPIO_OE_OUT,
2161 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2162 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2163 }
2164 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2165
2166 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2167 {
2168 if (AR_DEVID_7010(ah)) {
2169 val = val ? 0 : 1;
2170 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2171 AR_GPIO_BIT(gpio));
2172 return;
2173 }
2174
2175 if (AR_SREV_9271(ah))
2176 val = ~val;
2177
2178 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2179 AR_GPIO_BIT(gpio));
2180 }
2181 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2182
2183 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2184 {
2185 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2186 }
2187 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2188
2189 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2190 {
2191 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2192 }
2193 EXPORT_SYMBOL(ath9k_hw_setantenna);
2194
2195 /*********************/
2196 /* General Operation */
2197 /*********************/
2198
2199 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2200 {
2201 u32 bits = REG_READ(ah, AR_RX_FILTER);
2202 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2203
2204 if (phybits & AR_PHY_ERR_RADAR)
2205 bits |= ATH9K_RX_FILTER_PHYRADAR;
2206 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2207 bits |= ATH9K_RX_FILTER_PHYERR;
2208
2209 return bits;
2210 }
2211 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2212
2213 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2214 {
2215 u32 phybits;
2216
2217 ENABLE_REGWRITE_BUFFER(ah);
2218
2219 REG_WRITE(ah, AR_RX_FILTER, bits);
2220
2221 phybits = 0;
2222 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2223 phybits |= AR_PHY_ERR_RADAR;
2224 if (bits & ATH9K_RX_FILTER_PHYERR)
2225 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2226 REG_WRITE(ah, AR_PHY_ERR, phybits);
2227
2228 if (phybits)
2229 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2230 else
2231 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2232
2233 REGWRITE_BUFFER_FLUSH(ah);
2234 }
2235 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2236
2237 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2238 {
2239 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2240 return false;
2241
2242 ath9k_hw_init_pll(ah, NULL);
2243 return true;
2244 }
2245 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2246
2247 bool ath9k_hw_disable(struct ath_hw *ah)
2248 {
2249 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2250 return false;
2251
2252 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2253 return false;
2254
2255 ath9k_hw_init_pll(ah, NULL);
2256 return true;
2257 }
2258 EXPORT_SYMBOL(ath9k_hw_disable);
2259
2260 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2261 {
2262 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2263 struct ath9k_channel *chan = ah->curchan;
2264 struct ieee80211_channel *channel = chan->chan;
2265
2266 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2267
2268 ah->eep_ops->set_txpower(ah, chan,
2269 ath9k_regd_get_ctl(regulatory, chan),
2270 channel->max_antenna_gain * 2,
2271 channel->max_power * 2,
2272 min((u32) MAX_RATE_POWER,
2273 (u32) regulatory->power_limit), test);
2274 }
2275 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2276
2277 void ath9k_hw_setopmode(struct ath_hw *ah)
2278 {
2279 ath9k_hw_set_operating_mode(ah, ah->opmode);
2280 }
2281 EXPORT_SYMBOL(ath9k_hw_setopmode);
2282
2283 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2284 {
2285 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2286 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2287 }
2288 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2289
2290 void ath9k_hw_write_associd(struct ath_hw *ah)
2291 {
2292 struct ath_common *common = ath9k_hw_common(ah);
2293
2294 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2295 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2296 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2297 }
2298 EXPORT_SYMBOL(ath9k_hw_write_associd);
2299
2300 #define ATH9K_MAX_TSF_READ 10
2301
2302 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2303 {
2304 u32 tsf_lower, tsf_upper1, tsf_upper2;
2305 int i;
2306
2307 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2308 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2309 tsf_lower = REG_READ(ah, AR_TSF_L32);
2310 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2311 if (tsf_upper2 == tsf_upper1)
2312 break;
2313 tsf_upper1 = tsf_upper2;
2314 }
2315
2316 WARN_ON( i == ATH9K_MAX_TSF_READ );
2317
2318 return (((u64)tsf_upper1 << 32) | tsf_lower);
2319 }
2320 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2321
2322 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2323 {
2324 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2325 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2326 }
2327 EXPORT_SYMBOL(ath9k_hw_settsf64);
2328
2329 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2330 {
2331 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2332 AH_TSF_WRITE_TIMEOUT))
2333 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2334 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2335
2336 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2337 }
2338 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2339
2340 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2341 {
2342 if (setting)
2343 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2344 else
2345 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2346 }
2347 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2348
2349 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2350 {
2351 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2352 u32 macmode;
2353
2354 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2355 macmode = AR_2040_JOINED_RX_CLEAR;
2356 else
2357 macmode = 0;
2358
2359 REG_WRITE(ah, AR_2040_MODE, macmode);
2360 }
2361
2362 /* HW Generic timers configuration */
2363
2364 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2365 {
2366 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2367 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2368 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2369 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2370 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2371 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2372 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2373 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2374 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2375 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2376 AR_NDP2_TIMER_MODE, 0x0002},
2377 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2378 AR_NDP2_TIMER_MODE, 0x0004},
2379 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2380 AR_NDP2_TIMER_MODE, 0x0008},
2381 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2382 AR_NDP2_TIMER_MODE, 0x0010},
2383 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2384 AR_NDP2_TIMER_MODE, 0x0020},
2385 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2386 AR_NDP2_TIMER_MODE, 0x0040},
2387 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2388 AR_NDP2_TIMER_MODE, 0x0080}
2389 };
2390
2391 /* HW generic timer primitives */
2392
2393 /* compute and clear index of rightmost 1 */
2394 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2395 {
2396 u32 b;
2397
2398 b = *mask;
2399 b &= (0-b);
2400 *mask &= ~b;
2401 b *= debruijn32;
2402 b >>= 27;
2403
2404 return timer_table->gen_timer_index[b];
2405 }
2406
2407 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2408 {
2409 return REG_READ(ah, AR_TSF_L32);
2410 }
2411 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2412
2413 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2414 void (*trigger)(void *),
2415 void (*overflow)(void *),
2416 void *arg,
2417 u8 timer_index)
2418 {
2419 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2420 struct ath_gen_timer *timer;
2421
2422 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2423
2424 if (timer == NULL) {
2425 ath_err(ath9k_hw_common(ah),
2426 "Failed to allocate memory for hw timer[%d]\n",
2427 timer_index);
2428 return NULL;
2429 }
2430
2431 /* allocate a hardware generic timer slot */
2432 timer_table->timers[timer_index] = timer;
2433 timer->index = timer_index;
2434 timer->trigger = trigger;
2435 timer->overflow = overflow;
2436 timer->arg = arg;
2437
2438 return timer;
2439 }
2440 EXPORT_SYMBOL(ath_gen_timer_alloc);
2441
2442 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2443 struct ath_gen_timer *timer,
2444 u32 trig_timeout,
2445 u32 timer_period)
2446 {
2447 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2448 u32 tsf, timer_next;
2449
2450 BUG_ON(!timer_period);
2451
2452 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2453
2454 tsf = ath9k_hw_gettsf32(ah);
2455
2456 timer_next = tsf + trig_timeout;
2457
2458 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2459 "current tsf %x period %x timer_next %x\n",
2460 tsf, timer_period, timer_next);
2461
2462 /*
2463 * Program generic timer registers
2464 */
2465 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2466 timer_next);
2467 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2468 timer_period);
2469 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2470 gen_tmr_configuration[timer->index].mode_mask);
2471
2472 /* Enable both trigger and thresh interrupt masks */
2473 REG_SET_BIT(ah, AR_IMR_S5,
2474 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2475 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2476 }
2477 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2478
2479 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2480 {
2481 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2482
2483 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2484 (timer->index >= ATH_MAX_GEN_TIMER)) {
2485 return;
2486 }
2487
2488 /* Clear generic timer enable bits. */
2489 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2490 gen_tmr_configuration[timer->index].mode_mask);
2491
2492 /* Disable both trigger and thresh interrupt masks */
2493 REG_CLR_BIT(ah, AR_IMR_S5,
2494 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2495 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2496
2497 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2498 }
2499 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2500
2501 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2502 {
2503 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2504
2505 /* free the hardware generic timer slot */
2506 timer_table->timers[timer->index] = NULL;
2507 kfree(timer);
2508 }
2509 EXPORT_SYMBOL(ath_gen_timer_free);
2510
2511 /*
2512 * Generic Timer Interrupts handling
2513 */
2514 void ath_gen_timer_isr(struct ath_hw *ah)
2515 {
2516 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2517 struct ath_gen_timer *timer;
2518 struct ath_common *common = ath9k_hw_common(ah);
2519 u32 trigger_mask, thresh_mask, index;
2520
2521 /* get hardware generic timer interrupt status */
2522 trigger_mask = ah->intr_gen_timer_trigger;
2523 thresh_mask = ah->intr_gen_timer_thresh;
2524 trigger_mask &= timer_table->timer_mask.val;
2525 thresh_mask &= timer_table->timer_mask.val;
2526
2527 trigger_mask &= ~thresh_mask;
2528
2529 while (thresh_mask) {
2530 index = rightmost_index(timer_table, &thresh_mask);
2531 timer = timer_table->timers[index];
2532 BUG_ON(!timer);
2533 ath_dbg(common, ATH_DBG_HWTIMER,
2534 "TSF overflow for Gen timer %d\n", index);
2535 timer->overflow(timer->arg);
2536 }
2537
2538 while (trigger_mask) {
2539 index = rightmost_index(timer_table, &trigger_mask);
2540 timer = timer_table->timers[index];
2541 BUG_ON(!timer);
2542 ath_dbg(common, ATH_DBG_HWTIMER,
2543 "Gen timer[%d] trigger\n", index);
2544 timer->trigger(timer->arg);
2545 }
2546 }
2547 EXPORT_SYMBOL(ath_gen_timer_isr);
2548
2549 /********/
2550 /* HTC */
2551 /********/
2552
2553 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2554 {
2555 ah->htc_reset_init = true;
2556 }
2557 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2558
2559 static struct {
2560 u32 version;
2561 const char * name;
2562 } ath_mac_bb_names[] = {
2563 /* Devices with external radios */
2564 { AR_SREV_VERSION_5416_PCI, "5416" },
2565 { AR_SREV_VERSION_5416_PCIE, "5418" },
2566 { AR_SREV_VERSION_9100, "9100" },
2567 { AR_SREV_VERSION_9160, "9160" },
2568 /* Single-chip solutions */
2569 { AR_SREV_VERSION_9280, "9280" },
2570 { AR_SREV_VERSION_9285, "9285" },
2571 { AR_SREV_VERSION_9287, "9287" },
2572 { AR_SREV_VERSION_9271, "9271" },
2573 { AR_SREV_VERSION_9300, "9300" },
2574 { AR_SREV_VERSION_9485, "9485" },
2575 };
2576
2577 /* For devices with external radios */
2578 static struct {
2579 u16 version;
2580 const char * name;
2581 } ath_rf_names[] = {
2582 { 0, "5133" },
2583 { AR_RAD5133_SREV_MAJOR, "5133" },
2584 { AR_RAD5122_SREV_MAJOR, "5122" },
2585 { AR_RAD2133_SREV_MAJOR, "2133" },
2586 { AR_RAD2122_SREV_MAJOR, "2122" }
2587 };
2588
2589 /*
2590 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2591 */
2592 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2593 {
2594 int i;
2595
2596 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2597 if (ath_mac_bb_names[i].version == mac_bb_version) {
2598 return ath_mac_bb_names[i].name;
2599 }
2600 }
2601
2602 return "????";
2603 }
2604
2605 /*
2606 * Return the RF name. "????" is returned if the RF is unknown.
2607 * Used for devices with external radios.
2608 */
2609 static const char *ath9k_hw_rf_name(u16 rf_version)
2610 {
2611 int i;
2612
2613 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2614 if (ath_rf_names[i].version == rf_version) {
2615 return ath_rf_names[i].name;
2616 }
2617 }
2618
2619 return "????";
2620 }
2621
2622 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2623 {
2624 int used;
2625
2626 /* chipsets >= AR9280 are single-chip */
2627 if (AR_SREV_9280_20_OR_LATER(ah)) {
2628 used = snprintf(hw_name, len,
2629 "Atheros AR%s Rev:%x",
2630 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2631 ah->hw_version.macRev);
2632 }
2633 else {
2634 used = snprintf(hw_name, len,
2635 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2636 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2637 ah->hw_version.macRev,
2638 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2639 AR_RADIO_SREV_MAJOR)),
2640 ah->hw_version.phyRev);
2641 }
2642
2643 hw_name[used] = '\0';
2644 }
2645 EXPORT_SYMBOL(ath9k_hw_name);