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sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / net / wireless / ath / ath9k / main.c
blob17ebdf1e8b7bc567c20644eb150eec9058012a72
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static u8 parse_mpdudensity(u8 mpdudensity)
23 {
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55 }
56
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58 {
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
65 else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
66 pending = !list_empty(&txq->txq_fifo_pending);
67
68 spin_unlock_bh(&txq->axq_lock);
69 return pending;
70 }
71
72 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
73 {
74 unsigned long flags;
75 bool ret;
76
77 spin_lock_irqsave(&sc->sc_pm_lock, flags);
78 ret = ath9k_hw_setpower(sc->sc_ah, mode);
79 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
80
81 return ret;
82 }
83
84 void ath9k_ps_wakeup(struct ath_softc *sc)
85 {
86 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
87 unsigned long flags;
88 enum ath9k_power_mode power_mode;
89
90 spin_lock_irqsave(&sc->sc_pm_lock, flags);
91 if (++sc->ps_usecount != 1)
92 goto unlock;
93
94 power_mode = sc->sc_ah->power_mode;
95 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
96
97 /*
98 * While the hardware is asleep, the cycle counters contain no
99 * useful data. Better clear them now so that they don't mess up
100 * survey data results.
101 */
102 if (power_mode != ATH9K_PM_AWAKE) {
103 spin_lock(&common->cc_lock);
104 ath_hw_cycle_counters_update(common);
105 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
106 spin_unlock(&common->cc_lock);
107 }
108
109 unlock:
110 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
111 }
112
113 void ath9k_ps_restore(struct ath_softc *sc)
114 {
115 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
116 unsigned long flags;
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (--sc->ps_usecount != 0)
120 goto unlock;
121
122 spin_lock(&common->cc_lock);
123 ath_hw_cycle_counters_update(common);
124 spin_unlock(&common->cc_lock);
125
126 if (sc->ps_idle)
127 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
128 else if (sc->ps_enabled &&
129 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
130 PS_WAIT_FOR_CAB |
131 PS_WAIT_FOR_PSPOLL_DATA |
132 PS_WAIT_FOR_TX_ACK)))
133 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
134
135 unlock:
136 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
137 }
138
139 static void ath_start_ani(struct ath_common *common)
140 {
141 struct ath_hw *ah = common->ah;
142 unsigned long timestamp = jiffies_to_msecs(jiffies);
143 struct ath_softc *sc = (struct ath_softc *) common->priv;
144
145 if (!(sc->sc_flags & SC_OP_ANI_RUN))
146 return;
147
148 if (sc->sc_flags & SC_OP_OFFCHANNEL)
149 return;
150
151 common->ani.longcal_timer = timestamp;
152 common->ani.shortcal_timer = timestamp;
153 common->ani.checkani_timer = timestamp;
154
155 mod_timer(&common->ani.timer,
156 jiffies +
157 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
158 }
159
160 static void ath_update_survey_nf(struct ath_softc *sc, int channel)
161 {
162 struct ath_hw *ah = sc->sc_ah;
163 struct ath9k_channel *chan = &ah->channels[channel];
164 struct survey_info *survey = &sc->survey[channel];
165
166 if (chan->noisefloor) {
167 survey->filled |= SURVEY_INFO_NOISE_DBM;
168 survey->noise = chan->noisefloor;
169 }
170 }
171
172 /*
173 * Updates the survey statistics and returns the busy time since last
174 * update in %, if the measurement duration was long enough for the
175 * result to be useful, -1 otherwise.
176 */
177 static int ath_update_survey_stats(struct ath_softc *sc)
178 {
179 struct ath_hw *ah = sc->sc_ah;
180 struct ath_common *common = ath9k_hw_common(ah);
181 int pos = ah->curchan - &ah->channels[0];
182 struct survey_info *survey = &sc->survey[pos];
183 struct ath_cycle_counters *cc = &common->cc_survey;
184 unsigned int div = common->clockrate * 1000;
185 int ret = 0;
186
187 if (!ah->curchan)
188 return -1;
189
190 if (ah->power_mode == ATH9K_PM_AWAKE)
191 ath_hw_cycle_counters_update(common);
192
193 if (cc->cycles > 0) {
194 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
195 SURVEY_INFO_CHANNEL_TIME_BUSY |
196 SURVEY_INFO_CHANNEL_TIME_RX |
197 SURVEY_INFO_CHANNEL_TIME_TX;
198 survey->channel_time += cc->cycles / div;
199 survey->channel_time_busy += cc->rx_busy / div;
200 survey->channel_time_rx += cc->rx_frame / div;
201 survey->channel_time_tx += cc->tx_frame / div;
202 }
203
204 if (cc->cycles < div)
205 return -1;
206
207 if (cc->cycles > 0)
208 ret = cc->rx_busy * 100 / cc->cycles;
209
210 memset(cc, 0, sizeof(*cc));
211
212 ath_update_survey_nf(sc, pos);
213
214 return ret;
215 }
216
217 /*
218 * Set/change channels. If the channel is really being changed, it's done
219 * by reseting the chip. To accomplish this we must first cleanup any pending
220 * DMA, then restart stuff.
221 */
222 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
223 struct ath9k_channel *hchan)
224 {
225 struct ath_hw *ah = sc->sc_ah;
226 struct ath_common *common = ath9k_hw_common(ah);
227 struct ieee80211_conf *conf = &common->hw->conf;
228 bool fastcc = true, stopped;
229 struct ieee80211_channel *channel = hw->conf.channel;
230 struct ath9k_hw_cal_data *caldata = NULL;
231 int r;
232
233 if (sc->sc_flags & SC_OP_INVALID)
234 return -EIO;
235
236 sc->hw_busy_count = 0;
237
238 del_timer_sync(&common->ani.timer);
239 cancel_work_sync(&sc->paprd_work);
240 cancel_work_sync(&sc->hw_check_work);
241 cancel_delayed_work_sync(&sc->tx_complete_work);
242 cancel_delayed_work_sync(&sc->hw_pll_work);
243
244 ath9k_ps_wakeup(sc);
245
246 spin_lock_bh(&sc->sc_pcu_lock);
247
248 /*
249 * This is only performed if the channel settings have
250 * actually changed.
251 *
252 * To switch channels clear any pending DMA operations;
253 * wait long enough for the RX fifo to drain, reset the
254 * hardware at the new frequency, and then re-enable
255 * the relevant bits of the h/w.
256 */
257 ath9k_hw_disable_interrupts(ah);
258 stopped = ath_drain_all_txq(sc, false);
259
260 if (!ath_stoprecv(sc))
261 stopped = false;
262
263 if (!ath9k_hw_check_alive(ah))
264 stopped = false;
265
266 /* XXX: do not flush receive queue here. We don't want
267 * to flush data frames already in queue because of
268 * changing channel. */
269
270 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
271 fastcc = false;
272
273 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
274 caldata = &sc->caldata;
275
276 ath_dbg(common, ATH_DBG_CONFIG,
277 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
278 sc->sc_ah->curchan->channel,
279 channel->center_freq, conf_is_ht40(conf),
280 fastcc);
281
282 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
283 if (r) {
284 ath_err(common,
285 "Unable to reset channel (%u MHz), reset status %d\n",
286 channel->center_freq, r);
287 goto ps_restore;
288 }
289
290 if (ath_startrecv(sc) != 0) {
291 ath_err(common, "Unable to restart recv logic\n");
292 r = -EIO;
293 goto ps_restore;
294 }
295
296 ath9k_cmn_update_txpow(ah, sc->curtxpow,
297 sc->config.txpowlimit, &sc->curtxpow);
298 ath9k_hw_set_interrupts(ah, ah->imask);
299
300 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
301 if (sc->sc_flags & SC_OP_BEACONS)
302 ath_set_beacon(sc);
303 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
304 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
305 ath_start_ani(common);
306 }
307
308 ps_restore:
309 ieee80211_wake_queues(hw);
310
311 spin_unlock_bh(&sc->sc_pcu_lock);
312
313 ath9k_ps_restore(sc);
314 return r;
315 }
316
317 static void ath_paprd_activate(struct ath_softc *sc)
318 {
319 struct ath_hw *ah = sc->sc_ah;
320 struct ath9k_hw_cal_data *caldata = ah->caldata;
321 struct ath_common *common = ath9k_hw_common(ah);
322 int chain;
323
324 if (!caldata || !caldata->paprd_done)
325 return;
326
327 ath9k_ps_wakeup(sc);
328 ar9003_paprd_enable(ah, false);
329 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
330 if (!(common->tx_chainmask & BIT(chain)))
331 continue;
332
333 ar9003_paprd_populate_single_table(ah, caldata, chain);
334 }
335
336 ar9003_paprd_enable(ah, true);
337 ath9k_ps_restore(sc);
338 }
339
340 static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
341 {
342 struct ieee80211_hw *hw = sc->hw;
343 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
344 struct ath_hw *ah = sc->sc_ah;
345 struct ath_common *common = ath9k_hw_common(ah);
346 struct ath_tx_control txctl;
347 int time_left;
348
349 memset(&txctl, 0, sizeof(txctl));
350 txctl.txq = sc->tx.txq_map[WME_AC_BE];
351
352 memset(tx_info, 0, sizeof(*tx_info));
353 tx_info->band = hw->conf.channel->band;
354 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
355 tx_info->control.rates[0].idx = 0;
356 tx_info->control.rates[0].count = 1;
357 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
358 tx_info->control.rates[1].idx = -1;
359
360 init_completion(&sc->paprd_complete);
361 txctl.paprd = BIT(chain);
362
363 if (ath_tx_start(hw, skb, &txctl) != 0) {
364 ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n");
365 dev_kfree_skb_any(skb);
366 return false;
367 }
368
369 time_left = wait_for_completion_timeout(&sc->paprd_complete,
370 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
371
372 if (!time_left)
373 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
374 "Timeout waiting for paprd training on TX chain %d\n",
375 chain);
376
377 return !!time_left;
378 }
379
380 void ath_paprd_calibrate(struct work_struct *work)
381 {
382 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
383 struct ieee80211_hw *hw = sc->hw;
384 struct ath_hw *ah = sc->sc_ah;
385 struct ieee80211_hdr *hdr;
386 struct sk_buff *skb = NULL;
387 struct ath9k_hw_cal_data *caldata = ah->caldata;
388 struct ath_common *common = ath9k_hw_common(ah);
389 int ftype;
390 int chain_ok = 0;
391 int chain;
392 int len = 1800;
393
394 if (!caldata)
395 return;
396
397 if (ar9003_paprd_init_table(ah) < 0)
398 return;
399
400 skb = alloc_skb(len, GFP_KERNEL);
401 if (!skb)
402 return;
403
404 skb_put(skb, len);
405 memset(skb->data, 0, len);
406 hdr = (struct ieee80211_hdr *)skb->data;
407 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
408 hdr->frame_control = cpu_to_le16(ftype);
409 hdr->duration_id = cpu_to_le16(10);
410 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
411 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
412 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
413
414 ath9k_ps_wakeup(sc);
415 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
416 if (!(common->tx_chainmask & BIT(chain)))
417 continue;
418
419 chain_ok = 0;
420
421 ath_dbg(common, ATH_DBG_CALIBRATE,
422 "Sending PAPRD frame for thermal measurement "
423 "on chain %d\n", chain);
424 if (!ath_paprd_send_frame(sc, skb, chain))
425 goto fail_paprd;
426
427 ar9003_paprd_setup_gain_table(ah, chain);
428
429 ath_dbg(common, ATH_DBG_CALIBRATE,
430 "Sending PAPRD training frame on chain %d\n", chain);
431 if (!ath_paprd_send_frame(sc, skb, chain))
432 goto fail_paprd;
433
434 if (!ar9003_paprd_is_done(ah))
435 break;
436
437 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
438 break;
439
440 chain_ok = 1;
441 }
442 kfree_skb(skb);
443
444 if (chain_ok) {
445 caldata->paprd_done = true;
446 ath_paprd_activate(sc);
447 }
448
449 fail_paprd:
450 ath9k_ps_restore(sc);
451 }
452
453 /*
454 * This routine performs the periodic noise floor calibration function
455 * that is used to adjust and optimize the chip performance. This
456 * takes environmental changes (location, temperature) into account.
457 * When the task is complete, it reschedules itself depending on the
458 * appropriate interval that was calculated.
459 */
460 void ath_ani_calibrate(unsigned long data)
461 {
462 struct ath_softc *sc = (struct ath_softc *)data;
463 struct ath_hw *ah = sc->sc_ah;
464 struct ath_common *common = ath9k_hw_common(ah);
465 bool longcal = false;
466 bool shortcal = false;
467 bool aniflag = false;
468 unsigned int timestamp = jiffies_to_msecs(jiffies);
469 u32 cal_interval, short_cal_interval, long_cal_interval;
470 unsigned long flags;
471
472 if (ah->caldata && ah->caldata->nfcal_interference)
473 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
474 else
475 long_cal_interval = ATH_LONG_CALINTERVAL;
476
477 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
478 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
479
480 /* Only calibrate if awake */
481 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
482 goto set_timer;
483
484 ath9k_ps_wakeup(sc);
485
486 /* Long calibration runs independently of short calibration. */
487 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
488 longcal = true;
489 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
490 common->ani.longcal_timer = timestamp;
491 }
492
493 /* Short calibration applies only while caldone is false */
494 if (!common->ani.caldone) {
495 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
496 shortcal = true;
497 ath_dbg(common, ATH_DBG_ANI,
498 "shortcal @%lu\n", jiffies);
499 common->ani.shortcal_timer = timestamp;
500 common->ani.resetcal_timer = timestamp;
501 }
502 } else {
503 if ((timestamp - common->ani.resetcal_timer) >=
504 ATH_RESTART_CALINTERVAL) {
505 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
506 if (common->ani.caldone)
507 common->ani.resetcal_timer = timestamp;
508 }
509 }
510
511 /* Verify whether we must check ANI */
512 if ((timestamp - common->ani.checkani_timer) >=
513 ah->config.ani_poll_interval) {
514 aniflag = true;
515 common->ani.checkani_timer = timestamp;
516 }
517
518 /* Skip all processing if there's nothing to do. */
519 if (longcal || shortcal || aniflag) {
520 /* Call ANI routine if necessary */
521 if (aniflag) {
522 spin_lock_irqsave(&common->cc_lock, flags);
523 ath9k_hw_ani_monitor(ah, ah->curchan);
524 ath_update_survey_stats(sc);
525 spin_unlock_irqrestore(&common->cc_lock, flags);
526 }
527
528 /* Perform calibration if necessary */
529 if (longcal || shortcal) {
530 common->ani.caldone =
531 ath9k_hw_calibrate(ah,
532 ah->curchan,
533 common->rx_chainmask,
534 longcal);
535 }
536 }
537
538 ath9k_ps_restore(sc);
539
540 set_timer:
541 /*
542 * Set timer interval based on previous results.
543 * The interval must be the shortest necessary to satisfy ANI,
544 * short calibration and long calibration.
545 */
546 cal_interval = ATH_LONG_CALINTERVAL;
547 if (sc->sc_ah->config.enable_ani)
548 cal_interval = min(cal_interval,
549 (u32)ah->config.ani_poll_interval);
550 if (!common->ani.caldone)
551 cal_interval = min(cal_interval, (u32)short_cal_interval);
552
553 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
554 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
555 if (!ah->caldata->paprd_done)
556 ieee80211_queue_work(sc->hw, &sc->paprd_work);
557 else if (!ah->paprd_table_write_done)
558 ath_paprd_activate(sc);
559 }
560 }
561
562 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
563 {
564 struct ath_node *an;
565 struct ath_hw *ah = sc->sc_ah;
566 an = (struct ath_node *)sta->drv_priv;
567
568 #ifdef CONFIG_ATH9K_DEBUGFS
569 spin_lock(&sc->nodes_lock);
570 list_add(&an->list, &sc->nodes);
571 spin_unlock(&sc->nodes_lock);
572 an->sta = sta;
573 #endif
574 if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
575 sc->sc_flags |= SC_OP_ENABLE_APM;
576
577 if (sc->sc_flags & SC_OP_TXAGGR) {
578 ath_tx_node_init(sc, an);
579 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
580 sta->ht_cap.ampdu_factor);
581 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
582 }
583 }
584
585 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
586 {
587 struct ath_node *an = (struct ath_node *)sta->drv_priv;
588
589 #ifdef CONFIG_ATH9K_DEBUGFS
590 spin_lock(&sc->nodes_lock);
591 list_del(&an->list);
592 spin_unlock(&sc->nodes_lock);
593 an->sta = NULL;
594 #endif
595
596 if (sc->sc_flags & SC_OP_TXAGGR)
597 ath_tx_node_cleanup(sc, an);
598 }
599
600 void ath_hw_check(struct work_struct *work)
601 {
602 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
603 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
604 unsigned long flags;
605 int busy;
606
607 ath9k_ps_wakeup(sc);
608 if (ath9k_hw_check_alive(sc->sc_ah))
609 goto out;
610
611 spin_lock_irqsave(&common->cc_lock, flags);
612 busy = ath_update_survey_stats(sc);
613 spin_unlock_irqrestore(&common->cc_lock, flags);
614
615 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
616 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
617 if (busy >= 99) {
618 if (++sc->hw_busy_count >= 3)
619 ath_reset(sc, true);
620 } else if (busy >= 0)
621 sc->hw_busy_count = 0;
622
623 out:
624 ath9k_ps_restore(sc);
625 }
626
627 static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
628 {
629 static int count;
630 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
631
632 if (pll_sqsum >= 0x40000) {
633 count++;
634 if (count == 3) {
635 /* Rx is hung for more than 500ms. Reset it */
636 ath_dbg(common, ATH_DBG_RESET,
637 "Possible RX hang, resetting");
638 ath_reset(sc, true);
639 count = 0;
640 }
641 } else
642 count = 0;
643 }
644
645 void ath_hw_pll_work(struct work_struct *work)
646 {
647 struct ath_softc *sc = container_of(work, struct ath_softc,
648 hw_pll_work.work);
649 u32 pll_sqsum;
650
651 if (AR_SREV_9485(sc->sc_ah)) {
652
653 ath9k_ps_wakeup(sc);
654 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
655 ath9k_ps_restore(sc);
656
657 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
658
659 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
660 }
661 }
662
663
664 void ath9k_tasklet(unsigned long data)
665 {
666 struct ath_softc *sc = (struct ath_softc *)data;
667 struct ath_hw *ah = sc->sc_ah;
668 struct ath_common *common = ath9k_hw_common(ah);
669
670 u32 status = sc->intrstatus;
671 u32 rxmask;
672
673 if (status & ATH9K_INT_FATAL) {
674 ath_reset(sc, true);
675 return;
676 }
677
678 ath9k_ps_wakeup(sc);
679 spin_lock(&sc->sc_pcu_lock);
680
681 /*
682 * Only run the baseband hang check if beacons stop working in AP or
683 * IBSS mode, because it has a high false positive rate. For station
684 * mode it should not be necessary, since the upper layers will detect
685 * this through a beacon miss automatically and the following channel
686 * change will trigger a hardware reset anyway
687 */
688 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
689 !ath9k_hw_check_alive(ah))
690 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
691
692 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
693 /*
694 * TSF sync does not look correct; remain awake to sync with
695 * the next Beacon.
696 */
697 ath_dbg(common, ATH_DBG_PS,
698 "TSFOOR - Sync with next Beacon\n");
699 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC |
700 PS_TSFOOR_SYNC;
701 }
702
703 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
704 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
705 ATH9K_INT_RXORN);
706 else
707 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
708
709 if (status & rxmask) {
710 /* Check for high priority Rx first */
711 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
712 (status & ATH9K_INT_RXHP))
713 ath_rx_tasklet(sc, 0, true);
714
715 ath_rx_tasklet(sc, 0, false);
716 }
717
718 if (status & ATH9K_INT_TX) {
719 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
720 ath_tx_edma_tasklet(sc);
721 else
722 ath_tx_tasklet(sc);
723 }
724
725 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
726 if (status & ATH9K_INT_GENTIMER)
727 ath_gen_timer_isr(sc->sc_ah);
728
729 /* re-enable hardware interrupt */
730 ath9k_hw_enable_interrupts(ah);
731
732 spin_unlock(&sc->sc_pcu_lock);
733 ath9k_ps_restore(sc);
734 }
735
736 irqreturn_t ath_isr(int irq, void *dev)
737 {
738 #define SCHED_INTR ( \
739 ATH9K_INT_FATAL | \
740 ATH9K_INT_RXORN | \
741 ATH9K_INT_RXEOL | \
742 ATH9K_INT_RX | \
743 ATH9K_INT_RXLP | \
744 ATH9K_INT_RXHP | \
745 ATH9K_INT_TX | \
746 ATH9K_INT_BMISS | \
747 ATH9K_INT_CST | \
748 ATH9K_INT_TSFOOR | \
749 ATH9K_INT_GENTIMER)
750
751 struct ath_softc *sc = dev;
752 struct ath_hw *ah = sc->sc_ah;
753 struct ath_common *common = ath9k_hw_common(ah);
754 enum ath9k_int status;
755 bool sched = false;
756
757 /*
758 * The hardware is not ready/present, don't
759 * touch anything. Note this can happen early
760 * on if the IRQ is shared.
761 */
762 if (sc->sc_flags & SC_OP_INVALID)
763 return IRQ_NONE;
764
765
766 /* shared irq, not for us */
767
768 if (!ath9k_hw_intrpend(ah))
769 return IRQ_NONE;
770
771 /*
772 * Figure out the reason(s) for the interrupt. Note
773 * that the hal returns a pseudo-ISR that may include
774 * bits we haven't explicitly enabled so we mask the
775 * value to insure we only process bits we requested.
776 */
777 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
778 status &= ah->imask; /* discard unasked-for bits */
779
780 /*
781 * If there are no status bits set, then this interrupt was not
782 * for me (should have been caught above).
783 */
784 if (!status)
785 return IRQ_NONE;
786
787 /* Cache the status */
788 sc->intrstatus = status;
789
790 if (status & SCHED_INTR)
791 sched = true;
792
793 /*
794 * If a FATAL or RXORN interrupt is received, we have to reset the
795 * chip immediately.
796 */
797 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
798 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
799 goto chip_reset;
800
801 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
802 (status & ATH9K_INT_BB_WATCHDOG)) {
803
804 spin_lock(&common->cc_lock);
805 ath_hw_cycle_counters_update(common);
806 ar9003_hw_bb_watchdog_dbg_info(ah);
807 spin_unlock(&common->cc_lock);
808
809 goto chip_reset;
810 }
811
812 if (status & ATH9K_INT_SWBA)
813 tasklet_schedule(&sc->bcon_tasklet);
814
815 if (status & ATH9K_INT_TXURN)
816 ath9k_hw_updatetxtriglevel(ah, true);
817
818 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
819 if (status & ATH9K_INT_RXEOL) {
820 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
821 ath9k_hw_set_interrupts(ah, ah->imask);
822 }
823 }
824
825 if (status & ATH9K_INT_MIB) {
826 /*
827 * Disable interrupts until we service the MIB
828 * interrupt; otherwise it will continue to
829 * fire.
830 */
831 ath9k_hw_disable_interrupts(ah);
832 /*
833 * Let the hal handle the event. We assume
834 * it will clear whatever condition caused
835 * the interrupt.
836 */
837 spin_lock(&common->cc_lock);
838 ath9k_hw_proc_mib_event(ah);
839 spin_unlock(&common->cc_lock);
840 ath9k_hw_enable_interrupts(ah);
841 }
842
843 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
844 if (status & ATH9K_INT_TIM_TIMER) {
845 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
846 goto chip_reset;
847 /* Clear RxAbort bit so that we can
848 * receive frames */
849 ath9k_setpower(sc, ATH9K_PM_AWAKE);
850 ath9k_hw_setrxabort(sc->sc_ah, 0);
851 sc->ps_flags |= PS_WAIT_FOR_BEACON;
852 }
853
854 chip_reset:
855
856 ath_debug_stat_interrupt(sc, status);
857
858 if (sched) {
859 /* turn off every interrupt */
860 ath9k_hw_disable_interrupts(ah);
861 tasklet_schedule(&sc->intr_tq);
862 }
863
864 return IRQ_HANDLED;
865
866 #undef SCHED_INTR
867 }
868
869 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
870 {
871 struct ath_hw *ah = sc->sc_ah;
872 struct ath_common *common = ath9k_hw_common(ah);
873 struct ieee80211_channel *channel = hw->conf.channel;
874 int r;
875
876 ath9k_ps_wakeup(sc);
877 spin_lock_bh(&sc->sc_pcu_lock);
878
879 ath9k_hw_configpcipowersave(ah, 0, 0);
880
881 if (!ah->curchan)
882 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
883
884 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
885 if (r) {
886 ath_err(common,
887 "Unable to reset channel (%u MHz), reset status %d\n",
888 channel->center_freq, r);
889 }
890
891 ath9k_cmn_update_txpow(ah, sc->curtxpow,
892 sc->config.txpowlimit, &sc->curtxpow);
893 if (ath_startrecv(sc) != 0) {
894 ath_err(common, "Unable to restart recv logic\n");
895 goto out;
896 }
897 if (sc->sc_flags & SC_OP_BEACONS)
898 ath_set_beacon(sc); /* restart beacons */
899
900 /* Re-Enable interrupts */
901 ath9k_hw_set_interrupts(ah, ah->imask);
902
903 /* Enable LED */
904 ath9k_hw_cfg_output(ah, ah->led_pin,
905 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
906 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
907
908 ieee80211_wake_queues(hw);
909 ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
910
911 out:
912 spin_unlock_bh(&sc->sc_pcu_lock);
913
914 ath9k_ps_restore(sc);
915 }
916
917 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
918 {
919 struct ath_hw *ah = sc->sc_ah;
920 struct ieee80211_channel *channel = hw->conf.channel;
921 int r;
922
923 ath9k_ps_wakeup(sc);
924 cancel_delayed_work_sync(&sc->hw_pll_work);
925
926 spin_lock_bh(&sc->sc_pcu_lock);
927
928 ieee80211_stop_queues(hw);
929
930 /*
931 * Keep the LED on when the radio is disabled
932 * during idle unassociated state.
933 */
934 if (!sc->ps_idle) {
935 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
936 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
937 }
938
939 /* Disable interrupts */
940 ath9k_hw_disable_interrupts(ah);
941
942 ath_drain_all_txq(sc, false); /* clear pending tx frames */
943
944 ath_stoprecv(sc); /* turn off frame recv */
945 ath_flushrecv(sc); /* flush recv queue */
946
947 if (!ah->curchan)
948 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
949
950 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
951 if (r) {
952 ath_err(ath9k_hw_common(sc->sc_ah),
953 "Unable to reset channel (%u MHz), reset status %d\n",
954 channel->center_freq, r);
955 }
956
957 ath9k_hw_phy_disable(ah);
958
959 ath9k_hw_configpcipowersave(ah, 1, 1);
960
961 spin_unlock_bh(&sc->sc_pcu_lock);
962 ath9k_ps_restore(sc);
963 }
964
965 int ath_reset(struct ath_softc *sc, bool retry_tx)
966 {
967 struct ath_hw *ah = sc->sc_ah;
968 struct ath_common *common = ath9k_hw_common(ah);
969 struct ieee80211_hw *hw = sc->hw;
970 int r;
971
972 sc->hw_busy_count = 0;
973
974 /* Stop ANI */
975 del_timer_sync(&common->ani.timer);
976
977 ath9k_ps_wakeup(sc);
978 spin_lock_bh(&sc->sc_pcu_lock);
979
980 ieee80211_stop_queues(hw);
981
982 ath9k_hw_disable_interrupts(ah);
983 ath_drain_all_txq(sc, retry_tx);
984
985 ath_stoprecv(sc);
986 ath_flushrecv(sc);
987
988 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
989 if (r)
990 ath_err(common,
991 "Unable to reset hardware; reset status %d\n", r);
992
993 if (ath_startrecv(sc) != 0)
994 ath_err(common, "Unable to start recv logic\n");
995
996 /*
997 * We may be doing a reset in response to a request
998 * that changes the channel so update any state that
999 * might change as a result.
1000 */
1001 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1002 sc->config.txpowlimit, &sc->curtxpow);
1003
1004 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
1005 ath_set_beacon(sc); /* restart beacons */
1006
1007 ath9k_hw_set_interrupts(ah, ah->imask);
1008
1009 if (retry_tx) {
1010 int i;
1011 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1012 if (ATH_TXQ_SETUP(sc, i)) {
1013 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1014 ath_txq_schedule(sc, &sc->tx.txq[i]);
1015 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1016 }
1017 }
1018 }
1019
1020 ieee80211_wake_queues(hw);
1021 spin_unlock_bh(&sc->sc_pcu_lock);
1022
1023 /* Start ANI */
1024 ath_start_ani(common);
1025 ath9k_ps_restore(sc);
1026
1027 return r;
1028 }
1029
1030 /**********************/
1031 /* mac80211 callbacks */
1032 /**********************/
1033
1034 static int ath9k_start(struct ieee80211_hw *hw)
1035 {
1036 struct ath_softc *sc = hw->priv;
1037 struct ath_hw *ah = sc->sc_ah;
1038 struct ath_common *common = ath9k_hw_common(ah);
1039 struct ieee80211_channel *curchan = hw->conf.channel;
1040 struct ath9k_channel *init_channel;
1041 int r;
1042
1043 ath_dbg(common, ATH_DBG_CONFIG,
1044 "Starting driver with initial channel: %d MHz\n",
1045 curchan->center_freq);
1046
1047 ath9k_ps_wakeup(sc);
1048
1049 mutex_lock(&sc->mutex);
1050
1051 /* setup initial channel */
1052 sc->chan_idx = curchan->hw_value;
1053
1054 init_channel = ath9k_cmn_get_curchannel(hw, ah);
1055
1056 /* Reset SERDES registers */
1057 ath9k_hw_configpcipowersave(ah, 0, 0);
1058
1059 /*
1060 * The basic interface to setting the hardware in a good
1061 * state is ``reset''. On return the hardware is known to
1062 * be powered up and with interrupts disabled. This must
1063 * be followed by initialization of the appropriate bits
1064 * and then setup of the interrupt mask.
1065 */
1066 spin_lock_bh(&sc->sc_pcu_lock);
1067 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
1068 if (r) {
1069 ath_err(common,
1070 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1071 r, curchan->center_freq);
1072 spin_unlock_bh(&sc->sc_pcu_lock);
1073 goto mutex_unlock;
1074 }
1075
1076 /*
1077 * This is needed only to setup initial state
1078 * but it's best done after a reset.
1079 */
1080 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1081 sc->config.txpowlimit, &sc->curtxpow);
1082
1083 /*
1084 * Setup the hardware after reset:
1085 * The receive engine is set going.
1086 * Frame transmit is handled entirely
1087 * in the frame output path; there's nothing to do
1088 * here except setup the interrupt mask.
1089 */
1090 if (ath_startrecv(sc) != 0) {
1091 ath_err(common, "Unable to start recv logic\n");
1092 r = -EIO;
1093 spin_unlock_bh(&sc->sc_pcu_lock);
1094 goto mutex_unlock;
1095 }
1096 spin_unlock_bh(&sc->sc_pcu_lock);
1097
1098 /* Setup our intr mask. */
1099 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1100 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1101 ATH9K_INT_GLOBAL;
1102
1103 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1104 ah->imask |= ATH9K_INT_RXHP |
1105 ATH9K_INT_RXLP |
1106 ATH9K_INT_BB_WATCHDOG;
1107 else
1108 ah->imask |= ATH9K_INT_RX;
1109
1110 ah->imask |= ATH9K_INT_GTT;
1111
1112 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1113 ah->imask |= ATH9K_INT_CST;
1114
1115 sc->sc_flags &= ~SC_OP_INVALID;
1116 sc->sc_ah->is_monitoring = false;
1117
1118 /* Disable BMISS interrupt when we're not associated */
1119 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1120 ath9k_hw_set_interrupts(ah, ah->imask);
1121
1122 ieee80211_wake_queues(hw);
1123
1124 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1125
1126 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1127 !ah->btcoex_hw.enabled) {
1128 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1129 AR_STOMP_LOW_WLAN_WGHT);
1130 ath9k_hw_btcoex_enable(ah);
1131
1132 if (common->bus_ops->bt_coex_prep)
1133 common->bus_ops->bt_coex_prep(common);
1134 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1135 ath9k_btcoex_timer_resume(sc);
1136 }
1137
1138 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1139 common->bus_ops->extn_synch_en(common);
1140
1141 mutex_unlock:
1142 mutex_unlock(&sc->mutex);
1143
1144 ath9k_ps_restore(sc);
1145
1146 return r;
1147 }
1148
1149 static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1150 {
1151 struct ath_softc *sc = hw->priv;
1152 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1153 struct ath_tx_control txctl;
1154 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1155
1156 if (sc->ps_enabled) {
1157 /*
1158 * mac80211 does not set PM field for normal data frames, so we
1159 * need to update that based on the current PS mode.
1160 */
1161 if (ieee80211_is_data(hdr->frame_control) &&
1162 !ieee80211_is_nullfunc(hdr->frame_control) &&
1163 !ieee80211_has_pm(hdr->frame_control)) {
1164 ath_dbg(common, ATH_DBG_PS,
1165 "Add PM=1 for a TX frame while in PS mode\n");
1166 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1167 }
1168 }
1169
1170 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1171 /*
1172 * We are using PS-Poll and mac80211 can request TX while in
1173 * power save mode. Need to wake up hardware for the TX to be
1174 * completed and if needed, also for RX of buffered frames.
1175 */
1176 ath9k_ps_wakeup(sc);
1177 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1178 ath9k_hw_setrxabort(sc->sc_ah, 0);
1179 if (ieee80211_is_pspoll(hdr->frame_control)) {
1180 ath_dbg(common, ATH_DBG_PS,
1181 "Sending PS-Poll to pick a buffered frame\n");
1182 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
1183 } else {
1184 ath_dbg(common, ATH_DBG_PS,
1185 "Wake up to complete TX\n");
1186 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
1187 }
1188 /*
1189 * The actual restore operation will happen only after
1190 * the sc_flags bit is cleared. We are just dropping
1191 * the ps_usecount here.
1192 */
1193 ath9k_ps_restore(sc);
1194 }
1195
1196 memset(&txctl, 0, sizeof(struct ath_tx_control));
1197 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
1198
1199 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
1200
1201 if (ath_tx_start(hw, skb, &txctl) != 0) {
1202 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
1203 goto exit;
1204 }
1205
1206 return;
1207 exit:
1208 dev_kfree_skb_any(skb);
1209 }
1210
1211 static void ath9k_stop(struct ieee80211_hw *hw)
1212 {
1213 struct ath_softc *sc = hw->priv;
1214 struct ath_hw *ah = sc->sc_ah;
1215 struct ath_common *common = ath9k_hw_common(ah);
1216
1217 mutex_lock(&sc->mutex);
1218
1219 cancel_delayed_work_sync(&sc->tx_complete_work);
1220 cancel_delayed_work_sync(&sc->hw_pll_work);
1221 cancel_work_sync(&sc->paprd_work);
1222 cancel_work_sync(&sc->hw_check_work);
1223
1224 if (sc->sc_flags & SC_OP_INVALID) {
1225 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
1226 mutex_unlock(&sc->mutex);
1227 return;
1228 }
1229
1230 /* Ensure HW is awake when we try to shut it down. */
1231 ath9k_ps_wakeup(sc);
1232
1233 if (ah->btcoex_hw.enabled) {
1234 ath9k_hw_btcoex_disable(ah);
1235 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1236 ath9k_btcoex_timer_pause(sc);
1237 }
1238
1239 spin_lock_bh(&sc->sc_pcu_lock);
1240
1241 /* prevent tasklets to enable interrupts once we disable them */
1242 ah->imask &= ~ATH9K_INT_GLOBAL;
1243
1244 /* make sure h/w will not generate any interrupt
1245 * before setting the invalid flag. */
1246 ath9k_hw_disable_interrupts(ah);
1247
1248 if (!(sc->sc_flags & SC_OP_INVALID)) {
1249 ath_drain_all_txq(sc, false);
1250 ath_stoprecv(sc);
1251 ath9k_hw_phy_disable(ah);
1252 } else
1253 sc->rx.rxlink = NULL;
1254
1255 if (sc->rx.frag) {
1256 dev_kfree_skb_any(sc->rx.frag);
1257 sc->rx.frag = NULL;
1258 }
1259
1260 /* disable HAL and put h/w to sleep */
1261 ath9k_hw_disable(ah);
1262 ath9k_hw_configpcipowersave(ah, 1, 1);
1263
1264 spin_unlock_bh(&sc->sc_pcu_lock);
1265
1266 /* we can now sync irq and kill any running tasklets, since we already
1267 * disabled interrupts and not holding a spin lock */
1268 synchronize_irq(sc->irq);
1269 tasklet_kill(&sc->intr_tq);
1270 tasklet_kill(&sc->bcon_tasklet);
1271
1272 ath9k_ps_restore(sc);
1273
1274 sc->ps_idle = true;
1275 ath_radio_disable(sc, hw);
1276
1277 sc->sc_flags |= SC_OP_INVALID;
1278
1279 mutex_unlock(&sc->mutex);
1280
1281 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
1282 }
1283
1284 bool ath9k_uses_beacons(int type)
1285 {
1286 switch (type) {
1287 case NL80211_IFTYPE_AP:
1288 case NL80211_IFTYPE_ADHOC:
1289 case NL80211_IFTYPE_MESH_POINT:
1290 return true;
1291 default:
1292 return false;
1293 }
1294 }
1295
1296 static void ath9k_reclaim_beacon(struct ath_softc *sc,
1297 struct ieee80211_vif *vif)
1298 {
1299 struct ath_vif *avp = (void *)vif->drv_priv;
1300
1301 ath9k_set_beaconing_status(sc, false);
1302 ath_beacon_return(sc, avp);
1303 ath9k_set_beaconing_status(sc, true);
1304 sc->sc_flags &= ~SC_OP_BEACONS;
1305 }
1306
1307 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1308 {
1309 struct ath9k_vif_iter_data *iter_data = data;
1310 int i;
1311
1312 if (iter_data->hw_macaddr)
1313 for (i = 0; i < ETH_ALEN; i++)
1314 iter_data->mask[i] &=
1315 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1316
1317 switch (vif->type) {
1318 case NL80211_IFTYPE_AP:
1319 iter_data->naps++;
1320 break;
1321 case NL80211_IFTYPE_STATION:
1322 iter_data->nstations++;
1323 break;
1324 case NL80211_IFTYPE_ADHOC:
1325 iter_data->nadhocs++;
1326 break;
1327 case NL80211_IFTYPE_MESH_POINT:
1328 iter_data->nmeshes++;
1329 break;
1330 case NL80211_IFTYPE_WDS:
1331 iter_data->nwds++;
1332 break;
1333 default:
1334 iter_data->nothers++;
1335 break;
1336 }
1337 }
1338
1339 /* Called with sc->mutex held. */
1340 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1341 struct ieee80211_vif *vif,
1342 struct ath9k_vif_iter_data *iter_data)
1343 {
1344 struct ath_softc *sc = hw->priv;
1345 struct ath_hw *ah = sc->sc_ah;
1346 struct ath_common *common = ath9k_hw_common(ah);
1347
1348 /*
1349 * Use the hardware MAC address as reference, the hardware uses it
1350 * together with the BSSID mask when matching addresses.
1351 */
1352 memset(iter_data, 0, sizeof(*iter_data));
1353 iter_data->hw_macaddr = common->macaddr;
1354 memset(&iter_data->mask, 0xff, ETH_ALEN);
1355
1356 if (vif)
1357 ath9k_vif_iter(iter_data, vif->addr, vif);
1358
1359 /* Get list of all active MAC addresses */
1360 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1361 iter_data);
1362 }
1363
1364 /* Called with sc->mutex held. */
1365 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1366 struct ieee80211_vif *vif)
1367 {
1368 struct ath_softc *sc = hw->priv;
1369 struct ath_hw *ah = sc->sc_ah;
1370 struct ath_common *common = ath9k_hw_common(ah);
1371 struct ath9k_vif_iter_data iter_data;
1372
1373 ath9k_calculate_iter_data(hw, vif, &iter_data);
1374
1375 /* Set BSSID mask. */
1376 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1377 ath_hw_setbssidmask(common);
1378
1379 /* Set op-mode & TSF */
1380 if (iter_data.naps > 0) {
1381 ath9k_hw_set_tsfadjust(ah, 1);
1382 sc->sc_flags |= SC_OP_TSF_RESET;
1383 ah->opmode = NL80211_IFTYPE_AP;
1384 } else {
1385 ath9k_hw_set_tsfadjust(ah, 0);
1386 sc->sc_flags &= ~SC_OP_TSF_RESET;
1387
1388 if (iter_data.nmeshes)
1389 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1390 else if (iter_data.nwds)
1391 ah->opmode = NL80211_IFTYPE_AP;
1392 else if (iter_data.nadhocs)
1393 ah->opmode = NL80211_IFTYPE_ADHOC;
1394 else
1395 ah->opmode = NL80211_IFTYPE_STATION;
1396 }
1397
1398 /*
1399 * Enable MIB interrupts when there are hardware phy counters.
1400 */
1401 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
1402 if (ah->config.enable_ani)
1403 ah->imask |= ATH9K_INT_MIB;
1404 ah->imask |= ATH9K_INT_TSFOOR;
1405 } else {
1406 ah->imask &= ~ATH9K_INT_MIB;
1407 ah->imask &= ~ATH9K_INT_TSFOOR;
1408 }
1409
1410 ath9k_hw_set_interrupts(ah, ah->imask);
1411
1412 /* Set up ANI */
1413 if ((iter_data.naps + iter_data.nadhocs) > 0) {
1414 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1415 sc->sc_flags |= SC_OP_ANI_RUN;
1416 ath_start_ani(common);
1417 } else {
1418 sc->sc_flags &= ~SC_OP_ANI_RUN;
1419 del_timer_sync(&common->ani.timer);
1420 }
1421 }
1422
1423 /* Called with sc->mutex held, vif counts set up properly. */
1424 static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1425 struct ieee80211_vif *vif)
1426 {
1427 struct ath_softc *sc = hw->priv;
1428
1429 ath9k_calculate_summary_state(hw, vif);
1430
1431 if (ath9k_uses_beacons(vif->type)) {
1432 int error;
1433 /* This may fail because upper levels do not have beacons
1434 * properly configured yet. That's OK, we assume it
1435 * will be properly configured and then we will be notified
1436 * in the info_changed method and set up beacons properly
1437 * there.
1438 */
1439 ath9k_set_beaconing_status(sc, false);
1440 error = ath_beacon_alloc(sc, vif);
1441 if (!error)
1442 ath_beacon_config(sc, vif);
1443 ath9k_set_beaconing_status(sc, true);
1444 }
1445 }
1446
1447
1448 static int ath9k_add_interface(struct ieee80211_hw *hw,
1449 struct ieee80211_vif *vif)
1450 {
1451 struct ath_softc *sc = hw->priv;
1452 struct ath_hw *ah = sc->sc_ah;
1453 struct ath_common *common = ath9k_hw_common(ah);
1454 int ret = 0;
1455
1456 ath9k_ps_wakeup(sc);
1457 mutex_lock(&sc->mutex);
1458
1459 switch (vif->type) {
1460 case NL80211_IFTYPE_STATION:
1461 case NL80211_IFTYPE_WDS:
1462 case NL80211_IFTYPE_ADHOC:
1463 case NL80211_IFTYPE_AP:
1464 case NL80211_IFTYPE_MESH_POINT:
1465 break;
1466 default:
1467 ath_err(common, "Interface type %d not yet supported\n",
1468 vif->type);
1469 ret = -EOPNOTSUPP;
1470 goto out;
1471 }
1472
1473 if (ath9k_uses_beacons(vif->type)) {
1474 if (sc->nbcnvifs >= ATH_BCBUF) {
1475 ath_err(common, "Not enough beacon buffers when adding"
1476 " new interface of type: %i\n",
1477 vif->type);
1478 ret = -ENOBUFS;
1479 goto out;
1480 }
1481 }
1482
1483 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1484 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1485 sc->nvifs > 0)) {
1486 ath_err(common, "Cannot create ADHOC interface when other"
1487 " interfaces already exist.\n");
1488 ret = -EINVAL;
1489 goto out;
1490 }
1491
1492 ath_dbg(common, ATH_DBG_CONFIG,
1493 "Attach a VIF of type: %d\n", vif->type);
1494
1495 sc->nvifs++;
1496
1497 ath9k_do_vif_add_setup(hw, vif);
1498 out:
1499 mutex_unlock(&sc->mutex);
1500 ath9k_ps_restore(sc);
1501 return ret;
1502 }
1503
1504 static int ath9k_change_interface(struct ieee80211_hw *hw,
1505 struct ieee80211_vif *vif,
1506 enum nl80211_iftype new_type,
1507 bool p2p)
1508 {
1509 struct ath_softc *sc = hw->priv;
1510 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1511 int ret = 0;
1512
1513 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1514 mutex_lock(&sc->mutex);
1515 ath9k_ps_wakeup(sc);
1516
1517 /* See if new interface type is valid. */
1518 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1519 (sc->nvifs > 1)) {
1520 ath_err(common, "When using ADHOC, it must be the only"
1521 " interface.\n");
1522 ret = -EINVAL;
1523 goto out;
1524 }
1525
1526 if (ath9k_uses_beacons(new_type) &&
1527 !ath9k_uses_beacons(vif->type)) {
1528 if (sc->nbcnvifs >= ATH_BCBUF) {
1529 ath_err(common, "No beacon slot available\n");
1530 ret = -ENOBUFS;
1531 goto out;
1532 }
1533 }
1534
1535 /* Clean up old vif stuff */
1536 if (ath9k_uses_beacons(vif->type))
1537 ath9k_reclaim_beacon(sc, vif);
1538
1539 /* Add new settings */
1540 vif->type = new_type;
1541 vif->p2p = p2p;
1542
1543 ath9k_do_vif_add_setup(hw, vif);
1544 out:
1545 ath9k_ps_restore(sc);
1546 mutex_unlock(&sc->mutex);
1547 return ret;
1548 }
1549
1550 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1551 struct ieee80211_vif *vif)
1552 {
1553 struct ath_softc *sc = hw->priv;
1554 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1555
1556 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
1557
1558 ath9k_ps_wakeup(sc);
1559 mutex_lock(&sc->mutex);
1560
1561 sc->nvifs--;
1562
1563 /* Reclaim beacon resources */
1564 if (ath9k_uses_beacons(vif->type))
1565 ath9k_reclaim_beacon(sc, vif);
1566
1567 ath9k_calculate_summary_state(hw, NULL);
1568
1569 mutex_unlock(&sc->mutex);
1570 ath9k_ps_restore(sc);
1571 }
1572
1573 static void ath9k_enable_ps(struct ath_softc *sc)
1574 {
1575 struct ath_hw *ah = sc->sc_ah;
1576
1577 sc->ps_enabled = true;
1578 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1579 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1580 ah->imask |= ATH9K_INT_TIM_TIMER;
1581 ath9k_hw_set_interrupts(ah, ah->imask);
1582 }
1583 ath9k_hw_setrxabort(ah, 1);
1584 }
1585 }
1586
1587 static void ath9k_disable_ps(struct ath_softc *sc)
1588 {
1589 struct ath_hw *ah = sc->sc_ah;
1590
1591 sc->ps_enabled = false;
1592 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1593 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1594 ath9k_hw_setrxabort(ah, 0);
1595 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1596 PS_WAIT_FOR_CAB |
1597 PS_WAIT_FOR_PSPOLL_DATA |
1598 PS_WAIT_FOR_TX_ACK);
1599 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1600 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1601 ath9k_hw_set_interrupts(ah, ah->imask);
1602 }
1603 }
1604
1605 }
1606
1607 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1608 {
1609 struct ath_softc *sc = hw->priv;
1610 struct ath_hw *ah = sc->sc_ah;
1611 struct ath_common *common = ath9k_hw_common(ah);
1612 struct ieee80211_conf *conf = &hw->conf;
1613 bool disable_radio = false;
1614
1615 mutex_lock(&sc->mutex);
1616
1617 /*
1618 * Leave this as the first check because we need to turn on the
1619 * radio if it was disabled before prior to processing the rest
1620 * of the changes. Likewise we must only disable the radio towards
1621 * the end.
1622 */
1623 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1624 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1625 if (!sc->ps_idle) {
1626 ath_radio_enable(sc, hw);
1627 ath_dbg(common, ATH_DBG_CONFIG,
1628 "not-idle: enabling radio\n");
1629 } else {
1630 disable_radio = true;
1631 }
1632 }
1633
1634 /*
1635 * We just prepare to enable PS. We have to wait until our AP has
1636 * ACK'd our null data frame to disable RX otherwise we'll ignore
1637 * those ACKs and end up retransmitting the same null data frames.
1638 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1639 */
1640 if (changed & IEEE80211_CONF_CHANGE_PS) {
1641 unsigned long flags;
1642 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1643 if (conf->flags & IEEE80211_CONF_PS)
1644 ath9k_enable_ps(sc);
1645 else
1646 ath9k_disable_ps(sc);
1647 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1648 }
1649
1650 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1651 if (conf->flags & IEEE80211_CONF_MONITOR) {
1652 ath_dbg(common, ATH_DBG_CONFIG,
1653 "Monitor mode is enabled\n");
1654 sc->sc_ah->is_monitoring = true;
1655 } else {
1656 ath_dbg(common, ATH_DBG_CONFIG,
1657 "Monitor mode is disabled\n");
1658 sc->sc_ah->is_monitoring = false;
1659 }
1660 }
1661
1662 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
1663 struct ieee80211_channel *curchan = hw->conf.channel;
1664 int pos = curchan->hw_value;
1665 int old_pos = -1;
1666 unsigned long flags;
1667
1668 if (ah->curchan)
1669 old_pos = ah->curchan - &ah->channels[0];
1670
1671 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1672 sc->sc_flags |= SC_OP_OFFCHANNEL;
1673 else
1674 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
1675
1676 ath_dbg(common, ATH_DBG_CONFIG,
1677 "Set channel: %d MHz type: %d\n",
1678 curchan->center_freq, conf->channel_type);
1679
1680 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1681 curchan, conf->channel_type);
1682
1683 /* update survey stats for the old channel before switching */
1684 spin_lock_irqsave(&common->cc_lock, flags);
1685 ath_update_survey_stats(sc);
1686 spin_unlock_irqrestore(&common->cc_lock, flags);
1687
1688 /*
1689 * If the operating channel changes, change the survey in-use flags
1690 * along with it.
1691 * Reset the survey data for the new channel, unless we're switching
1692 * back to the operating channel from an off-channel operation.
1693 */
1694 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1695 sc->cur_survey != &sc->survey[pos]) {
1696
1697 if (sc->cur_survey)
1698 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1699
1700 sc->cur_survey = &sc->survey[pos];
1701
1702 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1703 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1704 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1705 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1706 }
1707
1708 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1709 ath_err(common, "Unable to set channel\n");
1710 mutex_unlock(&sc->mutex);
1711 return -EINVAL;
1712 }
1713
1714 /*
1715 * The most recent snapshot of channel->noisefloor for the old
1716 * channel is only available after the hardware reset. Copy it to
1717 * the survey stats now.
1718 */
1719 if (old_pos >= 0)
1720 ath_update_survey_nf(sc, old_pos);
1721 }
1722
1723 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1724 ath_dbg(common, ATH_DBG_CONFIG,
1725 "Set power: %d\n", conf->power_level);
1726 sc->config.txpowlimit = 2 * conf->power_level;
1727 ath9k_ps_wakeup(sc);
1728 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1729 sc->config.txpowlimit, &sc->curtxpow);
1730 ath9k_ps_restore(sc);
1731 }
1732
1733 if (disable_radio) {
1734 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1735 ath_radio_disable(sc, hw);
1736 }
1737
1738 mutex_unlock(&sc->mutex);
1739
1740 return 0;
1741 }
1742
1743 #define SUPPORTED_FILTERS \
1744 (FIF_PROMISC_IN_BSS | \
1745 FIF_ALLMULTI | \
1746 FIF_CONTROL | \
1747 FIF_PSPOLL | \
1748 FIF_OTHER_BSS | \
1749 FIF_BCN_PRBRESP_PROMISC | \
1750 FIF_PROBE_REQ | \
1751 FIF_FCSFAIL)
1752
1753 /* FIXME: sc->sc_full_reset ? */
1754 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1755 unsigned int changed_flags,
1756 unsigned int *total_flags,
1757 u64 multicast)
1758 {
1759 struct ath_softc *sc = hw->priv;
1760 u32 rfilt;
1761
1762 changed_flags &= SUPPORTED_FILTERS;
1763 *total_flags &= SUPPORTED_FILTERS;
1764
1765 sc->rx.rxfilter = *total_flags;
1766 ath9k_ps_wakeup(sc);
1767 rfilt = ath_calcrxfilter(sc);
1768 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1769 ath9k_ps_restore(sc);
1770
1771 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1772 "Set HW RX filter: 0x%x\n", rfilt);
1773 }
1774
1775 static int ath9k_sta_add(struct ieee80211_hw *hw,
1776 struct ieee80211_vif *vif,
1777 struct ieee80211_sta *sta)
1778 {
1779 struct ath_softc *sc = hw->priv;
1780 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1781 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1782 struct ieee80211_key_conf ps_key = { };
1783
1784 ath_node_attach(sc, sta);
1785
1786 if (vif->type != NL80211_IFTYPE_AP &&
1787 vif->type != NL80211_IFTYPE_AP_VLAN)
1788 return 0;
1789
1790 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
1791
1792 return 0;
1793 }
1794
1795 static void ath9k_del_ps_key(struct ath_softc *sc,
1796 struct ieee80211_vif *vif,
1797 struct ieee80211_sta *sta)
1798 {
1799 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1800 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1801 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1802
1803 if (!an->ps_key)
1804 return;
1805
1806 ath_key_delete(common, &ps_key);
1807 }
1808
1809 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1810 struct ieee80211_vif *vif,
1811 struct ieee80211_sta *sta)
1812 {
1813 struct ath_softc *sc = hw->priv;
1814
1815 ath9k_del_ps_key(sc, vif, sta);
1816 ath_node_detach(sc, sta);
1817
1818 return 0;
1819 }
1820
1821 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1822 struct ieee80211_vif *vif,
1823 enum sta_notify_cmd cmd,
1824 struct ieee80211_sta *sta)
1825 {
1826 struct ath_softc *sc = hw->priv;
1827 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1828
1829 switch (cmd) {
1830 case STA_NOTIFY_SLEEP:
1831 an->sleeping = true;
1832 if (ath_tx_aggr_sleep(sc, an))
1833 ieee80211_sta_set_tim(sta);
1834 break;
1835 case STA_NOTIFY_AWAKE:
1836 an->sleeping = false;
1837 ath_tx_aggr_wakeup(sc, an);
1838 break;
1839 }
1840 }
1841
1842 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
1843 const struct ieee80211_tx_queue_params *params)
1844 {
1845 struct ath_softc *sc = hw->priv;
1846 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1847 struct ath_txq *txq;
1848 struct ath9k_tx_queue_info qi;
1849 int ret = 0;
1850
1851 if (queue >= WME_NUM_AC)
1852 return 0;
1853
1854 txq = sc->tx.txq_map[queue];
1855
1856 ath9k_ps_wakeup(sc);
1857 mutex_lock(&sc->mutex);
1858
1859 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1860
1861 qi.tqi_aifs = params->aifs;
1862 qi.tqi_cwmin = params->cw_min;
1863 qi.tqi_cwmax = params->cw_max;
1864 qi.tqi_burstTime = params->txop;
1865
1866 ath_dbg(common, ATH_DBG_CONFIG,
1867 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1868 queue, txq->axq_qnum, params->aifs, params->cw_min,
1869 params->cw_max, params->txop);
1870
1871 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1872 if (ret)
1873 ath_err(common, "TXQ Update failed\n");
1874
1875 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1876 if (queue == WME_AC_BE && !ret)
1877 ath_beaconq_config(sc);
1878
1879 mutex_unlock(&sc->mutex);
1880 ath9k_ps_restore(sc);
1881
1882 return ret;
1883 }
1884
1885 static int ath9k_set_key(struct ieee80211_hw *hw,
1886 enum set_key_cmd cmd,
1887 struct ieee80211_vif *vif,
1888 struct ieee80211_sta *sta,
1889 struct ieee80211_key_conf *key)
1890 {
1891 struct ath_softc *sc = hw->priv;
1892 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1893 int ret = 0;
1894
1895 if (ath9k_modparam_nohwcrypt)
1896 return -ENOSPC;
1897
1898 if (vif->type == NL80211_IFTYPE_ADHOC &&
1899 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1900 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1901 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1902 /*
1903 * For now, disable hw crypto for the RSN IBSS group keys. This
1904 * could be optimized in the future to use a modified key cache
1905 * design to support per-STA RX GTK, but until that gets
1906 * implemented, use of software crypto for group addressed
1907 * frames is a acceptable to allow RSN IBSS to be used.
1908 */
1909 return -EOPNOTSUPP;
1910 }
1911
1912 mutex_lock(&sc->mutex);
1913 ath9k_ps_wakeup(sc);
1914 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
1915
1916 switch (cmd) {
1917 case SET_KEY:
1918 if (sta)
1919 ath9k_del_ps_key(sc, vif, sta);
1920
1921 ret = ath_key_config(common, vif, sta, key);
1922 if (ret >= 0) {
1923 key->hw_key_idx = ret;
1924 /* push IV and Michael MIC generation to stack */
1925 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1926 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1927 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1928 if (sc->sc_ah->sw_mgmt_crypto &&
1929 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1930 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
1931 ret = 0;
1932 }
1933 break;
1934 case DISABLE_KEY:
1935 ath_key_delete(common, key);
1936 break;
1937 default:
1938 ret = -EINVAL;
1939 }
1940
1941 ath9k_ps_restore(sc);
1942 mutex_unlock(&sc->mutex);
1943
1944 return ret;
1945 }
1946 static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1947 {
1948 struct ath_softc *sc = data;
1949 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1950 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1951 struct ath_vif *avp = (void *)vif->drv_priv;
1952
1953 switch (sc->sc_ah->opmode) {
1954 case NL80211_IFTYPE_ADHOC:
1955 /* There can be only one vif available */
1956 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1957 common->curaid = bss_conf->aid;
1958 ath9k_hw_write_associd(sc->sc_ah);
1959 /* configure beacon */
1960 if (bss_conf->enable_beacon)
1961 ath_beacon_config(sc, vif);
1962 break;
1963 case NL80211_IFTYPE_STATION:
1964 /*
1965 * Skip iteration if primary station vif's bss info
1966 * was not changed
1967 */
1968 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1969 break;
1970
1971 if (bss_conf->assoc) {
1972 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1973 avp->primary_sta_vif = true;
1974 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1975 common->curaid = bss_conf->aid;
1976 ath9k_hw_write_associd(sc->sc_ah);
1977 ath_dbg(common, ATH_DBG_CONFIG,
1978 "Bss Info ASSOC %d, bssid: %pM\n",
1979 bss_conf->aid, common->curbssid);
1980 ath_beacon_config(sc, vif);
1981 /*
1982 * Request a re-configuration of Beacon related timers
1983 * on the receipt of the first Beacon frame (i.e.,
1984 * after time sync with the AP).
1985 */
1986 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1987 /* Reset rssi stats */
1988 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1989 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1990
1991 sc->sc_flags |= SC_OP_ANI_RUN;
1992 ath_start_ani(common);
1993 }
1994 break;
1995 default:
1996 break;
1997 }
1998 }
1999
2000 static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2001 {
2002 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2003 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2004 struct ath_vif *avp = (void *)vif->drv_priv;
2005
2006 /* Reconfigure bss info */
2007 if (avp->primary_sta_vif && !bss_conf->assoc) {
2008 ath_dbg(common, ATH_DBG_CONFIG,
2009 "Bss Info DISASSOC %d, bssid %pM\n",
2010 common->curaid, common->curbssid);
2011 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
2012 avp->primary_sta_vif = false;
2013 memset(common->curbssid, 0, ETH_ALEN);
2014 common->curaid = 0;
2015 }
2016
2017 ieee80211_iterate_active_interfaces_atomic(
2018 sc->hw, ath9k_bss_iter, sc);
2019
2020 /*
2021 * None of station vifs are associated.
2022 * Clear bssid & aid
2023 */
2024 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
2025 !(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
2026 ath9k_hw_write_associd(sc->sc_ah);
2027 /* Stop ANI */
2028 sc->sc_flags &= ~SC_OP_ANI_RUN;
2029 del_timer_sync(&common->ani.timer);
2030 }
2031 }
2032
2033 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2034 struct ieee80211_vif *vif,
2035 struct ieee80211_bss_conf *bss_conf,
2036 u32 changed)
2037 {
2038 struct ath_softc *sc = hw->priv;
2039 struct ath_hw *ah = sc->sc_ah;
2040 struct ath_common *common = ath9k_hw_common(ah);
2041 struct ath_vif *avp = (void *)vif->drv_priv;
2042 int slottime;
2043 int error;
2044
2045 ath9k_ps_wakeup(sc);
2046 mutex_lock(&sc->mutex);
2047
2048 if (changed & BSS_CHANGED_BSSID) {
2049 ath9k_config_bss(sc, vif);
2050
2051 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2052 common->curbssid, common->curaid);
2053 }
2054
2055 /* Enable transmission of beacons (AP, IBSS, MESH) */
2056 if ((changed & BSS_CHANGED_BEACON) ||
2057 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2058 ath9k_set_beaconing_status(sc, false);
2059 error = ath_beacon_alloc(sc, vif);
2060 if (!error)
2061 ath_beacon_config(sc, vif);
2062 ath9k_set_beaconing_status(sc, true);
2063 }
2064
2065 if (changed & BSS_CHANGED_ERP_SLOT) {
2066 if (bss_conf->use_short_slot)
2067 slottime = 9;
2068 else
2069 slottime = 20;
2070 if (vif->type == NL80211_IFTYPE_AP) {
2071 /*
2072 * Defer update, so that connected stations can adjust
2073 * their settings at the same time.
2074 * See beacon.c for more details
2075 */
2076 sc->beacon.slottime = slottime;
2077 sc->beacon.updateslot = UPDATE;
2078 } else {
2079 ah->slottime = slottime;
2080 ath9k_hw_init_global_settings(ah);
2081 }
2082 }
2083
2084 /* Disable transmission of beacons */
2085 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2086 !bss_conf->enable_beacon) {
2087 ath9k_set_beaconing_status(sc, false);
2088 avp->is_bslot_active = false;
2089 ath9k_set_beaconing_status(sc, true);
2090 }
2091
2092 if (changed & BSS_CHANGED_BEACON_INT) {
2093 /*
2094 * In case of AP mode, the HW TSF has to be reset
2095 * when the beacon interval changes.
2096 */
2097 if (vif->type == NL80211_IFTYPE_AP) {
2098 sc->sc_flags |= SC_OP_TSF_RESET;
2099 ath9k_set_beaconing_status(sc, false);
2100 error = ath_beacon_alloc(sc, vif);
2101 if (!error)
2102 ath_beacon_config(sc, vif);
2103 ath9k_set_beaconing_status(sc, true);
2104 } else
2105 ath_beacon_config(sc, vif);
2106 }
2107
2108 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2109 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2110 bss_conf->use_short_preamble);
2111 if (bss_conf->use_short_preamble)
2112 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2113 else
2114 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2115 }
2116
2117 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2118 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2119 bss_conf->use_cts_prot);
2120 if (bss_conf->use_cts_prot &&
2121 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2122 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2123 else
2124 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2125 }
2126
2127 mutex_unlock(&sc->mutex);
2128 ath9k_ps_restore(sc);
2129 }
2130
2131 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2132 {
2133 struct ath_softc *sc = hw->priv;
2134 u64 tsf;
2135
2136 mutex_lock(&sc->mutex);
2137 ath9k_ps_wakeup(sc);
2138 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2139 ath9k_ps_restore(sc);
2140 mutex_unlock(&sc->mutex);
2141
2142 return tsf;
2143 }
2144
2145 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2146 {
2147 struct ath_softc *sc = hw->priv;
2148
2149 mutex_lock(&sc->mutex);
2150 ath9k_ps_wakeup(sc);
2151 ath9k_hw_settsf64(sc->sc_ah, tsf);
2152 ath9k_ps_restore(sc);
2153 mutex_unlock(&sc->mutex);
2154 }
2155
2156 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2157 {
2158 struct ath_softc *sc = hw->priv;
2159
2160 mutex_lock(&sc->mutex);
2161
2162 ath9k_ps_wakeup(sc);
2163 ath9k_hw_reset_tsf(sc->sc_ah);
2164 ath9k_ps_restore(sc);
2165
2166 mutex_unlock(&sc->mutex);
2167 }
2168
2169 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2170 struct ieee80211_vif *vif,
2171 enum ieee80211_ampdu_mlme_action action,
2172 struct ieee80211_sta *sta,
2173 u16 tid, u16 *ssn, u8 buf_size)
2174 {
2175 struct ath_softc *sc = hw->priv;
2176 int ret = 0;
2177
2178 local_bh_disable();
2179
2180 switch (action) {
2181 case IEEE80211_AMPDU_RX_START:
2182 if (!(sc->sc_flags & SC_OP_RXAGGR))
2183 ret = -ENOTSUPP;
2184 break;
2185 case IEEE80211_AMPDU_RX_STOP:
2186 break;
2187 case IEEE80211_AMPDU_TX_START:
2188 if (!(sc->sc_flags & SC_OP_TXAGGR))
2189 return -EOPNOTSUPP;
2190
2191 ath9k_ps_wakeup(sc);
2192 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2193 if (!ret)
2194 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2195 ath9k_ps_restore(sc);
2196 break;
2197 case IEEE80211_AMPDU_TX_STOP:
2198 ath9k_ps_wakeup(sc);
2199 ath_tx_aggr_stop(sc, sta, tid);
2200 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2201 ath9k_ps_restore(sc);
2202 break;
2203 case IEEE80211_AMPDU_TX_OPERATIONAL:
2204 ath9k_ps_wakeup(sc);
2205 ath_tx_aggr_resume(sc, sta, tid);
2206 ath9k_ps_restore(sc);
2207 break;
2208 default:
2209 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2210 }
2211
2212 local_bh_enable();
2213
2214 return ret;
2215 }
2216
2217 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2218 struct survey_info *survey)
2219 {
2220 struct ath_softc *sc = hw->priv;
2221 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2222 struct ieee80211_supported_band *sband;
2223 struct ieee80211_channel *chan;
2224 unsigned long flags;
2225 int pos;
2226
2227 spin_lock_irqsave(&common->cc_lock, flags);
2228 if (idx == 0)
2229 ath_update_survey_stats(sc);
2230
2231 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2232 if (sband && idx >= sband->n_channels) {
2233 idx -= sband->n_channels;
2234 sband = NULL;
2235 }
2236
2237 if (!sband)
2238 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
2239
2240 if (!sband || idx >= sband->n_channels) {
2241 spin_unlock_irqrestore(&common->cc_lock, flags);
2242 return -ENOENT;
2243 }
2244
2245 chan = &sband->channels[idx];
2246 pos = chan->hw_value;
2247 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2248 survey->channel = chan;
2249 spin_unlock_irqrestore(&common->cc_lock, flags);
2250
2251 return 0;
2252 }
2253
2254 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2255 {
2256 struct ath_softc *sc = hw->priv;
2257 struct ath_hw *ah = sc->sc_ah;
2258
2259 mutex_lock(&sc->mutex);
2260 ah->coverage_class = coverage_class;
2261 ath9k_hw_init_global_settings(ah);
2262 mutex_unlock(&sc->mutex);
2263 }
2264
2265 static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2266 {
2267 struct ath_softc *sc = hw->priv;
2268 struct ath_hw *ah = sc->sc_ah;
2269 struct ath_common *common = ath9k_hw_common(ah);
2270 int timeout = 200; /* ms */
2271 int i, j;
2272 bool drain_txq;
2273
2274 mutex_lock(&sc->mutex);
2275 cancel_delayed_work_sync(&sc->tx_complete_work);
2276
2277 if (sc->sc_flags & SC_OP_INVALID) {
2278 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
2279 mutex_unlock(&sc->mutex);
2280 return;
2281 }
2282
2283 if (drop)
2284 timeout = 1;
2285
2286 for (j = 0; j < timeout; j++) {
2287 bool npend = false;
2288
2289 if (j)
2290 usleep_range(1000, 2000);
2291
2292 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2293 if (!ATH_TXQ_SETUP(sc, i))
2294 continue;
2295
2296 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2297
2298 if (npend)
2299 break;
2300 }
2301
2302 if (!npend)
2303 goto out;
2304 }
2305
2306 ath9k_ps_wakeup(sc);
2307 spin_lock_bh(&sc->sc_pcu_lock);
2308 drain_txq = ath_drain_all_txq(sc, false);
2309 spin_unlock_bh(&sc->sc_pcu_lock);
2310 if (!drain_txq)
2311 ath_reset(sc, false);
2312 ath9k_ps_restore(sc);
2313 ieee80211_wake_queues(hw);
2314
2315 out:
2316 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2317 mutex_unlock(&sc->mutex);
2318 }
2319
2320 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2321 {
2322 struct ath_softc *sc = hw->priv;
2323 int i;
2324
2325 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2326 if (!ATH_TXQ_SETUP(sc, i))
2327 continue;
2328
2329 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2330 return true;
2331 }
2332 return false;
2333 }
2334
2335 struct ieee80211_ops ath9k_ops = {
2336 .tx = ath9k_tx,
2337 .start = ath9k_start,
2338 .stop = ath9k_stop,
2339 .add_interface = ath9k_add_interface,
2340 .change_interface = ath9k_change_interface,
2341 .remove_interface = ath9k_remove_interface,
2342 .config = ath9k_config,
2343 .configure_filter = ath9k_configure_filter,
2344 .sta_add = ath9k_sta_add,
2345 .sta_remove = ath9k_sta_remove,
2346 .sta_notify = ath9k_sta_notify,
2347 .conf_tx = ath9k_conf_tx,
2348 .bss_info_changed = ath9k_bss_info_changed,
2349 .set_key = ath9k_set_key,
2350 .get_tsf = ath9k_get_tsf,
2351 .set_tsf = ath9k_set_tsf,
2352 .reset_tsf = ath9k_reset_tsf,
2353 .ampdu_action = ath9k_ampdu_action,
2354 .get_survey = ath9k_get_survey,
2355 .rfkill_poll = ath9k_rfkill_poll_state,
2356 .set_coverage_class = ath9k_set_coverage_class,
2357 .flush = ath9k_flush,
2358 .tx_frames_pending = ath9k_tx_frames_pending,
2359 };