drivers/net/wireless/iwlegacy/iwl-3945-hw.h

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 /*
  64  * Please use this file (iwl-3945-hw.h) only for hardware-related definitions.
  65  * Please use iwl-commands.h for uCode API definitions.
  66  * Please use iwl-3945.h for driver implementation definitions.
  67  */
  68
  69 #ifndef __iwl_3945_hw__
  70 #define __iwl_3945_hw__
  71
  72 #include "iwl-eeprom.h"
  73
  74 /* RSSI to dBm */
  75 #define IWL39_RSSI_OFFSET       95
  76
  77 /*
  78  * EEPROM related constants, enums, and structures.
  79  */
  80 #define EEPROM_SKU_CAP_OP_MODE_MRC                      (1 << 7)
  81
  82 /*
  83  * Mapping of a Tx power level, at factory calibration temperature,
  84  *   to a radio/DSP gain table index.
  85  * One for each of 5 "sample" power levels in each band.
  86  * v_det is measured at the factory, using the 3945's built-in power amplifier
  87  *   (PA) output voltage detector.  This same detector is used during Tx of
  88  *   long packets in normal operation to provide feedback as to proper output
  89  *   level.
  90  * Data copied from EEPROM.
  91  * DO NOT ALTER THIS STRUCTURE!!!
  92  */
  93 struct iwl3945_eeprom_txpower_sample {
  94         u8 gain_index;          /* index into power (gain) setup table ... */
  95         s8 power;               /* ... for this pwr level for this chnl group */
  96         u16 v_det;              /* PA output voltage */
  97 } __packed;
  98
  99 /*
 100  * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
 101  * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
 102  * Tx power setup code interpolates between the 5 "sample" power levels
 103  *    to determine the nominal setup for a requested power level.
 104  * Data copied from EEPROM.
 105  * DO NOT ALTER THIS STRUCTURE!!!
 106  */
 107 struct iwl3945_eeprom_txpower_group {
 108         struct iwl3945_eeprom_txpower_sample samples[5];  /* 5 power levels */
 109         s32 a, b, c, d, e;      /* coefficients for voltage->power
 110                                  * formula (signed) */
 111         s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
 112                                  * frequency (signed) */
 113         s8 saturation_power;    /* highest power possible by h/w in this
 114                                  * band */
 115         u8 group_channel;       /* "representative" channel # in this band */
 116         s16 temperature;        /* h/w temperature at factory calib this band
 117                                  * (signed) */
 118 } __packed;
 119
 120 /*
 121  * Temperature-based Tx-power compensation data, not band-specific.
 122  * These coefficients are use to modify a/b/c/d/e coeffs based on
 123  *   difference between current temperature and factory calib temperature.
 124  * Data copied from EEPROM.
 125  */
 126 struct iwl3945_eeprom_temperature_corr {
 127         u32 Ta;
 128         u32 Tb;
 129         u32 Tc;
 130         u32 Td;
 131         u32 Te;
 132 } __packed;
 133
 134 /*
 135  * EEPROM map
 136  */
 137 struct iwl3945_eeprom {
 138         u8 reserved0[16];
 139         u16 device_id;  /* abs.ofs: 16 */
 140         u8 reserved1[2];
 141         u16 pmc;                /* abs.ofs: 20 */
 142         u8 reserved2[20];
 143         u8 mac_address[6];      /* abs.ofs: 42 */
 144         u8 reserved3[58];
 145         u16 board_revision;     /* abs.ofs: 106 */
 146         u8 reserved4[11];
 147         u8 board_pba_number[9]; /* abs.ofs: 119 */
 148         u8 reserved5[8];
 149         u16 version;            /* abs.ofs: 136 */
 150         u8 sku_cap;             /* abs.ofs: 138 */
 151         u8 leds_mode;           /* abs.ofs: 139 */
 152         u16 oem_mode;
 153         u16 wowlan_mode;        /* abs.ofs: 142 */
 154         u16 leds_time_interval; /* abs.ofs: 144 */
 155         u8 leds_off_time;       /* abs.ofs: 146 */
 156         u8 leds_on_time;        /* abs.ofs: 147 */
 157         u8 almgor_m_version;    /* abs.ofs: 148 */
 158         u8 antenna_switch_type; /* abs.ofs: 149 */
 159         u8 reserved6[42];
 160         u8 sku_id[4];           /* abs.ofs: 192 */
 161
 162 /*
 163  * Per-channel regulatory data.
 164  *
 165  * Each channel that *might* be supported by 3945 has a fixed location
 166  * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
 167  * txpower (MSB).
 168  *
 169  * Entries immediately below are for 20 MHz channel width.
 170  *
 171  * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 172  */
 173         u16 band_1_count;       /* abs.ofs: 196 */
 174         struct iwl_eeprom_channel band_1_channels[14];  /* abs.ofs: 198 */
 175
 176 /*
 177  * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
 178  * 5.0 GHz channels 7, 8, 11, 12, 16
 179  * (4915-5080MHz) (none of these is ever supported)
 180  */
 181         u16 band_2_count;       /* abs.ofs: 226 */
 182         struct iwl_eeprom_channel band_2_channels[13];  /* abs.ofs: 228 */
 183
 184 /*
 185  * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
 186  * (5170-5320MHz)
 187  */
 188         u16 band_3_count;       /* abs.ofs: 254 */
 189         struct iwl_eeprom_channel band_3_channels[12];  /* abs.ofs: 256 */
 190
 191 /*
 192  * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
 193  * (5500-5700MHz)
 194  */
 195         u16 band_4_count;       /* abs.ofs: 280 */
 196         struct iwl_eeprom_channel band_4_channels[11];  /* abs.ofs: 282 */
 197
 198 /*
 199  * 5.7 GHz channels 145, 149, 153, 157, 161, 165
 200  * (5725-5825MHz)
 201  */
 202         u16 band_5_count;       /* abs.ofs: 304 */
 203         struct iwl_eeprom_channel band_5_channels[6];  /* abs.ofs: 306 */
 204
 205         u8 reserved9[194];
 206
 207 /*
 208  * 3945 Txpower calibration data.
 209  */
 210 #define IWL_NUM_TX_CALIB_GROUPS 5
 211         struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS];
 212 /* abs.ofs: 512 */
 213         struct iwl3945_eeprom_temperature_corr corrections;  /* abs.ofs: 832 */
 214         u8 reserved16[172];     /* fill out to full 1024 byte block */
 215 } __packed;
 216
 217 #define IWL3945_EEPROM_IMG_SIZE 1024
 218
 219 /* End of EEPROM */
 220
 221 #define PCI_CFG_REV_ID_BIT_BASIC_SKU                (0x40)      /* bit 6    */
 222 #define PCI_CFG_REV_ID_BIT_RTP                      (0x80)      /* bit 7    */
 223
 224 /* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */
 225 #define IWL39_NUM_QUEUES        5
 226 #define IWL39_CMD_QUEUE_NUM     4
 227
 228 #define IWL_DEFAULT_TX_RETRY  15
 229
 230 /*********************************************/
 231
 232 #define RFD_SIZE                              4
 233 #define NUM_TFD_CHUNKS                        4
 234
 235 #define RX_QUEUE_SIZE                         256
 236 #define RX_QUEUE_MASK                         255
 237 #define RX_QUEUE_SIZE_LOG                     8
 238
 239 #define U32_PAD(n)              ((4-(n))&0x3)
 240
 241 #define TFD_CTL_COUNT_SET(n)       (n << 24)
 242 #define TFD_CTL_COUNT_GET(ctl)     ((ctl >> 24) & 7)
 243 #define TFD_CTL_PAD_SET(n)         (n << 28)
 244 #define TFD_CTL_PAD_GET(ctl)       (ctl >> 28)
 245
 246 /* Sizes and addresses for instruction and data memory (SRAM) in
 247  * 3945's embedded processor.  Driver access is via HBUS_TARG_MEM_* regs. */
 248 #define IWL39_RTC_INST_LOWER_BOUND              (0x000000)
 249 #define IWL39_RTC_INST_UPPER_BOUND              (0x014000)
 250
 251 #define IWL39_RTC_DATA_LOWER_BOUND              (0x800000)
 252 #define IWL39_RTC_DATA_UPPER_BOUND              (0x808000)
 253
 254 #define IWL39_RTC_INST_SIZE (IWL39_RTC_INST_UPPER_BOUND - \
 255                                 IWL39_RTC_INST_LOWER_BOUND)
 256 #define IWL39_RTC_DATA_SIZE (IWL39_RTC_DATA_UPPER_BOUND - \
 257                                 IWL39_RTC_DATA_LOWER_BOUND)
 258
 259 #define IWL39_MAX_INST_SIZE IWL39_RTC_INST_SIZE
 260 #define IWL39_MAX_DATA_SIZE IWL39_RTC_DATA_SIZE
 261
 262 /* Size of uCode instruction memory in bootstrap state machine */
 263 #define IWL39_MAX_BSM_SIZE IWL39_RTC_INST_SIZE
 264
 265 static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr)
 266 {
 267         return (addr >= IWL39_RTC_DATA_LOWER_BOUND) &&
 268                (addr < IWL39_RTC_DATA_UPPER_BOUND);
 269 }
 270
 271 /* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE
 272  * and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */
 273 struct iwl3945_shared {
 274         __le32 tx_base_ptr[8];
 275 } __packed;
 276
 277 static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags)
 278 {
 279         return le16_to_cpu(rate_n_flags) & 0xFF;
 280 }
 281
 282 static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags)
 283 {
 284         return le16_to_cpu(rate_n_flags);
 285 }
 286
 287 static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags)
 288 {
 289         return cpu_to_le16((u16)rate|flags);
 290 }
 291 #endif