?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sfc: Don't use enums as a bitmask.
[zen-stable.git] / drivers / net / wireless / iwlegacy / iwl-3945.c
blobd096dc28204d70a60df4391163e6cd0500fc6326
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/sched.h>
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/wireless.h>
38 #include <linux/firmware.h>
39 #include <linux/etherdevice.h>
40 #include <asm/unaligned.h>
41 #include <net/mac80211.h>
42
43 #include "iwl-fh.h"
44 #include "iwl-3945-fh.h"
45 #include "iwl-commands.h"
46 #include "iwl-sta.h"
47 #include "iwl-3945.h"
48 #include "iwl-eeprom.h"
49 #include "iwl-core.h"
50 #include "iwl-helpers.h"
51 #include "iwl-led.h"
52 #include "iwl-3945-led.h"
53 #include "iwl-3945-debugfs.h"
54
55 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
56 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
57 IWL_RATE_##r##M_IEEE, \
58 IWL_RATE_##ip##M_INDEX, \
59 IWL_RATE_##in##M_INDEX, \
60 IWL_RATE_##rp##M_INDEX, \
61 IWL_RATE_##rn##M_INDEX, \
62 IWL_RATE_##pp##M_INDEX, \
63 IWL_RATE_##np##M_INDEX, \
64 IWL_RATE_##r##M_INDEX_TABLE, \
65 IWL_RATE_##ip##M_INDEX_TABLE }
66
67 /*
68 * Parameter order:
69 * rate, prev rate, next rate, prev tgg rate, next tgg rate
70 *
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
73 *
74 */
75 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
76 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
80 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
88 };
89
90 static inline u8 iwl3945_get_prev_ieee_rate(u8 rate_index)
91 {
92 u8 rate = iwl3945_rates[rate_index].prev_ieee;
93
94 if (rate == IWL_RATE_INVALID)
95 rate = rate_index;
96 return rate;
97 }
98
99 /* 1 = enable the iwl3945_disable_events() function */
100 #define IWL_EVT_DISABLE (0)
101 #define IWL_EVT_DISABLE_SIZE (1532/32)
102
103 /**
104 * iwl3945_disable_events - Disable selected events in uCode event log
105 *
106 * Disable an event by writing "1"s into "disable"
107 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
108 * Default values of 0 enable uCode events to be logged.
109 * Use for only special debugging. This function is just a placeholder as-is,
110 * you'll need to provide the special bits! ...
111 * ... and set IWL_EVT_DISABLE to 1. */
112 void iwl3945_disable_events(struct iwl_priv *priv)
113 {
114 int i;
115 u32 base; /* SRAM address of event log header */
116 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
117 u32 array_size; /* # of u32 entries in array */
118 static const u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
119 0x00000000, /* 31 - 0 Event id numbers */
120 0x00000000, /* 63 - 32 */
121 0x00000000, /* 95 - 64 */
122 0x00000000, /* 127 - 96 */
123 0x00000000, /* 159 - 128 */
124 0x00000000, /* 191 - 160 */
125 0x00000000, /* 223 - 192 */
126 0x00000000, /* 255 - 224 */
127 0x00000000, /* 287 - 256 */
128 0x00000000, /* 319 - 288 */
129 0x00000000, /* 351 - 320 */
130 0x00000000, /* 383 - 352 */
131 0x00000000, /* 415 - 384 */
132 0x00000000, /* 447 - 416 */
133 0x00000000, /* 479 - 448 */
134 0x00000000, /* 511 - 480 */
135 0x00000000, /* 543 - 512 */
136 0x00000000, /* 575 - 544 */
137 0x00000000, /* 607 - 576 */
138 0x00000000, /* 639 - 608 */
139 0x00000000, /* 671 - 640 */
140 0x00000000, /* 703 - 672 */
141 0x00000000, /* 735 - 704 */
142 0x00000000, /* 767 - 736 */
143 0x00000000, /* 799 - 768 */
144 0x00000000, /* 831 - 800 */
145 0x00000000, /* 863 - 832 */
146 0x00000000, /* 895 - 864 */
147 0x00000000, /* 927 - 896 */
148 0x00000000, /* 959 - 928 */
149 0x00000000, /* 991 - 960 */
150 0x00000000, /* 1023 - 992 */
151 0x00000000, /* 1055 - 1024 */
152 0x00000000, /* 1087 - 1056 */
153 0x00000000, /* 1119 - 1088 */
154 0x00000000, /* 1151 - 1120 */
155 0x00000000, /* 1183 - 1152 */
156 0x00000000, /* 1215 - 1184 */
157 0x00000000, /* 1247 - 1216 */
158 0x00000000, /* 1279 - 1248 */
159 0x00000000, /* 1311 - 1280 */
160 0x00000000, /* 1343 - 1312 */
161 0x00000000, /* 1375 - 1344 */
162 0x00000000, /* 1407 - 1376 */
163 0x00000000, /* 1439 - 1408 */
164 0x00000000, /* 1471 - 1440 */
165 0x00000000, /* 1503 - 1472 */
166 };
167
168 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
169 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
170 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
171 return;
172 }
173
174 disable_ptr = iwl_legacy_read_targ_mem(priv, base + (4 * sizeof(u32)));
175 array_size = iwl_legacy_read_targ_mem(priv, base + (5 * sizeof(u32)));
176
177 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
178 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
179 disable_ptr);
180 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
181 iwl_legacy_write_targ_mem(priv,
182 disable_ptr + (i * sizeof(u32)),
183 evt_disable[i]);
184
185 } else {
186 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
187 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
188 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
189 disable_ptr, array_size);
190 }
191
192 }
193
194 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
195 {
196 int idx;
197
198 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
199 if (iwl3945_rates[idx].plcp == plcp)
200 return idx;
201 return -1;
202 }
203
204 #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
205 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
206
207 static const char *iwl3945_get_tx_fail_reason(u32 status)
208 {
209 switch (status & TX_STATUS_MSK) {
210 case TX_3945_STATUS_SUCCESS:
211 return "SUCCESS";
212 TX_STATUS_ENTRY(SHORT_LIMIT);
213 TX_STATUS_ENTRY(LONG_LIMIT);
214 TX_STATUS_ENTRY(FIFO_UNDERRUN);
215 TX_STATUS_ENTRY(MGMNT_ABORT);
216 TX_STATUS_ENTRY(NEXT_FRAG);
217 TX_STATUS_ENTRY(LIFE_EXPIRE);
218 TX_STATUS_ENTRY(DEST_PS);
219 TX_STATUS_ENTRY(ABORTED);
220 TX_STATUS_ENTRY(BT_RETRY);
221 TX_STATUS_ENTRY(STA_INVALID);
222 TX_STATUS_ENTRY(FRAG_DROPPED);
223 TX_STATUS_ENTRY(TID_DISABLE);
224 TX_STATUS_ENTRY(FRAME_FLUSHED);
225 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
226 TX_STATUS_ENTRY(TX_LOCKED);
227 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
228 }
229
230 return "UNKNOWN";
231 }
232 #else
233 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
234 {
235 return "";
236 }
237 #endif
238
239 /*
240 * get ieee prev rate from rate scale table.
241 * for A and B mode we need to overright prev
242 * value
243 */
244 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
245 {
246 int next_rate = iwl3945_get_prev_ieee_rate(rate);
247
248 switch (priv->band) {
249 case IEEE80211_BAND_5GHZ:
250 if (rate == IWL_RATE_12M_INDEX)
251 next_rate = IWL_RATE_9M_INDEX;
252 else if (rate == IWL_RATE_6M_INDEX)
253 next_rate = IWL_RATE_6M_INDEX;
254 break;
255 case IEEE80211_BAND_2GHZ:
256 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
257 iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS)) {
258 if (rate == IWL_RATE_11M_INDEX)
259 next_rate = IWL_RATE_5M_INDEX;
260 }
261 break;
262
263 default:
264 break;
265 }
266
267 return next_rate;
268 }
269
270
271 /**
272 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
273 *
274 * When FW advances 'R' index, all entries between old and new 'R' index
275 * need to be reclaimed. As result, some free space forms. If there is
276 * enough free space (> low mark), wake the stack that feeds us.
277 */
278 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
279 int txq_id, int index)
280 {
281 struct iwl_tx_queue *txq = &priv->txq[txq_id];
282 struct iwl_queue *q = &txq->q;
283 struct iwl_tx_info *tx_info;
284
285 BUG_ON(txq_id == IWL39_CMD_QUEUE_NUM);
286
287 for (index = iwl_legacy_queue_inc_wrap(index, q->n_bd);
288 q->read_ptr != index;
289 q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd)) {
290
291 tx_info = &txq->txb[txq->q.read_ptr];
292 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
293 tx_info->skb = NULL;
294 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
295 }
296
297 if (iwl_legacy_queue_space(q) > q->low_mark && (txq_id >= 0) &&
298 (txq_id != IWL39_CMD_QUEUE_NUM) &&
299 priv->mac80211_registered)
300 iwl_legacy_wake_queue(priv, txq);
301 }
302
303 /**
304 * iwl3945_rx_reply_tx - Handle Tx response
305 */
306 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
307 struct iwl_rx_mem_buffer *rxb)
308 {
309 struct iwl_rx_packet *pkt = rxb_addr(rxb);
310 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
311 int txq_id = SEQ_TO_QUEUE(sequence);
312 int index = SEQ_TO_INDEX(sequence);
313 struct iwl_tx_queue *txq = &priv->txq[txq_id];
314 struct ieee80211_tx_info *info;
315 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
316 u32 status = le32_to_cpu(tx_resp->status);
317 int rate_idx;
318 int fail;
319
320 if ((index >= txq->q.n_bd) || (iwl_legacy_queue_used(&txq->q, index) == 0)) {
321 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
322 "is out of range [0-%d] %d %d\n", txq_id,
323 index, txq->q.n_bd, txq->q.write_ptr,
324 txq->q.read_ptr);
325 return;
326 }
327
328 txq->time_stamp = jiffies;
329 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
330 ieee80211_tx_info_clear_status(info);
331
332 /* Fill the MRR chain with some info about on-chip retransmissions */
333 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
334 if (info->band == IEEE80211_BAND_5GHZ)
335 rate_idx -= IWL_FIRST_OFDM_RATE;
336
337 fail = tx_resp->failure_frame;
338
339 info->status.rates[0].idx = rate_idx;
340 info->status.rates[0].count = fail + 1; /* add final attempt */
341
342 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
343 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
344 IEEE80211_TX_STAT_ACK : 0;
345
346 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
347 txq_id, iwl3945_get_tx_fail_reason(status), status,
348 tx_resp->rate, tx_resp->failure_frame);
349
350 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
351 iwl3945_tx_queue_reclaim(priv, txq_id, index);
352
353 if (status & TX_ABORT_REQUIRED_MSK)
354 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
355 }
356
357
358
359 /*****************************************************************************
360 *
361 * Intel PRO/Wireless 3945ABG/BG Network Connection
362 *
363 * RX handler implementations
364 *
365 *****************************************************************************/
366 #ifdef CONFIG_IWLWIFI_LEGACY_DEBUGFS
367 static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
368 __le32 *stats)
369 {
370 int i;
371 __le32 *prev_stats;
372 u32 *accum_stats;
373 u32 *delta, *max_delta;
374
375 prev_stats = (__le32 *)&priv->_3945.statistics;
376 accum_stats = (u32 *)&priv->_3945.accum_statistics;
377 delta = (u32 *)&priv->_3945.delta_statistics;
378 max_delta = (u32 *)&priv->_3945.max_delta;
379
380 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
381 i += sizeof(__le32), stats++, prev_stats++, delta++,
382 max_delta++, accum_stats++) {
383 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
384 *delta = (le32_to_cpu(*stats) -
385 le32_to_cpu(*prev_stats));
386 *accum_stats += *delta;
387 if (*delta > *max_delta)
388 *max_delta = *delta;
389 }
390 }
391
392 /* reset accumulative statistics for "no-counter" type statistics */
393 priv->_3945.accum_statistics.general.temperature =
394 priv->_3945.statistics.general.temperature;
395 priv->_3945.accum_statistics.general.ttl_timestamp =
396 priv->_3945.statistics.general.ttl_timestamp;
397 }
398 #endif
399
400 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
401 struct iwl_rx_mem_buffer *rxb)
402 {
403 struct iwl_rx_packet *pkt = rxb_addr(rxb);
404
405 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
406 (int)sizeof(struct iwl3945_notif_statistics),
407 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
408 #ifdef CONFIG_IWLWIFI_LEGACY_DEBUGFS
409 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
410 #endif
411 iwl_legacy_recover_from_statistics(priv, pkt);
412
413 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
414 }
415
416 void iwl3945_reply_statistics(struct iwl_priv *priv,
417 struct iwl_rx_mem_buffer *rxb)
418 {
419 struct iwl_rx_packet *pkt = rxb_addr(rxb);
420 __le32 *flag = (__le32 *)&pkt->u.raw;
421
422 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
423 #ifdef CONFIG_IWLWIFI_LEGACY_DEBUGFS
424 memset(&priv->_3945.accum_statistics, 0,
425 sizeof(struct iwl3945_notif_statistics));
426 memset(&priv->_3945.delta_statistics, 0,
427 sizeof(struct iwl3945_notif_statistics));
428 memset(&priv->_3945.max_delta, 0,
429 sizeof(struct iwl3945_notif_statistics));
430 #endif
431 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
432 }
433 iwl3945_hw_rx_statistics(priv, rxb);
434 }
435
436
437 /******************************************************************************
438 *
439 * Misc. internal state and helper functions
440 *
441 ******************************************************************************/
442
443 /* This is necessary only for a number of statistics, see the caller. */
444 static int iwl3945_is_network_packet(struct iwl_priv *priv,
445 struct ieee80211_hdr *header)
446 {
447 /* Filter incoming packets to determine if they are targeted toward
448 * this network, discarding packets coming from ourselves */
449 switch (priv->iw_mode) {
450 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
451 /* packets to our IBSS update information */
452 return !compare_ether_addr(header->addr3, priv->bssid);
453 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
454 /* packets to our IBSS update information */
455 return !compare_ether_addr(header->addr2, priv->bssid);
456 default:
457 return 1;
458 }
459 }
460
461 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
462 struct iwl_rx_mem_buffer *rxb,
463 struct ieee80211_rx_status *stats)
464 {
465 struct iwl_rx_packet *pkt = rxb_addr(rxb);
466 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
467 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
468 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
469 u16 len = le16_to_cpu(rx_hdr->len);
470 struct sk_buff *skb;
471 __le16 fc = hdr->frame_control;
472
473 /* We received data from the HW, so stop the watchdog */
474 if (unlikely(len + IWL39_RX_FRAME_SIZE >
475 PAGE_SIZE << priv->hw_params.rx_page_order)) {
476 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
477 return;
478 }
479
480 /* We only process data packets if the interface is open */
481 if (unlikely(!priv->is_open)) {
482 IWL_DEBUG_DROP_LIMIT(priv,
483 "Dropping packet while interface is not open.\n");
484 return;
485 }
486
487 skb = dev_alloc_skb(128);
488 if (!skb) {
489 IWL_ERR(priv, "dev_alloc_skb failed\n");
490 return;
491 }
492
493 if (!iwl3945_mod_params.sw_crypto)
494 iwl_legacy_set_decrypted_flag(priv,
495 (struct ieee80211_hdr *)rxb_addr(rxb),
496 le32_to_cpu(rx_end->status), stats);
497
498 skb_add_rx_frag(skb, 0, rxb->page,
499 (void *)rx_hdr->payload - (void *)pkt, len);
500
501 iwl_legacy_update_stats(priv, false, fc, len);
502 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
503
504 ieee80211_rx(priv->hw, skb);
505 priv->alloc_rxb_page--;
506 rxb->page = NULL;
507 }
508
509 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
510
511 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
512 struct iwl_rx_mem_buffer *rxb)
513 {
514 struct ieee80211_hdr *header;
515 struct ieee80211_rx_status rx_status;
516 struct iwl_rx_packet *pkt = rxb_addr(rxb);
517 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
518 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
519 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
520 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
521 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
522 u8 network_packet;
523
524 rx_status.flag = 0;
525 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
526 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
527 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
528 rx_status.freq =
529 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel),
530 rx_status.band);
531
532 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
533 if (rx_status.band == IEEE80211_BAND_5GHZ)
534 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
535
536 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
537 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
538
539 /* set the preamble flag if appropriate */
540 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
541 rx_status.flag |= RX_FLAG_SHORTPRE;
542
543 if ((unlikely(rx_stats->phy_count > 20))) {
544 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
545 rx_stats->phy_count);
546 return;
547 }
548
549 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
550 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
551 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
552 return;
553 }
554
555
556
557 /* Convert 3945's rssi indicator to dBm */
558 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
559
560 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
561 rx_status.signal, rx_stats_sig_avg,
562 rx_stats_noise_diff);
563
564 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
565
566 network_packet = iwl3945_is_network_packet(priv, header);
567
568 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
569 network_packet ? '*' : ' ',
570 le16_to_cpu(rx_hdr->channel),
571 rx_status.signal, rx_status.signal,
572 rx_status.rate_idx);
573
574 iwl_legacy_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len),
575 header);
576
577 if (network_packet) {
578 priv->_3945.last_beacon_time =
579 le32_to_cpu(rx_end->beacon_timestamp);
580 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
581 priv->_3945.last_rx_rssi = rx_status.signal;
582 }
583
584 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
585 }
586
587 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
588 struct iwl_tx_queue *txq,
589 dma_addr_t addr, u16 len, u8 reset, u8 pad)
590 {
591 int count;
592 struct iwl_queue *q;
593 struct iwl3945_tfd *tfd, *tfd_tmp;
594
595 q = &txq->q;
596 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
597 tfd = &tfd_tmp[q->write_ptr];
598
599 if (reset)
600 memset(tfd, 0, sizeof(*tfd));
601
602 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
603
604 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
605 IWL_ERR(priv, "Error can not send more than %d chunks\n",
606 NUM_TFD_CHUNKS);
607 return -EINVAL;
608 }
609
610 tfd->tbs[count].addr = cpu_to_le32(addr);
611 tfd->tbs[count].len = cpu_to_le32(len);
612
613 count++;
614
615 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
616 TFD_CTL_PAD_SET(pad));
617
618 return 0;
619 }
620
621 /**
622 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
623 *
624 * Does NOT advance any indexes
625 */
626 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
627 {
628 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
629 int index = txq->q.read_ptr;
630 struct iwl3945_tfd *tfd = &tfd_tmp[index];
631 struct pci_dev *dev = priv->pci_dev;
632 int i;
633 int counter;
634
635 /* sanity check */
636 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
637 if (counter > NUM_TFD_CHUNKS) {
638 IWL_ERR(priv, "Too many chunks: %i\n", counter);
639 /* @todo issue fatal error, it is quite serious situation */
640 return;
641 }
642
643 /* Unmap tx_cmd */
644 if (counter)
645 pci_unmap_single(dev,
646 dma_unmap_addr(&txq->meta[index], mapping),
647 dma_unmap_len(&txq->meta[index], len),
648 PCI_DMA_TODEVICE);
649
650 /* unmap chunks if any */
651
652 for (i = 1; i < counter; i++)
653 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
654 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
655
656 /* free SKB */
657 if (txq->txb) {
658 struct sk_buff *skb;
659
660 skb = txq->txb[txq->q.read_ptr].skb;
661
662 /* can be called from irqs-disabled context */
663 if (skb) {
664 dev_kfree_skb_any(skb);
665 txq->txb[txq->q.read_ptr].skb = NULL;
666 }
667 }
668 }
669
670 /**
671 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
672 *
673 */
674 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
675 struct iwl_device_cmd *cmd,
676 struct ieee80211_tx_info *info,
677 struct ieee80211_hdr *hdr,
678 int sta_id, int tx_id)
679 {
680 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
681 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
682 u16 rate_mask;
683 int rate;
684 u8 rts_retry_limit;
685 u8 data_retry_limit;
686 __le32 tx_flags;
687 __le16 fc = hdr->frame_control;
688 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
689
690 rate = iwl3945_rates[rate_index].plcp;
691 tx_flags = tx_cmd->tx_flags;
692
693 /* We need to figure out how to get the sta->supp_rates while
694 * in this running context */
695 rate_mask = IWL_RATES_MASK_3945;
696
697 /* Set retry limit on DATA packets and Probe Responses*/
698 if (ieee80211_is_probe_resp(fc))
699 data_retry_limit = 3;
700 else
701 data_retry_limit = IWL_DEFAULT_TX_RETRY;
702 tx_cmd->data_retry_limit = data_retry_limit;
703
704 if (tx_id >= IWL39_CMD_QUEUE_NUM)
705 rts_retry_limit = 3;
706 else
707 rts_retry_limit = 7;
708
709 if (data_retry_limit < rts_retry_limit)
710 rts_retry_limit = data_retry_limit;
711 tx_cmd->rts_retry_limit = rts_retry_limit;
712
713 tx_cmd->rate = rate;
714 tx_cmd->tx_flags = tx_flags;
715
716 /* OFDM */
717 tx_cmd->supp_rates[0] =
718 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
719
720 /* CCK */
721 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
722
723 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
724 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
725 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
726 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
727 }
728
729 static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
730 {
731 unsigned long flags_spin;
732 struct iwl_station_entry *station;
733
734 if (sta_id == IWL_INVALID_STATION)
735 return IWL_INVALID_STATION;
736
737 spin_lock_irqsave(&priv->sta_lock, flags_spin);
738 station = &priv->stations[sta_id];
739
740 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
741 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
742 station->sta.mode = STA_CONTROL_MODIFY_MSK;
743 iwl_legacy_send_add_sta(priv, &station->sta, CMD_ASYNC);
744 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
745
746 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
747 sta_id, tx_rate);
748 return sta_id;
749 }
750
751 static void iwl3945_set_pwr_vmain(struct iwl_priv *priv)
752 {
753 /*
754 * (for documentation purposes)
755 * to set power to V_AUX, do
756
757 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
758 iwl_legacy_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
759 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
760 ~APMG_PS_CTRL_MSK_PWR_SRC);
761
762 iwl_poll_bit(priv, CSR_GPIO_IN,
763 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
764 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
765 }
766 */
767
768 iwl_legacy_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
769 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
770 ~APMG_PS_CTRL_MSK_PWR_SRC);
771
772 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
773 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
774 }
775
776 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
777 {
778 iwl_legacy_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
779 iwl_legacy_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
780 rxq->rb_stts_dma);
781 iwl_legacy_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
782 iwl_legacy_write_direct32(priv, FH39_RCSR_CONFIG(0),
783 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
784 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
785 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
786 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
787 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
788 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
789 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
790 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
791
792 /* fake read to flush all prev I/O */
793 iwl_legacy_read_direct32(priv, FH39_RSSR_CTRL);
794
795 return 0;
796 }
797
798 static int iwl3945_tx_reset(struct iwl_priv *priv)
799 {
800
801 /* bypass mode */
802 iwl_legacy_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
803
804 /* RA 0 is active */
805 iwl_legacy_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
806
807 /* all 6 fifo are active */
808 iwl_legacy_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
809
810 iwl_legacy_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
811 iwl_legacy_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
812 iwl_legacy_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
813 iwl_legacy_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
814
815 iwl_legacy_write_direct32(priv, FH39_TSSR_CBB_BASE,
816 priv->_3945.shared_phys);
817
818 iwl_legacy_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
819 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
820 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
821 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
822 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
823 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
824 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
825 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
826
827
828 return 0;
829 }
830
831 /**
832 * iwl3945_txq_ctx_reset - Reset TX queue context
833 *
834 * Destroys all DMA structures and initialize them again
835 */
836 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
837 {
838 int rc;
839 int txq_id, slots_num;
840
841 iwl3945_hw_txq_ctx_free(priv);
842
843 /* allocate tx queue structure */
844 rc = iwl_legacy_alloc_txq_mem(priv);
845 if (rc)
846 return rc;
847
848 /* Tx CMD queue */
849 rc = iwl3945_tx_reset(priv);
850 if (rc)
851 goto error;
852
853 /* Tx queue(s) */
854 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
855 slots_num = (txq_id == IWL39_CMD_QUEUE_NUM) ?
856 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
857 rc = iwl_legacy_tx_queue_init(priv, &priv->txq[txq_id],
858 slots_num, txq_id);
859 if (rc) {
860 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
861 goto error;
862 }
863 }
864
865 return rc;
866
867 error:
868 iwl3945_hw_txq_ctx_free(priv);
869 return rc;
870 }
871
872
873 /*
874 * Start up 3945's basic functionality after it has been reset
875 * (e.g. after platform boot, or shutdown via iwl_legacy_apm_stop())
876 * NOTE: This does not load uCode nor start the embedded processor
877 */
878 static int iwl3945_apm_init(struct iwl_priv *priv)
879 {
880 int ret = iwl_legacy_apm_init(priv);
881
882 /* Clear APMG (NIC's internal power management) interrupts */
883 iwl_legacy_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
884 iwl_legacy_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
885
886 /* Reset radio chip */
887 iwl_legacy_set_bits_prph(priv, APMG_PS_CTRL_REG,
888 APMG_PS_CTRL_VAL_RESET_REQ);
889 udelay(5);
890 iwl_legacy_clear_bits_prph(priv, APMG_PS_CTRL_REG,
891 APMG_PS_CTRL_VAL_RESET_REQ);
892
893 return ret;
894 }
895
896 static void iwl3945_nic_config(struct iwl_priv *priv)
897 {
898 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
899 unsigned long flags;
900 u8 rev_id = priv->pci_dev->revision;
901
902 spin_lock_irqsave(&priv->lock, flags);
903
904 /* Determine HW type */
905 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
906
907 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
908 IWL_DEBUG_INFO(priv, "RTP type\n");
909 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
910 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
911 iwl_legacy_set_bit(priv, CSR_HW_IF_CONFIG_REG,
912 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
913 } else {
914 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
915 iwl_legacy_set_bit(priv, CSR_HW_IF_CONFIG_REG,
916 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
917 }
918
919 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
920 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
921 iwl_legacy_set_bit(priv, CSR_HW_IF_CONFIG_REG,
922 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
923 } else
924 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
925
926 if ((eeprom->board_revision & 0xF0) == 0xD0) {
927 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
928 eeprom->board_revision);
929 iwl_legacy_set_bit(priv, CSR_HW_IF_CONFIG_REG,
930 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
931 } else {
932 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
933 eeprom->board_revision);
934 iwl_legacy_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
935 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
936 }
937
938 if (eeprom->almgor_m_version <= 1) {
939 iwl_legacy_set_bit(priv, CSR_HW_IF_CONFIG_REG,
940 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
941 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
942 eeprom->almgor_m_version);
943 } else {
944 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
945 eeprom->almgor_m_version);
946 iwl_legacy_set_bit(priv, CSR_HW_IF_CONFIG_REG,
947 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
948 }
949 spin_unlock_irqrestore(&priv->lock, flags);
950
951 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
952 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
953
954 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
955 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
956 }
957
958 int iwl3945_hw_nic_init(struct iwl_priv *priv)
959 {
960 int rc;
961 unsigned long flags;
962 struct iwl_rx_queue *rxq = &priv->rxq;
963
964 spin_lock_irqsave(&priv->lock, flags);
965 priv->cfg->ops->lib->apm_ops.init(priv);
966 spin_unlock_irqrestore(&priv->lock, flags);
967
968 iwl3945_set_pwr_vmain(priv);
969
970 priv->cfg->ops->lib->apm_ops.config(priv);
971
972 /* Allocate the RX queue, or reset if it is already allocated */
973 if (!rxq->bd) {
974 rc = iwl_legacy_rx_queue_alloc(priv);
975 if (rc) {
976 IWL_ERR(priv, "Unable to initialize Rx queue\n");
977 return -ENOMEM;
978 }
979 } else
980 iwl3945_rx_queue_reset(priv, rxq);
981
982 iwl3945_rx_replenish(priv);
983
984 iwl3945_rx_init(priv, rxq);
985
986
987 /* Look at using this instead:
988 rxq->need_update = 1;
989 iwl_legacy_rx_queue_update_write_ptr(priv, rxq);
990 */
991
992 iwl_legacy_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
993
994 rc = iwl3945_txq_ctx_reset(priv);
995 if (rc)
996 return rc;
997
998 set_bit(STATUS_INIT, &priv->status);
999
1000 return 0;
1001 }
1002
1003 /**
1004 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1005 *
1006 * Destroy all TX DMA queues and structures
1007 */
1008 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1009 {
1010 int txq_id;
1011
1012 /* Tx queues */
1013 if (priv->txq)
1014 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1015 txq_id++)
1016 if (txq_id == IWL39_CMD_QUEUE_NUM)
1017 iwl_legacy_cmd_queue_free(priv);
1018 else
1019 iwl_legacy_tx_queue_free(priv, txq_id);
1020
1021 /* free tx queue structure */
1022 iwl_legacy_txq_mem(priv);
1023 }
1024
1025 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1026 {
1027 int txq_id;
1028
1029 /* stop SCD */
1030 iwl_legacy_write_prph(priv, ALM_SCD_MODE_REG, 0);
1031 iwl_legacy_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1032
1033 /* reset TFD queues */
1034 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1035 iwl_legacy_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1036 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1037 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1038 1000);
1039 }
1040
1041 iwl3945_hw_txq_ctx_free(priv);
1042 }
1043
1044 /**
1045 * iwl3945_hw_reg_adjust_power_by_temp
1046 * return index delta into power gain settings table
1047 */
1048 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1049 {
1050 return (new_reading - old_reading) * (-11) / 100;
1051 }
1052
1053 /**
1054 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1055 */
1056 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1057 {
1058 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1059 }
1060
1061 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1062 {
1063 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1064 }
1065
1066 /**
1067 * iwl3945_hw_reg_txpower_get_temperature
1068 * get the current temperature by reading from NIC
1069 */
1070 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1071 {
1072 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1073 int temperature;
1074
1075 temperature = iwl3945_hw_get_temperature(priv);
1076
1077 /* driver's okay range is -260 to +25.
1078 * human readable okay range is 0 to +285 */
1079 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1080
1081 /* handle insane temp reading */
1082 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1083 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1084
1085 /* if really really hot(?),
1086 * substitute the 3rd band/group's temp measured at factory */
1087 if (priv->last_temperature > 100)
1088 temperature = eeprom->groups[2].temperature;
1089 else /* else use most recent "sane" value from driver */
1090 temperature = priv->last_temperature;
1091 }
1092
1093 return temperature; /* raw, not "human readable" */
1094 }
1095
1096 /* Adjust Txpower only if temperature variance is greater than threshold.
1097 *
1098 * Both are lower than older versions' 9 degrees */
1099 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1100
1101 /**
1102 * iwl3945_is_temp_calib_needed - determines if new calibration is needed
1103 *
1104 * records new temperature in tx_mgr->temperature.
1105 * replaces tx_mgr->last_temperature *only* if calib needed
1106 * (assumes caller will actually do the calibration!). */
1107 static int iwl3945_is_temp_calib_needed(struct iwl_priv *priv)
1108 {
1109 int temp_diff;
1110
1111 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1112 temp_diff = priv->temperature - priv->last_temperature;
1113
1114 /* get absolute value */
1115 if (temp_diff < 0) {
1116 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1117 temp_diff = -temp_diff;
1118 } else if (temp_diff == 0)
1119 IWL_DEBUG_POWER(priv, "Same temp,\n");
1120 else
1121 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1122
1123 /* if we don't need calibration, *don't* update last_temperature */
1124 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1125 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1126 return 0;
1127 }
1128
1129 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1130
1131 /* assume that caller will actually do calib ...
1132 * update the "last temperature" value */
1133 priv->last_temperature = priv->temperature;
1134 return 1;
1135 }
1136
1137 #define IWL_MAX_GAIN_ENTRIES 78
1138 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1139 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1140
1141 /* radio and DSP power table, each step is 1/2 dB.
1142 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1143 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1144 {
1145 {251, 127}, /* 2.4 GHz, highest power */
1146 {251, 127},
1147 {251, 127},
1148 {251, 127},
1149 {251, 125},
1150 {251, 110},
1151 {251, 105},
1152 {251, 98},
1153 {187, 125},
1154 {187, 115},
1155 {187, 108},
1156 {187, 99},
1157 {243, 119},
1158 {243, 111},
1159 {243, 105},
1160 {243, 97},
1161 {243, 92},
1162 {211, 106},
1163 {211, 100},
1164 {179, 120},
1165 {179, 113},
1166 {179, 107},
1167 {147, 125},
1168 {147, 119},
1169 {147, 112},
1170 {147, 106},
1171 {147, 101},
1172 {147, 97},
1173 {147, 91},
1174 {115, 107},
1175 {235, 121},
1176 {235, 115},
1177 {235, 109},
1178 {203, 127},
1179 {203, 121},
1180 {203, 115},
1181 {203, 108},
1182 {203, 102},
1183 {203, 96},
1184 {203, 92},
1185 {171, 110},
1186 {171, 104},
1187 {171, 98},
1188 {139, 116},
1189 {227, 125},
1190 {227, 119},
1191 {227, 113},
1192 {227, 107},
1193 {227, 101},
1194 {227, 96},
1195 {195, 113},
1196 {195, 106},
1197 {195, 102},
1198 {195, 95},
1199 {163, 113},
1200 {163, 106},
1201 {163, 102},
1202 {163, 95},
1203 {131, 113},
1204 {131, 106},
1205 {131, 102},
1206 {131, 95},
1207 {99, 113},
1208 {99, 106},
1209 {99, 102},
1210 {99, 95},
1211 {67, 113},
1212 {67, 106},
1213 {67, 102},
1214 {67, 95},
1215 {35, 113},
1216 {35, 106},
1217 {35, 102},
1218 {35, 95},
1219 {3, 113},
1220 {3, 106},
1221 {3, 102},
1222 {3, 95} }, /* 2.4 GHz, lowest power */
1223 {
1224 {251, 127}, /* 5.x GHz, highest power */
1225 {251, 120},
1226 {251, 114},
1227 {219, 119},
1228 {219, 101},
1229 {187, 113},
1230 {187, 102},
1231 {155, 114},
1232 {155, 103},
1233 {123, 117},
1234 {123, 107},
1235 {123, 99},
1236 {123, 92},
1237 {91, 108},
1238 {59, 125},
1239 {59, 118},
1240 {59, 109},
1241 {59, 102},
1242 {59, 96},
1243 {59, 90},
1244 {27, 104},
1245 {27, 98},
1246 {27, 92},
1247 {115, 118},
1248 {115, 111},
1249 {115, 104},
1250 {83, 126},
1251 {83, 121},
1252 {83, 113},
1253 {83, 105},
1254 {83, 99},
1255 {51, 118},
1256 {51, 111},
1257 {51, 104},
1258 {51, 98},
1259 {19, 116},
1260 {19, 109},
1261 {19, 102},
1262 {19, 98},
1263 {19, 93},
1264 {171, 113},
1265 {171, 107},
1266 {171, 99},
1267 {139, 120},
1268 {139, 113},
1269 {139, 107},
1270 {139, 99},
1271 {107, 120},
1272 {107, 113},
1273 {107, 107},
1274 {107, 99},
1275 {75, 120},
1276 {75, 113},
1277 {75, 107},
1278 {75, 99},
1279 {43, 120},
1280 {43, 113},
1281 {43, 107},
1282 {43, 99},
1283 {11, 120},
1284 {11, 113},
1285 {11, 107},
1286 {11, 99},
1287 {131, 107},
1288 {131, 99},
1289 {99, 120},
1290 {99, 113},
1291 {99, 107},
1292 {99, 99},
1293 {67, 120},
1294 {67, 113},
1295 {67, 107},
1296 {67, 99},
1297 {35, 120},
1298 {35, 113},
1299 {35, 107},
1300 {35, 99},
1301 {3, 120} } /* 5.x GHz, lowest power */
1302 };
1303
1304 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1305 {
1306 if (index < 0)
1307 return 0;
1308 if (index >= IWL_MAX_GAIN_ENTRIES)
1309 return IWL_MAX_GAIN_ENTRIES - 1;
1310 return (u8) index;
1311 }
1312
1313 /* Kick off thermal recalibration check every 60 seconds */
1314 #define REG_RECALIB_PERIOD (60)
1315
1316 /**
1317 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1318 *
1319 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1320 * or 6 Mbit (OFDM) rates.
1321 */
1322 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1323 s32 rate_index, const s8 *clip_pwrs,
1324 struct iwl_channel_info *ch_info,
1325 int band_index)
1326 {
1327 struct iwl3945_scan_power_info *scan_power_info;
1328 s8 power;
1329 u8 power_index;
1330
1331 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1332
1333 /* use this channel group's 6Mbit clipping/saturation pwr,
1334 * but cap at regulatory scan power restriction (set during init
1335 * based on eeprom channel data) for this channel. */
1336 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1337
1338 power = min(power, priv->tx_power_user_lmt);
1339 scan_power_info->requested_power = power;
1340
1341 /* find difference between new scan *power* and current "normal"
1342 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1343 * current "normal" temperature-compensated Tx power *index* for
1344 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1345 * *index*. */
1346 power_index = ch_info->power_info[rate_index].power_table_index
1347 - (power - ch_info->power_info
1348 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1349
1350 /* store reference index that we use when adjusting *all* scan
1351 * powers. So we can accommodate user (all channel) or spectrum
1352 * management (single channel) power changes "between" temperature
1353 * feedback compensation procedures.
1354 * don't force fit this reference index into gain table; it may be a
1355 * negative number. This will help avoid errors when we're at
1356 * the lower bounds (highest gains, for warmest temperatures)
1357 * of the table. */
1358
1359 /* don't exceed table bounds for "real" setting */
1360 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1361
1362 scan_power_info->power_table_index = power_index;
1363 scan_power_info->tpc.tx_gain =
1364 power_gain_table[band_index][power_index].tx_gain;
1365 scan_power_info->tpc.dsp_atten =
1366 power_gain_table[band_index][power_index].dsp_atten;
1367 }
1368
1369 /**
1370 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1371 *
1372 * Configures power settings for all rates for the current channel,
1373 * using values from channel info struct, and send to NIC
1374 */
1375 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1376 {
1377 int rate_idx, i;
1378 const struct iwl_channel_info *ch_info = NULL;
1379 struct iwl3945_txpowertable_cmd txpower = {
1380 .channel = priv->contexts[IWL_RXON_CTX_BSS].active.channel,
1381 };
1382 u16 chan;
1383
1384 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
1385 "TX Power requested while scanning!\n"))
1386 return -EAGAIN;
1387
1388 chan = le16_to_cpu(priv->contexts[IWL_RXON_CTX_BSS].active.channel);
1389
1390 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1391 ch_info = iwl_legacy_get_channel_info(priv, priv->band, chan);
1392 if (!ch_info) {
1393 IWL_ERR(priv,
1394 "Failed to get channel info for channel %d [%d]\n",
1395 chan, priv->band);
1396 return -EINVAL;
1397 }
1398
1399 if (!iwl_legacy_is_channel_valid(ch_info)) {
1400 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1401 "non-Tx channel.\n");
1402 return 0;
1403 }
1404
1405 /* fill cmd with power settings for all rates for current channel */
1406 /* Fill OFDM rate */
1407 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1408 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1409
1410 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1411 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1412
1413 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1414 le16_to_cpu(txpower.channel),
1415 txpower.band,
1416 txpower.power[i].tpc.tx_gain,
1417 txpower.power[i].tpc.dsp_atten,
1418 txpower.power[i].rate);
1419 }
1420 /* Fill CCK rates */
1421 for (rate_idx = IWL_FIRST_CCK_RATE;
1422 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1423 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1424 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1425
1426 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1427 le16_to_cpu(txpower.channel),
1428 txpower.band,
1429 txpower.power[i].tpc.tx_gain,
1430 txpower.power[i].tpc.dsp_atten,
1431 txpower.power[i].rate);
1432 }
1433
1434 return iwl_legacy_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1435 sizeof(struct iwl3945_txpowertable_cmd),
1436 &txpower);
1437
1438 }
1439
1440 /**
1441 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1442 * @ch_info: Channel to update. Uses power_info.requested_power.
1443 *
1444 * Replace requested_power and base_power_index ch_info fields for
1445 * one channel.
1446 *
1447 * Called if user or spectrum management changes power preferences.
1448 * Takes into account h/w and modulation limitations (clip power).
1449 *
1450 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1451 *
1452 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1453 * properly fill out the scan powers, and actual h/w gain settings,
1454 * and send changes to NIC
1455 */
1456 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1457 struct iwl_channel_info *ch_info)
1458 {
1459 struct iwl3945_channel_power_info *power_info;
1460 int power_changed = 0;
1461 int i;
1462 const s8 *clip_pwrs;
1463 int power;
1464
1465 /* Get this chnlgrp's rate-to-max/clip-powers table */
1466 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1467
1468 /* Get this channel's rate-to-current-power settings table */
1469 power_info = ch_info->power_info;
1470
1471 /* update OFDM Txpower settings */
1472 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1473 i++, ++power_info) {
1474 int delta_idx;
1475
1476 /* limit new power to be no more than h/w capability */
1477 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1478 if (power == power_info->requested_power)
1479 continue;
1480
1481 /* find difference between old and new requested powers,
1482 * update base (non-temp-compensated) power index */
1483 delta_idx = (power - power_info->requested_power) * 2;
1484 power_info->base_power_index -= delta_idx;
1485
1486 /* save new requested power value */
1487 power_info->requested_power = power;
1488
1489 power_changed = 1;
1490 }
1491
1492 /* update CCK Txpower settings, based on OFDM 12M setting ...
1493 * ... all CCK power settings for a given channel are the *same*. */
1494 if (power_changed) {
1495 power =
1496 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1497 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1498
1499 /* do all CCK rates' iwl3945_channel_power_info structures */
1500 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1501 power_info->requested_power = power;
1502 power_info->base_power_index =
1503 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1504 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1505 ++power_info;
1506 }
1507 }
1508
1509 return 0;
1510 }
1511
1512 /**
1513 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1514 *
1515 * NOTE: Returned power limit may be less (but not more) than requested,
1516 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1517 * (no consideration for h/w clipping limitations).
1518 */
1519 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1520 {
1521 s8 max_power;
1522
1523 #if 0
1524 /* if we're using TGd limits, use lower of TGd or EEPROM */
1525 if (ch_info->tgd_data.max_power != 0)
1526 max_power = min(ch_info->tgd_data.max_power,
1527 ch_info->eeprom.max_power_avg);
1528
1529 /* else just use EEPROM limits */
1530 else
1531 #endif
1532 max_power = ch_info->eeprom.max_power_avg;
1533
1534 return min(max_power, ch_info->max_power_avg);
1535 }
1536
1537 /**
1538 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1539 *
1540 * Compensate txpower settings of *all* channels for temperature.
1541 * This only accounts for the difference between current temperature
1542 * and the factory calibration temperatures, and bases the new settings
1543 * on the channel's base_power_index.
1544 *
1545 * If RxOn is "associated", this sends the new Txpower to NIC!
1546 */
1547 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1548 {
1549 struct iwl_channel_info *ch_info = NULL;
1550 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1551 int delta_index;
1552 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1553 u8 a_band;
1554 u8 rate_index;
1555 u8 scan_tbl_index;
1556 u8 i;
1557 int ref_temp;
1558 int temperature = priv->temperature;
1559
1560 if (priv->disable_tx_power_cal ||
1561 test_bit(STATUS_SCANNING, &priv->status)) {
1562 /* do not perform tx power calibration */
1563 return 0;
1564 }
1565 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1566 for (i = 0; i < priv->channel_count; i++) {
1567 ch_info = &priv->channel_info[i];
1568 a_band = iwl_legacy_is_channel_a_band(ch_info);
1569
1570 /* Get this chnlgrp's factory calibration temperature */
1571 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1572 temperature;
1573
1574 /* get power index adjustment based on current and factory
1575 * temps */
1576 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1577 ref_temp);
1578
1579 /* set tx power value for all rates, OFDM and CCK */
1580 for (rate_index = 0; rate_index < IWL_RATE_COUNT_3945;
1581 rate_index++) {
1582 int power_idx =
1583 ch_info->power_info[rate_index].base_power_index;
1584
1585 /* temperature compensate */
1586 power_idx += delta_index;
1587
1588 /* stay within table range */
1589 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1590 ch_info->power_info[rate_index].
1591 power_table_index = (u8) power_idx;
1592 ch_info->power_info[rate_index].tpc =
1593 power_gain_table[a_band][power_idx];
1594 }
1595
1596 /* Get this chnlgrp's rate-to-max/clip-powers table */
1597 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1598
1599 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1600 for (scan_tbl_index = 0;
1601 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1602 s32 actual_index = (scan_tbl_index == 0) ?
1603 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1604 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1605 actual_index, clip_pwrs,
1606 ch_info, a_band);
1607 }
1608 }
1609
1610 /* send Txpower command for current channel to ucode */
1611 return priv->cfg->ops->lib->send_tx_power(priv);
1612 }
1613
1614 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1615 {
1616 struct iwl_channel_info *ch_info;
1617 s8 max_power;
1618 u8 a_band;
1619 u8 i;
1620
1621 if (priv->tx_power_user_lmt == power) {
1622 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1623 "limit: %ddBm.\n", power);
1624 return 0;
1625 }
1626
1627 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1628 priv->tx_power_user_lmt = power;
1629
1630 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1631
1632 for (i = 0; i < priv->channel_count; i++) {
1633 ch_info = &priv->channel_info[i];
1634 a_band = iwl_legacy_is_channel_a_band(ch_info);
1635
1636 /* find minimum power of all user and regulatory constraints
1637 * (does not consider h/w clipping limitations) */
1638 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1639 max_power = min(power, max_power);
1640 if (max_power != ch_info->curr_txpow) {
1641 ch_info->curr_txpow = max_power;
1642
1643 /* this considers the h/w clipping limitations */
1644 iwl3945_hw_reg_set_new_power(priv, ch_info);
1645 }
1646 }
1647
1648 /* update txpower settings for all channels,
1649 * send to NIC if associated. */
1650 iwl3945_is_temp_calib_needed(priv);
1651 iwl3945_hw_reg_comp_txpower_temp(priv);
1652
1653 return 0;
1654 }
1655
1656 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv,
1657 struct iwl_rxon_context *ctx)
1658 {
1659 int rc = 0;
1660 struct iwl_rx_packet *pkt;
1661 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1662 struct iwl_host_cmd cmd = {
1663 .id = REPLY_RXON_ASSOC,
1664 .len = sizeof(rxon_assoc),
1665 .flags = CMD_WANT_SKB,
1666 .data = &rxon_assoc,
1667 };
1668 const struct iwl_legacy_rxon_cmd *rxon1 = &ctx->staging;
1669 const struct iwl_legacy_rxon_cmd *rxon2 = &ctx->active;
1670
1671 if ((rxon1->flags == rxon2->flags) &&
1672 (rxon1->filter_flags == rxon2->filter_flags) &&
1673 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1674 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1675 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1676 return 0;
1677 }
1678
1679 rxon_assoc.flags = ctx->staging.flags;
1680 rxon_assoc.filter_flags = ctx->staging.filter_flags;
1681 rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
1682 rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
1683 rxon_assoc.reserved = 0;
1684
1685 rc = iwl_legacy_send_cmd_sync(priv, &cmd);
1686 if (rc)
1687 return rc;
1688
1689 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1690 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1691 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1692 rc = -EIO;
1693 }
1694
1695 iwl_legacy_free_pages(priv, cmd.reply_page);
1696
1697 return rc;
1698 }
1699
1700 /**
1701 * iwl3945_commit_rxon - commit staging_rxon to hardware
1702 *
1703 * The RXON command in staging_rxon is committed to the hardware and
1704 * the active_rxon structure is updated with the new data. This
1705 * function correctly transitions out of the RXON_ASSOC_MSK state if
1706 * a HW tune is required based on the RXON structure changes.
1707 */
1708 int iwl3945_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
1709 {
1710 /* cast away the const for active_rxon in this function */
1711 struct iwl3945_rxon_cmd *active_rxon = (void *)&ctx->active;
1712 struct iwl3945_rxon_cmd *staging_rxon = (void *)&ctx->staging;
1713 int rc = 0;
1714 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1715
1716 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1717 return -EINVAL;
1718
1719 if (!iwl_legacy_is_alive(priv))
1720 return -1;
1721
1722 /* always get timestamp with Rx frame */
1723 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1724
1725 /* select antenna */
1726 staging_rxon->flags &=
1727 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1728 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1729
1730 rc = iwl_legacy_check_rxon_cmd(priv, ctx);
1731 if (rc) {
1732 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1733 return -EINVAL;
1734 }
1735
1736 /* If we don't need to send a full RXON, we can use
1737 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1738 * and other flags for the current radio configuration. */
1739 if (!iwl_legacy_full_rxon_required(priv,
1740 &priv->contexts[IWL_RXON_CTX_BSS])) {
1741 rc = iwl_legacy_send_rxon_assoc(priv,
1742 &priv->contexts[IWL_RXON_CTX_BSS]);
1743 if (rc) {
1744 IWL_ERR(priv, "Error setting RXON_ASSOC "
1745 "configuration (%d).\n", rc);
1746 return rc;
1747 }
1748
1749 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1750
1751 return 0;
1752 }
1753
1754 /* If we are currently associated and the new config requires
1755 * an RXON_ASSOC and the new config wants the associated mask enabled,
1756 * we must clear the associated from the active configuration
1757 * before we apply the new config */
1758 if (iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS) && new_assoc) {
1759 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1760 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1761
1762 /*
1763 * reserved4 and 5 could have been filled by the iwlcore code.
1764 * Let's clear them before pushing to the 3945.
1765 */
1766 active_rxon->reserved4 = 0;
1767 active_rxon->reserved5 = 0;
1768 rc = iwl_legacy_send_cmd_pdu(priv, REPLY_RXON,
1769 sizeof(struct iwl3945_rxon_cmd),
1770 &priv->contexts[IWL_RXON_CTX_BSS].active);
1771
1772 /* If the mask clearing failed then we set
1773 * active_rxon back to what it was previously */
1774 if (rc) {
1775 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1776 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1777 "configuration (%d).\n", rc);
1778 return rc;
1779 }
1780 iwl_legacy_clear_ucode_stations(priv,
1781 &priv->contexts[IWL_RXON_CTX_BSS]);
1782 iwl_legacy_restore_stations(priv,
1783 &priv->contexts[IWL_RXON_CTX_BSS]);
1784 }
1785
1786 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1787 "* with%s RXON_FILTER_ASSOC_MSK\n"
1788 "* channel = %d\n"
1789 "* bssid = %pM\n",
1790 (new_assoc ? "" : "out"),
1791 le16_to_cpu(staging_rxon->channel),
1792 staging_rxon->bssid_addr);
1793
1794 /*
1795 * reserved4 and 5 could have been filled by the iwlcore code.
1796 * Let's clear them before pushing to the 3945.
1797 */
1798 staging_rxon->reserved4 = 0;
1799 staging_rxon->reserved5 = 0;
1800
1801 iwl_legacy_set_rxon_hwcrypto(priv, ctx, !iwl3945_mod_params.sw_crypto);
1802
1803 /* Apply the new configuration */
1804 rc = iwl_legacy_send_cmd_pdu(priv, REPLY_RXON,
1805 sizeof(struct iwl3945_rxon_cmd),
1806 staging_rxon);
1807 if (rc) {
1808 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1809 return rc;
1810 }
1811
1812 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1813
1814 if (!new_assoc) {
1815 iwl_legacy_clear_ucode_stations(priv,
1816 &priv->contexts[IWL_RXON_CTX_BSS]);
1817 iwl_legacy_restore_stations(priv,
1818 &priv->contexts[IWL_RXON_CTX_BSS]);
1819 }
1820
1821 /* If we issue a new RXON command which required a tune then we must
1822 * send a new TXPOWER command or we won't be able to Tx any frames */
1823 rc = iwl_legacy_set_tx_power(priv, priv->tx_power_next, true);
1824 if (rc) {
1825 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1826 return rc;
1827 }
1828
1829 /* Init the hardware's rate fallback order based on the band */
1830 rc = iwl3945_init_hw_rate_table(priv);
1831 if (rc) {
1832 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1833 return -EIO;
1834 }
1835
1836 return 0;
1837 }
1838
1839 /**
1840 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1841 *
1842 * -- reset periodic timer
1843 * -- see if temp has changed enough to warrant re-calibration ... if so:
1844 * -- correct coeffs for temp (can reset temp timer)
1845 * -- save this temp as "last",
1846 * -- send new set of gain settings to NIC
1847 * NOTE: This should continue working, even when we're not associated,
1848 * so we can keep our internal table of scan powers current. */
1849 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1850 {
1851 /* This will kick in the "brute force"
1852 * iwl3945_hw_reg_comp_txpower_temp() below */
1853 if (!iwl3945_is_temp_calib_needed(priv))
1854 goto reschedule;
1855
1856 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1857 * This is based *only* on current temperature,
1858 * ignoring any previous power measurements */
1859 iwl3945_hw_reg_comp_txpower_temp(priv);
1860
1861 reschedule:
1862 queue_delayed_work(priv->workqueue,
1863 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1864 }
1865
1866 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1867 {
1868 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1869 _3945.thermal_periodic.work);
1870
1871 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1872 return;
1873
1874 mutex_lock(&priv->mutex);
1875 iwl3945_reg_txpower_periodic(priv);
1876 mutex_unlock(&priv->mutex);
1877 }
1878
1879 /**
1880 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1881 * for the channel.
1882 *
1883 * This function is used when initializing channel-info structs.
1884 *
1885 * NOTE: These channel groups do *NOT* match the bands above!
1886 * These channel groups are based on factory-tested channels;
1887 * on A-band, EEPROM's "group frequency" entries represent the top
1888 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1889 */
1890 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1891 const struct iwl_channel_info *ch_info)
1892 {
1893 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1894 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1895 u8 group;
1896 u16 group_index = 0; /* based on factory calib frequencies */
1897 u8 grp_channel;
1898
1899 /* Find the group index for the channel ... don't use index 1(?) */
1900 if (iwl_legacy_is_channel_a_band(ch_info)) {
1901 for (group = 1; group < 5; group++) {
1902 grp_channel = ch_grp[group].group_channel;
1903 if (ch_info->channel <= grp_channel) {
1904 group_index = group;
1905 break;
1906 }
1907 }
1908 /* group 4 has a few channels *above* its factory cal freq */
1909 if (group == 5)
1910 group_index = 4;
1911 } else
1912 group_index = 0; /* 2.4 GHz, group 0 */
1913
1914 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
1915 group_index);
1916 return group_index;
1917 }
1918
1919 /**
1920 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1921 *
1922 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1923 * into radio/DSP gain settings table for requested power.
1924 */
1925 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1926 s8 requested_power,
1927 s32 setting_index, s32 *new_index)
1928 {
1929 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
1930 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1931 s32 index0, index1;
1932 s32 power = 2 * requested_power;
1933 s32 i;
1934 const struct iwl3945_eeprom_txpower_sample *samples;
1935 s32 gains0, gains1;
1936 s32 res;
1937 s32 denominator;
1938
1939 chnl_grp = &eeprom->groups[setting_index];
1940 samples = chnl_grp->samples;
1941 for (i = 0; i < 5; i++) {
1942 if (power == samples[i].power) {
1943 *new_index = samples[i].gain_index;
1944 return 0;
1945 }
1946 }
1947
1948 if (power > samples[1].power) {
1949 index0 = 0;
1950 index1 = 1;
1951 } else if (power > samples[2].power) {
1952 index0 = 1;
1953 index1 = 2;
1954 } else if (power > samples[3].power) {
1955 index0 = 2;
1956 index1 = 3;
1957 } else {
1958 index0 = 3;
1959 index1 = 4;
1960 }
1961
1962 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
1963 if (denominator == 0)
1964 return -EINVAL;
1965 gains0 = (s32) samples[index0].gain_index * (1 << 19);
1966 gains1 = (s32) samples[index1].gain_index * (1 << 19);
1967 res = gains0 + (gains1 - gains0) *
1968 ((s32) power - (s32) samples[index0].power) / denominator +
1969 (1 << 18);
1970 *new_index = res >> 19;
1971 return 0;
1972 }
1973
1974 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
1975 {
1976 u32 i;
1977 s32 rate_index;
1978 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1979 const struct iwl3945_eeprom_txpower_group *group;
1980
1981 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
1982
1983 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
1984 s8 *clip_pwrs; /* table of power levels for each rate */
1985 s8 satur_pwr; /* saturation power for each chnl group */
1986 group = &eeprom->groups[i];
1987
1988 /* sanity check on factory saturation power value */
1989 if (group->saturation_power < 40) {
1990 IWL_WARN(priv, "Error: saturation power is %d, "
1991 "less than minimum expected 40\n",
1992 group->saturation_power);
1993 return;
1994 }
1995
1996 /*
1997 * Derive requested power levels for each rate, based on
1998 * hardware capabilities (saturation power for band).
1999 * Basic value is 3dB down from saturation, with further
2000 * power reductions for highest 3 data rates. These
2001 * backoffs provide headroom for high rate modulation
2002 * power peaks, without too much distortion (clipping).
2003 */
2004 /* we'll fill in this array with h/w max power levels */
2005 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2006
2007 /* divide factory saturation power by 2 to find -3dB level */
2008 satur_pwr = (s8) (group->saturation_power >> 1);
2009
2010 /* fill in channel group's nominal powers for each rate */
2011 for (rate_index = 0;
2012 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2013 switch (rate_index) {
2014 case IWL_RATE_36M_INDEX_TABLE:
2015 if (i == 0) /* B/G */
2016 *clip_pwrs = satur_pwr;
2017 else /* A */
2018 *clip_pwrs = satur_pwr - 5;
2019 break;
2020 case IWL_RATE_48M_INDEX_TABLE:
2021 if (i == 0)
2022 *clip_pwrs = satur_pwr - 7;
2023 else
2024 *clip_pwrs = satur_pwr - 10;
2025 break;
2026 case IWL_RATE_54M_INDEX_TABLE:
2027 if (i == 0)
2028 *clip_pwrs = satur_pwr - 9;
2029 else
2030 *clip_pwrs = satur_pwr - 12;
2031 break;
2032 default:
2033 *clip_pwrs = satur_pwr;
2034 break;
2035 }
2036 }
2037 }
2038 }
2039
2040 /**
2041 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2042 *
2043 * Second pass (during init) to set up priv->channel_info
2044 *
2045 * Set up Tx-power settings in our channel info database for each VALID
2046 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2047 * and current temperature.
2048 *
2049 * Since this is based on current temperature (at init time), these values may
2050 * not be valid for very long, but it gives us a starting/default point,
2051 * and allows us to active (i.e. using Tx) scan.
2052 *
2053 * This does *not* write values to NIC, just sets up our internal table.
2054 */
2055 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2056 {
2057 struct iwl_channel_info *ch_info = NULL;
2058 struct iwl3945_channel_power_info *pwr_info;
2059 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2060 int delta_index;
2061 u8 rate_index;
2062 u8 scan_tbl_index;
2063 const s8 *clip_pwrs; /* array of power levels for each rate */
2064 u8 gain, dsp_atten;
2065 s8 power;
2066 u8 pwr_index, base_pwr_index, a_band;
2067 u8 i;
2068 int temperature;
2069
2070 /* save temperature reference,
2071 * so we can determine next time to calibrate */
2072 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2073 priv->last_temperature = temperature;
2074
2075 iwl3945_hw_reg_init_channel_groups(priv);
2076
2077 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2078 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2079 i++, ch_info++) {
2080 a_band = iwl_legacy_is_channel_a_band(ch_info);
2081 if (!iwl_legacy_is_channel_valid(ch_info))
2082 continue;
2083
2084 /* find this channel's channel group (*not* "band") index */
2085 ch_info->group_index =
2086 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2087
2088 /* Get this chnlgrp's rate->max/clip-powers table */
2089 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2090
2091 /* calculate power index *adjustment* value according to
2092 * diff between current temperature and factory temperature */
2093 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2094 eeprom->groups[ch_info->group_index].
2095 temperature);
2096
2097 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2098 ch_info->channel, delta_index, temperature +
2099 IWL_TEMP_CONVERT);
2100
2101 /* set tx power value for all OFDM rates */
2102 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2103 rate_index++) {
2104 s32 uninitialized_var(power_idx);
2105 int rc;
2106
2107 /* use channel group's clip-power table,
2108 * but don't exceed channel's max power */
2109 s8 pwr = min(ch_info->max_power_avg,
2110 clip_pwrs[rate_index]);
2111
2112 pwr_info = &ch_info->power_info[rate_index];
2113
2114 /* get base (i.e. at factory-measured temperature)
2115 * power table index for this rate's power */
2116 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2117 ch_info->group_index,
2118 &power_idx);
2119 if (rc) {
2120 IWL_ERR(priv, "Invalid power index\n");
2121 return rc;
2122 }
2123 pwr_info->base_power_index = (u8) power_idx;
2124
2125 /* temperature compensate */
2126 power_idx += delta_index;
2127
2128 /* stay within range of gain table */
2129 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2130
2131 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2132 pwr_info->requested_power = pwr;
2133 pwr_info->power_table_index = (u8) power_idx;
2134 pwr_info->tpc.tx_gain =
2135 power_gain_table[a_band][power_idx].tx_gain;
2136 pwr_info->tpc.dsp_atten =
2137 power_gain_table[a_band][power_idx].dsp_atten;
2138 }
2139
2140 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2141 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2142 power = pwr_info->requested_power +
2143 IWL_CCK_FROM_OFDM_POWER_DIFF;
2144 pwr_index = pwr_info->power_table_index +
2145 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2146 base_pwr_index = pwr_info->base_power_index +
2147 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2148
2149 /* stay within table range */
2150 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2151 gain = power_gain_table[a_band][pwr_index].tx_gain;
2152 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2153
2154 /* fill each CCK rate's iwl3945_channel_power_info structure
2155 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2156 * NOTE: CCK rates start at end of OFDM rates! */
2157 for (rate_index = 0;
2158 rate_index < IWL_CCK_RATES; rate_index++) {
2159 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2160 pwr_info->requested_power = power;
2161 pwr_info->power_table_index = pwr_index;
2162 pwr_info->base_power_index = base_pwr_index;
2163 pwr_info->tpc.tx_gain = gain;
2164 pwr_info->tpc.dsp_atten = dsp_atten;
2165 }
2166
2167 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2168 for (scan_tbl_index = 0;
2169 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2170 s32 actual_index = (scan_tbl_index == 0) ?
2171 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2172 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2173 actual_index, clip_pwrs, ch_info, a_band);
2174 }
2175 }
2176
2177 return 0;
2178 }
2179
2180 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2181 {
2182 int rc;
2183
2184 iwl_legacy_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2185 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2186 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2187 if (rc < 0)
2188 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2189
2190 return 0;
2191 }
2192
2193 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2194 {
2195 int txq_id = txq->q.id;
2196
2197 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2198
2199 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2200
2201 iwl_legacy_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2202 iwl_legacy_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2203
2204 iwl_legacy_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2205 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2206 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2207 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2208 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2209 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2210
2211 /* fake read to flush all prev. writes */
2212 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2213
2214 return 0;
2215 }
2216
2217 /*
2218 * HCMD utils
2219 */
2220 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2221 {
2222 switch (cmd_id) {
2223 case REPLY_RXON:
2224 return sizeof(struct iwl3945_rxon_cmd);
2225 case POWER_TABLE_CMD:
2226 return sizeof(struct iwl3945_powertable_cmd);
2227 default:
2228 return len;
2229 }
2230 }
2231
2232
2233 static u16 iwl3945_build_addsta_hcmd(const struct iwl_legacy_addsta_cmd *cmd,
2234 u8 *data)
2235 {
2236 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2237 addsta->mode = cmd->mode;
2238 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2239 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2240 addsta->station_flags = cmd->station_flags;
2241 addsta->station_flags_msk = cmd->station_flags_msk;
2242 addsta->tid_disable_tx = cpu_to_le16(0);
2243 addsta->rate_n_flags = cmd->rate_n_flags;
2244 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2245 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2246 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2247
2248 return (u16)sizeof(struct iwl3945_addsta_cmd);
2249 }
2250
2251 static int iwl3945_add_bssid_station(struct iwl_priv *priv,
2252 const u8 *addr, u8 *sta_id_r)
2253 {
2254 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2255 int ret;
2256 u8 sta_id;
2257 unsigned long flags;
2258
2259 if (sta_id_r)
2260 *sta_id_r = IWL_INVALID_STATION;
2261
2262 ret = iwl_legacy_add_station_common(priv, ctx, addr, 0, NULL, &sta_id);
2263 if (ret) {
2264 IWL_ERR(priv, "Unable to add station %pM\n", addr);
2265 return ret;
2266 }
2267
2268 if (sta_id_r)
2269 *sta_id_r = sta_id;
2270
2271 spin_lock_irqsave(&priv->sta_lock, flags);
2272 priv->stations[sta_id].used |= IWL_STA_LOCAL;
2273 spin_unlock_irqrestore(&priv->sta_lock, flags);
2274
2275 return 0;
2276 }
2277 static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2278 struct ieee80211_vif *vif, bool add)
2279 {
2280 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2281 int ret;
2282
2283 if (add) {
2284 ret = iwl3945_add_bssid_station(priv, vif->bss_conf.bssid,
2285 &vif_priv->ibss_bssid_sta_id);
2286 if (ret)
2287 return ret;
2288
2289 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
2290 (priv->band == IEEE80211_BAND_5GHZ) ?
2291 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
2292 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
2293
2294 return 0;
2295 }
2296
2297 return iwl_legacy_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2298 vif->bss_conf.bssid);
2299 }
2300
2301 /**
2302 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2303 */
2304 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2305 {
2306 int rc, i, index, prev_index;
2307 struct iwl3945_rate_scaling_cmd rate_cmd = {
2308 .reserved = {0, 0, 0},
2309 };
2310 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2311
2312 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2313 index = iwl3945_rates[i].table_rs_index;
2314
2315 table[index].rate_n_flags =
2316 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2317 table[index].try_cnt = priv->retry_rate;
2318 prev_index = iwl3945_get_prev_ieee_rate(i);
2319 table[index].next_rate_index =
2320 iwl3945_rates[prev_index].table_rs_index;
2321 }
2322
2323 switch (priv->band) {
2324 case IEEE80211_BAND_5GHZ:
2325 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2326 /* If one of the following CCK rates is used,
2327 * have it fall back to the 6M OFDM rate */
2328 for (i = IWL_RATE_1M_INDEX_TABLE;
2329 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2330 table[i].next_rate_index =
2331 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2332
2333 /* Don't fall back to CCK rates */
2334 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2335 IWL_RATE_9M_INDEX_TABLE;
2336
2337 /* Don't drop out of OFDM rates */
2338 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2339 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2340 break;
2341
2342 case IEEE80211_BAND_2GHZ:
2343 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2344 /* If an OFDM rate is used, have it fall back to the
2345 * 1M CCK rates */
2346
2347 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2348 iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS)) {
2349
2350 index = IWL_FIRST_CCK_RATE;
2351 for (i = IWL_RATE_6M_INDEX_TABLE;
2352 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2353 table[i].next_rate_index =
2354 iwl3945_rates[index].table_rs_index;
2355
2356 index = IWL_RATE_11M_INDEX_TABLE;
2357 /* CCK shouldn't fall back to OFDM... */
2358 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2359 }
2360 break;
2361
2362 default:
2363 WARN_ON(1);
2364 break;
2365 }
2366
2367 /* Update the rate scaling for control frame Tx */
2368 rate_cmd.table_id = 0;
2369 rc = iwl_legacy_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2370 &rate_cmd);
2371 if (rc)
2372 return rc;
2373
2374 /* Update the rate scaling for data frame Tx */
2375 rate_cmd.table_id = 1;
2376 return iwl_legacy_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2377 &rate_cmd);
2378 }
2379
2380 /* Called when initializing driver */
2381 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2382 {
2383 memset((void *)&priv->hw_params, 0,
2384 sizeof(struct iwl_hw_params));
2385
2386 priv->_3945.shared_virt =
2387 dma_alloc_coherent(&priv->pci_dev->dev,
2388 sizeof(struct iwl3945_shared),
2389 &priv->_3945.shared_phys, GFP_KERNEL);
2390 if (!priv->_3945.shared_virt) {
2391 IWL_ERR(priv, "failed to allocate pci memory\n");
2392 return -ENOMEM;
2393 }
2394
2395 /* Assign number of Usable TX queues */
2396 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
2397
2398 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2399 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2400 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2401 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2402 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2403 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id = IWL3945_BROADCAST_ID;
2404
2405 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2406
2407 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2408 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2409 priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
2410
2411 return 0;
2412 }
2413
2414 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2415 struct iwl3945_frame *frame, u8 rate)
2416 {
2417 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2418 unsigned int frame_size;
2419
2420 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2421 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2422
2423 tx_beacon_cmd->tx.sta_id =
2424 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
2425 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2426
2427 frame_size = iwl3945_fill_beacon_frame(priv,
2428 tx_beacon_cmd->frame,
2429 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2430
2431 BUG_ON(frame_size > MAX_MPDU_SIZE);
2432 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2433
2434 tx_beacon_cmd->tx.rate = rate;
2435 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2436 TX_CMD_FLG_TSF_MSK);
2437
2438 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2439 tx_beacon_cmd->tx.supp_rates[0] =
2440 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2441
2442 tx_beacon_cmd->tx.supp_rates[1] =
2443 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2444
2445 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2446 }
2447
2448 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2449 {
2450 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2451 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2452 }
2453
2454 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2455 {
2456 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2457 iwl3945_bg_reg_txpower_periodic);
2458 }
2459
2460 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2461 {
2462 cancel_delayed_work(&priv->_3945.thermal_periodic);
2463 }
2464
2465 /* check contents of special bootstrap uCode SRAM */
2466 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2467 {
2468 __le32 *image = priv->ucode_boot.v_addr;
2469 u32 len = priv->ucode_boot.len;
2470 u32 reg;
2471 u32 val;
2472
2473 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2474
2475 /* verify BSM SRAM contents */
2476 val = iwl_legacy_read_prph(priv, BSM_WR_DWCOUNT_REG);
2477 for (reg = BSM_SRAM_LOWER_BOUND;
2478 reg < BSM_SRAM_LOWER_BOUND + len;
2479 reg += sizeof(u32), image++) {
2480 val = iwl_legacy_read_prph(priv, reg);
2481 if (val != le32_to_cpu(*image)) {
2482 IWL_ERR(priv, "BSM uCode verification failed at "
2483 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2484 BSM_SRAM_LOWER_BOUND,
2485 reg - BSM_SRAM_LOWER_BOUND, len,
2486 val, le32_to_cpu(*image));
2487 return -EIO;
2488 }
2489 }
2490
2491 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2492
2493 return 0;
2494 }
2495
2496
2497 /******************************************************************************
2498 *
2499 * EEPROM related functions
2500 *
2501 ******************************************************************************/
2502
2503 /*
2504 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2505 * embedded controller) as EEPROM reader; each read is a series of pulses
2506 * to/from the EEPROM chip, not a single event, so even reads could conflict
2507 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2508 * simply claims ownership, which should be safe when this function is called
2509 * (i.e. before loading uCode!).
2510 */
2511 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2512 {
2513 _iwl_legacy_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2514 return 0;
2515 }
2516
2517
2518 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2519 {
2520 return;
2521 }
2522
2523 /**
2524 * iwl3945_load_bsm - Load bootstrap instructions
2525 *
2526 * BSM operation:
2527 *
2528 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2529 * in special SRAM that does not power down during RFKILL. When powering back
2530 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2531 * the bootstrap program into the on-board processor, and starts it.
2532 *
2533 * The bootstrap program loads (via DMA) instructions and data for a new
2534 * program from host DRAM locations indicated by the host driver in the
2535 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2536 * automatically.
2537 *
2538 * When initializing the NIC, the host driver points the BSM to the
2539 * "initialize" uCode image. This uCode sets up some internal data, then
2540 * notifies host via "initialize alive" that it is complete.
2541 *
2542 * The host then replaces the BSM_DRAM_* pointer values to point to the
2543 * normal runtime uCode instructions and a backup uCode data cache buffer
2544 * (filled initially with starting data values for the on-board processor),
2545 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2546 * which begins normal operation.
2547 *
2548 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2549 * the backup data cache in DRAM before SRAM is powered down.
2550 *
2551 * When powering back up, the BSM loads the bootstrap program. This reloads
2552 * the runtime uCode instructions and the backup data cache into SRAM,
2553 * and re-launches the runtime uCode from where it left off.
2554 */
2555 static int iwl3945_load_bsm(struct iwl_priv *priv)
2556 {
2557 __le32 *image = priv->ucode_boot.v_addr;
2558 u32 len = priv->ucode_boot.len;
2559 dma_addr_t pinst;
2560 dma_addr_t pdata;
2561 u32 inst_len;
2562 u32 data_len;
2563 int rc;
2564 int i;
2565 u32 done;
2566 u32 reg_offset;
2567
2568 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2569
2570 /* make sure bootstrap program is no larger than BSM's SRAM size */
2571 if (len > IWL39_MAX_BSM_SIZE)
2572 return -EINVAL;
2573
2574 /* Tell bootstrap uCode where to find the "Initialize" uCode
2575 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2576 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2577 * after the "initialize" uCode has run, to point to
2578 * runtime/protocol instructions and backup data cache. */
2579 pinst = priv->ucode_init.p_addr;
2580 pdata = priv->ucode_init_data.p_addr;
2581 inst_len = priv->ucode_init.len;
2582 data_len = priv->ucode_init_data.len;
2583
2584 iwl_legacy_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2585 iwl_legacy_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2586 iwl_legacy_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2587 iwl_legacy_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2588
2589 /* Fill BSM memory with bootstrap instructions */
2590 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2591 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2592 reg_offset += sizeof(u32), image++)
2593 _iwl_legacy_write_prph(priv, reg_offset,
2594 le32_to_cpu(*image));
2595
2596 rc = iwl3945_verify_bsm(priv);
2597 if (rc)
2598 return rc;
2599
2600 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2601 iwl_legacy_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2602 iwl_legacy_write_prph(priv, BSM_WR_MEM_DST_REG,
2603 IWL39_RTC_INST_LOWER_BOUND);
2604 iwl_legacy_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2605
2606 /* Load bootstrap code into instruction SRAM now,
2607 * to prepare to load "initialize" uCode */
2608 iwl_legacy_write_prph(priv, BSM_WR_CTRL_REG,
2609 BSM_WR_CTRL_REG_BIT_START);
2610
2611 /* Wait for load of bootstrap uCode to finish */
2612 for (i = 0; i < 100; i++) {
2613 done = iwl_legacy_read_prph(priv, BSM_WR_CTRL_REG);
2614 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2615 break;
2616 udelay(10);
2617 }
2618 if (i < 100)
2619 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2620 else {
2621 IWL_ERR(priv, "BSM write did not complete!\n");
2622 return -EIO;
2623 }
2624
2625 /* Enable future boot loads whenever power management unit triggers it
2626 * (e.g. when powering back up after power-save shutdown) */
2627 iwl_legacy_write_prph(priv, BSM_WR_CTRL_REG,
2628 BSM_WR_CTRL_REG_BIT_START_EN);
2629
2630 return 0;
2631 }
2632
2633 static struct iwl_hcmd_ops iwl3945_hcmd = {
2634 .rxon_assoc = iwl3945_send_rxon_assoc,
2635 .commit_rxon = iwl3945_commit_rxon,
2636 };
2637
2638 static struct iwl_lib_ops iwl3945_lib = {
2639 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2640 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2641 .txq_init = iwl3945_hw_tx_queue_init,
2642 .load_ucode = iwl3945_load_bsm,
2643 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2644 .dump_nic_error_log = iwl3945_dump_nic_error_log,
2645 .apm_ops = {
2646 .init = iwl3945_apm_init,
2647 .config = iwl3945_nic_config,
2648 },
2649 .eeprom_ops = {
2650 .regulatory_bands = {
2651 EEPROM_REGULATORY_BAND_1_CHANNELS,
2652 EEPROM_REGULATORY_BAND_2_CHANNELS,
2653 EEPROM_REGULATORY_BAND_3_CHANNELS,
2654 EEPROM_REGULATORY_BAND_4_CHANNELS,
2655 EEPROM_REGULATORY_BAND_5_CHANNELS,
2656 EEPROM_REGULATORY_BAND_NO_HT40,
2657 EEPROM_REGULATORY_BAND_NO_HT40,
2658 },
2659 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2660 .release_semaphore = iwl3945_eeprom_release_semaphore,
2661 },
2662 .send_tx_power = iwl3945_send_tx_power,
2663 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2664
2665 .debugfs_ops = {
2666 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2667 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2668 .general_stats_read = iwl3945_ucode_general_stats_read,
2669 },
2670 };
2671
2672 static const struct iwl_legacy_ops iwl3945_legacy_ops = {
2673 .post_associate = iwl3945_post_associate,
2674 .config_ap = iwl3945_config_ap,
2675 .manage_ibss_station = iwl3945_manage_ibss_station,
2676 };
2677
2678 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2679 .get_hcmd_size = iwl3945_get_hcmd_size,
2680 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2681 .request_scan = iwl3945_request_scan,
2682 .post_scan = iwl3945_post_scan,
2683 };
2684
2685 static const struct iwl_ops iwl3945_ops = {
2686 .lib = &iwl3945_lib,
2687 .hcmd = &iwl3945_hcmd,
2688 .utils = &iwl3945_hcmd_utils,
2689 .led = &iwl3945_led_ops,
2690 .legacy = &iwl3945_legacy_ops,
2691 .ieee80211_ops = &iwl3945_hw_ops,
2692 };
2693
2694 static struct iwl_base_params iwl3945_base_params = {
2695 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2696 .num_of_queues = IWL39_NUM_QUEUES,
2697 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2698 .set_l0s = false,
2699 .use_bsm = true,
2700 .led_compensation = 64,
2701 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2702 .wd_timeout = IWL_DEF_WD_TIMEOUT,
2703 .max_event_log_size = 512,
2704 };
2705
2706 static struct iwl_cfg iwl3945_bg_cfg = {
2707 .name = "3945BG",
2708 .fw_name_pre = IWL3945_FW_PRE,
2709 .ucode_api_max = IWL3945_UCODE_API_MAX,
2710 .ucode_api_min = IWL3945_UCODE_API_MIN,
2711 .sku = IWL_SKU_G,
2712 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2713 .ops = &iwl3945_ops,
2714 .mod_params = &iwl3945_mod_params,
2715 .base_params = &iwl3945_base_params,
2716 .led_mode = IWL_LED_BLINK,
2717 };
2718
2719 static struct iwl_cfg iwl3945_abg_cfg = {
2720 .name = "3945ABG",
2721 .fw_name_pre = IWL3945_FW_PRE,
2722 .ucode_api_max = IWL3945_UCODE_API_MAX,
2723 .ucode_api_min = IWL3945_UCODE_API_MIN,
2724 .sku = IWL_SKU_A|IWL_SKU_G,
2725 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2726 .ops = &iwl3945_ops,
2727 .mod_params = &iwl3945_mod_params,
2728 .base_params = &iwl3945_base_params,
2729 .led_mode = IWL_LED_BLINK,
2730 };
2731
2732 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2733 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2734 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2735 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2736 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2737 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2738 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2739 {0}
2740 };
2741
2742 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);