| blob | f67bc9b31b28544091b5140ad86eee5ff8fe166f |
1 /*
2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11 <http://rt2x00.serialmonkey.com>
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the
25 Free Software Foundation, Inc.,
26 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
29 /*
30 Module: rt2800
31 Abstract: Data structures and registers for the rt2800 modules.
32 Supported chipsets: RT2800E, RT2800ED & RT2800U.
33 */
35 #ifndef RT2800_H
36 #define RT2800_H
38 /*
39 * RF chip defines.
40 *
41 * RF2820 2.4G 2T3R
42 * RF2850 2.4G/5G 2T3R
43 * RF2720 2.4G 1T2R
44 * RF2750 2.4G/5G 1T2R
45 * RF3020 2.4G 1T1R
46 * RF2020 2.4G B/G
47 * RF3021 2.4G 1T2R
48 * RF3022 2.4G 2T2R
49 * RF3052 2.4G/5G 2T2R
50 * RF2853 2.4G/5G 3T3R
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54 * RF5370 2.4G 1T1R
55 * RF5390 2.4G 1T1R
56 */
57 #define RF2820 0x0001
58 #define RF2850 0x0002
59 #define RF2720 0x0003
60 #define RF2750 0x0004
61 #define RF3020 0x0005
62 #define RF2020 0x0006
63 #define RF3021 0x0007
64 #define RF3022 0x0008
65 #define RF3052 0x0009
66 #define RF2853 0x000a
67 #define RF3320 0x000b
68 #define RF3322 0x000c
69 #define RF3853 0x000d
70 #define RF5370 0x5370
71 #define RF5390 0x5390
73 /*
74 * Chipset revisions.
75 */
76 #define REV_RT2860C 0x0100
77 #define REV_RT2860D 0x0101
78 #define REV_RT2872E 0x0200
79 #define REV_RT3070E 0x0200
80 #define REV_RT3070F 0x0201
81 #define REV_RT3071E 0x0211
82 #define REV_RT3090E 0x0211
83 #define REV_RT3390E 0x0211
84 #define REV_RT5390F 0x0502
86 /*
87 * Signal information.
88 * Default offset is required for RSSI <-> dBm conversion.
89 */
90 #define DEFAULT_RSSI_OFFSET 120
92 /*
93 * Register layout information.
94 */
95 #define CSR_REG_BASE 0x1000
96 #define CSR_REG_SIZE 0x0800
97 #define EEPROM_BASE 0x0000
98 #define EEPROM_SIZE 0x0110
99 #define BBP_BASE 0x0000
100 #define BBP_SIZE 0x0080
101 #define RF_BASE 0x0004
102 #define RF_SIZE 0x0010
104 /*
105 * Number of TX queues.
106 */
107 #define NUM_TX_QUEUES 4
109 /*
110 * Registers.
111 */
113 /*
114 * E2PROM_CSR: PCI EEPROM control register.
115 * RELOAD: Write 1 to reload eeprom content.
116 * TYPE: 0: 93c46, 1:93c66.
117 * LOAD_STATUS: 1:loading, 0:done.
118 */
119 #define E2PROM_CSR 0x0004
120 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
121 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
122 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
123 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
124 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
125 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
126 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
128 /*
129 * AUX_CTRL: Aux/PCI-E related configuration
130 */
131 #define AUX_CTRL 0x10c
132 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
133 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
135 /*
136 * OPT_14: Unknown register used by rt3xxx devices.
137 */
138 #define OPT_14_CSR 0x0114
139 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
141 /*
142 * INT_SOURCE_CSR: Interrupt source register.
143 * Write one to clear corresponding bit.
144 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
145 */
146 #define INT_SOURCE_CSR 0x0200
147 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
148 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
149 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
150 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
151 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
152 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
153 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
154 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
155 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
156 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
157 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
158 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
159 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
160 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
161 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
162 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
163 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
164 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
166 /*
167 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
168 */
169 #define INT_MASK_CSR 0x0204
170 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
171 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
172 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
173 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
174 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
175 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
176 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
177 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
178 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
179 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
180 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
181 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
182 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
183 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
184 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
185 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
186 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
187 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
189 /*
190 * WPDMA_GLO_CFG
191 */
192 #define WPDMA_GLO_CFG 0x0208
193 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
194 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
195 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
196 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
197 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
198 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
199 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
200 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
201 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
203 /*
204 * WPDMA_RST_IDX
205 */
206 #define WPDMA_RST_IDX 0x020c
207 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
208 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
209 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
210 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
211 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
212 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
213 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
215 /*
216 * DELAY_INT_CFG
217 */
218 #define DELAY_INT_CFG 0x0210
219 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
220 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
221 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
222 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
223 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
224 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
226 /*
227 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
228 * AIFSN0: AC_VO
229 * AIFSN1: AC_VI
230 * AIFSN2: AC_BE
231 * AIFSN3: AC_BK
232 */
233 #define WMM_AIFSN_CFG 0x0214
234 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
235 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
236 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
237 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
239 /*
240 * WMM_CWMIN_CSR: CWmin for each EDCA AC
241 * CWMIN0: AC_VO
242 * CWMIN1: AC_VI
243 * CWMIN2: AC_BE
244 * CWMIN3: AC_BK
245 */
246 #define WMM_CWMIN_CFG 0x0218
247 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
248 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
249 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
250 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
252 /*
253 * WMM_CWMAX_CSR: CWmax for each EDCA AC
254 * CWMAX0: AC_VO
255 * CWMAX1: AC_VI
256 * CWMAX2: AC_BE
257 * CWMAX3: AC_BK
258 */
259 #define WMM_CWMAX_CFG 0x021c
260 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
261 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
262 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
263 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
265 /*
266 * AC_TXOP0: AC_VO/AC_VI TXOP register
267 * AC0TXOP: AC_VO in unit of 32us
268 * AC1TXOP: AC_VI in unit of 32us
269 */
270 #define WMM_TXOP0_CFG 0x0220
271 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
272 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
274 /*
275 * AC_TXOP1: AC_BE/AC_BK TXOP register
276 * AC2TXOP: AC_BE in unit of 32us
277 * AC3TXOP: AC_BK in unit of 32us
278 */
279 #define WMM_TXOP1_CFG 0x0224
280 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
281 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
283 /*
284 * GPIO_CTRL_CFG:
285 * GPIOD: GPIO direction, 0: Output, 1: Input
286 */
287 #define GPIO_CTRL_CFG 0x0228
288 #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
289 #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
290 #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
291 #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
292 #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
293 #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
294 #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
295 #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
296 #define GPIO_CTRL_CFG_GPIOD_BIT0 FIELD32(0x00000100)
297 #define GPIO_CTRL_CFG_GPIOD_BIT1 FIELD32(0x00000200)
298 #define GPIO_CTRL_CFG_GPIOD_BIT2 FIELD32(0x00000400)
299 #define GPIO_CTRL_CFG_GPIOD_BIT3 FIELD32(0x00000800)
300 #define GPIO_CTRL_CFG_GPIOD_BIT4 FIELD32(0x00001000)
301 #define GPIO_CTRL_CFG_GPIOD_BIT5 FIELD32(0x00002000)
302 #define GPIO_CTRL_CFG_GPIOD_BIT6 FIELD32(0x00004000)
303 #define GPIO_CTRL_CFG_GPIOD_BIT7 FIELD32(0x00008000)
305 /*
306 * MCU_CMD_CFG
307 */
308 #define MCU_CMD_CFG 0x022c
310 /*
311 * AC_VO register offsets
312 */
313 #define TX_BASE_PTR0 0x0230
314 #define TX_MAX_CNT0 0x0234
315 #define TX_CTX_IDX0 0x0238
316 #define TX_DTX_IDX0 0x023c
318 /*
319 * AC_VI register offsets
320 */
321 #define TX_BASE_PTR1 0x0240
322 #define TX_MAX_CNT1 0x0244
323 #define TX_CTX_IDX1 0x0248
324 #define TX_DTX_IDX1 0x024c
326 /*
327 * AC_BE register offsets
328 */
329 #define TX_BASE_PTR2 0x0250
330 #define TX_MAX_CNT2 0x0254
331 #define TX_CTX_IDX2 0x0258
332 #define TX_DTX_IDX2 0x025c
334 /*
335 * AC_BK register offsets
336 */
337 #define TX_BASE_PTR3 0x0260
338 #define TX_MAX_CNT3 0x0264
339 #define TX_CTX_IDX3 0x0268
340 #define TX_DTX_IDX3 0x026c
342 /*
343 * HCCA register offsets
344 */
345 #define TX_BASE_PTR4 0x0270
346 #define TX_MAX_CNT4 0x0274
347 #define TX_CTX_IDX4 0x0278
348 #define TX_DTX_IDX4 0x027c
350 /*
351 * MGMT register offsets
352 */
353 #define TX_BASE_PTR5 0x0280
354 #define TX_MAX_CNT5 0x0284
355 #define TX_CTX_IDX5 0x0288
356 #define TX_DTX_IDX5 0x028c
358 /*
359 * RX register offsets
360 */
361 #define RX_BASE_PTR 0x0290
362 #define RX_MAX_CNT 0x0294
363 #define RX_CRX_IDX 0x0298
364 #define RX_DRX_IDX 0x029c
366 /*
367 * USB_DMA_CFG
368 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
369 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
370 * PHY_CLEAR: phy watch dog enable.
371 * TX_CLEAR: Clear USB DMA TX path.
372 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
373 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
374 * RX_BULK_EN: Enable USB DMA Rx.
375 * TX_BULK_EN: Enable USB DMA Tx.
376 * EP_OUT_VALID: OUT endpoint data valid.
377 * RX_BUSY: USB DMA RX FSM busy.
378 * TX_BUSY: USB DMA TX FSM busy.
379 */
380 #define USB_DMA_CFG 0x02a0
381 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
382 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
383 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
384 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
385 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
386 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
387 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
388 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
389 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
390 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
391 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
393 /*
394 * US_CYC_CNT
395 * BT_MODE_EN: Bluetooth mode enable
396 * CLOCK CYCLE: Clock cycle count in 1us.
397 * PCI:0x21, PCIE:0x7d, USB:0x1e
398 */
399 #define US_CYC_CNT 0x02a4
400 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
401 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
403 /*
404 * PBF_SYS_CTRL
405 * HOST_RAM_WRITE: enable Host program ram write selection
406 */
407 #define PBF_SYS_CTRL 0x0400
408 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
409 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
411 /*
412 * HOST-MCU shared memory
413 */
414 #define HOST_CMD_CSR 0x0404
415 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
417 /*
418 * PBF registers
419 * Most are for debug. Driver doesn't touch PBF register.
420 */
421 #define PBF_CFG 0x0408
422 #define PBF_MAX_PCNT 0x040c
423 #define PBF_CTRL 0x0410
424 #define PBF_INT_STA 0x0414
425 #define PBF_INT_ENA 0x0418
427 /*
428 * BCN_OFFSET0:
429 */
430 #define BCN_OFFSET0 0x042c
431 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
432 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
433 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
434 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
436 /*
437 * BCN_OFFSET1:
438 */
439 #define BCN_OFFSET1 0x0430
440 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
441 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
442 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
443 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
445 /*
446 * TXRXQ_PCNT: PBF register
447 * PCNT_TX0Q: Page count for TX hardware queue 0
448 * PCNT_TX1Q: Page count for TX hardware queue 1
449 * PCNT_TX2Q: Page count for TX hardware queue 2
450 * PCNT_RX0Q: Page count for RX hardware queue
451 */
452 #define TXRXQ_PCNT 0x0438
453 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
454 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
455 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
456 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
458 /*
459 * PBF register
460 * Debug. Driver doesn't touch PBF register.
461 */
462 #define PBF_DBG 0x043c
464 /*
465 * RF registers
466 */
467 #define RF_CSR_CFG 0x0500
468 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
469 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
470 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
471 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
473 /*
474 * EFUSE_CSR: RT30x0 EEPROM
475 */
476 #define EFUSE_CTRL 0x0580
477 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
478 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
479 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
480 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
482 /*
483 * EFUSE_DATA0
484 */
485 #define EFUSE_DATA0 0x0590
487 /*
488 * EFUSE_DATA1
489 */
490 #define EFUSE_DATA1 0x0594
492 /*
493 * EFUSE_DATA2
494 */
495 #define EFUSE_DATA2 0x0598
497 /*
498 * EFUSE_DATA3
499 */
500 #define EFUSE_DATA3 0x059c
502 /*
503 * LDO_CFG0
504 */
505 #define LDO_CFG0 0x05d4
506 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
507 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
508 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
509 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
510 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
511 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
512 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
514 /*
515 * GPIO_SWITCH
516 */
517 #define GPIO_SWITCH 0x05dc
518 #define GPIO_SWITCH_0 FIELD32(0x00000001)
519 #define GPIO_SWITCH_1 FIELD32(0x00000002)
520 #define GPIO_SWITCH_2 FIELD32(0x00000004)
521 #define GPIO_SWITCH_3 FIELD32(0x00000008)
522 #define GPIO_SWITCH_4 FIELD32(0x00000010)
523 #define GPIO_SWITCH_5 FIELD32(0x00000020)
524 #define GPIO_SWITCH_6 FIELD32(0x00000040)
525 #define GPIO_SWITCH_7 FIELD32(0x00000080)
527 /*
528 * MAC Control/Status Registers(CSR).
529 * Some values are set in TU, whereas 1 TU == 1024 us.
530 */
532 /*
533 * MAC_CSR0: ASIC revision number.
534 * ASIC_REV: 0
535 * ASIC_VER: 2860 or 2870
536 */
537 #define MAC_CSR0 0x1000
538 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
539 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
541 /*
542 * MAC_SYS_CTRL:
543 */
544 #define MAC_SYS_CTRL 0x1004
545 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
546 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
547 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
548 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
549 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
550 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
551 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
552 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
554 /*
555 * MAC_ADDR_DW0: STA MAC register 0
556 */
557 #define MAC_ADDR_DW0 0x1008
558 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
559 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
560 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
561 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
563 /*
564 * MAC_ADDR_DW1: STA MAC register 1
565 * UNICAST_TO_ME_MASK:
566 * Used to mask off bits from byte 5 of the MAC address
567 * to determine the UNICAST_TO_ME bit for RX frames.
568 * The full mask is complemented by BSS_ID_MASK:
569 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
570 */
571 #define MAC_ADDR_DW1 0x100c
572 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
573 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
574 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
576 /*
577 * MAC_BSSID_DW0: BSSID register 0
578 */
579 #define MAC_BSSID_DW0 0x1010
580 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
581 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
582 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
583 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
585 /*
586 * MAC_BSSID_DW1: BSSID register 1
587 * BSS_ID_MASK:
588 * 0: 1-BSSID mode (BSS index = 0)
589 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
590 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
591 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
592 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
593 * BSSID. This will make sure that those bits will be ignored
594 * when determining the MY_BSS of RX frames.
595 */
596 #define MAC_BSSID_DW1 0x1014
597 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
598 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
599 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
600 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
602 /*
603 * MAX_LEN_CFG: Maximum frame length register.
604 * MAX_MPDU: rt2860b max 16k bytes
605 * MAX_PSDU: Maximum PSDU length
606 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
607 */
608 #define MAX_LEN_CFG 0x1018
609 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
610 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
611 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
612 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
614 /*
615 * BBP_CSR_CFG: BBP serial control register
616 * VALUE: Register value to program into BBP
617 * REG_NUM: Selected BBP register
618 * READ_CONTROL: 0 write BBP, 1 read BBP
619 * BUSY: ASIC is busy executing BBP commands
620 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
621 * BBP_RW_MODE: 0 serial, 1 parallel
622 */
623 #define BBP_CSR_CFG 0x101c
624 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
625 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
626 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
627 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
628 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
629 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
631 /*
632 * RF_CSR_CFG0: RF control register
633 * REGID_AND_VALUE: Register value to program into RF
634 * BITWIDTH: Selected RF register
635 * STANDBYMODE: 0 high when standby, 1 low when standby
636 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
637 * BUSY: ASIC is busy executing RF commands
638 */
639 #define RF_CSR_CFG0 0x1020
640 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
641 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
642 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
643 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
644 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
645 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
647 /*
648 * RF_CSR_CFG1: RF control register
649 * REGID_AND_VALUE: Register value to program into RF
650 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
651 * 0: 3 system clock cycle (37.5usec)
652 * 1: 5 system clock cycle (62.5usec)
653 */
654 #define RF_CSR_CFG1 0x1024
655 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
656 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
658 /*
659 * RF_CSR_CFG2: RF control register
660 * VALUE: Register value to program into RF
661 */
662 #define RF_CSR_CFG2 0x1028
663 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
665 /*
666 * LED_CFG: LED control
667 * color LED's:
668 * 0: off
669 * 1: blinking upon TX2
670 * 2: periodic slow blinking
671 * 3: always on
672 * LED polarity:
673 * 0: active low
674 * 1: active high
675 */
676 #define LED_CFG 0x102c
677 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
678 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
679 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
680 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
681 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
682 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
683 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
685 /*
686 * AMPDU_BA_WINSIZE: Force BlockAck window size
687 * FORCE_WINSIZE_ENABLE:
688 * 0: Disable forcing of BlockAck window size
689 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
690 * window size values in the TXWI
691 * FORCE_WINSIZE: BlockAck window size
692 */
693 #define AMPDU_BA_WINSIZE 0x1040
694 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
695 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
697 /*
698 * XIFS_TIME_CFG: MAC timing
699 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
700 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
701 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
702 * when MAC doesn't reference BBP signal BBRXEND
703 * EIFS: unit 1us
704 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
705 *
706 */
707 #define XIFS_TIME_CFG 0x1100
708 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
709 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
710 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
711 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
712 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
714 /*
715 * BKOFF_SLOT_CFG:
716 */
717 #define BKOFF_SLOT_CFG 0x1104
718 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
719 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
721 /*
722 * NAV_TIME_CFG:
723 */
724 #define NAV_TIME_CFG 0x1108
725 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
726 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
727 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
728 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
730 /*
731 * CH_TIME_CFG: count as channel busy
732 * EIFS_BUSY: Count EIFS as channel busy
733 * NAV_BUSY: Count NAS as channel busy
734 * RX_BUSY: Count RX as channel busy
735 * TX_BUSY: Count TX as channel busy
736 * TMR_EN: Enable channel statistics timer
737 */
738 #define CH_TIME_CFG 0x110c
739 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
740 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
741 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
742 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
743 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
745 /*
746 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
747 */
748 #define PBF_LIFE_TIMER 0x1110
750 /*
751 * BCN_TIME_CFG:
752 * BEACON_INTERVAL: in unit of 1/16 TU
753 * TSF_TICKING: Enable TSF auto counting
754 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
755 * BEACON_GEN: Enable beacon generator
756 */
757 #define BCN_TIME_CFG 0x1114
758 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
759 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
760 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
761 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
762 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
763 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
765 /*
766 * TBTT_SYNC_CFG:
767 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
768 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
769 */
770 #define TBTT_SYNC_CFG 0x1118
771 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
772 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
773 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
774 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
776 /*
777 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
778 */
779 #define TSF_TIMER_DW0 0x111c
780 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
782 /*
783 * TSF_TIMER_DW1: Local msb TSF timer, read-only
784 */
785 #define TSF_TIMER_DW1 0x1120
786 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
788 /*
789 * TBTT_TIMER: TImer remains till next TBTT, read-only
790 */
791 #define TBTT_TIMER 0x1124
793 /*
794 * INT_TIMER_CFG: timer configuration
795 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
796 * GP_TIMER: period of general purpose timer in units of 1/16 TU
797 */
798 #define INT_TIMER_CFG 0x1128
799 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
800 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
802 /*
803 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
804 */
805 #define INT_TIMER_EN 0x112c
806 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
807 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
809 /*
810 * CH_IDLE_STA: channel idle time (in us)
811 */
812 #define CH_IDLE_STA 0x1130
814 /*
815 * CH_BUSY_STA: channel busy time on primary channel (in us)
816 */
817 #define CH_BUSY_STA 0x1134
819 /*
820 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
821 */
822 #define CH_BUSY_STA_SEC 0x1138
824 /*
825 * MAC_STATUS_CFG:
826 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
827 * if 1 or higher one of the 2 registers is busy.
828 */
829 #define MAC_STATUS_CFG 0x1200
830 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
832 /*
833 * PWR_PIN_CFG:
834 */
835 #define PWR_PIN_CFG 0x1204
837 /*
838 * AUTOWAKEUP_CFG: Manual power control / status register
839 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
840 * AUTOWAKE: 0:sleep, 1:awake
841 */
842 #define AUTOWAKEUP_CFG 0x1208
843 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
844 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
845 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
847 /*
848 * EDCA_AC0_CFG:
849 */
850 #define EDCA_AC0_CFG 0x1300
851 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
852 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
853 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
854 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
856 /*
857 * EDCA_AC1_CFG:
858 */
859 #define EDCA_AC1_CFG 0x1304
860 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
861 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
862 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
863 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
865 /*
866 * EDCA_AC2_CFG:
867 */
868 #define EDCA_AC2_CFG 0x1308
869 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
870 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
871 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
872 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
874 /*
875 * EDCA_AC3_CFG:
876 */
877 #define EDCA_AC3_CFG 0x130c
878 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
879 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
880 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
881 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
883 /*
884 * EDCA_TID_AC_MAP:
885 */
886 #define EDCA_TID_AC_MAP 0x1310
888 /*
889 * TX_PWR_CFG:
890 */
891 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
892 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
893 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
894 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
895 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
896 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
897 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
898 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
900 /*
901 * TX_PWR_CFG_0:
902 */
903 #define TX_PWR_CFG_0 0x1314
904 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
905 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
906 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
907 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
908 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
909 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
910 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
911 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
913 /*
914 * TX_PWR_CFG_1:
915 */
916 #define TX_PWR_CFG_1 0x1318
917 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
918 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
919 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
920 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
921 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
922 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
923 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
924 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
926 /*
927 * TX_PWR_CFG_2:
928 */
929 #define TX_PWR_CFG_2 0x131c
930 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
931 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
932 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
933 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
934 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
935 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
936 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
937 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
939 /*
940 * TX_PWR_CFG_3:
941 */
942 #define TX_PWR_CFG_3 0x1320
943 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
944 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
945 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
946 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
947 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
948 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
949 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
950 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
952 /*
953 * TX_PWR_CFG_4:
954 */
955 #define TX_PWR_CFG_4 0x1324
956 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
957 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
958 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
959 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
961 /*
962 * TX_PIN_CFG:
963 */
964 #define TX_PIN_CFG 0x1328
965 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
966 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
967 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
968 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
969 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
970 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
971 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
972 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
973 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
974 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
975 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
976 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
977 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
978 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
979 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
980 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
981 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
982 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
983 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
984 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
986 /*
987 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
988 */
989 #define TX_BAND_CFG 0x132c
990 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
991 #define TX_BAND_CFG_A FIELD32(0x00000002)
992 #define TX_BAND_CFG_BG FIELD32(0x00000004)
994 /*
995 * TX_SW_CFG0:
996 */
997 #define TX_SW_CFG0 0x1330
999 /*
1000 * TX_SW_CFG1:
1001 */
1002 #define TX_SW_CFG1 0x1334
1004 /*
1005 * TX_SW_CFG2:
1006 */
1007 #define TX_SW_CFG2 0x1338
1009 /*
1010 * TXOP_THRES_CFG:
1011 */
1012 #define TXOP_THRES_CFG 0x133c
1014 /*
1015 * TXOP_CTRL_CFG:
1016 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1017 * AC_TRUN_EN: Enable/Disable truncation for AC change
1018 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1019 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1020 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1021 * RESERVED_TRUN_EN: Reserved
1022 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1023 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1024 * transmissions if extension CCA is clear).
1025 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1026 * EXT_CWMIN: CwMin for extension channel backoff
1027 * 0: Disabled
1028 *
1029 */
1030 #define TXOP_CTRL_CFG 0x1340
1031 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1032 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1033 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1034 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1035 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1036 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1037 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1038 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1039 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1040 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1042 /*
1043 * TX_RTS_CFG:
1044 * RTS_THRES: unit:byte
1045 * RTS_FBK_EN: enable rts rate fallback
1046 */
1047 #define TX_RTS_CFG 0x1344
1048 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1049 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1050 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1052 /*
1053 * TX_TIMEOUT_CFG:
1054 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1055 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1056 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1057 * it is recommended that:
1058 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1059 */
1060 #define TX_TIMEOUT_CFG 0x1348
1061 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1062 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1063 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1065 /*
1066 * TX_RTY_CFG:
1067 * SHORT_RTY_LIMIT: short retry limit
1068 * LONG_RTY_LIMIT: long retry limit
1069 * LONG_RTY_THRE: Long retry threshoold
1070 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1071 * 0:expired by retry limit, 1: expired by mpdu life timer
1072 * AGG_RTY_MODE: Aggregate MPDU retry mode
1073 * 0:expired by retry limit, 1: expired by mpdu life timer
1074 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1075 */
1076 #define TX_RTY_CFG 0x134c
1077 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1078 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1079 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1080 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1081 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1082 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1084 /*
1085 * TX_LINK_CFG:
1086 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1087 * MFB_ENABLE: TX apply remote MFB 1:enable
1088 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1089 * 0: not apply remote remote unsolicit (MFS=7)
1090 * TX_MRQ_EN: MCS request TX enable
1091 * TX_RDG_EN: RDG TX enable
1092 * TX_CF_ACK_EN: Piggyback CF-ACK enable
1093 * REMOTE_MFB: remote MCS feedback
1094 * REMOTE_MFS: remote MCS feedback sequence number
1095 */
1096 #define TX_LINK_CFG 0x1350
1097 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1098 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1099 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1100 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1101 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1102 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1103 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1104 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1106 /*
1107 * HT_FBK_CFG0:
1108 */
1109 #define HT_FBK_CFG0 0x1354
1110 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1111 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1112 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1113 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1114 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1115 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1116 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1117 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1119 /*
1120 * HT_FBK_CFG1:
1121 */
1122 #define HT_FBK_CFG1 0x1358
1123 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1124 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1125 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1126 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1127 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1128 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1129 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1130 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1132 /*
1133 * LG_FBK_CFG0:
1134 */
1135 #define LG_FBK_CFG0 0x135c
1136 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1137 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1138 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1139 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1140 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1141 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1142 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1143 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1145 /*
1146 * LG_FBK_CFG1:
1147 */
1148 #define LG_FBK_CFG1 0x1360
1149 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1150 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1151 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1152 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1154 /*
1155 * CCK_PROT_CFG: CCK Protection
1156 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1157 * PROTECT_CTRL: Protection control frame type for CCK TX
1158 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1159 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1160 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1161 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1162 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1163 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1164 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1165 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1166 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1167 * RTS_TH_EN: RTS threshold enable on CCK TX
1168 */
1169 #define CCK_PROT_CFG 0x1364
1170 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1171 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1172 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1173 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1174 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1175 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1176 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1177 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1178 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1179 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1180 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1182 /*
1183 * OFDM_PROT_CFG: OFDM Protection
1184 */
1185 #define OFDM_PROT_CFG 0x1368
1186 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1187 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1188 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1189 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1190 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1191 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1192 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1193 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1194 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1195 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1196 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1198 /*
1199 * MM20_PROT_CFG: MM20 Protection
1200 */
1201 #define MM20_PROT_CFG 0x136c
1202 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1203 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1204 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1205 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1206 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1207 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1208 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1209 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1210 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1211 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1212 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1214 /*
1215 * MM40_PROT_CFG: MM40 Protection
1216 */
1217 #define MM40_PROT_CFG 0x1370
1218 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1219 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1220 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1221 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1222 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1223 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1224 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1225 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1226 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1227 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1228 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1230 /*
1231 * GF20_PROT_CFG: GF20 Protection
1232 */
1233 #define GF20_PROT_CFG 0x1374
1234 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1235 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1236 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1237 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1238 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1239 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1240 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1241 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1242 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1243 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1244 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1246 /*
1247 * GF40_PROT_CFG: GF40 Protection
1248 */
1249 #define GF40_PROT_CFG 0x1378
1250 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1251 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1252 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1253 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1254 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1255 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1256 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1257 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1258 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1259 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1260 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1262 /*
1263 * EXP_CTS_TIME:
1264 */
1265 #define EXP_CTS_TIME 0x137c
1267 /*
1268 * EXP_ACK_TIME:
1269 */
1270 #define EXP_ACK_TIME 0x1380
1272 /*
1273 * RX_FILTER_CFG: RX configuration register.
1274 */
1275 #define RX_FILTER_CFG 0x1400
1276 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1277 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1278 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1279 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1280 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1281 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1282 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1283 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1284 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1285 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1286 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1287 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1288 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1289 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1290 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1291 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1292 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1294 /*
1295 * AUTO_RSP_CFG:
1296 * AUTORESPONDER: 0: disable, 1: enable
1297 * BAC_ACK_POLICY: 0:long, 1:short preamble
1298 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1299 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1300 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1301 * DUAL_CTS_EN: Power bit value in control frame
1302 * ACK_CTS_PSM_BIT:Power bit value in control frame
1303 */
1304 #define AUTO_RSP_CFG 0x1404
1305 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1306 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1307 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1308 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1309 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1310 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1311 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1313 /*
1314 * LEGACY_BASIC_RATE:
1315 */
1316 #define LEGACY_BASIC_RATE 0x1408
1318 /*
1319 * HT_BASIC_RATE:
1320 */
1321 #define HT_BASIC_RATE 0x140c
1323 /*
1324 * HT_CTRL_CFG:
1325 */
1326 #define HT_CTRL_CFG 0x1410
1328 /*
1329 * SIFS_COST_CFG:
1330 */
1331 #define SIFS_COST_CFG 0x1414
1333 /*
1334 * RX_PARSER_CFG:
1335 * Set NAV for all received frames
1336 */
1337 #define RX_PARSER_CFG 0x1418
1339 /*
1340 * TX_SEC_CNT0:
1341 */
1342 #define TX_SEC_CNT0 0x1500
1344 /*
1345 * RX_SEC_CNT0:
1346 */
1347 #define RX_SEC_CNT0 0x1504
1349 /*
1350 * CCMP_FC_MUTE:
1351 */
1352 #define CCMP_FC_MUTE 0x1508
1354 /*
1355 * TXOP_HLDR_ADDR0:
1356 */
1357 #define TXOP_HLDR_ADDR0 0x1600
1359 /*
1360 * TXOP_HLDR_ADDR1:
1361 */
1362 #define TXOP_HLDR_ADDR1 0x1604
1364 /*
1365 * TXOP_HLDR_ET:
1366 */
1367 #define TXOP_HLDR_ET 0x1608
1369 /*
1370 * QOS_CFPOLL_RA_DW0:
1371 */
1372 #define QOS_CFPOLL_RA_DW0 0x160c
1374 /*
1375 * QOS_CFPOLL_RA_DW1:
1376 */
1377 #define QOS_CFPOLL_RA_DW1 0x1610
1379 /*
1380 * QOS_CFPOLL_QC:
1381 */
1382 #define QOS_CFPOLL_QC 0x1614
1384 /*
1385 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1386 */
1387 #define RX_STA_CNT0 0x1700
1388 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1389 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1391 /*
1392 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1393 */
1394 #define RX_STA_CNT1 0x1704
1395 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1396 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1398 /*
1399 * RX_STA_CNT2:
1400 */
1401 #define RX_STA_CNT2 0x1708
1402 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1403 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1405 /*
1406 * TX_STA_CNT0: TX Beacon count
1407 */
1408 #define TX_STA_CNT0 0x170c
1409 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1410 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1412 /*
1413 * TX_STA_CNT1: TX tx count
1414 */
1415 #define TX_STA_CNT1 0x1710
1416 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1417 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1419 /*
1420 * TX_STA_CNT2: TX tx count
1421 */
1422 #define TX_STA_CNT2 0x1714
1423 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1424 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1426 /*
1427 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1428 *
1429 * This register is implemented as FIFO with 16 entries in the HW. Each
1430 * register read fetches the next tx result. If the FIFO is full because
1431 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1432 * triggered, the hw seems to simply drop further tx results.
1433 *
1434 * VALID: 1: this tx result is valid
1435 * 0: no valid tx result -> driver should stop reading
1436 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1437 * to match a frame with its tx result (even though the PID is
1438 * only 4 bits wide).
1439 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1440 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1441 * This identification number is calculated by ((idx % 3) + 1).
1442 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1443 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1444 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1445 * WCID: The wireless client ID.
1446 * MCS: The tx rate used during the last transmission of this frame, be it
1447 * successful or not.
1448 * PHYMODE: The phymode used for the transmission.
1449 */
1450 #define TX_STA_FIFO 0x1718
1451 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1452 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1453 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1454 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1455 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1456 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1457 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1458 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1459 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1460 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1461 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1463 /*
1464 * TX_AGG_CNT: Debug counter
1465 */
1466 #define TX_AGG_CNT 0x171c
1467 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1468 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1470 /*
1471 * TX_AGG_CNT0:
1472 */
1473 #define TX_AGG_CNT0 0x1720
1474 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1475 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1477 /*
1478 * TX_AGG_CNT1:
1479 */
1480 #define TX_AGG_CNT1 0x1724
1481 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1482 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1484 /*
1485 * TX_AGG_CNT2:
1486 */
1487 #define TX_AGG_CNT2 0x1728
1488 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1489 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1491 /*
1492 * TX_AGG_CNT3:
1493 */
1494 #define TX_AGG_CNT3 0x172c
1495 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1496 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1498 /*
1499 * TX_AGG_CNT4:
1500 */
1501 #define TX_AGG_CNT4 0x1730
1502 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1503 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1505 /*
1506 * TX_AGG_CNT5:
1507 */
1508 #define TX_AGG_CNT5 0x1734
1509 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1510 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1512 /*
1513 * TX_AGG_CNT6:
1514 */
1515 #define TX_AGG_CNT6 0x1738
1516 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1517 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1519 /*
1520 * TX_AGG_CNT7:
1521 */
1522 #define TX_AGG_CNT7 0x173c
1523 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1524 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1526 /*
1527 * MPDU_DENSITY_CNT:
1528 * TX_ZERO_DEL: TX zero length delimiter count
1529 * RX_ZERO_DEL: RX zero length delimiter count
1530 */
1531 #define MPDU_DENSITY_CNT 0x1740
1532 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1533 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1535 /*
1536 * Security key table memory.
1537 *
1538 * The pairwise key table shares some memory with the beacon frame
1539 * buffers 6 and 7. That basically means that when beacon 6 & 7
1540 * are used we should only use the reduced pairwise key table which
1541 * has a maximum of 222 entries.
1542 *
1543 * ---------------------------------------------
1544 * |0x4000 | Pairwise Key | Reduced Pairwise |
1545 * | | Table | Key Table |
1546 * | | Size: 256 * 32 | Size: 222 * 32 |
1547 * |0x5BC0 | |-------------------
1548 * | | | Beacon 6 |
1549 * |0x5DC0 | |-------------------
1550 * | | | Beacon 7 |
1551 * |0x5FC0 | |-------------------
1552 * |0x5FFF | |
1553 * --------------------------
1554 *
1555 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1556 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1557 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1558 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1559 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1560 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1561 */
1562 #define MAC_WCID_BASE 0x1800
1563 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1564 #define MAC_IVEIV_TABLE_BASE 0x6000
1565 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1566 #define SHARED_KEY_TABLE_BASE 0x6c00
1567 #define SHARED_KEY_MODE_BASE 0x7000
1569 #define MAC_WCID_ENTRY(__idx) \
1570 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1571 #define PAIRWISE_KEY_ENTRY(__idx) \
1572 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1573 #define MAC_IVEIV_ENTRY(__idx) \
1574 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1575 #define MAC_WCID_ATTR_ENTRY(__idx) \
1576 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1577 #define SHARED_KEY_ENTRY(__idx) \
1578 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1579 #define SHARED_KEY_MODE_ENTRY(__idx) \
1580 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1597 /*
1598 * MAC_WCID_ATTRIBUTE:
1599 */
1600 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1601 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1602 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1603 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1604 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1605 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1606 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1607 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1609 /*
1610 * SHARED_KEY_MODE:
1611 */
1612 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1613 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1614 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1615 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1616 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1617 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1618 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1619 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1621 /*
1622 * HOST-MCU communication
1623 */
1625 /*
1626 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1627 */
1628 #define H2M_MAILBOX_CSR 0x7010
1629 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1630 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1631 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1632 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1634 /*
1635 * H2M_MAILBOX_CID:
1636 */
1637 #define H2M_MAILBOX_CID 0x7014
1638 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1639 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1640 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1641 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1643 /*
1644 * H2M_MAILBOX_STATUS:
1645 */
1646 #define H2M_MAILBOX_STATUS 0x701c
1648 /*
1649 * H2M_INT_SRC:
1650 */
1651 #define H2M_INT_SRC 0x7024
1653 /*
1654 * H2M_BBP_AGENT:
1655 */
1656 #define H2M_BBP_AGENT 0x7028
1658 /*
1659 * MCU_LEDCS: LED control for MCU Mailbox.
1660 */
1661 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1662 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1664 /*
1665 * HW_CS_CTS_BASE:
1666 * Carrier-sense CTS frame base address.
1667 * It's where mac stores carrier-sense frame for carrier-sense function.
1668 */
1669 #define HW_CS_CTS_BASE 0x7700
1671 /*
1672 * HW_DFS_CTS_BASE:
1673 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1674 */
1675 #define HW_DFS_CTS_BASE 0x7780
1677 /*
1678 * TXRX control registers - base address 0x3000
1679 */
1681 /*
1682 * TXRX_CSR1:
1683 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1684 */
1685 #define TXRX_CSR1 0x77d0
1687 /*
1688 * HW_DEBUG_SETTING_BASE:
1689 * since NULL frame won't be that long (256 byte)
1690 * We steal 16 tail bytes to save debugging settings
1691 */
1692 #define HW_DEBUG_SETTING_BASE 0x77f0
1693 #define HW_DEBUG_SETTING_BASE2 0x7770
1695 /*
1696 * HW_BEACON_BASE
1697 * In order to support maximum 8 MBSS and its maximum length
1698 * is 512 bytes for each beacon
1699 * Three section discontinue memory segments will be used.
1700 * 1. The original region for BCN 0~3
1701 * 2. Extract memory from FCE table for BCN 4~5
1702 * 3. Extract memory from Pair-wise key table for BCN 6~7
1703 * It occupied those memory of wcid 238~253 for BCN 6
1704 * and wcid 222~237 for BCN 7 (see Security key table memory
1705 * for more info).
1706 *
1707 * IMPORTANT NOTE: Not sure why legacy driver does this,
1708 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1709 */
1710 #define HW_BEACON_BASE0 0x7800
1711 #define HW_BEACON_BASE1 0x7a00
1712 #define HW_BEACON_BASE2 0x7c00
1713 #define HW_BEACON_BASE3 0x7e00
1714 #define HW_BEACON_BASE4 0x7200
1715 #define HW_BEACON_BASE5 0x7400
1716 #define HW_BEACON_BASE6 0x5dc0
1717 #define HW_BEACON_BASE7 0x5bc0
1719 #define HW_BEACON_OFFSET(__index) \
1720 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
1721 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
1722 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
1724 /*
1725 * BBP registers.
1726 * The wordsize of the BBP is 8 bits.
1727 */
1729 /*
1730 * BBP 1: TX Antenna & Power Control
1731 * POWER_CTRL:
1732 * 0 - normal,
1733 * 1 - drop tx power by 6dBm,
1734 * 2 - drop tx power by 12dBm,
1735 * 3 - increase tx power by 6dBm
1736 */
1737 #define BBP1_TX_POWER_CTRL FIELD8(0x07)
1738 #define BBP1_TX_ANTENNA FIELD8(0x18)
1740 /*
1741 * BBP 3: RX Antenna
1742 */
1743 #define BBP3_RX_ANTENNA FIELD8(0x18)
1744 #define BBP3_HT40_MINUS FIELD8(0x20)
1746 /*
1747 * BBP 4: Bandwidth
1748 */
1749 #define BBP4_TX_BF FIELD8(0x01)
1750 #define BBP4_BANDWIDTH FIELD8(0x18)
1751 #define BBP4_MAC_IF_CTRL FIELD8(0x40)
1753 /*
1754 * BBP 109
1755 */
1756 #define BBP109_TX0_POWER FIELD8(0x0f)
1757 #define BBP109_TX1_POWER FIELD8(0xf0)
1759 /*
1760 * BBP 138: Unknown
1761 */
1762 #define BBP138_RX_ADC1 FIELD8(0x02)
1763 #define BBP138_RX_ADC2 FIELD8(0x04)
1764 #define BBP138_TX_DAC1 FIELD8(0x20)
1765 #define BBP138_TX_DAC2 FIELD8(0x40)
1767 /*
1768 * BBP 152: Rx Ant
1769 */
1770 #define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1772 /*
1773 * RFCSR registers
1774 * The wordsize of the RFCSR is 8 bits.
1775 */
1777 /*
1778 * RFCSR 1:
1779 */
1780 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1781 #define RFCSR1_PLL_PD FIELD8(0x02)
1782 #define RFCSR1_RX0_PD FIELD8(0x04)
1783 #define RFCSR1_TX0_PD FIELD8(0x08)
1784 #define RFCSR1_RX1_PD FIELD8(0x10)
1785 #define RFCSR1_TX1_PD FIELD8(0x20)
1787 /*
1788 * RFCSR 2:
1789 */
1790 #define RFCSR2_RESCAL_EN FIELD8(0x80)
1792 /*
1793 * RFCSR 6:
1794 */
1795 #define RFCSR6_R1 FIELD8(0x03)
1796 #define RFCSR6_R2 FIELD8(0x40)
1798 /*
1799 * RFCSR 7:
1800 */
1801 #define RFCSR7_RF_TUNING FIELD8(0x01)
1803 /*
1804 * RFCSR 11:
1805 */
1806 #define RFCSR11_R FIELD8(0x03)
1808 /*
1809 * RFCSR 12:
1810 */
1811 #define RFCSR12_TX_POWER FIELD8(0x1f)
1813 /*
1814 * RFCSR 13:
1815 */
1816 #define RFCSR13_TX_POWER FIELD8(0x1f)
1818 /*
1819 * RFCSR 15:
1820 */
1821 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
1823 /*
1824 * RFCSR 17:
1825 */
1826 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1827 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
1828 #define RFCSR17_R FIELD8(0x20)
1829 #define RFCSR17_CODE FIELD8(0x7f)
1831 /*
1832 * RFCSR 20:
1833 */
1834 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
1836 /*
1837 * RFCSR 21:
1838 */
1839 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
1841 /*
1842 * RFCSR 22:
1843 */
1844 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1846 /*
1847 * RFCSR 23:
1848 */
1849 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1851 /*
1852 * RFCSR 27:
1853 */
1854 #define RFCSR27_R1 FIELD8(0x03)
1855 #define RFCSR27_R2 FIELD8(0x04)
1856 #define RFCSR27_R3 FIELD8(0x30)
1857 #define RFCSR27_R4 FIELD8(0x40)
1859 /*
1860 * RFCSR 30:
1861 */
1862 #define RFCSR30_TX_H20M FIELD8(0x02)
1863 #define RFCSR30_RX_H20M FIELD8(0x04)
1864 #define RFCSR30_RX_VCM FIELD8(0x18)
1865 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1867 /*
1868 * RFCSR 31:
1869 */
1870 #define RFCSR31_RX_AGC_FC FIELD8(0x1f)
1871 #define RFCSR31_RX_H20M FIELD8(0x20)
1873 /*
1874 * RFCSR 38:
1875 */
1876 #define RFCSR38_RX_LO1_EN FIELD8(0x20)
1878 /*
1879 * RFCSR 39:
1880 */
1881 #define RFCSR39_RX_LO2_EN FIELD8(0x80)
1883 /*
1884 * RFCSR 49:
1885 */
1886 #define RFCSR49_TX FIELD8(0x3f)
1888 /*
1889 * RF registers
1890 */
1892 /*
1893 * RF 2
1894 */
1895 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1896 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1897 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1899 /*
1900 * RF 3
1901 */
1902 #define RF3_TXPOWER_G FIELD32(0x00003e00)
1903 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1904 #define RF3_TXPOWER_A FIELD32(0x00003c00)
1906 /*
1907 * RF 4
1908 */
1909 #define RF4_TXPOWER_G FIELD32(0x000007c0)
1910 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1911 #define RF4_TXPOWER_A FIELD32(0x00000780)
1912 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1913 #define RF4_HT40 FIELD32(0x00200000)
1915 /*
1916 * EEPROM content.
1917 * The wordsize of the EEPROM is 16 bits.
1918 */
1920 /*
1921 * Chip ID
1922 */
1923 #define EEPROM_CHIP_ID 0x0000
1925 /*
1926 * EEPROM Version
1927 */
1928 #define EEPROM_VERSION 0x0001
1929 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
1930 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
1932 /*
1933 * HW MAC address.
1934 */
1935 #define EEPROM_MAC_ADDR_0 0x0002
1936 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1937 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1938 #define EEPROM_MAC_ADDR_1 0x0003
1939 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1940 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1941 #define EEPROM_MAC_ADDR_2 0x0004
1942 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1943 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1945 /*
1946 * EEPROM NIC Configuration 0
1947 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1948 * TXPATH: 1: 1T, 2: 2T, 3: 3T
1949 * RF_TYPE: RFIC type
1950 */
1951 #define EEPROM_NIC_CONF0 0x001a
1952 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
1953 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
1954 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
1956 /*
1957 * EEPROM NIC Configuration 1
1958 * HW_RADIO: 0: disable, 1: enable
1959 * EXTERNAL_TX_ALC: 0: disable, 1: enable
1960 * EXTERNAL_LNA_2G: 0: disable, 1: enable
1961 * EXTERNAL_LNA_5G: 0: disable, 1: enable
1962 * CARDBUS_ACCEL: 0: enable, 1: disable
1963 * BW40M_SB_2G: 0: disable, 1: enable
1964 * BW40M_SB_5G: 0: disable, 1: enable
1965 * WPS_PBC: 0: disable, 1: enable
1966 * BW40M_2G: 0: enable, 1: disable
1967 * BW40M_5G: 0: enable, 1: disable
1968 * BROADBAND_EXT_LNA: 0: disable, 1: enable
1969 * ANT_DIVERSITY: 00: Disable, 01: Diversity,
1970 * 10: Main antenna, 11: Aux antenna
1971 * INTERNAL_TX_ALC: 0: disable, 1: enable
1972 * BT_COEXIST: 0: disable, 1: enable
1973 * DAC_TEST: 0: disable, 1: enable
1974 */
1975 #define EEPROM_NIC_CONF1 0x001b
1976 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
1977 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
1978 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
1979 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
1980 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
1981 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
1982 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
1983 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
1984 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
1985 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
1986 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
1987 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
1988 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
1989 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
1990 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
1992 /*
1993 * EEPROM frequency
1994 */
1995 #define EEPROM_FREQ 0x001d
1996 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1997 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1998 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2000 /*
2001 * EEPROM LED
2002 * POLARITY_RDY_G: Polarity RDY_G setting.
2003 * POLARITY_RDY_A: Polarity RDY_A setting.
2004 * POLARITY_ACT: Polarity ACT setting.
2005 * POLARITY_GPIO_0: Polarity GPIO0 setting.
2006 * POLARITY_GPIO_1: Polarity GPIO1 setting.
2007 * POLARITY_GPIO_2: Polarity GPIO2 setting.
2008 * POLARITY_GPIO_3: Polarity GPIO3 setting.
2009 * POLARITY_GPIO_4: Polarity GPIO4 setting.
2010 * LED_MODE: Led mode.
2011 */
2012 #define EEPROM_LED_AG_CONF 0x001e
2013 #define EEPROM_LED_ACT_CONF 0x001f
2014 #define EEPROM_LED_POLARITY 0x0020
2015 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2016 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2017 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2018 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2019 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2020 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2021 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2022 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2023 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2025 /*
2026 * EEPROM NIC Configuration 2
2027 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2028 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2029 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2030 */
2031 #define EEPROM_NIC_CONF2 0x0021
2032 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2033 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2034 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2036 /*
2037 * EEPROM LNA
2038 */
2039 #define EEPROM_LNA 0x0022
2040 #define EEPROM_LNA_BG FIELD16(0x00ff)
2041 #define EEPROM_LNA_A0 FIELD16(0xff00)
2043 /*
2044 * EEPROM RSSI BG offset
2045 */
2046 #define EEPROM_RSSI_BG 0x0023
2047 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2048 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2050 /*
2051 * EEPROM RSSI BG2 offset
2052 */
2053 #define EEPROM_RSSI_BG2 0x0024
2054 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2055 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2057 /*
2058 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2059 */
2060 #define EEPROM_TXMIXER_GAIN_BG 0x0024
2061 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2063 /*
2064 * EEPROM RSSI A offset
2065 */
2066 #define EEPROM_RSSI_A 0x0025
2067 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2068 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2070 /*
2071 * EEPROM RSSI A2 offset
2072 */
2073 #define EEPROM_RSSI_A2 0x0026
2074 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2075 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2077 /*
2078 * EEPROM EIRP Maximum TX power values(unit: dbm)
2079 */
2080 #define EEPROM_EIRP_MAX_TX_POWER 0x0027
2081 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2082 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2084 /*
2085 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2086 * This is delta in 40MHZ.
2087 * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2088 * TYPE: 1: Plus the delta value, 0: minus the delta value
2089 * ENABLE: enable tx power compensation for 40BW
2090 */
2091 #define EEPROM_TXPOWER_DELTA 0x0028
2092 #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2093 #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2094 #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2095 #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2096 #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2097 #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2099 /*
2100 * EEPROM TXPOWER 802.11BG
2101 */
2102 #define EEPROM_TXPOWER_BG1 0x0029
2103 #define EEPROM_TXPOWER_BG2 0x0030
2104 #define EEPROM_TXPOWER_BG_SIZE 7
2105 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2106 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2108 /*
2109 * EEPROM temperature compensation boundaries 802.11BG
2110 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2111 * reduced by (agc_step * -4)
2112 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2113 * reduced by (agc_step * -3)
2114 */
2115 #define EEPROM_TSSI_BOUND_BG1 0x0037
2116 #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2117 #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2119 /*
2120 * EEPROM temperature compensation boundaries 802.11BG
2121 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2122 * reduced by (agc_step * -2)
2123 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2124 * reduced by (agc_step * -1)
2125 */
2126 #define EEPROM_TSSI_BOUND_BG2 0x0038
2127 #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2128 #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2130 /*
2131 * EEPROM temperature compensation boundaries 802.11BG
2132 * REF: Reference TSSI value, no tx power changes needed
2133 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2134 * increased by (agc_step * 1)
2135 */
2136 #define EEPROM_TSSI_BOUND_BG3 0x0039
2137 #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2138 #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2140 /*
2141 * EEPROM temperature compensation boundaries 802.11BG
2142 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2143 * increased by (agc_step * 2)
2144 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2145 * increased by (agc_step * 3)
2146 */
2147 #define EEPROM_TSSI_BOUND_BG4 0x003a
2148 #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2149 #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2151 /*
2152 * EEPROM temperature compensation boundaries 802.11BG
2153 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2154 * increased by (agc_step * 4)
2155 * AGC_STEP: Temperature compensation step.
2156 */
2157 #define EEPROM_TSSI_BOUND_BG5 0x003b
2158 #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2159 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2161 /*
2162 * EEPROM TXPOWER 802.11A
2163 */
2164 #define EEPROM_TXPOWER_A1 0x003c
2165 #define EEPROM_TXPOWER_A2 0x0053
2166 #define EEPROM_TXPOWER_A_SIZE 6
2167 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2168 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2170 /*
2171 * EEPROM temperature compensation boundaries 802.11A
2172 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2173 * reduced by (agc_step * -4)
2174 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2175 * reduced by (agc_step * -3)
2176 */
2177 #define EEPROM_TSSI_BOUND_A1 0x006a
2178 #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2179 #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2181 /*
2182 * EEPROM temperature compensation boundaries 802.11A
2183 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2184 * reduced by (agc_step * -2)
2185 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2186 * reduced by (agc_step * -1)
2187 */
2188 #define EEPROM_TSSI_BOUND_A2 0x006b
2189 #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2190 #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2192 /*
2193 * EEPROM temperature compensation boundaries 802.11A
2194 * REF: Reference TSSI value, no tx power changes needed
2195 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2196 * increased by (agc_step * 1)
2197 */
2198 #define EEPROM_TSSI_BOUND_A3 0x006c
2199 #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2200 #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2202 /*
2203 * EEPROM temperature compensation boundaries 802.11A
2204 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2205 * increased by (agc_step * 2)
2206 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2207 * increased by (agc_step * 3)
2208 */
2209 #define EEPROM_TSSI_BOUND_A4 0x006d
2210 #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2211 #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2213 /*
2214 * EEPROM temperature compensation boundaries 802.11A
2215 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2216 * increased by (agc_step * 4)
2217 * AGC_STEP: Temperature compensation step.
2218 */
2219 #define EEPROM_TSSI_BOUND_A5 0x006e
2220 #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2221 #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2223 /*
2224 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2225 */
2226 #define EEPROM_TXPOWER_BYRATE 0x006f
2227 #define EEPROM_TXPOWER_BYRATE_SIZE 9
2229 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2230 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2231 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2232 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2234 /*
2235 * EEPROM BBP.
2236 */
2237 #define EEPROM_BBP_START 0x0078
2238 #define EEPROM_BBP_SIZE 16
2239 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
2240 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
2242 /*
2243 * MCU mailbox commands.
2244 */
2245 #define MCU_SLEEP 0x30
2246 #define MCU_WAKEUP 0x31
2247 #define MCU_RADIO_OFF 0x35
2248 #define MCU_CURRENT 0x36
2249 #define MCU_LED 0x50
2250 #define MCU_LED_STRENGTH 0x51
2251 #define MCU_LED_AG_CONF 0x52
2252 #define MCU_LED_ACT_CONF 0x53
2253 #define MCU_LED_LED_POLARITY 0x54
2254 #define MCU_RADAR 0x60
2255 #define MCU_BOOT_SIGNAL 0x72
2256 #define MCU_ANT_SELECT 0X73
2257 #define MCU_BBP_SIGNAL 0x80
2258 #define MCU_POWER_SAVE 0x83
2260 /*
2261 * MCU mailbox tokens
2262 */
2263 #define TOKEN_WAKUP 3
2265 /*
2266 * DMA descriptor defines.
2267 */
2268 #define TXWI_DESC_SIZE (4 * sizeof(__le32))
2269 #define RXWI_DESC_SIZE (4 * sizeof(__le32))
2271 /*
2272 * TX WI structure
2273 */
2275 /*
2276 * Word0
2277 * FRAG: 1 To inform TKIP engine this is a fragment.
2278 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2279 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2280 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2281 * duplicate the frame to both channels).
2282 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2283 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2284 * aggregate consecutive frames with the same RA and QoS TID. If
2285 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2286 * directly after a frame B with AMPDU=1, frame A might still
2287 * get aggregated into the AMPDU started by frame B. So, setting
2288 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2289 * MPDU, it can still end up in an AMPDU if the previous frame
2290 * was tagged as AMPDU.
2291 */
2292 #define TXWI_W0_FRAG FIELD32(0x00000001)
2293 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2294 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
2295 #define TXWI_W0_TS FIELD32(0x00000008)
2296 #define TXWI_W0_AMPDU FIELD32(0x00000010)
2297 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2298 #define TXWI_W0_TX_OP FIELD32(0x00000300)
2299 #define TXWI_W0_MCS FIELD32(0x007f0000)
2300 #define TXWI_W0_BW FIELD32(0x00800000)
2301 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2302 #define TXWI_W0_STBC FIELD32(0x06000000)
2303 #define TXWI_W0_IFS FIELD32(0x08000000)
2304 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2306 /*
2307 * Word1
2308 * ACK: 0: No Ack needed, 1: Ack needed
2309 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2310 * BW_WIN_SIZE: BA windows size of the recipient
2311 * WIRELESS_CLI_ID: Client ID for WCID table access
2312 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2313 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2314 * frame was processed. If multiple frames are aggregated together
2315 * (AMPDU==1) the reported tx status will always contain the packet
2316 * id of the first frame. 0: Don't report tx status for this frame.
2317 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2318 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2319 * This identification number is calculated by ((idx % 3) + 1).
2320 * The (+1) is required to prevent PACKETID to become 0.
2321 */
2322 #define TXWI_W1_ACK FIELD32(0x00000001)
2323 #define TXWI_W1_NSEQ FIELD32(0x00000002)
2324 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2325 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2326 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2327 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
2328 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2329 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2331 /*
2332 * Word2
2333 */
2334 #define TXWI_W2_IV FIELD32(0xffffffff)
2336 /*
2337 * Word3
2338 */
2339 #define TXWI_W3_EIV FIELD32(0xffffffff)
2341 /*
2342 * RX WI structure
2343 */
2345 /*
2346 * Word0
2347 */
2348 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2349 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2350 #define RXWI_W0_BSSID FIELD32(0x00001c00)
2351 #define RXWI_W0_UDF FIELD32(0x0000e000)
2352 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2353 #define RXWI_W0_TID FIELD32(0xf0000000)
2355 /*
2356 * Word1
2357 */
2358 #define RXWI_W1_FRAG FIELD32(0x0000000f)
2359 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2360 #define RXWI_W1_MCS FIELD32(0x007f0000)
2361 #define RXWI_W1_BW FIELD32(0x00800000)
2362 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2363 #define RXWI_W1_STBC FIELD32(0x06000000)
2364 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2366 /*
2367 * Word2
2368 */
2369 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2370 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2371 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2373 /*
2374 * Word3
2375 */
2376 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2377 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2379 /*
2380 * Macros for converting txpower from EEPROM to mac80211 value
2381 * and from mac80211 value to register value.
2382 */
2383 #define MIN_G_TXPOWER 0
2384 #define MIN_A_TXPOWER -7
2385 #define MAX_G_TXPOWER 31
2386 #define MAX_A_TXPOWER 15
2387 #define DEFAULT_TXPOWER 5
2389 #define TXPOWER_G_FROM_DEV(__txpower) \
2390 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2392 #define TXPOWER_G_TO_DEV(__txpower) \
2393 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
2395 #define TXPOWER_A_FROM_DEV(__txpower) \
2396 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2398 #define TXPOWER_A_TO_DEV(__txpower) \
2399 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2401 /*
2402 * Board's maximun TX power limitation
2403 */
2404 #define EIRP_MAX_TX_POWER_LIMIT 0x50