drivers/net/wireless/rtlwifi/pci.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL_PCI_H__
  31 #define __RTL_PCI_H__
  32
  33 #include <linux/pci.h>
  34 /*
  35 1: MSDU packet queue,
  36 2: Rx Command Queue
  37 */
  38 #define RTL_PCI_RX_MPDU_QUEUE                   0
  39 #define RTL_PCI_RX_CMD_QUEUE                    1
  40 #define RTL_PCI_MAX_RX_QUEUE                    2
  41
  42 #define RTL_PCI_MAX_RX_COUNT                    64
  43 #define RTL_PCI_MAX_TX_QUEUE_COUNT              9
  44
  45 #define RT_TXDESC_NUM                           128
  46 #define RT_TXDESC_NUM_BE_QUEUE                  256
  47
  48 #define BK_QUEUE                                0
  49 #define BE_QUEUE                                1
  50 #define VI_QUEUE                                2
  51 #define VO_QUEUE                                3
  52 #define BEACON_QUEUE                            4
  53 #define TXCMD_QUEUE                             5
  54 #define MGNT_QUEUE                              6
  55 #define HIGH_QUEUE                              7
  56 #define HCCA_QUEUE                              8
  57
  58 #define RTL_PCI_DEVICE(vend, dev, cfg)  \
  59         .vendor = (vend), \
  60         .device = (dev), \
  61         .subvendor = PCI_ANY_ID, \
  62         .subdevice = PCI_ANY_ID,\
  63         .driver_data = (kernel_ulong_t)&(cfg)
  64
  65 #define INTEL_VENDOR_ID                         0x8086
  66 #define SIS_VENDOR_ID                           0x1039
  67 #define ATI_VENDOR_ID                           0x1002
  68 #define ATI_DEVICE_ID                           0x7914
  69 #define AMD_VENDOR_ID                           0x1022
  70
  71 #define PCI_MAX_BRIDGE_NUMBER                   255
  72 #define PCI_MAX_DEVICES                         32
  73 #define PCI_MAX_FUNCTION                        8
  74
  75 #define PCI_CONF_ADDRESS        0x0CF8  /*PCI Configuration Space Address */
  76 #define PCI_CONF_DATA           0x0CFC  /*PCI Configuration Space Data */
  77
  78 #define PCI_CLASS_BRIDGE_DEV            0x06
  79 #define PCI_SUBCLASS_BR_PCI_TO_PCI      0x04
  80 #define PCI_CAPABILITY_ID_PCI_EXPRESS   0x10
  81 #define PCI_CAP_ID_EXP                  0x10
  82
  83 #define U1DONTCARE                      0xFF
  84 #define U2DONTCARE                      0xFFFF
  85 #define U4DONTCARE                      0xFFFFFFFF
  86
  87 #define RTL_PCI_8192_DID        0x8192  /*8192 PCI-E */
  88 #define RTL_PCI_8192SE_DID      0x8192  /*8192 SE */
  89 #define RTL_PCI_8174_DID        0x8174  /*8192 SE */
  90 #define RTL_PCI_8173_DID        0x8173  /*8191 SE Crab */
  91 #define RTL_PCI_8172_DID        0x8172  /*8191 SE RE */
  92 #define RTL_PCI_8171_DID        0x8171  /*8191 SE Unicron */
  93 #define RTL_PCI_0045_DID        0x0045  /*8190 PCI for Ceraga */
  94 #define RTL_PCI_0046_DID        0x0046  /*8190 Cardbus for Ceraga */
  95 #define RTL_PCI_0044_DID        0x0044  /*8192e PCIE for Ceraga */
  96 #define RTL_PCI_0047_DID        0x0047  /*8192e Express Card for Ceraga */
  97 #define RTL_PCI_700F_DID        0x700F
  98 #define RTL_PCI_701F_DID        0x701F
  99 #define RTL_PCI_DLINK_DID       0x3304
 100 #define RTL_PCI_8192CET_DID     0x8191  /*8192ce */
 101 #define RTL_PCI_8192CE_DID      0x8178  /*8192ce */
 102 #define RTL_PCI_8191CE_DID      0x8177  /*8192ce */
 103 #define RTL_PCI_8188CE_DID      0x8176  /*8192ce */
 104 #define RTL_PCI_8192CU_DID      0x8191  /*8192ce */
 105 #define RTL_PCI_8192DE_DID      0x8193  /*8192de */
 106 #define RTL_PCI_8192DE_DID2     0x002B  /*92DE*/
 107
 108 /*8192 support 16 pages of IO registers*/
 109 #define RTL_MEM_MAPPED_IO_RANGE_8190PCI         0x1000
 110 #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE        0x4000
 111 #define RTL_MEM_MAPPED_IO_RANGE_8192SE          0x4000
 112 #define RTL_MEM_MAPPED_IO_RANGE_8192CE          0x4000
 113 #define RTL_MEM_MAPPED_IO_RANGE_8192DE          0x4000
 114
 115 #define RTL_PCI_REVISION_ID_8190PCI             0x00
 116 #define RTL_PCI_REVISION_ID_8192PCIE            0x01
 117 #define RTL_PCI_REVISION_ID_8192SE              0x10
 118 #define RTL_PCI_REVISION_ID_8192CE              0x1
 119 #define RTL_PCI_REVISION_ID_8192DE              0x0
 120
 121 #define RTL_DEFAULT_HARDWARE_TYPE       HARDWARE_TYPE_RTL8192CE
 122
 123 enum pci_bridge_vendor {
 124         PCI_BRIDGE_VENDOR_INTEL = 0x0,  /*0b'0000,0001 */
 125         PCI_BRIDGE_VENDOR_ATI,          /*0b'0000,0010*/
 126         PCI_BRIDGE_VENDOR_AMD,          /*0b'0000,0100*/
 127         PCI_BRIDGE_VENDOR_SIS,          /*0b'0000,1000*/
 128         PCI_BRIDGE_VENDOR_UNKNOWN,      /*0b'0100,0000*/
 129         PCI_BRIDGE_VENDOR_MAX,
 130 };
 131
 132 struct rtl_pci_capabilities_header {
 133         u8 capability_id;
 134         u8 next;
 135 };
 136
 137 struct rtl_rx_desc {
 138         u32 dword[8];
 139 } __packed;
 140
 141 struct rtl_tx_desc {
 142         u32 dword[16];
 143 } __packed;
 144
 145 struct rtl_tx_cmd_desc {
 146         u32 dword[16];
 147 } __packed;
 148
 149 struct rtl8192_tx_ring {
 150         struct rtl_tx_desc *desc;
 151         dma_addr_t dma;
 152         unsigned int idx;
 153         unsigned int entries;
 154         struct sk_buff_head queue;
 155 };
 156
 157 struct rtl8192_rx_ring {
 158         struct rtl_rx_desc *desc;
 159         dma_addr_t dma;
 160         unsigned int idx;
 161         struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
 162 };
 163
 164 struct rtl_pci {
 165         struct pci_dev *pdev;
 166
 167         bool driver_is_goingto_unload;
 168         bool up_first_time;
 169         bool first_init;
 170         bool being_init_adapter;
 171         bool init_ready;
 172         bool irq_enabled;
 173
 174         /*Tx */
 175         struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
 176         int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
 177         u32 transmit_config;
 178
 179         /*Rx */
 180         struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
 181         int rxringcount;
 182         u16 rxbuffersize;
 183         u32 receive_config;
 184
 185         /*irq */
 186         u8 irq_alloc;
 187         u32 irq_mask[2];
 188
 189         /*Bcn control register setting */
 190         u32 reg_bcn_ctrl_val;
 191
 192          /*ASPM*/ u8 const_pci_aspm;
 193         u8 const_amdpci_aspm;
 194         u8 const_hwsw_rfoff_d3;
 195         u8 const_support_pciaspm;
 196         /*pci-e bridge */
 197         u8 const_hostpci_aspm_setting;
 198         /*pci-e device */
 199         u8 const_devicepci_aspm_setting;
 200         /*If it supports ASPM, Offset[560h] = 0x40,
 201            otherwise Offset[560h] = 0x00. */
 202         bool support_aspm;
 203         bool support_backdoor;
 204
 205         /*QOS & EDCA */
 206         enum acm_method acm_method;
 207
 208         u16 shortretry_limit;
 209         u16 longretry_limit;
 210 };
 211
 212 struct mp_adapter {
 213         u8 linkctrl_reg;
 214
 215         u8 busnumber;
 216         u8 devnumber;
 217         u8 funcnumber;
 218
 219         u8 pcibridge_busnum;
 220         u8 pcibridge_devnum;
 221         u8 pcibridge_funcnum;
 222
 223         u8 pcibridge_vendor;
 224         u16 pcibridge_vendorid;
 225         u16 pcibridge_deviceid;
 226
 227         u32 pcicfg_addrport;
 228         u8 num4bytes;
 229
 230         u8 pcibridge_pciehdr_offset;
 231         u8 pcibridge_linkctrlreg;
 232
 233         bool amd_l1_patch;
 234 };
 235
 236 struct rtl_pci_priv {
 237         struct rtl_pci dev;
 238         struct mp_adapter ndis_adapter;
 239         struct rtl_led_ctl ledctl;
 240         struct bt_coexist_info bt_coexist;
 241 };
 242
 243 #define rtl_pcipriv(hw)         (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
 244 #define rtl_pcidev(pcipriv)     (&((pcipriv)->dev))
 245
 246 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
 247
 248 extern struct rtl_intf_ops rtl_pci_ops;
 249
 250 int __devinit rtl_pci_probe(struct pci_dev *pdev,
 251                             const struct pci_device_id *id);
 252 void rtl_pci_disconnect(struct pci_dev *pdev);
 253 int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state);
 254 int rtl_pci_resume(struct pci_dev *pdev);
 255
 256 static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
 257 {
 258         return readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 259 }
 260
 261 static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
 262 {
 263         return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 264 }
 265
 266 static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
 267 {
 268         return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 269 }
 270
 271 static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
 272 {
 273         writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 274 }
 275
 276 static inline void pci_write16_async(struct rtl_priv *rtlpriv,
 277                                      u32 addr, u16 val)
 278 {
 279         writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 280 }
 281
 282 static inline void pci_write32_async(struct rtl_priv *rtlpriv,
 283                                      u32 addr, u32 val)
 284 {
 285         writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 286 }
 287
 288 static inline void rtl_pci_raw_write_port_ulong(u32 port, u32 val)
 289 {
 290         outl(val, port);
 291 }
 292
 293 static inline void rtl_pci_raw_write_port_uchar(u32 port, u8 val)
 294 {
 295         outb(val, port);
 296 }
 297
 298 static inline void rtl_pci_raw_read_port_uchar(u32 port, u8 *pval)
 299 {
 300         *pval = inb(port);
 301 }
 302
 303 static inline void rtl_pci_raw_read_port_ushort(u32 port, u16 *pval)
 304 {
 305         *pval = inw(port);
 306 }
 307
 308 static inline void rtl_pci_raw_read_port_ulong(u32 port, u32 *pval)
 309 {
 310         *pval = inl(port);
 311 }
 312
 313 #endif