drivers/net/wireless/rtlwifi/rtl8192se/def.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29 #ifndef __REALTEK_92S_DEF_H__
  30 #define __REALTEK_92S_DEF_H__
  31
  32 #define RX_MPDU_QUEUE                           0
  33 #define RX_CMD_QUEUE                            1
  34 #define RX_MAX_QUEUE                            2
  35
  36 #define DESC92S_RATE1M                          0x00
  37 #define DESC92S_RATE2M                          0x01
  38 #define DESC92S_RATE5_5M                        0x02
  39 #define DESC92S_RATE11M                         0x03
  40 #define DESC92S_RATE6M                          0x04
  41 #define DESC92S_RATE9M                          0x05
  42 #define DESC92S_RATE12M                         0x06
  43 #define DESC92S_RATE18M                         0x07
  44 #define DESC92S_RATE24M                         0x08
  45 #define DESC92S_RATE36M                         0x09
  46 #define DESC92S_RATE48M                         0x0a
  47 #define DESC92S_RATE54M                         0x0b
  48 #define DESC92S_RATEMCS0                        0x0c
  49 #define DESC92S_RATEMCS1                        0x0d
  50 #define DESC92S_RATEMCS2                        0x0e
  51 #define DESC92S_RATEMCS3                        0x0f
  52 #define DESC92S_RATEMCS4                        0x10
  53 #define DESC92S_RATEMCS5                        0x11
  54 #define DESC92S_RATEMCS6                        0x12
  55 #define DESC92S_RATEMCS7                        0x13
  56 #define DESC92S_RATEMCS8                        0x14
  57 #define DESC92S_RATEMCS9                        0x15
  58 #define DESC92S_RATEMCS10                       0x16
  59 #define DESC92S_RATEMCS11                       0x17
  60 #define DESC92S_RATEMCS12                       0x18
  61 #define DESC92S_RATEMCS13                       0x19
  62 #define DESC92S_RATEMCS14                       0x1a
  63 #define DESC92S_RATEMCS15                       0x1b
  64 #define DESC92S_RATEMCS15_SG                    0x1c
  65 #define DESC92S_RATEMCS32                       0x20
  66
  67 #define SHORT_SLOT_TIME                         9
  68 #define NON_SHORT_SLOT_TIME                     20
  69
  70 /* Rx smooth factor */
  71 #define RX_SMOOTH_FACTOR                        20
  72
  73 /* Queue Select Value in TxDesc */
  74 #define QSLT_BK                                 0x2
  75 #define QSLT_BE                                 0x0
  76 #define QSLT_VI                                 0x5
  77 #define QSLT_VO                                 0x6
  78 #define QSLT_BEACON                             0x10
  79 #define QSLT_HIGH                               0x11
  80 #define QSLT_MGNT                               0x12
  81 #define QSLT_CMD                                0x13
  82
  83 #define PHY_RSSI_SLID_WIN_MAX                   100
  84 #define PHY_LINKQUALITY_SLID_WIN_MAX            20
  85 #define PHY_BEACON_RSSI_SLID_WIN_MAX            10
  86
  87 /* Tx Desc */
  88 #define TX_DESC_SIZE_RTL8192S                   (16 * 4)
  89 #define TX_CMDDESC_SIZE_RTL8192S                (16 * 4)
  90
  91 /* Define a macro that takes a le32 word, converts it to host ordering,
  92  * right shifts by a specified count, creates a mask of the specified
  93  * bit count, and extracts that number of bits.
  94  */
  95
  96 #define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask)             \
  97         ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
  98         BIT_LEN_MASK_32(__mask))
  99
 100 /* Define a macro that clears a bit field in an le32 word and
 101  * sets the specified value into that bit field. The resulting
 102  * value remains in le32 ordering; however, it is properly converted
 103  * to host ordering for the clear and set operations before conversion
 104  * back to le32.
 105  */
 106
 107 #define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val)      \
 108         (*(__le32 *)(__pdesc) =                                 \
 109         (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) &     \
 110         (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) |        \
 111         (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
 112
 113 /* macros to read/write various fields in RX or TX descriptors */
 114
 115 /* Dword 0 */
 116 #define SET_TX_DESC_PKT_SIZE(__pdesc, __val)                    \
 117         SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
 118 #define SET_TX_DESC_OFFSET(__pdesc, __val)                      \
 119         SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
 120 #define SET_TX_DESC_TYPE(__pdesc, __val)                        \
 121         SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
 122 #define SET_TX_DESC_LAST_SEG(__pdesc, __val)                    \
 123         SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
 124 #define SET_TX_DESC_FIRST_SEG(__pdesc, __val)                   \
 125         SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
 126 #define SET_TX_DESC_LINIP(__pdesc, __val)                       \
 127         SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
 128 #define SET_TX_DESC_AMSDU(__pdesc, __val)                       \
 129         SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
 130 #define SET_TX_DESC_GREEN_FIELD(__pdesc, __val)                 \
 131         SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
 132 #define SET_TX_DESC_OWN(__pdesc, __val)                         \
 133         SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
 134
 135 #define GET_TX_DESC_OWN(__pdesc)                                \
 136         SHIFT_AND_MASK_LE(__pdesc, 31, 1)
 137
 138 /* Dword 1 */
 139 #define SET_TX_DESC_MACID(__pdesc, __val)                       \
 140         SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
 141 #define SET_TX_DESC_MORE_DATA(__pdesc, __val)                   \
 142         SET_BITS_OFFSET_LE(__pdesc + 4, 5, 1, __val)
 143 #define SET_TX_DESC_MORE_FRAG(__pdesc, __val)                   \
 144         SET_BITS_OFFSET_LE(__pdesc + 4, 6, 1, __val)
 145 #define SET_TX_DESC_PIFS(__pdesc, __val)                        \
 146         SET_BITS_OFFSET_LE(__pdesc + 4, 7, 1, __val)
 147 #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val)                   \
 148         SET_BITS_OFFSET_LE(__pdesc + 4, 8, 5, __val)
 149 #define SET_TX_DESC_ACK_POLICY(__pdesc, __val)                  \
 150         SET_BITS_OFFSET_LE(__pdesc + 4, 13, 2, __val)
 151 #define SET_TX_DESC_NO_ACM(__pdesc, __val)                      \
 152         SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
 153 #define SET_TX_DESC_NON_QOS(__pdesc, __val)                     \
 154         SET_BITS_OFFSET_LE(__pdesc + 4, 16, 1, __val)
 155 #define SET_TX_DESC_KEY_ID(__pdesc, __val)                      \
 156         SET_BITS_OFFSET_LE(__pdesc + 4, 17, 2, __val)
 157 #define SET_TX_DESC_OUI(__pdesc, __val)                         \
 158         SET_BITS_OFFSET_LE(__pdesc + 4, 19, 1, __val)
 159 #define SET_TX_DESC_PKT_TYPE(__pdesc, __val)                    \
 160         SET_BITS_OFFSET_LE(__pdesc + 4, 20, 1, __val)
 161 #define SET_TX_DESC_EN_DESC_ID(__pdesc, __val)                  \
 162         SET_BITS_OFFSET_LE(__pdesc + 4, 21, 1, __val)
 163 #define SET_TX_DESC_SEC_TYPE(__pdesc, __val)                    \
 164         SET_BITS_OFFSET_LE(__pdesc + 4, 22, 2, __val)
 165 #define SET_TX_DESC_WDS(__pdesc, __val)                         \
 166         SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
 167 #define SET_TX_DESC_HTC(__pdesc, __val)                         \
 168         SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
 169 #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val)                  \
 170         SET_BITS_OFFSET_LE(__pdesc + 4, 26, 5, __val)
 171 #define SET_TX_DESC_HWPC(__pdesc, __val)                        \
 172         SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
 173
 174 /* Dword 2 */
 175 #define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val)            \
 176         SET_BITS_OFFSET_LE(__pdesc + 8, 0, 6, __val)
 177 #define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val)          \
 178         SET_BITS_OFFSET_LE(__pdesc + 8, 6, 1, __val)
 179 #define SET_TX_DESC_TSFL(__pdesc, __val)                        \
 180         SET_BITS_OFFSET_LE(__pdesc + 8, 7, 5, __val)
 181 #define SET_TX_DESC_RTS_RETRY_COUNT(__pdesc, __val)             \
 182         SET_BITS_OFFSET_LE(__pdesc + 8, 12, 6, __val)
 183 #define SET_TX_DESC_DATA_RETRY_COUNT(__pdesc, __val)            \
 184         SET_BITS_OFFSET_LE(__pdesc + 8, 18, 6, __val)
 185 #define SET_TX_DESC_RSVD_MACID(__pdesc, __val)                  \
 186         SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val)
 187 #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val)                  \
 188         SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val)
 189 #define SET_TX_DESC_AGG_BREAK(__pdesc, __val)                   \
 190         SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
 191 #define SET_TX_DESC_OWN_MAC(__pdesc, __val)                     \
 192         SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val)
 193
 194 /* Dword 3 */
 195 #define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val)              \
 196         SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val)
 197 #define SET_TX_DESC_TAIL_PAGE(__pdesc, __val)                   \
 198         SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val)
 199 #define SET_TX_DESC_SEQ(__pdesc, __val)                         \
 200         SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val)
 201 #define SET_TX_DESC_FRAG(__pdesc, __val)                        \
 202         SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val)
 203
 204 /* Dword 4 */
 205 #define SET_TX_DESC_RTS_RATE(__pdesc, __val)                    \
 206         SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val)
 207 #define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val)              \
 208         SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val)
 209 #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val)           \
 210         SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val)
 211 #define SET_TX_DESC_CTS_ENABLE(__pdesc, __val)                  \
 212         SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val)
 213 #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val)                  \
 214         SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val)
 215 #define SET_TX_DESC_RA_BRSR_ID(__pdesc, __val)                  \
 216         SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val)
 217 #define SET_TX_DESC_TXHT(__pdesc, __val)                        \
 218         SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val)
 219 #define SET_TX_DESC_TX_SHORT(__pdesc, __val)                    \
 220         SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val)
 221 #define SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val)                \
 222         SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val)
 223 #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val)              \
 224         SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val)
 225 #define SET_TX_DESC_TX_STBC(__pdesc, __val)                     \
 226         SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val)
 227 #define SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val)        \
 228         SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val)
 229 #define SET_TX_DESC_RTS_HT(__pdesc, __val)                      \
 230         SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val)
 231 #define SET_TX_DESC_RTS_SHORT(__pdesc, __val)                   \
 232         SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val)
 233 #define SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val)               \
 234         SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val)
 235 #define SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val)             \
 236         SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val)
 237 #define SET_TX_DESC_RTS_STBC(__pdesc, __val)                    \
 238         SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val)
 239 #define SET_TX_DESC_USER_RATE(__pdesc, __val)                   \
 240         SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val)
 241
 242 /* Dword 5 */
 243 #define SET_TX_DESC_PACKET_ID(__pdesc, __val)                   \
 244         SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val)
 245 #define SET_TX_DESC_TX_RATE(__pdesc, __val)                     \
 246         SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val)
 247 #define SET_TX_DESC_DISABLE_FB(__pdesc, __val)                  \
 248         SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val)
 249 #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val)          \
 250         SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val)
 251 #define SET_TX_DESC_TX_AGC(__pdesc, __val)                      \
 252         SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val)
 253
 254 /* Dword 6 */
 255 #define SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val)                \
 256         SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val)
 257 #define SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val)               \
 258         SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val)
 259
 260 /* Dword 7 */
 261 #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val)              \
 262         SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val)
 263 #define SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val)            \
 264         SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val)
 265 #define SET_TX_DESC_TCP_ENABLE(__pdesc, __val)                  \
 266         SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val)
 267
 268 /* Dword 8 */
 269 #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val)           \
 270         SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val)
 271 #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc)                  \
 272         SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32)
 273
 274 /* Dword 9 */
 275 #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val)           \
 276         SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val)
 277
 278 /* Because the PCI Tx descriptors are chaied at the
 279  * initialization and all the NextDescAddresses in
 280  * these descriptors cannot not be cleared (,or
 281  * driver/HW cannot find the next descriptor), the
 282  * offset 36 (NextDescAddresses) is reserved when
 283  * the desc is cleared. */
 284 #define TX_DESC_NEXT_DESC_OFFSET                        36
 285 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)               \
 286 do {                                                            \
 287         if (_size > TX_DESC_NEXT_DESC_OFFSET)                   \
 288                 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET);   \
 289         else                                                    \
 290                 memset(__pdesc, 0, _size);                      \
 291 } while (0);
 292
 293 /* Rx Desc */
 294 #define RX_STATUS_DESC_SIZE                             24
 295 #define RX_DRV_INFO_SIZE_UNIT                           8
 296
 297 /* DWORD 0 */
 298 #define SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val)              \
 299         SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
 300 #define SET_RX_STATUS_DESC_CRC32(__pdesc, __val)                \
 301         SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val)
 302 #define SET_RX_STATUS_DESC_ICV(__pdesc, __val)                  \
 303         SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val)
 304 #define SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val)         \
 305         SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val)
 306 #define SET_RX_STATUS_DESC_SECURITY(__pdesc, __val)             \
 307         SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val)
 308 #define SET_RX_STATUS_DESC_QOS(__pdesc, __val)                  \
 309         SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val)
 310 #define SET_RX_STATUS_DESC_SHIFT(__pdesc, __val)                \
 311         SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
 312 #define SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val)           \
 313         SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
 314 #define SET_RX_STATUS_DESC_SWDEC(__pdesc, __val)                \
 315         SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
 316 #define SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val)             \
 317         SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
 318 #define SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val)            \
 319         SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
 320 #define SET_RX_STATUS_DESC_EOR(__pdesc, __val)                  \
 321         SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
 322 #define SET_RX_STATUS_DESC_OWN(__pdesc, __val)                  \
 323         SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
 324
 325 #define GET_RX_STATUS_DESC_PKT_LEN(__pdesc)                     \
 326         SHIFT_AND_MASK_LE(__pdesc, 0, 14)
 327 #define GET_RX_STATUS_DESC_CRC32(__pdesc)                       \
 328         SHIFT_AND_MASK_LE(__pdesc, 14, 1)
 329 #define GET_RX_STATUS_DESC_ICV(__pdesc)                         \
 330         SHIFT_AND_MASK_LE(__pdesc, 15, 1)
 331 #define GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc)                \
 332         SHIFT_AND_MASK_LE(__pdesc, 16, 4)
 333 #define GET_RX_STATUS_DESC_SECURITY(__pdesc)                    \
 334         SHIFT_AND_MASK_LE(__pdesc, 20, 3)
 335 #define GET_RX_STATUS_DESC_QOS(__pdesc)                         \
 336         SHIFT_AND_MASK_LE(__pdesc, 23, 1)
 337 #define GET_RX_STATUS_DESC_SHIFT(__pdesc)                       \
 338         SHIFT_AND_MASK_LE(__pdesc, 24, 2)
 339 #define GET_RX_STATUS_DESC_PHY_STATUS(__pdesc)                  \
 340         SHIFT_AND_MASK_LE(__pdesc, 26, 1)
 341 #define GET_RX_STATUS_DESC_SWDEC(__pdesc)                       \
 342         SHIFT_AND_MASK_LE(__pdesc, 27, 1)
 343 #define GET_RX_STATUS_DESC_LAST_SEG(__pdesc)                    \
 344         SHIFT_AND_MASK_LE(__pdesc, 28, 1)
 345 #define GET_RX_STATUS_DESC_FIRST_SEG(__pdesc)                   \
 346         SHIFT_AND_MASK_LE(__pdesc, 29, 1)
 347 #define GET_RX_STATUS_DESC_EOR(__pdesc)                         \
 348         SHIFT_AND_MASK_LE(__pdesc, 30, 1)
 349 #define GET_RX_STATUS_DESC_OWN(__pdesc)                         \
 350         SHIFT_AND_MASK_LE(__pdesc, 31, 1)
 351
 352 /* DWORD 1 */
 353 #define SET_RX_STATUS_DESC_MACID(__pdesc, __val)                \
 354         SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
 355 #define SET_RX_STATUS_DESC_TID(__pdesc, __val)                  \
 356         SET_BITS_OFFSET_LE(__pdesc + 4, 5, 4, __val)
 357 #define SET_RX_STATUS_DESC_PAGGR(__pdesc, __val)                \
 358         SET_BITS_OFFSET_LE(__pdesc + 4, 14, 1, __val)
 359 #define SET_RX_STATUS_DESC_FAGGR(__pdesc, __val)                \
 360         SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
 361 #define SET_RX_STATUS_DESC_A1_FIT(__pdesc, __val)               \
 362         SET_BITS_OFFSET_LE(__pdesc + 4, 16, 4, __val)
 363 #define SET_RX_STATUS_DESC_A2_FIT(__pdesc, __val)               \
 364         SET_BITS_OFFSET_LE(__pdesc + 4, 20, 4, __val)
 365 #define SET_RX_STATUS_DESC_PAM(__pdesc, __val)                  \
 366         SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
 367 #define SET_RX_STATUS_DESC_PWR(__pdesc, __val)                  \
 368         SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
 369 #define SET_RX_STATUS_DESC_MOREDATA(__pdesc, __val)             \
 370         SET_BITS_OFFSET_LE(__pdesc + 4, 26, 1, __val)
 371 #define SET_RX_STATUS_DESC_MOREFRAG(__pdesc, __val)             \
 372         SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
 373 #define SET_RX_STATUS_DESC_TYPE(__pdesc, __val)                 \
 374         SET_BITS_OFFSET_LE(__pdesc + 4, 28, 2, __val)
 375 #define SET_RX_STATUS_DESC_MC(__pdesc, __val)                   \
 376         SET_BITS_OFFSET_LE(__pdesc + 4, 30, 1, __val)
 377 #define SET_RX_STATUS_DESC_BC(__pdesc, __val)                   \
 378         SET_BITS_OFFSET_LE(__pdesc + 4, 31, 1, __val)
 379
 380 #define GET_RX_STATUS_DEC_MACID(__pdesc)                        \
 381         SHIFT_AND_MASK_LE(__pdesc + 4, 0, 5)
 382 #define GET_RX_STATUS_DESC_TID(__pdesc)                         \
 383         SHIFT_AND_MASK_LE(__pdesc + 4, 5, 4)
 384 #define GET_RX_STATUS_DESC_PAGGR(__pdesc)                       \
 385         SHIFT_AND_MASK_LE(__pdesc + 4, 14, 1)
 386 #define GET_RX_STATUS_DESC_FAGGR(__pdesc)                       \
 387         SHIFT_AND_MASK_LE(__pdesc + 4, 15, 1)
 388 #define GET_RX_STATUS_DESC_A1_FIT(__pdesc)                      \
 389         SHIFT_AND_MASK_LE(__pdesc + 4, 16, 4)
 390 #define GET_RX_STATUS_DESC_A2_FIT(__pdesc)                      \
 391         SHIFT_AND_MASK_LE(__pdesc + 4, 20, 4)
 392 #define GET_RX_STATUS_DESC_PAM(__pdesc)                         \
 393         SHIFT_AND_MASK_LE(__pdesc + 4, 24, 1)
 394 #define GET_RX_STATUS_DESC_PWR(__pdesc)                         \
 395         SHIFT_AND_MASK_LE(__pdesc + 4, 25, 1)
 396 #define GET_RX_STATUS_DESC_MORE_DATA(__pdesc)                   \
 397         SHIFT_AND_MASK_LE(__pdesc + 4, 26, 1)
 398 #define GET_RX_STATUS_DESC_MORE_FRAG(__pdesc)                   \
 399         SHIFT_AND_MASK_LE(__pdesc + 4, 27, 1)
 400 #define GET_RX_STATUS_DESC_TYPE(__pdesc)                        \
 401         SHIFT_AND_MASK_LE(__pdesc + 4, 28, 2)
 402 #define GET_RX_STATUS_DESC_MC(__pdesc)                          \
 403         SHIFT_AND_MASK_LE(__pdesc + 4, 30, 1)
 404 #define GET_RX_STATUS_DESC_BC(__pdesc)                          \
 405         SHIFT_AND_MASK_LE(__pdesc + 4, 31, 1)
 406
 407 /* DWORD 2 */
 408 #define SET_RX_STATUS_DESC_SEQ(__pdesc, __val)                  \
 409         SET_BITS_OFFSET_LE(__pdesc + 8, 0, 12, __val)
 410 #define SET_RX_STATUS_DESC_FRAG(__pdesc, __val)                 \
 411         SET_BITS_OFFSET_LE(__pdesc + 8, 12, 4, __val)
 412 #define SET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc, __val)          \
 413         SET_BITS_OFFSET_LE(__pdesc + 8, 16, 8, __val)
 414 #define SET_RX_STATUS_DESC_NEXT_IND(__pdesc, __val)             \
 415         SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
 416
 417 #define GET_RX_STATUS_DESC_SEQ(__pdesc)                         \
 418         SHIFT_AND_MASK_LE(__pdesc + 8, 0, 12)
 419 #define GET_RX_STATUS_DESC_FRAG(__pdesc)                        \
 420         SHIFT_AND_MASK_LE(__pdesc + 8, 12, 4)
 421 #define GET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc)                 \
 422         SHIFT_AND_MASK_LE(__pdesc + 8, 16, 8)
 423 #define GET_RX_STATUS_DESC_NEXT_IND(__pdesc)                    \
 424         SHIFT_AND_MASK_LE(__pdesc + 8, 30, 1)
 425
 426 /* DWORD 3 */
 427 #define SET_RX_STATUS_DESC_RX_MCS(__pdesc, __val)               \
 428         SET_BITS_OFFSET_LE(__pdesc + 12, 0, 6, __val)
 429 #define SET_RX_STATUS_DESC_RX_HT(__pdesc, __val)                \
 430         SET_BITS_OFFSET_LE(__pdesc + 12, 6, 1, __val)
 431 #define SET_RX_STATUS_DESC_AMSDU(__pdesc, __val)                \
 432         SET_BITS_OFFSET_LE(__pdesc + 12, 7, 1, __val)
 433 #define SET_RX_STATUS_DESC_SPLCP(__pdesc, __val)                \
 434         SET_BITS_OFFSET_LE(__pdesc + 12, 8, 1, __val)
 435 #define SET_RX_STATUS_DESC_BW(__pdesc, __val)                   \
 436         SET_BITS_OFFSET_LE(__pdesc + 12, 9, 1, __val)
 437 #define SET_RX_STATUS_DESC_HTC(__pdesc, __val)                  \
 438         SET_BITS_OFFSET_LE(__pdesc + 12, 10, 1, __val)
 439 #define SET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc, __val)          \
 440         SET_BITS_OFFSET_LE(__pdesc + 12, 11, 1, __val)
 441 #define SET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc, __val)           \
 442         SET_BITS_OFFSET_LE(__pdesc + 12, 12, 1, __val)
 443 #define SET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc, __val)        \
 444         SET_BITS_OFFSET_LE(__pdesc + 12, 13, 1, __val)
 445 #define SET_RX_STATUS_DESC_HWPC_ERR(__pdesc, __val)             \
 446         SET_BITS_OFFSET_LE(__pdesc + 12, 14, 1, __val)
 447 #define SET_RX_STATUS_DESC_HWPC_IND(__pdesc, __val)             \
 448         SET_BITS_OFFSET_LE(__pdesc + 12, 15, 1, __val)
 449 #define SET_RX_STATUS_DESC_IV0(__pdesc, __val)                  \
 450         SET_BITS_OFFSET_LE(__pdesc + 12, 16, 16, __val)
 451
 452 #define GET_RX_STATUS_DESC_RX_MCS(__pdesc)                      \
 453         SHIFT_AND_MASK_LE(__pdesc + 12, 0, 6)
 454 #define GET_RX_STATUS_DESC_RX_HT(__pdesc)                       \
 455         SHIFT_AND_MASK_LE(__pdesc + 12, 6, 1)
 456 #define GET_RX_STATUS_DESC_AMSDU(__pdesc)                       \
 457         SHIFT_AND_MASK_LE(__pdesc + 12, 7, 1)
 458 #define GET_RX_STATUS_DESC_SPLCP(__pdesc)                       \
 459         SHIFT_AND_MASK_LE(__pdesc + 12, 8, 1)
 460 #define GET_RX_STATUS_DESC_BW(__pdesc)                          \
 461         SHIFT_AND_MASK_LE(__pdesc + 12, 9, 1)
 462 #define GET_RX_STATUS_DESC_HTC(__pdesc)                         \
 463         SHIFT_AND_MASK_LE(__pdesc + 12, 10, 1)
 464 #define GET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc)                 \
 465         SHIFT_AND_MASK_LE(__pdesc + 12, 11, 1)
 466 #define GET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc)                  \
 467         SHIFT_AND_MASK_LE(__pdesc + 12, 12, 1)
 468 #define GET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc)               \
 469         SHIFT_AND_MASK_LE(__pdesc + 12, 13, 1)
 470 #define GET_RX_STATUS_DESC_HWPC_ERR(__pdesc)                    \
 471         SHIFT_AND_MASK_LE(__pdesc + 12, 14, 1)
 472 #define GET_RX_STATUS_DESC_HWPC_IND(__pdesc)                    \
 473         SHIFT_AND_MASK_LE(__pdesc + 12, 15, 1)
 474 #define GET_RX_STATUS_DESC_IV0(__pdesc)                         \
 475         SHIFT_AND_MASK_LE(__pdesc + 12, 16, 16)
 476
 477 /* DWORD 4 */
 478 #define SET_RX_STATUS_DESC_IV1(__pdesc, __val)                  \
 479         SET_BITS_OFFSET_LE(__pdesc + 16, 0, 32, __val)
 480 #define GET_RX_STATUS_DESC_IV1(__pdesc)                         \
 481         SHIFT_AND_MASK_LE(__pdesc + 16, 0, 32)
 482
 483 /* DWORD 5 */
 484 #define SET_RX_STATUS_DESC_TSFL(__pdesc, __val)                 \
 485         SET_BITS_OFFSET_LE(__pdesc + 20, 0, 32, __val)
 486 #define GET_RX_STATUS_DESC_TSFL(__pdesc)                        \
 487         SHIFT_AND_MASK_LE(__pdesc + 20, 0, 32)
 488
 489 /* DWORD 6 */
 490 #define SET_RX_STATUS__DESC_BUFF_ADDR(__pdesc, __val)   \
 491         SET_BITS_OFFSET_LE(__pdesc + 24, 0, 32, __val)
 492
 493 #define RX_HAL_IS_CCK_RATE(_pdesc)\
 494         (GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92S_RATE1M || \
 495          GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92S_RATE2M || \
 496          GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92S_RATE5_5M ||\
 497          GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92S_RATE11M)
 498
 499 enum rf_optype {
 500         RF_OP_BY_SW_3WIRE = 0,
 501         RF_OP_BY_FW,
 502         RF_OP_MAX
 503 };
 504
 505 enum ic_inferiority {
 506         IC_INFERIORITY_A = 0,
 507         IC_INFERIORITY_B = 1,
 508 };
 509
 510 enum fwcmd_iotype {
 511         /* For DIG DM */
 512         FW_CMD_DIG_ENABLE = 0,
 513         FW_CMD_DIG_DISABLE = 1,
 514         FW_CMD_DIG_HALT = 2,
 515         FW_CMD_DIG_RESUME = 3,
 516         /* For High Power DM */
 517         FW_CMD_HIGH_PWR_ENABLE = 4,
 518         FW_CMD_HIGH_PWR_DISABLE = 5,
 519         /* For Rate adaptive DM */
 520         FW_CMD_RA_RESET = 6,
 521         FW_CMD_RA_ACTIVE = 7,
 522         FW_CMD_RA_REFRESH_N = 8,
 523         FW_CMD_RA_REFRESH_BG = 9,
 524         FW_CMD_RA_INIT = 10,
 525         /* For FW supported IQK */
 526         FW_CMD_IQK_INIT = 11,
 527         /* Tx power tracking switch,
 528          * MP driver only */
 529         FW_CMD_TXPWR_TRACK_ENABLE = 12,
 530         /* Tx power tracking switch,
 531          * MP driver only */
 532         FW_CMD_TXPWR_TRACK_DISABLE = 13,
 533         /* Tx power tracking with thermal
 534          * indication, for Normal driver */
 535         FW_CMD_TXPWR_TRACK_THERMAL = 14,
 536         FW_CMD_PAUSE_DM_BY_SCAN = 15,
 537         FW_CMD_RESUME_DM_BY_SCAN = 16,
 538         FW_CMD_RA_REFRESH_N_COMB = 17,
 539         FW_CMD_RA_REFRESH_BG_COMB = 18,
 540         FW_CMD_ANTENNA_SW_ENABLE = 19,
 541         FW_CMD_ANTENNA_SW_DISABLE = 20,
 542         /* Tx Status report for CCX from FW */
 543         FW_CMD_TX_FEEDBACK_CCX_ENABLE = 21,
 544         /* Indifate firmware that driver
 545          * enters LPS, For PS-Poll issue */
 546         FW_CMD_LPS_ENTER = 22,
 547         /* Indicate firmware that driver
 548          * leave LPS*/
 549         FW_CMD_LPS_LEAVE = 23,
 550         /* Set DIG mode to signal strength */
 551         FW_CMD_DIG_MODE_SS = 24,
 552         /* Set DIG mode to false alarm. */
 553         FW_CMD_DIG_MODE_FA = 25,
 554         FW_CMD_ADD_A2_ENTRY = 26,
 555         FW_CMD_CTRL_DM_BY_DRIVER = 27,
 556         FW_CMD_CTRL_DM_BY_DRIVER_NEW = 28,
 557         FW_CMD_PAPE_CONTROL = 29,
 558         FW_CMD_IQK_ENABLE = 30,
 559 };
 560
 561 /*
 562  * Driver info contain PHY status
 563  * and other variabel size info
 564  * PHY Status content as below
 565  */
 566 struct  rx_fwinfo {
 567         /* DWORD 0 */
 568         u8 gain_trsw[4];
 569         /* DWORD 1 */
 570         u8 pwdb_all;
 571         u8 cfosho[4];
 572         /* DWORD 2 */
 573         u8 cfotail[4];
 574         /* DWORD 3 */
 575         s8 rxevm[2];
 576         s8 rxsnr[4];
 577         /* DWORD 4 */
 578         u8 pdsnr[2];
 579         /* DWORD 5 */
 580         u8 csi_current[2];
 581         u8 csi_target[2];
 582         /* DWORD 6 */
 583         u8 sigevm;
 584         u8 max_ex_pwr;
 585         u8 ex_intf_flag:1;
 586         u8 sgi_en:1;
 587         u8 rxsc:2;
 588         u8 reserve:4;
 589 };
 590
 591 struct phy_sts_cck_8192s_t {
 592         u8 adc_pwdb_x[4];
 593         u8 sq_rpt;
 594         u8 cck_agc_rpt;
 595 };
 596
 597 #endif
 598