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Realtek cr: Remove unused Macros
[zen-stable.git] / drivers / usb / gadget / fsl_udc_core.c
blob5e3dbed7d0036ec6a38b1216e04ae4ae063fa6d3
1 /*
2 * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * Author: Li Yang <leoli@freescale.com>
6 * Jiang Bo <tanya.jiang@freescale.com>
7 *
8 * Description:
9 * Freescale high-speed USB SOC DR module device controller driver.
10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
11 * The driver is previously named as mpc_udc. Based on bare board
12 * code from Dave Liu and Shlomi Gridish.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20 #undef VERBOSE
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/ioport.h>
25 #include <linux/types.h>
26 #include <linux/errno.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/list.h>
30 #include <linux/interrupt.h>
31 #include <linux/proc_fs.h>
32 #include <linux/mm.h>
33 #include <linux/moduleparam.h>
34 #include <linux/device.h>
35 #include <linux/usb/ch9.h>
36 #include <linux/usb/gadget.h>
37 #include <linux/usb/otg.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/platform_device.h>
40 #include <linux/fsl_devices.h>
41 #include <linux/dmapool.h>
42 #include <linux/delay.h>
43
44 #include <asm/byteorder.h>
45 #include <asm/io.h>
46 #include <asm/system.h>
47 #include <asm/unaligned.h>
48 #include <asm/dma.h>
49 #include <asm/cacheflush.h>
50
51 #include "fsl_usb2_udc.h"
52
53 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
54 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
55 #define DRIVER_VERSION "Apr 20, 2007"
56
57 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
59 static const char driver_name[] = "fsl-usb2-udc";
60 static const char driver_desc[] = DRIVER_DESC;
61
62 static struct usb_dr_device *dr_regs;
63 #ifndef CONFIG_ARCH_MXC
64 static struct usb_sys_interface *usb_sys_regs;
65 #endif
66
67 /* it is initialized in probe() */
68 static struct fsl_udc *udc_controller = NULL;
69
70 static const struct usb_endpoint_descriptor
71 fsl_ep0_desc = {
72 .bLength = USB_DT_ENDPOINT_SIZE,
73 .bDescriptorType = USB_DT_ENDPOINT,
74 .bEndpointAddress = 0,
75 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
76 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
77 };
78
79 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
80
81 #ifdef CONFIG_PPC32
82 /*
83 * On some SoCs, the USB controller registers can be big or little endian,
84 * depending on the version of the chip. In order to be able to run the
85 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
86 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
87 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
88 * call through those pointers. Platform code for SoCs that have BE USB
89 * registers should set pdata->big_endian_mmio flag.
90 *
91 * This also applies to controller-to-cpu accessors for the USB descriptors,
92 * since their endianness is also SoC dependant. Platform code for SoCs that
93 * have BE USB descriptors should set pdata->big_endian_desc flag.
94 */
95 static u32 _fsl_readl_be(const unsigned __iomem *p)
96 {
97 return in_be32(p);
98 }
99
100 static u32 _fsl_readl_le(const unsigned __iomem *p)
101 {
102 return in_le32(p);
103 }
104
105 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
106 {
107 out_be32(p, v);
108 }
109
110 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
111 {
112 out_le32(p, v);
113 }
114
115 static u32 (*_fsl_readl)(const unsigned __iomem *p);
116 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
117
118 #define fsl_readl(p) (*_fsl_readl)((p))
119 #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
120
121 static inline u32 cpu_to_hc32(const u32 x)
122 {
123 return udc_controller->pdata->big_endian_desc
124 ? (__force u32)cpu_to_be32(x)
125 : (__force u32)cpu_to_le32(x);
126 }
127
128 static inline u32 hc32_to_cpu(const u32 x)
129 {
130 return udc_controller->pdata->big_endian_desc
131 ? be32_to_cpu((__force __be32)x)
132 : le32_to_cpu((__force __le32)x);
133 }
134 #else /* !CONFIG_PPC32 */
135 #define fsl_readl(addr) readl(addr)
136 #define fsl_writel(val32, addr) writel(val32, addr)
137 #define cpu_to_hc32(x) cpu_to_le32(x)
138 #define hc32_to_cpu(x) le32_to_cpu(x)
139 #endif /* CONFIG_PPC32 */
140
141 /********************************************************************
142 * Internal Used Function
143 ********************************************************************/
144 /*-----------------------------------------------------------------
145 * done() - retire a request; caller blocked irqs
146 * @status : request status to be set, only works when
147 * request is still in progress.
148 *--------------------------------------------------------------*/
149 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
150 {
151 struct fsl_udc *udc = NULL;
152 unsigned char stopped = ep->stopped;
153 struct ep_td_struct *curr_td, *next_td;
154 int j;
155
156 udc = (struct fsl_udc *)ep->udc;
157 /* Removed the req from fsl_ep->queue */
158 list_del_init(&req->queue);
159
160 /* req.status should be set as -EINPROGRESS in ep_queue() */
161 if (req->req.status == -EINPROGRESS)
162 req->req.status = status;
163 else
164 status = req->req.status;
165
166 /* Free dtd for the request */
167 next_td = req->head;
168 for (j = 0; j < req->dtd_count; j++) {
169 curr_td = next_td;
170 if (j != req->dtd_count - 1) {
171 next_td = curr_td->next_td_virt;
172 }
173 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
174 }
175
176 if (req->mapped) {
177 dma_unmap_single(ep->udc->gadget.dev.parent,
178 req->req.dma, req->req.length,
179 ep_is_in(ep)
180 ? DMA_TO_DEVICE
181 : DMA_FROM_DEVICE);
182 req->req.dma = DMA_ADDR_INVALID;
183 req->mapped = 0;
184 } else
185 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
186 req->req.dma, req->req.length,
187 ep_is_in(ep)
188 ? DMA_TO_DEVICE
189 : DMA_FROM_DEVICE);
190
191 if (status && (status != -ESHUTDOWN))
192 VDBG("complete %s req %p stat %d len %u/%u",
193 ep->ep.name, &req->req, status,
194 req->req.actual, req->req.length);
195
196 ep->stopped = 1;
197
198 spin_unlock(&ep->udc->lock);
199 /* complete() is from gadget layer,
200 * eg fsg->bulk_in_complete() */
201 if (req->req.complete)
202 req->req.complete(&ep->ep, &req->req);
203
204 spin_lock(&ep->udc->lock);
205 ep->stopped = stopped;
206 }
207
208 /*-----------------------------------------------------------------
209 * nuke(): delete all requests related to this ep
210 * called with spinlock held
211 *--------------------------------------------------------------*/
212 static void nuke(struct fsl_ep *ep, int status)
213 {
214 ep->stopped = 1;
215
216 /* Flush fifo */
217 fsl_ep_fifo_flush(&ep->ep);
218
219 /* Whether this eq has request linked */
220 while (!list_empty(&ep->queue)) {
221 struct fsl_req *req = NULL;
222
223 req = list_entry(ep->queue.next, struct fsl_req, queue);
224 done(ep, req, status);
225 }
226 }
227
228 /*------------------------------------------------------------------
229 Internal Hardware related function
230 ------------------------------------------------------------------*/
231
232 static int dr_controller_setup(struct fsl_udc *udc)
233 {
234 unsigned int tmp, portctrl, ep_num;
235 unsigned int max_no_of_ep;
236 #ifndef CONFIG_ARCH_MXC
237 unsigned int ctrl;
238 #endif
239 unsigned long timeout;
240 #define FSL_UDC_RESET_TIMEOUT 1000
241
242 /* Config PHY interface */
243 portctrl = fsl_readl(&dr_regs->portsc1);
244 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
245 switch (udc->phy_mode) {
246 case FSL_USB2_PHY_ULPI:
247 portctrl |= PORTSCX_PTS_ULPI;
248 break;
249 case FSL_USB2_PHY_UTMI_WIDE:
250 portctrl |= PORTSCX_PTW_16BIT;
251 /* fall through */
252 case FSL_USB2_PHY_UTMI:
253 portctrl |= PORTSCX_PTS_UTMI;
254 break;
255 case FSL_USB2_PHY_SERIAL:
256 portctrl |= PORTSCX_PTS_FSLS;
257 break;
258 default:
259 return -EINVAL;
260 }
261 fsl_writel(portctrl, &dr_regs->portsc1);
262
263 /* Stop and reset the usb controller */
264 tmp = fsl_readl(&dr_regs->usbcmd);
265 tmp &= ~USB_CMD_RUN_STOP;
266 fsl_writel(tmp, &dr_regs->usbcmd);
267
268 tmp = fsl_readl(&dr_regs->usbcmd);
269 tmp |= USB_CMD_CTRL_RESET;
270 fsl_writel(tmp, &dr_regs->usbcmd);
271
272 /* Wait for reset to complete */
273 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
274 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
275 if (time_after(jiffies, timeout)) {
276 ERR("udc reset timeout!\n");
277 return -ETIMEDOUT;
278 }
279 cpu_relax();
280 }
281
282 /* Set the controller as device mode */
283 tmp = fsl_readl(&dr_regs->usbmode);
284 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
285 tmp |= USB_MODE_CTRL_MODE_DEVICE;
286 /* Disable Setup Lockout */
287 tmp |= USB_MODE_SETUP_LOCK_OFF;
288 if (udc->pdata->es)
289 tmp |= USB_MODE_ES;
290 fsl_writel(tmp, &dr_regs->usbmode);
291
292 /* Clear the setup status */
293 fsl_writel(0, &dr_regs->usbsts);
294
295 tmp = udc->ep_qh_dma;
296 tmp &= USB_EP_LIST_ADDRESS_MASK;
297 fsl_writel(tmp, &dr_regs->endpointlistaddr);
298
299 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
300 udc->ep_qh, (int)tmp,
301 fsl_readl(&dr_regs->endpointlistaddr));
302
303 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
304 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
305 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
306 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
307 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
308 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
309 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
310 }
311 /* Config control enable i/o output, cpu endian register */
312 #ifndef CONFIG_ARCH_MXC
313 if (udc->pdata->have_sysif_regs) {
314 ctrl = __raw_readl(&usb_sys_regs->control);
315 ctrl |= USB_CTRL_IOENB;
316 __raw_writel(ctrl, &usb_sys_regs->control);
317 }
318 #endif
319
320 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
321 /* Turn on cache snooping hardware, since some PowerPC platforms
322 * wholly rely on hardware to deal with cache coherent. */
323
324 if (udc->pdata->have_sysif_regs) {
325 /* Setup Snooping for all the 4GB space */
326 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
327 __raw_writel(tmp, &usb_sys_regs->snoop1);
328 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
329 __raw_writel(tmp, &usb_sys_regs->snoop2);
330 }
331 #endif
332
333 return 0;
334 }
335
336 /* Enable DR irq and set controller to run state */
337 static void dr_controller_run(struct fsl_udc *udc)
338 {
339 u32 temp;
340
341 /* Enable DR irq reg */
342 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
343 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
344 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
345
346 fsl_writel(temp, &dr_regs->usbintr);
347
348 /* Clear stopped bit */
349 udc->stopped = 0;
350
351 /* Set the controller as device mode */
352 temp = fsl_readl(&dr_regs->usbmode);
353 temp |= USB_MODE_CTRL_MODE_DEVICE;
354 fsl_writel(temp, &dr_regs->usbmode);
355
356 /* Set controller to Run */
357 temp = fsl_readl(&dr_regs->usbcmd);
358 temp |= USB_CMD_RUN_STOP;
359 fsl_writel(temp, &dr_regs->usbcmd);
360 }
361
362 static void dr_controller_stop(struct fsl_udc *udc)
363 {
364 unsigned int tmp;
365
366 pr_debug("%s\n", __func__);
367
368 /* if we're in OTG mode, and the Host is currently using the port,
369 * stop now and don't rip the controller out from under the
370 * ehci driver
371 */
372 if (udc->gadget.is_otg) {
373 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
374 pr_debug("udc: Leaving early\n");
375 return;
376 }
377 }
378
379 /* disable all INTR */
380 fsl_writel(0, &dr_regs->usbintr);
381
382 /* Set stopped bit for isr */
383 udc->stopped = 1;
384
385 /* disable IO output */
386 /* usb_sys_regs->control = 0; */
387
388 /* set controller to Stop */
389 tmp = fsl_readl(&dr_regs->usbcmd);
390 tmp &= ~USB_CMD_RUN_STOP;
391 fsl_writel(tmp, &dr_regs->usbcmd);
392 }
393
394 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
395 unsigned char ep_type)
396 {
397 unsigned int tmp_epctrl = 0;
398
399 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
400 if (dir) {
401 if (ep_num)
402 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
403 tmp_epctrl |= EPCTRL_TX_ENABLE;
404 tmp_epctrl &= ~EPCTRL_TX_TYPE;
405 tmp_epctrl |= ((unsigned int)(ep_type)
406 << EPCTRL_TX_EP_TYPE_SHIFT);
407 } else {
408 if (ep_num)
409 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
410 tmp_epctrl |= EPCTRL_RX_ENABLE;
411 tmp_epctrl &= ~EPCTRL_RX_TYPE;
412 tmp_epctrl |= ((unsigned int)(ep_type)
413 << EPCTRL_RX_EP_TYPE_SHIFT);
414 }
415
416 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
417 }
418
419 static void
420 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
421 {
422 u32 tmp_epctrl = 0;
423
424 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
425
426 if (value) {
427 /* set the stall bit */
428 if (dir)
429 tmp_epctrl |= EPCTRL_TX_EP_STALL;
430 else
431 tmp_epctrl |= EPCTRL_RX_EP_STALL;
432 } else {
433 /* clear the stall bit and reset data toggle */
434 if (dir) {
435 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
436 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
437 } else {
438 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
439 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
440 }
441 }
442 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
443 }
444
445 /* Get stall status of a specific ep
446 Return: 0: not stalled; 1:stalled */
447 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
448 {
449 u32 epctrl;
450
451 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
452 if (dir)
453 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
454 else
455 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
456 }
457
458 /********************************************************************
459 Internal Structure Build up functions
460 ********************************************************************/
461
462 /*------------------------------------------------------------------
463 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
464 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
465 * @mult: Mult field
466 ------------------------------------------------------------------*/
467 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
468 unsigned char dir, unsigned char ep_type,
469 unsigned int max_pkt_len,
470 unsigned int zlt, unsigned char mult)
471 {
472 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
473 unsigned int tmp = 0;
474
475 /* set the Endpoint Capabilites in QH */
476 switch (ep_type) {
477 case USB_ENDPOINT_XFER_CONTROL:
478 /* Interrupt On Setup (IOS). for control ep */
479 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
480 | EP_QUEUE_HEAD_IOS;
481 break;
482 case USB_ENDPOINT_XFER_ISOC:
483 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
484 | (mult << EP_QUEUE_HEAD_MULT_POS);
485 break;
486 case USB_ENDPOINT_XFER_BULK:
487 case USB_ENDPOINT_XFER_INT:
488 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
489 break;
490 default:
491 VDBG("error ep type is %d", ep_type);
492 return;
493 }
494 if (zlt)
495 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
496
497 p_QH->max_pkt_length = cpu_to_hc32(tmp);
498 p_QH->next_dtd_ptr = 1;
499 p_QH->size_ioc_int_sts = 0;
500 }
501
502 /* Setup qh structure and ep register for ep0. */
503 static void ep0_setup(struct fsl_udc *udc)
504 {
505 /* the intialization of an ep includes: fields in QH, Regs,
506 * fsl_ep struct */
507 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
508 USB_MAX_CTRL_PAYLOAD, 0, 0);
509 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
510 USB_MAX_CTRL_PAYLOAD, 0, 0);
511 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
512 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
513
514 return;
515
516 }
517
518 /***********************************************************************
519 Endpoint Management Functions
520 ***********************************************************************/
521
522 /*-------------------------------------------------------------------------
523 * when configurations are set, or when interface settings change
524 * for example the do_set_interface() in gadget layer,
525 * the driver will enable or disable the relevant endpoints
526 * ep0 doesn't use this routine. It is always enabled.
527 -------------------------------------------------------------------------*/
528 static int fsl_ep_enable(struct usb_ep *_ep,
529 const struct usb_endpoint_descriptor *desc)
530 {
531 struct fsl_udc *udc = NULL;
532 struct fsl_ep *ep = NULL;
533 unsigned short max = 0;
534 unsigned char mult = 0, zlt;
535 int retval = -EINVAL;
536 unsigned long flags = 0;
537
538 ep = container_of(_ep, struct fsl_ep, ep);
539
540 /* catch various bogus parameters */
541 if (!_ep || !desc || ep->desc
542 || (desc->bDescriptorType != USB_DT_ENDPOINT))
543 return -EINVAL;
544
545 udc = ep->udc;
546
547 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
548 return -ESHUTDOWN;
549
550 max = le16_to_cpu(desc->wMaxPacketSize);
551
552 /* Disable automatic zlp generation. Driver is responsible to indicate
553 * explicitly through req->req.zero. This is needed to enable multi-td
554 * request. */
555 zlt = 1;
556
557 /* Assume the max packet size from gadget is always correct */
558 switch (desc->bmAttributes & 0x03) {
559 case USB_ENDPOINT_XFER_CONTROL:
560 case USB_ENDPOINT_XFER_BULK:
561 case USB_ENDPOINT_XFER_INT:
562 /* mult = 0. Execute N Transactions as demonstrated by
563 * the USB variable length packet protocol where N is
564 * computed using the Maximum Packet Length (dQH) and
565 * the Total Bytes field (dTD) */
566 mult = 0;
567 break;
568 case USB_ENDPOINT_XFER_ISOC:
569 /* Calculate transactions needed for high bandwidth iso */
570 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
571 max = max & 0x7ff; /* bit 0~10 */
572 /* 3 transactions at most */
573 if (mult > 3)
574 goto en_done;
575 break;
576 default:
577 goto en_done;
578 }
579
580 spin_lock_irqsave(&udc->lock, flags);
581 ep->ep.maxpacket = max;
582 ep->desc = desc;
583 ep->stopped = 0;
584
585 /* Controller related setup */
586 /* Init EPx Queue Head (Ep Capabilites field in QH
587 * according to max, zlt, mult) */
588 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
589 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
590 ? USB_SEND : USB_RECV),
591 (unsigned char) (desc->bmAttributes
592 & USB_ENDPOINT_XFERTYPE_MASK),
593 max, zlt, mult);
594
595 /* Init endpoint ctrl register */
596 dr_ep_setup((unsigned char) ep_index(ep),
597 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
598 ? USB_SEND : USB_RECV),
599 (unsigned char) (desc->bmAttributes
600 & USB_ENDPOINT_XFERTYPE_MASK));
601
602 spin_unlock_irqrestore(&udc->lock, flags);
603 retval = 0;
604
605 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
606 ep->desc->bEndpointAddress & 0x0f,
607 (desc->bEndpointAddress & USB_DIR_IN)
608 ? "in" : "out", max);
609 en_done:
610 return retval;
611 }
612
613 /*---------------------------------------------------------------------
614 * @ep : the ep being unconfigured. May not be ep0
615 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
616 *---------------------------------------------------------------------*/
617 static int fsl_ep_disable(struct usb_ep *_ep)
618 {
619 struct fsl_udc *udc = NULL;
620 struct fsl_ep *ep = NULL;
621 unsigned long flags = 0;
622 u32 epctrl;
623 int ep_num;
624
625 ep = container_of(_ep, struct fsl_ep, ep);
626 if (!_ep || !ep->desc) {
627 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
628 return -EINVAL;
629 }
630
631 /* disable ep on controller */
632 ep_num = ep_index(ep);
633 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
634 if (ep_is_in(ep)) {
635 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
636 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
637 } else {
638 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
639 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
640 }
641 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
642
643 udc = (struct fsl_udc *)ep->udc;
644 spin_lock_irqsave(&udc->lock, flags);
645
646 /* nuke all pending requests (does flush) */
647 nuke(ep, -ESHUTDOWN);
648
649 ep->desc = NULL;
650 ep->stopped = 1;
651 spin_unlock_irqrestore(&udc->lock, flags);
652
653 VDBG("disabled %s OK", _ep->name);
654 return 0;
655 }
656
657 /*---------------------------------------------------------------------
658 * allocate a request object used by this endpoint
659 * the main operation is to insert the req->queue to the eq->queue
660 * Returns the request, or null if one could not be allocated
661 *---------------------------------------------------------------------*/
662 static struct usb_request *
663 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
664 {
665 struct fsl_req *req = NULL;
666
667 req = kzalloc(sizeof *req, gfp_flags);
668 if (!req)
669 return NULL;
670
671 req->req.dma = DMA_ADDR_INVALID;
672 INIT_LIST_HEAD(&req->queue);
673
674 return &req->req;
675 }
676
677 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
678 {
679 struct fsl_req *req = NULL;
680
681 req = container_of(_req, struct fsl_req, req);
682
683 if (_req)
684 kfree(req);
685 }
686
687 /*-------------------------------------------------------------------------*/
688 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
689 {
690 int i = ep_index(ep) * 2 + ep_is_in(ep);
691 u32 temp, bitmask, tmp_stat;
692 struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
693
694 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
695 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
696
697 bitmask = ep_is_in(ep)
698 ? (1 << (ep_index(ep) + 16))
699 : (1 << (ep_index(ep)));
700
701 /* check if the pipe is empty */
702 if (!(list_empty(&ep->queue))) {
703 /* Add td to the end */
704 struct fsl_req *lastreq;
705 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
706 lastreq->tail->next_td_ptr =
707 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
708 /* Read prime bit, if 1 goto done */
709 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
710 goto out;
711
712 do {
713 /* Set ATDTW bit in USBCMD */
714 temp = fsl_readl(&dr_regs->usbcmd);
715 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
716
717 /* Read correct status bit */
718 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
719
720 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
721
722 /* Write ATDTW bit to 0 */
723 temp = fsl_readl(&dr_regs->usbcmd);
724 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
725
726 if (tmp_stat)
727 goto out;
728 }
729
730 /* Write dQH next pointer and terminate bit to 0 */
731 temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
732 dQH->next_dtd_ptr = cpu_to_hc32(temp);
733
734 /* Clear active and halt bit */
735 temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
736 | EP_QUEUE_HEAD_STATUS_HALT));
737 dQH->size_ioc_int_sts &= temp;
738
739 /* Ensure that updates to the QH will occur before priming. */
740 wmb();
741
742 /* Prime endpoint by writing 1 to ENDPTPRIME */
743 temp = ep_is_in(ep)
744 ? (1 << (ep_index(ep) + 16))
745 : (1 << (ep_index(ep)));
746 fsl_writel(temp, &dr_regs->endpointprime);
747 out:
748 return;
749 }
750
751 /* Fill in the dTD structure
752 * @req: request that the transfer belongs to
753 * @length: return actually data length of the dTD
754 * @dma: return dma address of the dTD
755 * @is_last: return flag if it is the last dTD of the request
756 * return: pointer to the built dTD */
757 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
758 dma_addr_t *dma, int *is_last)
759 {
760 u32 swap_temp;
761 struct ep_td_struct *dtd;
762
763 /* how big will this transfer be? */
764 *length = min(req->req.length - req->req.actual,
765 (unsigned)EP_MAX_LENGTH_TRANSFER);
766
767 dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
768 if (dtd == NULL)
769 return dtd;
770
771 dtd->td_dma = *dma;
772 /* Clear reserved field */
773 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
774 swap_temp &= ~DTD_RESERVED_FIELDS;
775 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
776
777 /* Init all of buffer page pointers */
778 swap_temp = (u32) (req->req.dma + req->req.actual);
779 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
780 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
781 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
782 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
783 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
784
785 req->req.actual += *length;
786
787 /* zlp is needed if req->req.zero is set */
788 if (req->req.zero) {
789 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
790 *is_last = 1;
791 else
792 *is_last = 0;
793 } else if (req->req.length == req->req.actual)
794 *is_last = 1;
795 else
796 *is_last = 0;
797
798 if ((*is_last) == 0)
799 VDBG("multi-dtd request!");
800 /* Fill in the transfer size; set active bit */
801 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
802
803 /* Enable interrupt for the last dtd of a request */
804 if (*is_last && !req->req.no_interrupt)
805 swap_temp |= DTD_IOC;
806
807 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
808
809 mb();
810
811 VDBG("length = %d address= 0x%x", *length, (int)*dma);
812
813 return dtd;
814 }
815
816 /* Generate dtd chain for a request */
817 static int fsl_req_to_dtd(struct fsl_req *req)
818 {
819 unsigned count;
820 int is_last;
821 int is_first =1;
822 struct ep_td_struct *last_dtd = NULL, *dtd;
823 dma_addr_t dma;
824
825 do {
826 dtd = fsl_build_dtd(req, &count, &dma, &is_last);
827 if (dtd == NULL)
828 return -ENOMEM;
829
830 if (is_first) {
831 is_first = 0;
832 req->head = dtd;
833 } else {
834 last_dtd->next_td_ptr = cpu_to_hc32(dma);
835 last_dtd->next_td_virt = dtd;
836 }
837 last_dtd = dtd;
838
839 req->dtd_count++;
840 } while (!is_last);
841
842 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
843
844 req->tail = dtd;
845
846 return 0;
847 }
848
849 /* queues (submits) an I/O request to an endpoint */
850 static int
851 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
852 {
853 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
854 struct fsl_req *req = container_of(_req, struct fsl_req, req);
855 struct fsl_udc *udc;
856 unsigned long flags;
857
858 /* catch various bogus parameters */
859 if (!_req || !req->req.complete || !req->req.buf
860 || !list_empty(&req->queue)) {
861 VDBG("%s, bad params", __func__);
862 return -EINVAL;
863 }
864 if (unlikely(!_ep || !ep->desc)) {
865 VDBG("%s, bad ep", __func__);
866 return -EINVAL;
867 }
868 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
869 if (req->req.length > ep->ep.maxpacket)
870 return -EMSGSIZE;
871 }
872
873 udc = ep->udc;
874 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
875 return -ESHUTDOWN;
876
877 req->ep = ep;
878
879 /* map virtual address to hardware */
880 if (req->req.dma == DMA_ADDR_INVALID) {
881 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
882 req->req.buf,
883 req->req.length, ep_is_in(ep)
884 ? DMA_TO_DEVICE
885 : DMA_FROM_DEVICE);
886 req->mapped = 1;
887 } else {
888 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
889 req->req.dma, req->req.length,
890 ep_is_in(ep)
891 ? DMA_TO_DEVICE
892 : DMA_FROM_DEVICE);
893 req->mapped = 0;
894 }
895
896 req->req.status = -EINPROGRESS;
897 req->req.actual = 0;
898 req->dtd_count = 0;
899
900 spin_lock_irqsave(&udc->lock, flags);
901
902 /* build dtds and push them to device queue */
903 if (!fsl_req_to_dtd(req)) {
904 fsl_queue_td(ep, req);
905 } else {
906 spin_unlock_irqrestore(&udc->lock, flags);
907 return -ENOMEM;
908 }
909
910 /* Update ep0 state */
911 if ((ep_index(ep) == 0))
912 udc->ep0_state = DATA_STATE_XMIT;
913
914 /* irq handler advances the queue */
915 if (req != NULL)
916 list_add_tail(&req->queue, &ep->queue);
917 spin_unlock_irqrestore(&udc->lock, flags);
918
919 return 0;
920 }
921
922 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
923 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
924 {
925 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
926 struct fsl_req *req;
927 unsigned long flags;
928 int ep_num, stopped, ret = 0;
929 u32 epctrl;
930
931 if (!_ep || !_req)
932 return -EINVAL;
933
934 spin_lock_irqsave(&ep->udc->lock, flags);
935 stopped = ep->stopped;
936
937 /* Stop the ep before we deal with the queue */
938 ep->stopped = 1;
939 ep_num = ep_index(ep);
940 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
941 if (ep_is_in(ep))
942 epctrl &= ~EPCTRL_TX_ENABLE;
943 else
944 epctrl &= ~EPCTRL_RX_ENABLE;
945 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
946
947 /* make sure it's actually queued on this endpoint */
948 list_for_each_entry(req, &ep->queue, queue) {
949 if (&req->req == _req)
950 break;
951 }
952 if (&req->req != _req) {
953 ret = -EINVAL;
954 goto out;
955 }
956
957 /* The request is in progress, or completed but not dequeued */
958 if (ep->queue.next == &req->queue) {
959 _req->status = -ECONNRESET;
960 fsl_ep_fifo_flush(_ep); /* flush current transfer */
961
962 /* The request isn't the last request in this ep queue */
963 if (req->queue.next != &ep->queue) {
964 struct ep_queue_head *qh;
965 struct fsl_req *next_req;
966
967 qh = ep->qh;
968 next_req = list_entry(req->queue.next, struct fsl_req,
969 queue);
970
971 /* Point the QH to the first TD of next request */
972 fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
973 }
974
975 /* The request hasn't been processed, patch up the TD chain */
976 } else {
977 struct fsl_req *prev_req;
978
979 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
980 fsl_writel(fsl_readl(&req->tail->next_td_ptr),
981 &prev_req->tail->next_td_ptr);
982
983 }
984
985 done(ep, req, -ECONNRESET);
986
987 /* Enable EP */
988 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
989 if (ep_is_in(ep))
990 epctrl |= EPCTRL_TX_ENABLE;
991 else
992 epctrl |= EPCTRL_RX_ENABLE;
993 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
994 ep->stopped = stopped;
995
996 spin_unlock_irqrestore(&ep->udc->lock, flags);
997 return ret;
998 }
999
1000 /*-------------------------------------------------------------------------*/
1001
1002 /*-----------------------------------------------------------------
1003 * modify the endpoint halt feature
1004 * @ep: the non-isochronous endpoint being stalled
1005 * @value: 1--set halt 0--clear halt
1006 * Returns zero, or a negative error code.
1007 *----------------------------------------------------------------*/
1008 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1009 {
1010 struct fsl_ep *ep = NULL;
1011 unsigned long flags = 0;
1012 int status = -EOPNOTSUPP; /* operation not supported */
1013 unsigned char ep_dir = 0, ep_num = 0;
1014 struct fsl_udc *udc = NULL;
1015
1016 ep = container_of(_ep, struct fsl_ep, ep);
1017 udc = ep->udc;
1018 if (!_ep || !ep->desc) {
1019 status = -EINVAL;
1020 goto out;
1021 }
1022
1023 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1024 status = -EOPNOTSUPP;
1025 goto out;
1026 }
1027
1028 /* Attempt to halt IN ep will fail if any transfer requests
1029 * are still queue */
1030 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1031 status = -EAGAIN;
1032 goto out;
1033 }
1034
1035 status = 0;
1036 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1037 ep_num = (unsigned char)(ep_index(ep));
1038 spin_lock_irqsave(&ep->udc->lock, flags);
1039 dr_ep_change_stall(ep_num, ep_dir, value);
1040 spin_unlock_irqrestore(&ep->udc->lock, flags);
1041
1042 if (ep_index(ep) == 0) {
1043 udc->ep0_state = WAIT_FOR_SETUP;
1044 udc->ep0_dir = 0;
1045 }
1046 out:
1047 VDBG(" %s %s halt stat %d", ep->ep.name,
1048 value ? "set" : "clear", status);
1049
1050 return status;
1051 }
1052
1053 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1054 {
1055 struct fsl_ep *ep;
1056 struct fsl_udc *udc;
1057 int size = 0;
1058 u32 bitmask;
1059 struct ep_queue_head *d_qh;
1060
1061 ep = container_of(_ep, struct fsl_ep, ep);
1062 if (!_ep || (!ep->desc && ep_index(ep) != 0))
1063 return -ENODEV;
1064
1065 udc = (struct fsl_udc *)ep->udc;
1066
1067 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1068 return -ESHUTDOWN;
1069
1070 d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
1071
1072 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1073 (1 << (ep_index(ep)));
1074
1075 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1076 size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1077 >> DTD_LENGTH_BIT_POS;
1078
1079 pr_debug("%s %u\n", __func__, size);
1080 return size;
1081 }
1082
1083 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1084 {
1085 struct fsl_ep *ep;
1086 int ep_num, ep_dir;
1087 u32 bits;
1088 unsigned long timeout;
1089 #define FSL_UDC_FLUSH_TIMEOUT 1000
1090
1091 if (!_ep) {
1092 return;
1093 } else {
1094 ep = container_of(_ep, struct fsl_ep, ep);
1095 if (!ep->desc)
1096 return;
1097 }
1098 ep_num = ep_index(ep);
1099 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1100
1101 if (ep_num == 0)
1102 bits = (1 << 16) | 1;
1103 else if (ep_dir == USB_SEND)
1104 bits = 1 << (16 + ep_num);
1105 else
1106 bits = 1 << ep_num;
1107
1108 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1109 do {
1110 fsl_writel(bits, &dr_regs->endptflush);
1111
1112 /* Wait until flush complete */
1113 while (fsl_readl(&dr_regs->endptflush)) {
1114 if (time_after(jiffies, timeout)) {
1115 ERR("ep flush timeout\n");
1116 return;
1117 }
1118 cpu_relax();
1119 }
1120 /* See if we need to flush again */
1121 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1122 }
1123
1124 static struct usb_ep_ops fsl_ep_ops = {
1125 .enable = fsl_ep_enable,
1126 .disable = fsl_ep_disable,
1127
1128 .alloc_request = fsl_alloc_request,
1129 .free_request = fsl_free_request,
1130
1131 .queue = fsl_ep_queue,
1132 .dequeue = fsl_ep_dequeue,
1133
1134 .set_halt = fsl_ep_set_halt,
1135 .fifo_status = fsl_ep_fifo_status,
1136 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1137 };
1138
1139 /*-------------------------------------------------------------------------
1140 Gadget Driver Layer Operations
1141 -------------------------------------------------------------------------*/
1142
1143 /*----------------------------------------------------------------------
1144 * Get the current frame number (from DR frame_index Reg )
1145 *----------------------------------------------------------------------*/
1146 static int fsl_get_frame(struct usb_gadget *gadget)
1147 {
1148 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1149 }
1150
1151 /*-----------------------------------------------------------------------
1152 * Tries to wake up the host connected to this gadget
1153 -----------------------------------------------------------------------*/
1154 static int fsl_wakeup(struct usb_gadget *gadget)
1155 {
1156 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1157 u32 portsc;
1158
1159 /* Remote wakeup feature not enabled by host */
1160 if (!udc->remote_wakeup)
1161 return -ENOTSUPP;
1162
1163 portsc = fsl_readl(&dr_regs->portsc1);
1164 /* not suspended? */
1165 if (!(portsc & PORTSCX_PORT_SUSPEND))
1166 return 0;
1167 /* trigger force resume */
1168 portsc |= PORTSCX_PORT_FORCE_RESUME;
1169 fsl_writel(portsc, &dr_regs->portsc1);
1170 return 0;
1171 }
1172
1173 static int can_pullup(struct fsl_udc *udc)
1174 {
1175 return udc->driver && udc->softconnect && udc->vbus_active;
1176 }
1177
1178 /* Notify controller that VBUS is powered, Called by whatever
1179 detects VBUS sessions */
1180 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1181 {
1182 struct fsl_udc *udc;
1183 unsigned long flags;
1184
1185 udc = container_of(gadget, struct fsl_udc, gadget);
1186 spin_lock_irqsave(&udc->lock, flags);
1187 VDBG("VBUS %s", is_active ? "on" : "off");
1188 udc->vbus_active = (is_active != 0);
1189 if (can_pullup(udc))
1190 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1191 &dr_regs->usbcmd);
1192 else
1193 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1194 &dr_regs->usbcmd);
1195 spin_unlock_irqrestore(&udc->lock, flags);
1196 return 0;
1197 }
1198
1199 /* constrain controller's VBUS power usage
1200 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1201 * reporting how much power the device may consume. For example, this
1202 * could affect how quickly batteries are recharged.
1203 *
1204 * Returns zero on success, else negative errno.
1205 */
1206 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1207 {
1208 struct fsl_udc *udc;
1209
1210 udc = container_of(gadget, struct fsl_udc, gadget);
1211 if (udc->transceiver)
1212 return otg_set_power(udc->transceiver, mA);
1213 return -ENOTSUPP;
1214 }
1215
1216 /* Change Data+ pullup status
1217 * this func is used by usb_gadget_connect/disconnet
1218 */
1219 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1220 {
1221 struct fsl_udc *udc;
1222
1223 udc = container_of(gadget, struct fsl_udc, gadget);
1224 udc->softconnect = (is_on != 0);
1225 if (can_pullup(udc))
1226 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1227 &dr_regs->usbcmd);
1228 else
1229 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1230 &dr_regs->usbcmd);
1231
1232 return 0;
1233 }
1234
1235 static int fsl_start(struct usb_gadget_driver *driver,
1236 int (*bind)(struct usb_gadget *));
1237 static int fsl_stop(struct usb_gadget_driver *driver);
1238 /* defined in gadget.h */
1239 static struct usb_gadget_ops fsl_gadget_ops = {
1240 .get_frame = fsl_get_frame,
1241 .wakeup = fsl_wakeup,
1242 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1243 .vbus_session = fsl_vbus_session,
1244 .vbus_draw = fsl_vbus_draw,
1245 .pullup = fsl_pullup,
1246 .start = fsl_start,
1247 .stop = fsl_stop,
1248 };
1249
1250 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1251 on new transaction */
1252 static void ep0stall(struct fsl_udc *udc)
1253 {
1254 u32 tmp;
1255
1256 /* must set tx and rx to stall at the same time */
1257 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1258 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1259 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1260 udc->ep0_state = WAIT_FOR_SETUP;
1261 udc->ep0_dir = 0;
1262 }
1263
1264 /* Prime a status phase for ep0 */
1265 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1266 {
1267 struct fsl_req *req = udc->status_req;
1268 struct fsl_ep *ep;
1269
1270 if (direction == EP_DIR_IN)
1271 udc->ep0_dir = USB_DIR_IN;
1272 else
1273 udc->ep0_dir = USB_DIR_OUT;
1274
1275 ep = &udc->eps[0];
1276 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1277
1278 req->ep = ep;
1279 req->req.length = 0;
1280 req->req.status = -EINPROGRESS;
1281 req->req.actual = 0;
1282 req->req.complete = NULL;
1283 req->dtd_count = 0;
1284
1285 if (fsl_req_to_dtd(req) == 0)
1286 fsl_queue_td(ep, req);
1287 else
1288 return -ENOMEM;
1289
1290 list_add_tail(&req->queue, &ep->queue);
1291
1292 return 0;
1293 }
1294
1295 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1296 {
1297 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1298
1299 if (ep->name)
1300 nuke(ep, -ESHUTDOWN);
1301 }
1302
1303 /*
1304 * ch9 Set address
1305 */
1306 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1307 {
1308 /* Save the new address to device struct */
1309 udc->device_address = (u8) value;
1310 /* Update usb state */
1311 udc->usb_state = USB_STATE_ADDRESS;
1312 /* Status phase */
1313 if (ep0_prime_status(udc, EP_DIR_IN))
1314 ep0stall(udc);
1315 }
1316
1317 /*
1318 * ch9 Get status
1319 */
1320 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1321 u16 index, u16 length)
1322 {
1323 u16 tmp = 0; /* Status, cpu endian */
1324 struct fsl_req *req;
1325 struct fsl_ep *ep;
1326
1327 ep = &udc->eps[0];
1328
1329 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1330 /* Get device status */
1331 tmp = 1 << USB_DEVICE_SELF_POWERED;
1332 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1333 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1334 /* Get interface status */
1335 /* We don't have interface information in udc driver */
1336 tmp = 0;
1337 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1338 /* Get endpoint status */
1339 struct fsl_ep *target_ep;
1340
1341 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1342
1343 /* stall if endpoint doesn't exist */
1344 if (!target_ep->desc)
1345 goto stall;
1346 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1347 << USB_ENDPOINT_HALT;
1348 }
1349
1350 udc->ep0_dir = USB_DIR_IN;
1351 /* Borrow the per device status_req */
1352 req = udc->status_req;
1353 /* Fill in the reqest structure */
1354 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1355
1356 /* flush cache for the req buffer */
1357 flush_dcache_range((u32)req->req.buf, (u32)req->req.buf + 8);
1358
1359 req->ep = ep;
1360 req->req.length = 2;
1361 req->req.status = -EINPROGRESS;
1362 req->req.actual = 0;
1363 req->req.complete = NULL;
1364 req->dtd_count = 0;
1365
1366 /* prime the data phase */
1367 if ((fsl_req_to_dtd(req) == 0))
1368 fsl_queue_td(ep, req);
1369 else /* no mem */
1370 goto stall;
1371
1372 list_add_tail(&req->queue, &ep->queue);
1373 udc->ep0_state = DATA_STATE_XMIT;
1374 return;
1375 stall:
1376 ep0stall(udc);
1377 }
1378
1379 static void setup_received_irq(struct fsl_udc *udc,
1380 struct usb_ctrlrequest *setup)
1381 {
1382 u16 wValue = le16_to_cpu(setup->wValue);
1383 u16 wIndex = le16_to_cpu(setup->wIndex);
1384 u16 wLength = le16_to_cpu(setup->wLength);
1385
1386 udc_reset_ep_queue(udc, 0);
1387
1388 /* We process some stardard setup requests here */
1389 switch (setup->bRequest) {
1390 case USB_REQ_GET_STATUS:
1391 /* Data+Status phase from udc */
1392 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1393 != (USB_DIR_IN | USB_TYPE_STANDARD))
1394 break;
1395 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1396 return;
1397
1398 case USB_REQ_SET_ADDRESS:
1399 /* Status phase from udc */
1400 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1401 | USB_RECIP_DEVICE))
1402 break;
1403 ch9setaddress(udc, wValue, wIndex, wLength);
1404 return;
1405
1406 case USB_REQ_CLEAR_FEATURE:
1407 case USB_REQ_SET_FEATURE:
1408 /* Status phase from udc */
1409 {
1410 int rc = -EOPNOTSUPP;
1411 u16 ptc = 0;
1412
1413 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1414 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1415 int pipe = get_pipe_by_windex(wIndex);
1416 struct fsl_ep *ep;
1417
1418 if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1419 break;
1420 ep = get_ep_by_pipe(udc, pipe);
1421
1422 spin_unlock(&udc->lock);
1423 rc = fsl_ep_set_halt(&ep->ep,
1424 (setup->bRequest == USB_REQ_SET_FEATURE)
1425 ? 1 : 0);
1426 spin_lock(&udc->lock);
1427
1428 } else if ((setup->bRequestType & (USB_RECIP_MASK
1429 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1430 | USB_TYPE_STANDARD)) {
1431 /* Note: The driver has not include OTG support yet.
1432 * This will be set when OTG support is added */
1433 if (wValue == USB_DEVICE_TEST_MODE)
1434 ptc = wIndex >> 8;
1435 else if (gadget_is_otg(&udc->gadget)) {
1436 if (setup->bRequest ==
1437 USB_DEVICE_B_HNP_ENABLE)
1438 udc->gadget.b_hnp_enable = 1;
1439 else if (setup->bRequest ==
1440 USB_DEVICE_A_HNP_SUPPORT)
1441 udc->gadget.a_hnp_support = 1;
1442 else if (setup->bRequest ==
1443 USB_DEVICE_A_ALT_HNP_SUPPORT)
1444 udc->gadget.a_alt_hnp_support = 1;
1445 }
1446 rc = 0;
1447 } else
1448 break;
1449
1450 if (rc == 0) {
1451 if (ep0_prime_status(udc, EP_DIR_IN))
1452 ep0stall(udc);
1453 }
1454 if (ptc) {
1455 u32 tmp;
1456
1457 mdelay(10);
1458 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1459 fsl_writel(tmp, &dr_regs->portsc1);
1460 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1461 }
1462
1463 return;
1464 }
1465
1466 default:
1467 break;
1468 }
1469
1470 /* Requests handled by gadget */
1471 if (wLength) {
1472 /* Data phase from gadget, status phase from udc */
1473 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1474 ? USB_DIR_IN : USB_DIR_OUT;
1475 spin_unlock(&udc->lock);
1476 if (udc->driver->setup(&udc->gadget,
1477 &udc->local_setup_buff) < 0)
1478 ep0stall(udc);
1479 spin_lock(&udc->lock);
1480 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1481 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1482 } else {
1483 /* No data phase, IN status from gadget */
1484 udc->ep0_dir = USB_DIR_IN;
1485 spin_unlock(&udc->lock);
1486 if (udc->driver->setup(&udc->gadget,
1487 &udc->local_setup_buff) < 0)
1488 ep0stall(udc);
1489 spin_lock(&udc->lock);
1490 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1491 }
1492 }
1493
1494 /* Process request for Data or Status phase of ep0
1495 * prime status phase if needed */
1496 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1497 struct fsl_req *req)
1498 {
1499 if (udc->usb_state == USB_STATE_ADDRESS) {
1500 /* Set the new address */
1501 u32 new_address = (u32) udc->device_address;
1502 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1503 &dr_regs->deviceaddr);
1504 }
1505
1506 done(ep0, req, 0);
1507
1508 switch (udc->ep0_state) {
1509 case DATA_STATE_XMIT:
1510 /* receive status phase */
1511 if (ep0_prime_status(udc, EP_DIR_OUT))
1512 ep0stall(udc);
1513 break;
1514 case DATA_STATE_RECV:
1515 /* send status phase */
1516 if (ep0_prime_status(udc, EP_DIR_IN))
1517 ep0stall(udc);
1518 break;
1519 case WAIT_FOR_OUT_STATUS:
1520 udc->ep0_state = WAIT_FOR_SETUP;
1521 break;
1522 case WAIT_FOR_SETUP:
1523 ERR("Unexpect ep0 packets\n");
1524 break;
1525 default:
1526 ep0stall(udc);
1527 break;
1528 }
1529 }
1530
1531 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1532 * being corrupted by another incoming setup packet */
1533 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1534 {
1535 u32 temp;
1536 struct ep_queue_head *qh;
1537 struct fsl_usb2_platform_data *pdata = udc->pdata;
1538
1539 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1540
1541 /* Clear bit in ENDPTSETUPSTAT */
1542 temp = fsl_readl(&dr_regs->endptsetupstat);
1543 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1544
1545 /* while a hazard exists when setup package arrives */
1546 do {
1547 /* Set Setup Tripwire */
1548 temp = fsl_readl(&dr_regs->usbcmd);
1549 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1550
1551 /* Copy the setup packet to local buffer */
1552 if (pdata->le_setup_buf) {
1553 u32 *p = (u32 *)buffer_ptr;
1554 u32 *s = (u32 *)qh->setup_buffer;
1555
1556 /* Convert little endian setup buffer to CPU endian */
1557 *p++ = le32_to_cpu(*s++);
1558 *p = le32_to_cpu(*s);
1559 } else {
1560 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1561 }
1562 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1563
1564 /* Clear Setup Tripwire */
1565 temp = fsl_readl(&dr_regs->usbcmd);
1566 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1567 }
1568
1569 /* process-ep_req(): free the completed Tds for this req */
1570 static int process_ep_req(struct fsl_udc *udc, int pipe,
1571 struct fsl_req *curr_req)
1572 {
1573 struct ep_td_struct *curr_td;
1574 int td_complete, actual, remaining_length, j, tmp;
1575 int status = 0;
1576 int errors = 0;
1577 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1578 int direction = pipe % 2;
1579
1580 curr_td = curr_req->head;
1581 td_complete = 0;
1582 actual = curr_req->req.length;
1583
1584 for (j = 0; j < curr_req->dtd_count; j++) {
1585 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1586 & DTD_PACKET_SIZE)
1587 >> DTD_LENGTH_BIT_POS;
1588 actual -= remaining_length;
1589
1590 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1591 if (errors & DTD_ERROR_MASK) {
1592 if (errors & DTD_STATUS_HALTED) {
1593 ERR("dTD error %08x QH=%d\n", errors, pipe);
1594 /* Clear the errors and Halt condition */
1595 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1596 tmp &= ~errors;
1597 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1598 status = -EPIPE;
1599 /* FIXME: continue with next queued TD? */
1600
1601 break;
1602 }
1603 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1604 VDBG("Transfer overflow");
1605 status = -EPROTO;
1606 break;
1607 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1608 VDBG("ISO error");
1609 status = -EILSEQ;
1610 break;
1611 } else
1612 ERR("Unknown error has occurred (0x%x)!\n",
1613 errors);
1614
1615 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1616 & DTD_STATUS_ACTIVE) {
1617 VDBG("Request not complete");
1618 status = REQ_UNCOMPLETE;
1619 return status;
1620 } else if (remaining_length) {
1621 if (direction) {
1622 VDBG("Transmit dTD remaining length not zero");
1623 status = -EPROTO;
1624 break;
1625 } else {
1626 td_complete++;
1627 break;
1628 }
1629 } else {
1630 td_complete++;
1631 VDBG("dTD transmitted successful");
1632 }
1633
1634 if (j != curr_req->dtd_count - 1)
1635 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1636 }
1637
1638 if (status)
1639 return status;
1640
1641 curr_req->req.actual = actual;
1642
1643 return 0;
1644 }
1645
1646 /* Process a DTD completion interrupt */
1647 static void dtd_complete_irq(struct fsl_udc *udc)
1648 {
1649 u32 bit_pos;
1650 int i, ep_num, direction, bit_mask, status;
1651 struct fsl_ep *curr_ep;
1652 struct fsl_req *curr_req, *temp_req;
1653
1654 /* Clear the bits in the register */
1655 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1656 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1657
1658 if (!bit_pos)
1659 return;
1660
1661 for (i = 0; i < udc->max_ep * 2; i++) {
1662 ep_num = i >> 1;
1663 direction = i % 2;
1664
1665 bit_mask = 1 << (ep_num + 16 * direction);
1666
1667 if (!(bit_pos & bit_mask))
1668 continue;
1669
1670 curr_ep = get_ep_by_pipe(udc, i);
1671
1672 /* If the ep is configured */
1673 if (curr_ep->name == NULL) {
1674 WARNING("Invalid EP?");
1675 continue;
1676 }
1677
1678 /* process the req queue until an uncomplete request */
1679 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1680 queue) {
1681 status = process_ep_req(udc, i, curr_req);
1682
1683 VDBG("status of process_ep_req= %d, ep = %d",
1684 status, ep_num);
1685 if (status == REQ_UNCOMPLETE)
1686 break;
1687 /* write back status to req */
1688 curr_req->req.status = status;
1689
1690 if (ep_num == 0) {
1691 ep0_req_complete(udc, curr_ep, curr_req);
1692 break;
1693 } else
1694 done(curr_ep, curr_req, status);
1695 }
1696 }
1697 }
1698
1699 /* Process a port change interrupt */
1700 static void port_change_irq(struct fsl_udc *udc)
1701 {
1702 u32 speed;
1703
1704 if (udc->bus_reset)
1705 udc->bus_reset = 0;
1706
1707 /* Bus resetting is finished */
1708 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
1709 /* Get the speed */
1710 speed = (fsl_readl(&dr_regs->portsc1)
1711 & PORTSCX_PORT_SPEED_MASK);
1712 switch (speed) {
1713 case PORTSCX_PORT_SPEED_HIGH:
1714 udc->gadget.speed = USB_SPEED_HIGH;
1715 break;
1716 case PORTSCX_PORT_SPEED_FULL:
1717 udc->gadget.speed = USB_SPEED_FULL;
1718 break;
1719 case PORTSCX_PORT_SPEED_LOW:
1720 udc->gadget.speed = USB_SPEED_LOW;
1721 break;
1722 default:
1723 udc->gadget.speed = USB_SPEED_UNKNOWN;
1724 break;
1725 }
1726 }
1727
1728 /* Update USB state */
1729 if (!udc->resume_state)
1730 udc->usb_state = USB_STATE_DEFAULT;
1731 }
1732
1733 /* Process suspend interrupt */
1734 static void suspend_irq(struct fsl_udc *udc)
1735 {
1736 udc->resume_state = udc->usb_state;
1737 udc->usb_state = USB_STATE_SUSPENDED;
1738
1739 /* report suspend to the driver, serial.c does not support this */
1740 if (udc->driver->suspend)
1741 udc->driver->suspend(&udc->gadget);
1742 }
1743
1744 static void bus_resume(struct fsl_udc *udc)
1745 {
1746 udc->usb_state = udc->resume_state;
1747 udc->resume_state = 0;
1748
1749 /* report resume to the driver, serial.c does not support this */
1750 if (udc->driver->resume)
1751 udc->driver->resume(&udc->gadget);
1752 }
1753
1754 /* Clear up all ep queues */
1755 static int reset_queues(struct fsl_udc *udc)
1756 {
1757 u8 pipe;
1758
1759 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1760 udc_reset_ep_queue(udc, pipe);
1761
1762 /* report disconnect; the driver is already quiesced */
1763 spin_unlock(&udc->lock);
1764 udc->driver->disconnect(&udc->gadget);
1765 spin_lock(&udc->lock);
1766
1767 return 0;
1768 }
1769
1770 /* Process reset interrupt */
1771 static void reset_irq(struct fsl_udc *udc)
1772 {
1773 u32 temp;
1774 unsigned long timeout;
1775
1776 /* Clear the device address */
1777 temp = fsl_readl(&dr_regs->deviceaddr);
1778 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1779
1780 udc->device_address = 0;
1781
1782 /* Clear usb state */
1783 udc->resume_state = 0;
1784 udc->ep0_dir = 0;
1785 udc->ep0_state = WAIT_FOR_SETUP;
1786 udc->remote_wakeup = 0; /* default to 0 on reset */
1787 udc->gadget.b_hnp_enable = 0;
1788 udc->gadget.a_hnp_support = 0;
1789 udc->gadget.a_alt_hnp_support = 0;
1790
1791 /* Clear all the setup token semaphores */
1792 temp = fsl_readl(&dr_regs->endptsetupstat);
1793 fsl_writel(temp, &dr_regs->endptsetupstat);
1794
1795 /* Clear all the endpoint complete status bits */
1796 temp = fsl_readl(&dr_regs->endptcomplete);
1797 fsl_writel(temp, &dr_regs->endptcomplete);
1798
1799 timeout = jiffies + 100;
1800 while (fsl_readl(&dr_regs->endpointprime)) {
1801 /* Wait until all endptprime bits cleared */
1802 if (time_after(jiffies, timeout)) {
1803 ERR("Timeout for reset\n");
1804 break;
1805 }
1806 cpu_relax();
1807 }
1808
1809 /* Write 1s to the flush register */
1810 fsl_writel(0xffffffff, &dr_regs->endptflush);
1811
1812 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1813 VDBG("Bus reset");
1814 /* Bus is reseting */
1815 udc->bus_reset = 1;
1816 /* Reset all the queues, include XD, dTD, EP queue
1817 * head and TR Queue */
1818 reset_queues(udc);
1819 udc->usb_state = USB_STATE_DEFAULT;
1820 } else {
1821 VDBG("Controller reset");
1822 /* initialize usb hw reg except for regs for EP, not
1823 * touch usbintr reg */
1824 dr_controller_setup(udc);
1825
1826 /* Reset all internal used Queues */
1827 reset_queues(udc);
1828
1829 ep0_setup(udc);
1830
1831 /* Enable DR IRQ reg, Set Run bit, change udc state */
1832 dr_controller_run(udc);
1833 udc->usb_state = USB_STATE_ATTACHED;
1834 }
1835 }
1836
1837 /*
1838 * USB device controller interrupt handler
1839 */
1840 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1841 {
1842 struct fsl_udc *udc = _udc;
1843 u32 irq_src;
1844 irqreturn_t status = IRQ_NONE;
1845 unsigned long flags;
1846
1847 /* Disable ISR for OTG host mode */
1848 if (udc->stopped)
1849 return IRQ_NONE;
1850 spin_lock_irqsave(&udc->lock, flags);
1851 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1852 /* Clear notification bits */
1853 fsl_writel(irq_src, &dr_regs->usbsts);
1854
1855 /* VDBG("irq_src [0x%8x]", irq_src); */
1856
1857 /* Need to resume? */
1858 if (udc->usb_state == USB_STATE_SUSPENDED)
1859 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1860 bus_resume(udc);
1861
1862 /* USB Interrupt */
1863 if (irq_src & USB_STS_INT) {
1864 VDBG("Packet int");
1865 /* Setup package, we only support ep0 as control ep */
1866 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1867 tripwire_handler(udc, 0,
1868 (u8 *) (&udc->local_setup_buff));
1869 setup_received_irq(udc, &udc->local_setup_buff);
1870 status = IRQ_HANDLED;
1871 }
1872
1873 /* completion of dtd */
1874 if (fsl_readl(&dr_regs->endptcomplete)) {
1875 dtd_complete_irq(udc);
1876 status = IRQ_HANDLED;
1877 }
1878 }
1879
1880 /* SOF (for ISO transfer) */
1881 if (irq_src & USB_STS_SOF) {
1882 status = IRQ_HANDLED;
1883 }
1884
1885 /* Port Change */
1886 if (irq_src & USB_STS_PORT_CHANGE) {
1887 port_change_irq(udc);
1888 status = IRQ_HANDLED;
1889 }
1890
1891 /* Reset Received */
1892 if (irq_src & USB_STS_RESET) {
1893 VDBG("reset int");
1894 reset_irq(udc);
1895 status = IRQ_HANDLED;
1896 }
1897
1898 /* Sleep Enable (Suspend) */
1899 if (irq_src & USB_STS_SUSPEND) {
1900 suspend_irq(udc);
1901 status = IRQ_HANDLED;
1902 }
1903
1904 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1905 VDBG("Error IRQ %x", irq_src);
1906 }
1907
1908 spin_unlock_irqrestore(&udc->lock, flags);
1909 return status;
1910 }
1911
1912 /*----------------------------------------------------------------*
1913 * Hook to gadget drivers
1914 * Called by initialization code of gadget drivers
1915 *----------------------------------------------------------------*/
1916 static int fsl_start(struct usb_gadget_driver *driver,
1917 int (*bind)(struct usb_gadget *))
1918 {
1919 int retval = -ENODEV;
1920 unsigned long flags = 0;
1921
1922 if (!udc_controller)
1923 return -ENODEV;
1924
1925 if (!driver || (driver->speed != USB_SPEED_FULL
1926 && driver->speed != USB_SPEED_HIGH)
1927 || !bind || !driver->disconnect || !driver->setup)
1928 return -EINVAL;
1929
1930 if (udc_controller->driver)
1931 return -EBUSY;
1932
1933 /* lock is needed but whether should use this lock or another */
1934 spin_lock_irqsave(&udc_controller->lock, flags);
1935
1936 driver->driver.bus = NULL;
1937 /* hook up the driver */
1938 udc_controller->driver = driver;
1939 udc_controller->gadget.dev.driver = &driver->driver;
1940 spin_unlock_irqrestore(&udc_controller->lock, flags);
1941
1942 /* bind udc driver to gadget driver */
1943 retval = bind(&udc_controller->gadget);
1944 if (retval) {
1945 VDBG("bind to %s --> %d", driver->driver.name, retval);
1946 udc_controller->gadget.dev.driver = NULL;
1947 udc_controller->driver = NULL;
1948 goto out;
1949 }
1950
1951 if (udc_controller->transceiver) {
1952 /* Suspend the controller until OTG enable it */
1953 udc_controller->stopped = 1;
1954 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1955
1956 /* connect to bus through transceiver */
1957 if (udc_controller->transceiver) {
1958 retval = otg_set_peripheral(udc_controller->transceiver,
1959 &udc_controller->gadget);
1960 if (retval < 0) {
1961 ERR("can't bind to transceiver\n");
1962 driver->unbind(&udc_controller->gadget);
1963 udc_controller->gadget.dev.driver = 0;
1964 udc_controller->driver = 0;
1965 return retval;
1966 }
1967 }
1968 } else {
1969 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1970 dr_controller_run(udc_controller);
1971 udc_controller->usb_state = USB_STATE_ATTACHED;
1972 udc_controller->ep0_state = WAIT_FOR_SETUP;
1973 udc_controller->ep0_dir = 0;
1974 }
1975 printk(KERN_INFO "%s: bind to driver %s\n",
1976 udc_controller->gadget.name, driver->driver.name);
1977
1978 out:
1979 if (retval)
1980 printk(KERN_WARNING "gadget driver register failed %d\n",
1981 retval);
1982 return retval;
1983 }
1984
1985 /* Disconnect from gadget driver */
1986 static int fsl_stop(struct usb_gadget_driver *driver)
1987 {
1988 struct fsl_ep *loop_ep;
1989 unsigned long flags;
1990
1991 if (!udc_controller)
1992 return -ENODEV;
1993
1994 if (!driver || driver != udc_controller->driver || !driver->unbind)
1995 return -EINVAL;
1996
1997 if (udc_controller->transceiver)
1998 otg_set_peripheral(udc_controller->transceiver, NULL);
1999
2000 /* stop DR, disable intr */
2001 dr_controller_stop(udc_controller);
2002
2003 /* in fact, no needed */
2004 udc_controller->usb_state = USB_STATE_ATTACHED;
2005 udc_controller->ep0_state = WAIT_FOR_SETUP;
2006 udc_controller->ep0_dir = 0;
2007
2008 /* stand operation */
2009 spin_lock_irqsave(&udc_controller->lock, flags);
2010 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2011 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2012 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2013 ep.ep_list)
2014 nuke(loop_ep, -ESHUTDOWN);
2015 spin_unlock_irqrestore(&udc_controller->lock, flags);
2016
2017 /* report disconnect; the controller is already quiesced */
2018 driver->disconnect(&udc_controller->gadget);
2019
2020 /* unbind gadget and unhook driver. */
2021 driver->unbind(&udc_controller->gadget);
2022 udc_controller->gadget.dev.driver = NULL;
2023 udc_controller->driver = NULL;
2024
2025 printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2026 driver->driver.name);
2027 return 0;
2028 }
2029
2030 /*-------------------------------------------------------------------------
2031 PROC File System Support
2032 -------------------------------------------------------------------------*/
2033 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2034
2035 #include <linux/seq_file.h>
2036
2037 static const char proc_filename[] = "driver/fsl_usb2_udc";
2038
2039 static int fsl_proc_read(char *page, char **start, off_t off, int count,
2040 int *eof, void *_dev)
2041 {
2042 char *buf = page;
2043 char *next = buf;
2044 unsigned size = count;
2045 unsigned long flags;
2046 int t, i;
2047 u32 tmp_reg;
2048 struct fsl_ep *ep = NULL;
2049 struct fsl_req *req;
2050
2051 struct fsl_udc *udc = udc_controller;
2052 if (off != 0)
2053 return 0;
2054
2055 spin_lock_irqsave(&udc->lock, flags);
2056
2057 /* ------basic driver information ---- */
2058 t = scnprintf(next, size,
2059 DRIVER_DESC "\n"
2060 "%s version: %s\n"
2061 "Gadget driver: %s\n\n",
2062 driver_name, DRIVER_VERSION,
2063 udc->driver ? udc->driver->driver.name : "(none)");
2064 size -= t;
2065 next += t;
2066
2067 /* ------ DR Registers ----- */
2068 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2069 t = scnprintf(next, size,
2070 "USBCMD reg:\n"
2071 "SetupTW: %d\n"
2072 "Run/Stop: %s\n\n",
2073 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2074 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2075 size -= t;
2076 next += t;
2077
2078 tmp_reg = fsl_readl(&dr_regs->usbsts);
2079 t = scnprintf(next, size,
2080 "USB Status Reg:\n"
2081 "Dr Suspend: %d Reset Received: %d System Error: %s "
2082 "USB Error Interrupt: %s\n\n",
2083 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2084 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2085 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2086 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2087 size -= t;
2088 next += t;
2089
2090 tmp_reg = fsl_readl(&dr_regs->usbintr);
2091 t = scnprintf(next, size,
2092 "USB Intrrupt Enable Reg:\n"
2093 "Sleep Enable: %d SOF Received Enable: %d "
2094 "Reset Enable: %d\n"
2095 "System Error Enable: %d "
2096 "Port Change Dectected Enable: %d\n"
2097 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2098 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2099 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2100 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2101 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2102 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2103 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2104 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2105 size -= t;
2106 next += t;
2107
2108 tmp_reg = fsl_readl(&dr_regs->frindex);
2109 t = scnprintf(next, size,
2110 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2111 (tmp_reg & USB_FRINDEX_MASKS));
2112 size -= t;
2113 next += t;
2114
2115 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2116 t = scnprintf(next, size,
2117 "USB Device Address Reg: Device Addr is 0x%x\n\n",
2118 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2119 size -= t;
2120 next += t;
2121
2122 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2123 t = scnprintf(next, size,
2124 "USB Endpoint List Address Reg: "
2125 "Device Addr is 0x%x\n\n",
2126 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2127 size -= t;
2128 next += t;
2129
2130 tmp_reg = fsl_readl(&dr_regs->portsc1);
2131 t = scnprintf(next, size,
2132 "USB Port Status&Control Reg:\n"
2133 "Port Transceiver Type : %s Port Speed: %s\n"
2134 "PHY Low Power Suspend: %s Port Reset: %s "
2135 "Port Suspend Mode: %s\n"
2136 "Over-current Change: %s "
2137 "Port Enable/Disable Change: %s\n"
2138 "Port Enabled/Disabled: %s "
2139 "Current Connect Status: %s\n\n", ( {
2140 char *s;
2141 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2142 case PORTSCX_PTS_UTMI:
2143 s = "UTMI"; break;
2144 case PORTSCX_PTS_ULPI:
2145 s = "ULPI "; break;
2146 case PORTSCX_PTS_FSLS:
2147 s = "FS/LS Serial"; break;
2148 default:
2149 s = "None"; break;
2150 }
2151 s;} ), ( {
2152 char *s;
2153 switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
2154 case PORTSCX_PORT_SPEED_FULL:
2155 s = "Full Speed"; break;
2156 case PORTSCX_PORT_SPEED_LOW:
2157 s = "Low Speed"; break;
2158 case PORTSCX_PORT_SPEED_HIGH:
2159 s = "High Speed"; break;
2160 default:
2161 s = "Undefined"; break;
2162 }
2163 s;
2164 } ),
2165 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2166 "Normal PHY mode" : "Low power mode",
2167 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2168 "Not in Reset",
2169 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2170 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2171 "No",
2172 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2173 "Not change",
2174 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2175 "Not correct",
2176 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2177 "Attached" : "Not-Att");
2178 size -= t;
2179 next += t;
2180
2181 tmp_reg = fsl_readl(&dr_regs->usbmode);
2182 t = scnprintf(next, size,
2183 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2184 char *s;
2185 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2186 case USB_MODE_CTRL_MODE_IDLE:
2187 s = "Idle"; break;
2188 case USB_MODE_CTRL_MODE_DEVICE:
2189 s = "Device Controller"; break;
2190 case USB_MODE_CTRL_MODE_HOST:
2191 s = "Host Controller"; break;
2192 default:
2193 s = "None"; break;
2194 }
2195 s;
2196 } ));
2197 size -= t;
2198 next += t;
2199
2200 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2201 t = scnprintf(next, size,
2202 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2203 (tmp_reg & EP_SETUP_STATUS_MASK));
2204 size -= t;
2205 next += t;
2206
2207 for (i = 0; i < udc->max_ep / 2; i++) {
2208 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2209 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2210 i, tmp_reg);
2211 size -= t;
2212 next += t;
2213 }
2214 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2215 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2216 size -= t;
2217 next += t;
2218
2219 #ifndef CONFIG_ARCH_MXC
2220 if (udc->pdata->have_sysif_regs) {
2221 tmp_reg = usb_sys_regs->snoop1;
2222 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2223 size -= t;
2224 next += t;
2225
2226 tmp_reg = usb_sys_regs->control;
2227 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2228 tmp_reg);
2229 size -= t;
2230 next += t;
2231 }
2232 #endif
2233
2234 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2235 ep = &udc->eps[0];
2236 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2237 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2238 size -= t;
2239 next += t;
2240
2241 if (list_empty(&ep->queue)) {
2242 t = scnprintf(next, size, "its req queue is empty\n\n");
2243 size -= t;
2244 next += t;
2245 } else {
2246 list_for_each_entry(req, &ep->queue, queue) {
2247 t = scnprintf(next, size,
2248 "req %p actual 0x%x length 0x%x buf %p\n",
2249 &req->req, req->req.actual,
2250 req->req.length, req->req.buf);
2251 size -= t;
2252 next += t;
2253 }
2254 }
2255 /* other gadget->eplist ep */
2256 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2257 if (ep->desc) {
2258 t = scnprintf(next, size,
2259 "\nFor %s Maxpkt is 0x%x "
2260 "index is 0x%x\n",
2261 ep->ep.name, ep_maxpacket(ep),
2262 ep_index(ep));
2263 size -= t;
2264 next += t;
2265
2266 if (list_empty(&ep->queue)) {
2267 t = scnprintf(next, size,
2268 "its req queue is empty\n\n");
2269 size -= t;
2270 next += t;
2271 } else {
2272 list_for_each_entry(req, &ep->queue, queue) {
2273 t = scnprintf(next, size,
2274 "req %p actual 0x%x length "
2275 "0x%x buf %p\n",
2276 &req->req, req->req.actual,
2277 req->req.length, req->req.buf);
2278 size -= t;
2279 next += t;
2280 } /* end for each_entry of ep req */
2281 } /* end for else */
2282 } /* end for if(ep->queue) */
2283 } /* end (ep->desc) */
2284
2285 spin_unlock_irqrestore(&udc->lock, flags);
2286
2287 *eof = 1;
2288 return count - size;
2289 }
2290
2291 #define create_proc_file() create_proc_read_entry(proc_filename, \
2292 0, NULL, fsl_proc_read, NULL)
2293
2294 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2295
2296 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2297
2298 #define create_proc_file() do {} while (0)
2299 #define remove_proc_file() do {} while (0)
2300
2301 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2302
2303 /*-------------------------------------------------------------------------*/
2304
2305 /* Release udc structures */
2306 static void fsl_udc_release(struct device *dev)
2307 {
2308 complete(udc_controller->done);
2309 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2310 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2311 kfree(udc_controller);
2312 }
2313
2314 /******************************************************************
2315 Internal structure setup functions
2316 *******************************************************************/
2317 /*------------------------------------------------------------------
2318 * init resource for globle controller
2319 * Return the udc handle on success or NULL on failure
2320 ------------------------------------------------------------------*/
2321 static int __init struct_udc_setup(struct fsl_udc *udc,
2322 struct platform_device *pdev)
2323 {
2324 struct fsl_usb2_platform_data *pdata;
2325 size_t size;
2326
2327 pdata = pdev->dev.platform_data;
2328 udc->phy_mode = pdata->phy_mode;
2329
2330 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2331 if (!udc->eps) {
2332 ERR("malloc fsl_ep failed\n");
2333 return -1;
2334 }
2335
2336 /* initialized QHs, take care of alignment */
2337 size = udc->max_ep * sizeof(struct ep_queue_head);
2338 if (size < QH_ALIGNMENT)
2339 size = QH_ALIGNMENT;
2340 else if ((size % QH_ALIGNMENT) != 0) {
2341 size += QH_ALIGNMENT + 1;
2342 size &= ~(QH_ALIGNMENT - 1);
2343 }
2344 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2345 &udc->ep_qh_dma, GFP_KERNEL);
2346 if (!udc->ep_qh) {
2347 ERR("malloc QHs for udc failed\n");
2348 kfree(udc->eps);
2349 return -1;
2350 }
2351
2352 udc->ep_qh_size = size;
2353
2354 /* Initialize ep0 status request structure */
2355 /* FIXME: fsl_alloc_request() ignores ep argument */
2356 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2357 struct fsl_req, req);
2358 /* allocate a small amount of memory to get valid address */
2359 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2360 udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
2361
2362 udc->resume_state = USB_STATE_NOTATTACHED;
2363 udc->usb_state = USB_STATE_POWERED;
2364 udc->ep0_dir = 0;
2365 udc->remote_wakeup = 0; /* default to 0 on reset */
2366
2367 return 0;
2368 }
2369
2370 /*----------------------------------------------------------------
2371 * Setup the fsl_ep struct for eps
2372 * Link fsl_ep->ep to gadget->ep_list
2373 * ep0out is not used so do nothing here
2374 * ep0in should be taken care
2375 *--------------------------------------------------------------*/
2376 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2377 char *name, int link)
2378 {
2379 struct fsl_ep *ep = &udc->eps[index];
2380
2381 ep->udc = udc;
2382 strcpy(ep->name, name);
2383 ep->ep.name = ep->name;
2384
2385 ep->ep.ops = &fsl_ep_ops;
2386 ep->stopped = 0;
2387
2388 /* for ep0: maxP defined in desc
2389 * for other eps, maxP is set by epautoconfig() called by gadget layer
2390 */
2391 ep->ep.maxpacket = (unsigned short) ~0;
2392
2393 /* the queue lists any req for this ep */
2394 INIT_LIST_HEAD(&ep->queue);
2395
2396 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2397 if (link)
2398 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2399 ep->gadget = &udc->gadget;
2400 ep->qh = &udc->ep_qh[index];
2401
2402 return 0;
2403 }
2404
2405 /* Driver probe function
2406 * all intialization operations implemented here except enabling usb_intr reg
2407 * board setup should have been done in the platform code
2408 */
2409 static int __init fsl_udc_probe(struct platform_device *pdev)
2410 {
2411 struct fsl_usb2_platform_data *pdata;
2412 struct resource *res;
2413 int ret = -ENODEV;
2414 unsigned int i;
2415 u32 dccparams;
2416
2417 if (strcmp(pdev->name, driver_name)) {
2418 VDBG("Wrong device");
2419 return -ENODEV;
2420 }
2421
2422 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2423 if (udc_controller == NULL) {
2424 ERR("malloc udc failed\n");
2425 return -ENOMEM;
2426 }
2427
2428 pdata = pdev->dev.platform_data;
2429 udc_controller->pdata = pdata;
2430 spin_lock_init(&udc_controller->lock);
2431 udc_controller->stopped = 1;
2432
2433 #ifdef CONFIG_USB_OTG
2434 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2435 udc_controller->transceiver = otg_get_transceiver();
2436 if (!udc_controller->transceiver) {
2437 ERR("Can't find OTG driver!\n");
2438 ret = -ENODEV;
2439 goto err_kfree;
2440 }
2441 }
2442 #endif
2443
2444 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2445 if (!res) {
2446 ret = -ENXIO;
2447 goto err_kfree;
2448 }
2449
2450 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2451 if (!request_mem_region(res->start, res->end - res->start + 1,
2452 driver_name)) {
2453 ERR("request mem region for %s failed\n", pdev->name);
2454 ret = -EBUSY;
2455 goto err_kfree;
2456 }
2457 }
2458
2459 dr_regs = ioremap(res->start, resource_size(res));
2460 if (!dr_regs) {
2461 ret = -ENOMEM;
2462 goto err_release_mem_region;
2463 }
2464
2465 pdata->regs = (void *)dr_regs;
2466
2467 /*
2468 * do platform specific init: check the clock, grab/config pins, etc.
2469 */
2470 if (pdata->init && pdata->init(pdev)) {
2471 ret = -ENODEV;
2472 goto err_iounmap_noclk;
2473 }
2474
2475 /* Set accessors only after pdata->init() ! */
2476 if (pdata->big_endian_mmio) {
2477 _fsl_readl = _fsl_readl_be;
2478 _fsl_writel = _fsl_writel_be;
2479 } else {
2480 _fsl_readl = _fsl_readl_le;
2481 _fsl_writel = _fsl_writel_le;
2482 }
2483
2484 #ifndef CONFIG_ARCH_MXC
2485 if (pdata->have_sysif_regs)
2486 usb_sys_regs = (struct usb_sys_interface *)
2487 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2488 #endif
2489
2490 /* Initialize USB clocks */
2491 ret = fsl_udc_clk_init(pdev);
2492 if (ret < 0)
2493 goto err_iounmap_noclk;
2494
2495 /* Read Device Controller Capability Parameters register */
2496 dccparams = fsl_readl(&dr_regs->dccparams);
2497 if (!(dccparams & DCCPARAMS_DC)) {
2498 ERR("This SOC doesn't support device role\n");
2499 ret = -ENODEV;
2500 goto err_iounmap;
2501 }
2502 /* Get max device endpoints */
2503 /* DEN is bidirectional ep number, max_ep doubles the number */
2504 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2505
2506 udc_controller->irq = platform_get_irq(pdev, 0);
2507 if (!udc_controller->irq) {
2508 ret = -ENODEV;
2509 goto err_iounmap;
2510 }
2511
2512 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2513 driver_name, udc_controller);
2514 if (ret != 0) {
2515 ERR("cannot request irq %d err %d\n",
2516 udc_controller->irq, ret);
2517 goto err_iounmap;
2518 }
2519
2520 /* Initialize the udc structure including QH member and other member */
2521 if (struct_udc_setup(udc_controller, pdev)) {
2522 ERR("Can't initialize udc data structure\n");
2523 ret = -ENOMEM;
2524 goto err_free_irq;
2525 }
2526
2527 if (!udc_controller->transceiver) {
2528 /* initialize usb hw reg except for regs for EP,
2529 * leave usbintr reg untouched */
2530 dr_controller_setup(udc_controller);
2531 }
2532
2533 fsl_udc_clk_finalize(pdev);
2534
2535 /* Setup gadget structure */
2536 udc_controller->gadget.ops = &fsl_gadget_ops;
2537 udc_controller->gadget.is_dualspeed = 1;
2538 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2539 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2540 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2541 udc_controller->gadget.name = driver_name;
2542
2543 /* Setup gadget.dev and register with kernel */
2544 dev_set_name(&udc_controller->gadget.dev, "gadget");
2545 udc_controller->gadget.dev.release = fsl_udc_release;
2546 udc_controller->gadget.dev.parent = &pdev->dev;
2547 ret = device_register(&udc_controller->gadget.dev);
2548 if (ret < 0)
2549 goto err_free_irq;
2550
2551 if (udc_controller->transceiver)
2552 udc_controller->gadget.is_otg = 1;
2553
2554 /* setup QH and epctrl for ep0 */
2555 ep0_setup(udc_controller);
2556
2557 /* setup udc->eps[] for ep0 */
2558 struct_ep_setup(udc_controller, 0, "ep0", 0);
2559 /* for ep0: the desc defined here;
2560 * for other eps, gadget layer called ep_enable with defined desc
2561 */
2562 udc_controller->eps[0].desc = &fsl_ep0_desc;
2563 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2564
2565 /* setup the udc->eps[] for non-control endpoints and link
2566 * to gadget.ep_list */
2567 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2568 char name[14];
2569
2570 sprintf(name, "ep%dout", i);
2571 struct_ep_setup(udc_controller, i * 2, name, 1);
2572 sprintf(name, "ep%din", i);
2573 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2574 }
2575
2576 /* use dma_pool for TD management */
2577 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2578 sizeof(struct ep_td_struct),
2579 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2580 if (udc_controller->td_pool == NULL) {
2581 ret = -ENOMEM;
2582 goto err_unregister;
2583 }
2584
2585 ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2586 if (ret)
2587 goto err_del_udc;
2588
2589 create_proc_file();
2590 return 0;
2591
2592 err_del_udc:
2593 dma_pool_destroy(udc_controller->td_pool);
2594 err_unregister:
2595 device_unregister(&udc_controller->gadget.dev);
2596 err_free_irq:
2597 free_irq(udc_controller->irq, udc_controller);
2598 err_iounmap:
2599 if (pdata->exit)
2600 pdata->exit(pdev);
2601 fsl_udc_clk_release();
2602 err_iounmap_noclk:
2603 iounmap(dr_regs);
2604 err_release_mem_region:
2605 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2606 release_mem_region(res->start, res->end - res->start + 1);
2607 err_kfree:
2608 kfree(udc_controller);
2609 udc_controller = NULL;
2610 return ret;
2611 }
2612
2613 /* Driver removal function
2614 * Free resources and finish pending transactions
2615 */
2616 static int __exit fsl_udc_remove(struct platform_device *pdev)
2617 {
2618 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2619 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2620
2621 DECLARE_COMPLETION(done);
2622
2623 if (!udc_controller)
2624 return -ENODEV;
2625
2626 usb_del_gadget_udc(&udc_controller->gadget);
2627 udc_controller->done = &done;
2628
2629 fsl_udc_clk_release();
2630
2631 /* DR has been stopped in usb_gadget_unregister_driver() */
2632 remove_proc_file();
2633
2634 /* Free allocated memory */
2635 kfree(udc_controller->status_req->req.buf);
2636 kfree(udc_controller->status_req);
2637 kfree(udc_controller->eps);
2638
2639 dma_pool_destroy(udc_controller->td_pool);
2640 free_irq(udc_controller->irq, udc_controller);
2641 iounmap(dr_regs);
2642 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2643 release_mem_region(res->start, res->end - res->start + 1);
2644
2645 device_unregister(&udc_controller->gadget.dev);
2646 /* free udc --wait for the release() finished */
2647 wait_for_completion(&done);
2648
2649 /*
2650 * do platform specific un-initialization:
2651 * release iomux pins, etc.
2652 */
2653 if (pdata->exit)
2654 pdata->exit(pdev);
2655
2656 return 0;
2657 }
2658
2659 /*-----------------------------------------------------------------
2660 * Modify Power management attributes
2661 * Used by OTG statemachine to disable gadget temporarily
2662 -----------------------------------------------------------------*/
2663 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2664 {
2665 dr_controller_stop(udc_controller);
2666 return 0;
2667 }
2668
2669 /*-----------------------------------------------------------------
2670 * Invoked on USB resume. May be called in_interrupt.
2671 * Here we start the DR controller and enable the irq
2672 *-----------------------------------------------------------------*/
2673 static int fsl_udc_resume(struct platform_device *pdev)
2674 {
2675 /* Enable DR irq reg and set controller Run */
2676 if (udc_controller->stopped) {
2677 dr_controller_setup(udc_controller);
2678 dr_controller_run(udc_controller);
2679 }
2680 udc_controller->usb_state = USB_STATE_ATTACHED;
2681 udc_controller->ep0_state = WAIT_FOR_SETUP;
2682 udc_controller->ep0_dir = 0;
2683 return 0;
2684 }
2685
2686 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2687 {
2688 struct fsl_udc *udc = udc_controller;
2689 u32 mode, usbcmd;
2690
2691 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2692
2693 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2694
2695 /*
2696 * If the controller is already stopped, then this must be a
2697 * PM suspend. Remember this fact, so that we will leave the
2698 * controller stopped at PM resume time.
2699 */
2700 if (udc->stopped) {
2701 pr_debug("gadget already stopped, leaving early\n");
2702 udc->already_stopped = 1;
2703 return 0;
2704 }
2705
2706 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2707 pr_debug("gadget not in device mode, leaving early\n");
2708 return 0;
2709 }
2710
2711 /* stop the controller */
2712 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2713 fsl_writel(usbcmd, &dr_regs->usbcmd);
2714
2715 udc->stopped = 1;
2716
2717 pr_info("USB Gadget suspended\n");
2718
2719 return 0;
2720 }
2721
2722 static int fsl_udc_otg_resume(struct device *dev)
2723 {
2724 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2725 udc_controller->stopped, udc_controller->already_stopped);
2726
2727 /*
2728 * If the controller was stopped at suspend time, then
2729 * don't resume it now.
2730 */
2731 if (udc_controller->already_stopped) {
2732 udc_controller->already_stopped = 0;
2733 pr_debug("gadget was already stopped, leaving early\n");
2734 return 0;
2735 }
2736
2737 pr_info("USB Gadget resume\n");
2738
2739 return fsl_udc_resume(NULL);
2740 }
2741
2742 /*-------------------------------------------------------------------------
2743 Register entry point for the peripheral controller driver
2744 --------------------------------------------------------------------------*/
2745
2746 static struct platform_driver udc_driver = {
2747 .remove = __exit_p(fsl_udc_remove),
2748 /* these suspend and resume are not usb suspend and resume */
2749 .suspend = fsl_udc_suspend,
2750 .resume = fsl_udc_resume,
2751 .driver = {
2752 .name = (char *)driver_name,
2753 .owner = THIS_MODULE,
2754 /* udc suspend/resume called from OTG driver */
2755 .suspend = fsl_udc_otg_suspend,
2756 .resume = fsl_udc_otg_resume,
2757 },
2758 };
2759
2760 static int __init udc_init(void)
2761 {
2762 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2763 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2764 }
2765
2766 module_init(udc_init);
2767
2768 static void __exit udc_exit(void)
2769 {
2770 platform_driver_unregister(&udc_driver);
2771 printk(KERN_WARNING "%s unregistered\n", driver_desc);
2772 }
2773
2774 module_exit(udc_exit);
2775
2776 MODULE_DESCRIPTION(DRIVER_DESC);
2777 MODULE_AUTHOR(DRIVER_AUTHOR);
2778 MODULE_LICENSE("GPL");
2779 MODULE_ALIAS("platform:fsl-usb2-udc");