drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25
  26 #include "xhci.h"
  27
  28 /* Device for a quirk */
  29 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  30 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  31
  32 static const char hcd_name[] = "xhci_hcd";
  33
  34 /* called after powerup, by probe or system-pm "wakeup" */
  35 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  36 {
  37         /*
  38          * TODO: Implement finding debug ports later.
  39          * TODO: see if there are any quirks that need to be added to handle
  40          * new extended capabilities.
  41          */
  42
  43         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  44         if (!pci_set_mwi(pdev))
  45                 xhci_dbg(xhci, "MWI active\n");
  46
  47         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  48         return 0;
  49 }
  50
  51 /* called during probe() after chip reset completes */
  52 static int xhci_pci_setup(struct usb_hcd *hcd)
  53 {
  54         struct xhci_hcd         *xhci;
  55         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  56         int                     retval;
  57         u32                     temp;
  58
  59         hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
  60
  61         if (usb_hcd_is_primary_hcd(hcd)) {
  62                 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
  63                 if (!xhci)
  64                         return -ENOMEM;
  65                 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
  66                 xhci->main_hcd = hcd;
  67                 /* Mark the first roothub as being USB 2.0.
  68                  * The xHCI driver will register the USB 3.0 roothub.
  69                  */
  70                 hcd->speed = HCD_USB2;
  71                 hcd->self.root_hub->speed = USB_SPEED_HIGH;
  72                 /*
  73                  * USB 2.0 roothub under xHCI has an integrated TT,
  74                  * (rate matching hub) as opposed to having an OHCI/UHCI
  75                  * companion controller.
  76                  */
  77                 hcd->has_tt = 1;
  78         } else {
  79                 /* xHCI private pointer was set in xhci_pci_probe for the second
  80                  * registered roothub.
  81                  */
  82                 xhci = hcd_to_xhci(hcd);
  83                 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  84                 if (HCC_64BIT_ADDR(temp)) {
  85                         xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
  86                         dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
  87                 } else {
  88                         dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
  89                 }
  90                 return 0;
  91         }
  92
  93         xhci->cap_regs = hcd->regs;
  94         xhci->op_regs = hcd->regs +
  95                 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
  96         xhci->run_regs = hcd->regs +
  97                 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
  98         /* Cache read-only capability registers */
  99         xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
 100         xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
 101         xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
 102         xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
 103         xhci->hci_version = HC_VERSION(xhci->hcc_params);
 104         xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
 105         xhci_print_registers(xhci);
 106
 107         /* Look for vendor-specific quirks */
 108         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 109                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) {
 110                 if (pdev->revision == 0x0) {
 111                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 112                         xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
 113                                         " endpoint cmd after reset endpoint\n");
 114                 }
 115                 /* Fresco Logic confirms: all revisions of this chip do not
 116                  * support MSI, even though some of them claim to in their PCI
 117                  * capabilities.
 118                  */
 119                 xhci->quirks |= XHCI_BROKEN_MSI;
 120                 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
 121                                 "has broken MSI implementation\n",
 122                                 pdev->revision);
 123         }
 124
 125         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 126                 xhci->quirks |= XHCI_NEC_HOST;
 127
 128         /* AMD PLL quirk */
 129         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 130                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 131         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 132                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 133                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 134                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 135                 xhci->limit_active_eps = 64;
 136         }
 137
 138         /* Make sure the HC is halted. */
 139         retval = xhci_halt(xhci);
 140         if (retval)
 141                 goto error;
 142
 143         xhci_dbg(xhci, "Resetting HCD\n");
 144         /* Reset the internal HC memory state and registers. */
 145         retval = xhci_reset(xhci);
 146         if (retval)
 147                 goto error;
 148         xhci_dbg(xhci, "Reset complete\n");
 149
 150         temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
 151         if (HCC_64BIT_ADDR(temp)) {
 152                 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
 153                 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
 154         } else {
 155                 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
 156         }
 157
 158         xhci_dbg(xhci, "Calling HCD init\n");
 159         /* Initialize HCD and host controller data structures. */
 160         retval = xhci_init(hcd);
 161         if (retval)
 162                 goto error;
 163         xhci_dbg(xhci, "Called HCD init\n");
 164
 165         pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 166         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 167
 168         /* Find any debug ports */
 169         retval = xhci_pci_reinit(xhci, pdev);
 170         if (!retval)
 171                 return retval;
 172
 173 error:
 174         kfree(xhci);
 175         return retval;
 176 }
 177
 178 /*
 179  * We need to register our own PCI probe function (instead of the USB core's
 180  * function) in order to create a second roothub under xHCI.
 181  */
 182 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 183 {
 184         int retval;
 185         struct xhci_hcd *xhci;
 186         struct hc_driver *driver;
 187         struct usb_hcd *hcd;
 188
 189         driver = (struct hc_driver *)id->driver_data;
 190         /* Register the USB 2.0 roothub.
 191          * FIXME: USB core must know to register the USB 2.0 roothub first.
 192          * This is sort of silly, because we could just set the HCD driver flags
 193          * to say USB 2.0, but I'm not sure what the implications would be in
 194          * the other parts of the HCD code.
 195          */
 196         retval = usb_hcd_pci_probe(dev, id);
 197
 198         if (retval)
 199                 return retval;
 200
 201         /* USB 2.0 roothub is stored in the PCI device now. */
 202         hcd = dev_get_drvdata(&dev->dev);
 203         xhci = hcd_to_xhci(hcd);
 204         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 205                                 pci_name(dev), hcd);
 206         if (!xhci->shared_hcd) {
 207                 retval = -ENOMEM;
 208                 goto dealloc_usb2_hcd;
 209         }
 210
 211         /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
 212          * is called by usb_add_hcd().
 213          */
 214         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
 215
 216         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 217                         IRQF_DISABLED | IRQF_SHARED);
 218         if (retval)
 219                 goto put_usb3_hcd;
 220         /* Roothub already marked as USB 3.0 speed */
 221         return 0;
 222
 223 put_usb3_hcd:
 224         usb_put_hcd(xhci->shared_hcd);
 225 dealloc_usb2_hcd:
 226         usb_hcd_pci_remove(dev);
 227         return retval;
 228 }
 229
 230 static void xhci_pci_remove(struct pci_dev *dev)
 231 {
 232         struct xhci_hcd *xhci;
 233
 234         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 235         if (xhci->shared_hcd) {
 236                 usb_remove_hcd(xhci->shared_hcd);
 237                 usb_put_hcd(xhci->shared_hcd);
 238         }
 239         usb_hcd_pci_remove(dev);
 240         kfree(xhci);
 241 }
 242
 243 #ifdef CONFIG_PM
 244 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 245 {
 246         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 247         int     retval = 0;
 248
 249         if (hcd->state != HC_STATE_SUSPENDED ||
 250                         xhci->shared_hcd->state != HC_STATE_SUSPENDED)
 251                 return -EINVAL;
 252
 253         retval = xhci_suspend(xhci);
 254
 255         return retval;
 256 }
 257
 258 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 259 {
 260         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 261         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 262         int                     retval = 0;
 263
 264         /* The BIOS on systems with the Intel Panther Point chipset may or may
 265          * not support xHCI natively.  That means that during system resume, it
 266          * may switch the ports back to EHCI so that users can use their
 267          * keyboard to select a kernel from GRUB after resume from hibernate.
 268          *
 269          * The BIOS is supposed to remember whether the OS had xHCI ports
 270          * enabled before resume, and switch the ports back to xHCI when the
 271          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 272          * writers.
 273          *
 274          * Unconditionally switch the ports back to xHCI after a system resume.
 275          * We can't tell whether the EHCI or xHCI controller will be resumed
 276          * first, so we have to do the port switchover in both drivers.  Writing
 277          * a '1' to the port switchover registers should have no effect if the
 278          * port was already switched over.
 279          */
 280         if (usb_is_intel_switchable_xhci(pdev))
 281                 usb_enable_xhci_ports(pdev);
 282
 283         retval = xhci_resume(xhci, hibernated);
 284         return retval;
 285 }
 286 #endif /* CONFIG_PM */
 287
 288 static const struct hc_driver xhci_pci_hc_driver = {
 289         .description =          hcd_name,
 290         .product_desc =         "xHCI Host Controller",
 291         .hcd_priv_size =        sizeof(struct xhci_hcd *),
 292
 293         /*
 294          * generic hardware linkage
 295          */
 296         .irq =                  xhci_irq,
 297         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
 298
 299         /*
 300          * basic lifecycle operations
 301          */
 302         .reset =                xhci_pci_setup,
 303         .start =                xhci_run,
 304 #ifdef CONFIG_PM
 305         .pci_suspend =          xhci_pci_suspend,
 306         .pci_resume =           xhci_pci_resume,
 307 #endif
 308         .stop =                 xhci_stop,
 309         .shutdown =             xhci_shutdown,
 310
 311         /*
 312          * managing i/o requests and associated device resources
 313          */
 314         .urb_enqueue =          xhci_urb_enqueue,
 315         .urb_dequeue =          xhci_urb_dequeue,
 316         .alloc_dev =            xhci_alloc_dev,
 317         .free_dev =             xhci_free_dev,
 318         .alloc_streams =        xhci_alloc_streams,
 319         .free_streams =         xhci_free_streams,
 320         .add_endpoint =         xhci_add_endpoint,
 321         .drop_endpoint =        xhci_drop_endpoint,
 322         .endpoint_reset =       xhci_endpoint_reset,
 323         .check_bandwidth =      xhci_check_bandwidth,
 324         .reset_bandwidth =      xhci_reset_bandwidth,
 325         .address_device =       xhci_address_device,
 326         .update_hub_device =    xhci_update_hub_device,
 327         .reset_device =         xhci_discover_or_reset_device,
 328
 329         /*
 330          * scheduling support
 331          */
 332         .get_frame_number =     xhci_get_frame,
 333
 334         /* Root hub support */
 335         .hub_control =          xhci_hub_control,
 336         .hub_status_data =      xhci_hub_status_data,
 337         .bus_suspend =          xhci_bus_suspend,
 338         .bus_resume =           xhci_bus_resume,
 339 };
 340
 341 /*-------------------------------------------------------------------------*/
 342
 343 /* PCI driver selection metadata; PCI hotplugging uses this */
 344 static const struct pci_device_id pci_ids[] = { {
 345         /* handle any USB 3.0 xHCI controller */
 346         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 347         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 348         },
 349         { /* end: all zeroes */ }
 350 };
 351 MODULE_DEVICE_TABLE(pci, pci_ids);
 352
 353 /* pci driver glue; this is a "new style" PCI driver module */
 354 static struct pci_driver xhci_pci_driver = {
 355         .name =         (char *) hcd_name,
 356         .id_table =     pci_ids,
 357
 358         .probe =        xhci_pci_probe,
 359         .remove =       xhci_pci_remove,
 360         /* suspend and resume implemented later */
 361
 362         .shutdown =     usb_hcd_pci_shutdown,
 363 #ifdef CONFIG_PM_SLEEP
 364         .driver = {
 365                 .pm = &usb_hcd_pci_pm_ops
 366         },
 367 #endif
 368 };
 369
 370 int xhci_register_pci(void)
 371 {
 372         return pci_register_driver(&xhci_pci_driver);
 373 }
 374
 375 void xhci_unregister_pci(void)
 376 {
 377         pci_unregister_driver(&xhci_pci_driver);
 378 }